drivers/media/video/cx25821/cx25821-medusa-video.c

   1 /*
   2  *  Driver for the Conexant CX25821 PCIe bridge
   3  *
   4  *  Copyright (C) 2009 Conexant Systems Inc.
   5  *  Authors  <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License, or
  10  *  (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *
  16  *  GNU General Public License for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License
  19  *  along with this program; if not, write to the Free Software
  20  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  24
  25 #include "cx25821.h"
  26 #include "cx25821-medusa-video.h"
  27 #include "cx25821-biffuncs.h"
  28
  29 /*
  30  * medusa_enable_bluefield_output()
  31  *
  32  * Enable the generation of blue filed output if no video
  33  *
  34  */
  35 static void medusa_enable_bluefield_output(struct cx25821_dev *dev, int channel,
  36                                            int enable)
  37 {
  38         int ret_val = 1;
  39         u32 value = 0;
  40         u32 tmp = 0;
  41         int out_ctrl = OUT_CTRL1;
  42         int out_ctrl_ns = OUT_CTRL_NS;
  43
  44         switch (channel) {
  45         default:
  46         case VDEC_A:
  47                 break;
  48         case VDEC_B:
  49                 out_ctrl = VDEC_B_OUT_CTRL1;
  50                 out_ctrl_ns = VDEC_B_OUT_CTRL_NS;
  51                 break;
  52         case VDEC_C:
  53                 out_ctrl = VDEC_C_OUT_CTRL1;
  54                 out_ctrl_ns = VDEC_C_OUT_CTRL_NS;
  55                 break;
  56         case VDEC_D:
  57                 out_ctrl = VDEC_D_OUT_CTRL1;
  58                 out_ctrl_ns = VDEC_D_OUT_CTRL_NS;
  59                 break;
  60         case VDEC_E:
  61                 out_ctrl = VDEC_E_OUT_CTRL1;
  62                 out_ctrl_ns = VDEC_E_OUT_CTRL_NS;
  63                 return;
  64         case VDEC_F:
  65                 out_ctrl = VDEC_F_OUT_CTRL1;
  66                 out_ctrl_ns = VDEC_F_OUT_CTRL_NS;
  67                 return;
  68         case VDEC_G:
  69                 out_ctrl = VDEC_G_OUT_CTRL1;
  70                 out_ctrl_ns = VDEC_G_OUT_CTRL_NS;
  71                 return;
  72         case VDEC_H:
  73                 out_ctrl = VDEC_H_OUT_CTRL1;
  74                 out_ctrl_ns = VDEC_H_OUT_CTRL_NS;
  75                 return;
  76         }
  77
  78         value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl, &tmp);
  79         value &= 0xFFFFFF7F;    /* clear BLUE_FIELD_EN */
  80         if (enable)
  81                 value |= 0x00000080;    /* set BLUE_FIELD_EN */
  82         ret_val = cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl, value);
  83
  84         value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl_ns, &tmp);
  85         value &= 0xFFFFFF7F;
  86         if (enable)
  87                 value |= 0x00000080;    /* set BLUE_FIELD_EN */
  88         ret_val = cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl_ns, value);
  89 }
  90
  91 static int medusa_initialize_ntsc(struct cx25821_dev *dev)
  92 {
  93         int ret_val = 0;
  94         int i = 0;
  95         u32 value = 0;
  96         u32 tmp = 0;
  97
  98         mutex_lock(&dev->lock);
  99
 100         for (i = 0; i < MAX_DECODERS; i++) {
 101                 /* set video format NTSC-M */
 102                 value = cx25821_i2c_read(&dev->i2c_bus[0],
 103                                 MODE_CTRL + (0x200 * i), &tmp);
 104                 value &= 0xFFFFFFF0;
 105                 /* enable the fast locking mode bit[16] */
 106                 value |= 0x10001;
 107                 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 108                                 MODE_CTRL + (0x200 * i), value);
 109
 110                 /* resolution NTSC 720x480 */
 111                 value = cx25821_i2c_read(&dev->i2c_bus[0],
 112                                 HORIZ_TIM_CTRL + (0x200 * i), &tmp);
 113                 value &= 0x00C00C00;
 114                 value |= 0x612D0074;
 115                 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 116                                 HORIZ_TIM_CTRL + (0x200 * i), value);
 117
 118                 value = cx25821_i2c_read(&dev->i2c_bus[0],
 119                                 VERT_TIM_CTRL + (0x200 * i), &tmp);
 120                 value &= 0x00C00C00;
 121                 value |= 0x1C1E001A;    /* vblank_cnt + 2 to get camera ID */
 122                 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 123                                 VERT_TIM_CTRL + (0x200 * i), value);
 124
 125                 /* chroma subcarrier step size */
 126                 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 127                                 SC_STEP_SIZE + (0x200 * i), 0x43E00000);
 128
 129                 /* enable VIP optional active */
 130                 value = cx25821_i2c_read(&dev->i2c_bus[0],
 131                                 OUT_CTRL_NS + (0x200 * i), &tmp);
 132                 value &= 0xFFFBFFFF;
 133                 value |= 0x00040000;
 134                 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 135                                 OUT_CTRL_NS + (0x200 * i), value);
 136
 137                 /* enable VIP optional active (VIP_OPT_AL) for direct output. */
 138                 value = cx25821_i2c_read(&dev->i2c_bus[0],
 139                                 OUT_CTRL1 + (0x200 * i), &tmp);
 140                 value &= 0xFFFBFFFF;
 141                 value |= 0x00040000;
 142                 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 143                                 OUT_CTRL1 + (0x200 * i), value);
 144
 145                 /*
 146                  * clear VPRES_VERT_EN bit, fixes the chroma run away problem
 147                  * when the input switching rate < 16 fields
 148                 */
 149                 value = cx25821_i2c_read(&dev->i2c_bus[0],
 150                                 MISC_TIM_CTRL + (0x200 * i), &tmp);
 151                 /* disable special play detection */
 152                 value = setBitAtPos(value, 14);
 153                 value = clearBitAtPos(value, 15);
 154                 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 155                                 MISC_TIM_CTRL + (0x200 * i), value);
 156
 157                 /* set vbi_gate_en to 0 */
 158                 value = cx25821_i2c_read(&dev->i2c_bus[0],
 159                                 DFE_CTRL1 + (0x200 * i), &tmp);
 160                 value = clearBitAtPos(value, 29);
 161                 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 162                                 DFE_CTRL1 + (0x200 * i), value);
 163
 164                 /* Enable the generation of blue field output if no video */
 165                 medusa_enable_bluefield_output(dev, i, 1);
 166         }
 167
 168         for (i = 0; i < MAX_ENCODERS; i++) {
 169                 /* NTSC hclock */
 170                 value = cx25821_i2c_read(&dev->i2c_bus[0],
 171                                 DENC_A_REG_1 + (0x100 * i), &tmp);
 172                 value &= 0xF000FC00;
 173                 value |= 0x06B402D0;
 174                 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 175                                 DENC_A_REG_1 + (0x100 * i), value);
 176
 177                 /* burst begin and burst end */
 178                 value = cx25821_i2c_read(&dev->i2c_bus[0],
 179                                 DENC_A_REG_2 + (0x100 * i), &tmp);
 180                 value &= 0xFF000000;
 181                 value |= 0x007E9054;
 182                 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 183                                 DENC_A_REG_2 + (0x100 * i), value);
 184
 185                 value = cx25821_i2c_read(&dev->i2c_bus[0],
 186                                 DENC_A_REG_3 + (0x100 * i), &tmp);
 187                 value &= 0xFC00FE00;
 188                 value |= 0x00EC00F0;
 189                 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 190                                 DENC_A_REG_3 + (0x100 * i), value);
 191
 192                 /* set NTSC vblank, no phase alternation, 7.5 IRE pedestal */
 193                 value = cx25821_i2c_read(&dev->i2c_bus[0],
 194                                 DENC_A_REG_4 + (0x100 * i), &tmp);
 195                 value &= 0x00FCFFFF;
 196                 value |= 0x13020000;
 197                 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 198                                 DENC_A_REG_4 + (0x100 * i), value);
 199
 200                 value = cx25821_i2c_read(&dev->i2c_bus[0],
 201                                 DENC_A_REG_5 + (0x100 * i), &tmp);
 202                 value &= 0xFFFF0000;
 203                 value |= 0x0000E575;
 204                 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 205                                 DENC_A_REG_5 + (0x100 * i), value);
 206
 207                 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 208                                 DENC_A_REG_6 + (0x100 * i), 0x009A89C1);
 209
 210                 /* Subcarrier Increment */
 211                 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 212                                 DENC_A_REG_7 + (0x100 * i), 0x21F07C1F);
 213         }
 214
 215         /* set picture resolutions */
 216         /* 0 - 720 */
 217         ret_val = cx25821_i2c_write(&dev->i2c_bus[0], HSCALE_CTRL, 0x0);
 218         /* 0 - 480 */
 219         ret_val = cx25821_i2c_write(&dev->i2c_bus[0], VSCALE_CTRL, 0x0);
 220
 221         /* set Bypass input format to NTSC 525 lines */
 222         value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp);
 223         value |= 0x00080200;
 224         ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value);
 225
 226         mutex_unlock(&dev->lock);
 227
 228         return ret_val;
 229 }
 230
 231 static int medusa_PALCombInit(struct cx25821_dev *dev, int dec)
 232 {
 233         int ret_val = -1;
 234         u32 value = 0, tmp = 0;
 235
 236         /* Setup for 2D threshold */
 237         ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 238                         COMB_2D_HFS_CFG + (0x200 * dec), 0x20002861);
 239         ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 240                         COMB_2D_HFD_CFG + (0x200 * dec), 0x20002861);
 241         ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 242                         COMB_2D_LF_CFG + (0x200 * dec), 0x200A1023);
 243
 244         /* Setup flat chroma and luma thresholds */
 245         value = cx25821_i2c_read(&dev->i2c_bus[0],
 246                         COMB_FLAT_THRESH_CTRL + (0x200 * dec), &tmp);
 247         value &= 0x06230000;
 248         ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 249                         COMB_FLAT_THRESH_CTRL + (0x200 * dec), value);
 250
 251         /* set comb 2D blend */
 252         ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 253                         COMB_2D_BLEND + (0x200 * dec), 0x210F0F0F);
 254
 255         /* COMB MISC CONTROL */
 256         ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 257                         COMB_MISC_CTRL + (0x200 * dec), 0x41120A7F);
 258
 259         return ret_val;
 260 }
 261
 262 static int medusa_initialize_pal(struct cx25821_dev *dev)
 263 {
 264         int ret_val = 0;
 265         int i = 0;
 266         u32 value = 0;
 267         u32 tmp = 0;
 268
 269         mutex_lock(&dev->lock);
 270
 271         for (i = 0; i < MAX_DECODERS; i++) {
 272                 /* set video format PAL-BDGHI */
 273                 value = cx25821_i2c_read(&dev->i2c_bus[0],
 274                                 MODE_CTRL + (0x200 * i), &tmp);
 275                 value &= 0xFFFFFFF0;
 276                 /* enable the fast locking mode bit[16] */
 277                 value |= 0x10004;
 278                 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 279                                 MODE_CTRL + (0x200 * i), value);
 280
 281                 /* resolution PAL 720x576 */
 282                 value = cx25821_i2c_read(&dev->i2c_bus[0],
 283                                 HORIZ_TIM_CTRL + (0x200 * i), &tmp);
 284                 value &= 0x00C00C00;
 285                 value |= 0x632D007D;
 286                 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 287                                 HORIZ_TIM_CTRL + (0x200 * i), value);
 288
 289                 /* vblank656_cnt=x26, vactive_cnt=240h, vblank_cnt=x24 */
 290                 value = cx25821_i2c_read(&dev->i2c_bus[0],
 291                                 VERT_TIM_CTRL + (0x200 * i), &tmp);
 292                 value &= 0x00C00C00;
 293                 value |= 0x28240026;    /* vblank_cnt + 2 to get camera ID */
 294                 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 295                                 VERT_TIM_CTRL + (0x200 * i), value);
 296
 297                 /* chroma subcarrier step size */
 298                 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 299                                 SC_STEP_SIZE + (0x200 * i), 0x5411E2D0);
 300
 301                 /* enable VIP optional active */
 302                 value = cx25821_i2c_read(&dev->i2c_bus[0],
 303                                 OUT_CTRL_NS + (0x200 * i), &tmp);
 304                 value &= 0xFFFBFFFF;
 305                 value |= 0x00040000;
 306                 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 307                                 OUT_CTRL_NS + (0x200 * i), value);
 308
 309                 /* enable VIP optional active (VIP_OPT_AL) for direct output. */
 310                 value = cx25821_i2c_read(&dev->i2c_bus[0],
 311                                 OUT_CTRL1 + (0x200 * i), &tmp);
 312                 value &= 0xFFFBFFFF;
 313                 value |= 0x00040000;
 314                 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 315                                 OUT_CTRL1 + (0x200 * i), value);
 316
 317                 /*
 318                  * clear VPRES_VERT_EN bit, fixes the chroma run away problem
 319                  * when the input switching rate < 16 fields
 320                  */
 321                 value = cx25821_i2c_read(&dev->i2c_bus[0],
 322                                 MISC_TIM_CTRL + (0x200 * i), &tmp);
 323                 /* disable special play detection */
 324                 value = setBitAtPos(value, 14);
 325                 value = clearBitAtPos(value, 15);
 326                 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 327                                 MISC_TIM_CTRL + (0x200 * i), value);
 328
 329                 /* set vbi_gate_en to 0 */
 330                 value = cx25821_i2c_read(&dev->i2c_bus[0],
 331                                 DFE_CTRL1 + (0x200 * i), &tmp);
 332                 value = clearBitAtPos(value, 29);
 333                 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 334                                 DFE_CTRL1 + (0x200 * i), value);
 335
 336                 medusa_PALCombInit(dev, i);
 337
 338                 /* Enable the generation of blue field output if no video */
 339                 medusa_enable_bluefield_output(dev, i, 1);
 340         }
 341
 342         for (i = 0; i < MAX_ENCODERS; i++) {
 343                 /* PAL hclock */
 344                 value = cx25821_i2c_read(&dev->i2c_bus[0],
 345                                 DENC_A_REG_1 + (0x100 * i), &tmp);
 346                 value &= 0xF000FC00;
 347                 value |= 0x06C002D0;
 348                 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 349                                 DENC_A_REG_1 + (0x100 * i), value);
 350
 351                 /* burst begin and burst end */
 352                 value = cx25821_i2c_read(&dev->i2c_bus[0],
 353                                 DENC_A_REG_2 + (0x100 * i), &tmp);
 354                 value &= 0xFF000000;
 355                 value |= 0x007E9754;
 356                 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 357                                 DENC_A_REG_2 + (0x100 * i), value);
 358
 359                 /* hblank and vactive */
 360                 value = cx25821_i2c_read(&dev->i2c_bus[0],
 361                                 DENC_A_REG_3 + (0x100 * i), &tmp);
 362                 value &= 0xFC00FE00;
 363                 value |= 0x00FC0120;
 364                 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 365                                 DENC_A_REG_3 + (0x100 * i), value);
 366
 367                 /* set PAL vblank, phase alternation, 0 IRE pedestal */
 368                 value = cx25821_i2c_read(&dev->i2c_bus[0],
 369                                 DENC_A_REG_4 + (0x100 * i), &tmp);
 370                 value &= 0x00FCFFFF;
 371                 value |= 0x14010000;
 372                 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 373                                 DENC_A_REG_4 + (0x100 * i), value);
 374
 375                 value = cx25821_i2c_read(&dev->i2c_bus[0],
 376                                 DENC_A_REG_5 + (0x100 * i), &tmp);
 377                 value &= 0xFFFF0000;
 378                 value |= 0x0000F078;
 379                 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 380                                 DENC_A_REG_5 + (0x100 * i), value);
 381
 382                 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 383                                 DENC_A_REG_6 + (0x100 * i), 0x00A493CF);
 384
 385                 /* Subcarrier Increment */
 386                 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 387                                 DENC_A_REG_7 + (0x100 * i), 0x2A098ACB);
 388         }
 389
 390         /* set picture resolutions */
 391         /* 0 - 720 */
 392         ret_val = cx25821_i2c_write(&dev->i2c_bus[0], HSCALE_CTRL, 0x0);
 393         /* 0 - 576 */
 394         ret_val = cx25821_i2c_write(&dev->i2c_bus[0], VSCALE_CTRL, 0x0);
 395
 396         /* set Bypass input format to PAL 625 lines */
 397         value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp);
 398         value &= 0xFFF7FDFF;
 399         ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value);
 400
 401         mutex_unlock(&dev->lock);
 402
 403         return ret_val;
 404 }
 405
 406 int medusa_set_videostandard(struct cx25821_dev *dev)
 407 {
 408         int status = STATUS_SUCCESS;
 409         u32 value = 0, tmp = 0;
 410
 411         if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK)
 412                 status = medusa_initialize_pal(dev);
 413         else
 414                 status = medusa_initialize_ntsc(dev);
 415
 416         /* Enable DENC_A output */
 417         value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_A_REG_4, &tmp);
 418         value = setBitAtPos(value, 4);
 419         status = cx25821_i2c_write(&dev->i2c_bus[0], DENC_A_REG_4, value);
 420
 421         /* Enable DENC_B output */
 422         value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_B_REG_4, &tmp);
 423         value = setBitAtPos(value, 4);
 424         status = cx25821_i2c_write(&dev->i2c_bus[0], DENC_B_REG_4, value);
 425
 426         return status;
 427 }
 428
 429 void medusa_set_resolution(struct cx25821_dev *dev, int width,
 430                            int decoder_select)
 431 {
 432         int decoder = 0;
 433         int decoder_count = 0;
 434         int ret_val = 0;
 435         u32 hscale = 0x0;
 436         u32 vscale = 0x0;
 437         const int MAX_WIDTH = 720;
 438
 439         mutex_lock(&dev->lock);
 440
 441         /* validate the width */
 442         if (width > MAX_WIDTH) {
 443                 pr_info("%s(): width %d > MAX_WIDTH %d ! resetting to MAX_WIDTH\n",
 444                         __func__, width, MAX_WIDTH);
 445                 width = MAX_WIDTH;
 446         }
 447
 448         if (decoder_select <= 7 && decoder_select >= 0) {
 449                 decoder = decoder_select;
 450                 decoder_count = decoder_select + 1;
 451         } else {
 452                 decoder = 0;
 453                 decoder_count = _num_decoders;
 454         }
 455
 456         switch (width) {
 457         case 320:
 458                 hscale = 0x13E34B;
 459                 vscale = 0x0;
 460                 break;
 461
 462         case 352:
 463                 hscale = 0x10A273;
 464                 vscale = 0x0;
 465                 break;
 466
 467         case 176:
 468                 hscale = 0x3115B2;
 469                 vscale = 0x1E00;
 470                 break;
 471
 472         case 160:
 473                 hscale = 0x378D84;
 474                 vscale = 0x1E00;
 475                 break;
 476
 477         default:                /* 720 */
 478                 hscale = 0x0;
 479                 vscale = 0x0;
 480                 break;
 481         }
 482
 483         for (; decoder < decoder_count; decoder++) {
 484                 /* write scaling values for each decoder */
 485                 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 486                                 HSCALE_CTRL + (0x200 * decoder), hscale);
 487                 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
 488                                 VSCALE_CTRL + (0x200 * decoder), vscale);
 489         }
 490
 491         mutex_unlock(&dev->lock);
 492 }
 493
 494 static void medusa_set_decoderduration(struct cx25821_dev *dev, int decoder,
 495                                        int duration)
 496 {
 497         int ret_val = 0;
 498         u32 fld_cnt = 0;
 499         u32 tmp = 0;
 500         u32 disp_cnt_reg = DISP_AB_CNT;
 501
 502         mutex_lock(&dev->lock);
 503
 504         /* no support */
 505         if (decoder < VDEC_A && decoder > VDEC_H) {
 506                 mutex_unlock(&dev->lock);
 507                 return;
 508         }
 509
 510         switch (decoder) {
 511         default:
 512                 break;
 513         case VDEC_C:
 514         case VDEC_D:
 515                 disp_cnt_reg = DISP_CD_CNT;
 516                 break;
 517         case VDEC_E:
 518         case VDEC_F:
 519                 disp_cnt_reg = DISP_EF_CNT;
 520                 break;
 521         case VDEC_G:
 522         case VDEC_H:
 523                 disp_cnt_reg = DISP_GH_CNT;
 524                 break;
 525         }
 526
 527         _display_field_cnt[decoder] = duration;
 528
 529         /* update hardware */
 530         fld_cnt = cx25821_i2c_read(&dev->i2c_bus[0], disp_cnt_reg, &tmp);
 531
 532         if (!(decoder % 2)) {   /* EVEN decoder */
 533                 fld_cnt &= 0xFFFF0000;
 534                 fld_cnt |= duration;
 535         } else {
 536                 fld_cnt &= 0x0000FFFF;
 537                 fld_cnt |= ((u32) duration) << 16;
 538         }
 539
 540         ret_val = cx25821_i2c_write(&dev->i2c_bus[0], disp_cnt_reg, fld_cnt);
 541
 542         mutex_unlock(&dev->lock);
 543 }
 544
 545 /* Map to Medusa register setting */
 546 static int mapM(int srcMin, int srcMax, int srcVal, int dstMin, int dstMax,
 547                 int *dstVal)
 548 {
 549         int numerator;
 550         int denominator;
 551         int quotient;
 552
 553         if ((srcMin == srcMax) || (srcVal < srcMin) || (srcVal > srcMax))
 554                 return -1;
 555         /*
 556          * This is the overall expression used:
 557          * *dstVal =
 558          *   (srcVal - srcMin)*(dstMax - dstMin) / (srcMax - srcMin) + dstMin;
 559          * but we need to account for rounding so below we use the modulus
 560          * operator to find the remainder and increment if necessary.
 561          */
 562         numerator = (srcVal - srcMin) * (dstMax - dstMin);
 563         denominator = srcMax - srcMin;
 564         quotient = numerator / denominator;
 565
 566         if (2 * (numerator % denominator) >= denominator)
 567                 quotient++;
 568
 569         *dstVal = quotient + dstMin;
 570
 571         return 0;
 572 }
 573
 574 static unsigned long convert_to_twos(long numeric, unsigned long bits_len)
 575 {
 576         unsigned char temp;
 577
 578         if (numeric >= 0)
 579                 return numeric;
 580         else {
 581                 temp = ~(abs(numeric) & 0xFF);
 582                 temp += 1;
 583                 return temp;
 584         }
 585 }
 586
 587 int medusa_set_brightness(struct cx25821_dev *dev, int brightness, int decoder)
 588 {
 589         int ret_val = 0;
 590         int value = 0;
 591         u32 val = 0, tmp = 0;
 592
 593         mutex_lock(&dev->lock);
 594         if ((brightness > VIDEO_PROCAMP_MAX) ||
 595             (brightness < VIDEO_PROCAMP_MIN)) {
 596                 mutex_unlock(&dev->lock);
 597                 return -1;
 598         }
 599         ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, brightness,
 600                         SIGNED_BYTE_MIN, SIGNED_BYTE_MAX, &value);
 601         value = convert_to_twos(value, 8);
 602         val = cx25821_i2c_read(&dev->i2c_bus[0],
 603                         VDEC_A_BRITE_CTRL + (0x200 * decoder), &tmp);
 604         val &= 0xFFFFFF00;
 605         ret_val |= cx25821_i2c_write(&dev->i2c_bus[0],
 606                         VDEC_A_BRITE_CTRL + (0x200 * decoder), val | value);
 607         mutex_unlock(&dev->lock);
 608         return ret_val;
 609 }
 610
 611 int medusa_set_contrast(struct cx25821_dev *dev, int contrast, int decoder)
 612 {
 613         int ret_val = 0;
 614         int value = 0;
 615         u32 val = 0, tmp = 0;
 616
 617         mutex_lock(&dev->lock);
 618
 619         if ((contrast > VIDEO_PROCAMP_MAX) || (contrast < VIDEO_PROCAMP_MIN)) {
 620                 mutex_unlock(&dev->lock);
 621                 return -1;
 622         }
 623
 624         ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, contrast,
 625                         UNSIGNED_BYTE_MIN, UNSIGNED_BYTE_MAX, &value);
 626         val = cx25821_i2c_read(&dev->i2c_bus[0],
 627                         VDEC_A_CNTRST_CTRL + (0x200 * decoder), &tmp);
 628         val &= 0xFFFFFF00;
 629         ret_val |= cx25821_i2c_write(&dev->i2c_bus[0],
 630                         VDEC_A_CNTRST_CTRL + (0x200 * decoder), val | value);
 631
 632         mutex_unlock(&dev->lock);
 633         return ret_val;
 634 }
 635
 636 int medusa_set_hue(struct cx25821_dev *dev, int hue, int decoder)
 637 {
 638         int ret_val = 0;
 639         int value = 0;
 640         u32 val = 0, tmp = 0;
 641
 642         mutex_lock(&dev->lock);
 643
 644         if ((hue > VIDEO_PROCAMP_MAX) || (hue < VIDEO_PROCAMP_MIN)) {
 645                 mutex_unlock(&dev->lock);
 646                 return -1;
 647         }
 648
 649         ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, hue,
 650                         SIGNED_BYTE_MIN, SIGNED_BYTE_MAX, &value);
 651
 652         value = convert_to_twos(value, 8);
 653         val = cx25821_i2c_read(&dev->i2c_bus[0],
 654                         VDEC_A_HUE_CTRL + (0x200 * decoder), &tmp);
 655         val &= 0xFFFFFF00;
 656
 657         ret_val |= cx25821_i2c_write(&dev->i2c_bus[0],
 658                         VDEC_A_HUE_CTRL + (0x200 * decoder), val | value);
 659
 660         mutex_unlock(&dev->lock);
 661         return ret_val;
 662 }
 663
 664 int medusa_set_saturation(struct cx25821_dev *dev, int saturation, int decoder)
 665 {
 666         int ret_val = 0;
 667         int value = 0;
 668         u32 val = 0, tmp = 0;
 669
 670         mutex_lock(&dev->lock);
 671
 672         if ((saturation > VIDEO_PROCAMP_MAX) ||
 673             (saturation < VIDEO_PROCAMP_MIN)) {
 674                 mutex_unlock(&dev->lock);
 675                 return -1;
 676         }
 677
 678         ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, saturation,
 679                         UNSIGNED_BYTE_MIN, UNSIGNED_BYTE_MAX, &value);
 680
 681         val = cx25821_i2c_read(&dev->i2c_bus[0],
 682                         VDEC_A_USAT_CTRL + (0x200 * decoder), &tmp);
 683         val &= 0xFFFFFF00;
 684         ret_val |= cx25821_i2c_write(&dev->i2c_bus[0],
 685                         VDEC_A_USAT_CTRL + (0x200 * decoder), val | value);
 686
 687         val = cx25821_i2c_read(&dev->i2c_bus[0],
 688                         VDEC_A_VSAT_CTRL + (0x200 * decoder), &tmp);
 689         val &= 0xFFFFFF00;
 690         ret_val |= cx25821_i2c_write(&dev->i2c_bus[0],
 691                         VDEC_A_VSAT_CTRL + (0x200 * decoder), val | value);
 692
 693         mutex_unlock(&dev->lock);
 694         return ret_val;
 695 }
 696
 697 /* Program the display sequence and monitor output. */
 698
 699 int medusa_video_init(struct cx25821_dev *dev)
 700 {
 701         u32 value = 0, tmp = 0;
 702         int ret_val = 0;
 703         int i = 0;
 704
 705         mutex_lock(&dev->lock);
 706
 707         _num_decoders = dev->_max_num_decoders;
 708
 709         /* disable Auto source selection on all video decoders */
 710         value = cx25821_i2c_read(&dev->i2c_bus[0], MON_A_CTRL, &tmp);
 711         value &= 0xFFFFF0FF;
 712         ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MON_A_CTRL, value);
 713
 714         if (ret_val < 0)
 715                 goto error;
 716
 717         /* Turn off Master source switch enable */
 718         value = cx25821_i2c_read(&dev->i2c_bus[0], MON_A_CTRL, &tmp);
 719         value &= 0xFFFFFFDF;
 720         ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MON_A_CTRL, value);
 721
 722         if (ret_val < 0)
 723                 goto error;
 724
 725         mutex_unlock(&dev->lock);
 726
 727         for (i = 0; i < _num_decoders; i++)
 728                 medusa_set_decoderduration(dev, i, _display_field_cnt[i]);
 729
 730         mutex_lock(&dev->lock);
 731
 732         /* Select monitor as DENC A input, power up the DAC */
 733         value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_AB_CTRL, &tmp);
 734         value &= 0xFF70FF70;
 735         value |= 0x00090008;    /* set en_active */
 736         ret_val = cx25821_i2c_write(&dev->i2c_bus[0], DENC_AB_CTRL, value);
 737
 738         if (ret_val < 0)
 739                 goto error;
 740
 741         /* enable input is VIP/656 */
 742         value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp);
 743         value |= 0x00040100;    /* enable VIP */
 744         ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value);
 745
 746         if (ret_val < 0)
 747                 goto error;
 748
 749         /* select AFE clock to output mode */
 750         value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp);
 751         value &= 0x83FFFFFF;
 752         ret_val = cx25821_i2c_write(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL,
 753                         value | 0x10000000);
 754
 755         if (ret_val < 0)
 756                 goto error;
 757
 758         /* Turn on all of the data out and control output pins. */
 759         value = cx25821_i2c_read(&dev->i2c_bus[0], PIN_OE_CTRL, &tmp);
 760         value &= 0xFEF0FE00;
 761         if (_num_decoders == MAX_DECODERS) {
 762                 /*
 763                  * Note: The octal board does not support control pins(bit16-19)
 764                  * These bits are ignored in the octal board.
 765                  *
 766                  * disable VDEC A-C port, default to Mobilygen Interface
 767                  */
 768                 value |= 0x010001F8;
 769         } else {
 770                 /* disable VDEC A-C port, default to Mobilygen Interface */
 771                 value |= 0x010F0108;
 772         }
 773
 774         value |= 7;
 775         ret_val = cx25821_i2c_write(&dev->i2c_bus[0], PIN_OE_CTRL, value);
 776
 777         if (ret_val < 0)
 778                 goto error;
 779
 780
 781         mutex_unlock(&dev->lock);
 782
 783         ret_val = medusa_set_videostandard(dev);
 784
 785         return ret_val;
 786
 787 error:
 788         mutex_unlock(&dev->lock);
 789         return ret_val;
 790 }