2 * Driver for the Conexant CX25821 PCIe bridge
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26 #include "cx25821-medusa-video.h"
27 #include "cx25821-biffuncs.h"
30 * medusa_enable_bluefield_output()
32 * Enable the generation of blue filed output if no video
35 static void medusa_enable_bluefield_output(struct cx25821_dev *dev, int channel,
41 int out_ctrl = OUT_CTRL1;
42 int out_ctrl_ns = OUT_CTRL_NS;
49 out_ctrl = VDEC_B_OUT_CTRL1;
50 out_ctrl_ns = VDEC_B_OUT_CTRL_NS;
53 out_ctrl = VDEC_C_OUT_CTRL1;
54 out_ctrl_ns = VDEC_C_OUT_CTRL_NS;
57 out_ctrl = VDEC_D_OUT_CTRL1;
58 out_ctrl_ns = VDEC_D_OUT_CTRL_NS;
61 out_ctrl = VDEC_E_OUT_CTRL1;
62 out_ctrl_ns = VDEC_E_OUT_CTRL_NS;
65 out_ctrl = VDEC_F_OUT_CTRL1;
66 out_ctrl_ns = VDEC_F_OUT_CTRL_NS;
69 out_ctrl = VDEC_G_OUT_CTRL1;
70 out_ctrl_ns = VDEC_G_OUT_CTRL_NS;
73 out_ctrl = VDEC_H_OUT_CTRL1;
74 out_ctrl_ns = VDEC_H_OUT_CTRL_NS;
78 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl, &tmp);
79 value &= 0xFFFFFF7F; /* clear BLUE_FIELD_EN */
81 value |= 0x00000080; /* set BLUE_FIELD_EN */
82 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl, value);
84 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl_ns, &tmp);
87 value |= 0x00000080; /* set BLUE_FIELD_EN */
88 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl_ns, value);
91 static int medusa_initialize_ntsc(struct cx25821_dev *dev)
98 mutex_lock(&dev->lock);
100 for (i = 0; i < MAX_DECODERS; i++) {
101 /* set video format NTSC-M */
103 cx25821_i2c_read(&dev->i2c_bus[0], MODE_CTRL + (0x200 * i),
106 /* enable the fast locking mode bit[16] */
109 cx25821_i2c_write(&dev->i2c_bus[0], MODE_CTRL + (0x200 * i),
112 /* resolution NTSC 720x480 */
114 cx25821_i2c_read(&dev->i2c_bus[0],
115 HORIZ_TIM_CTRL + (0x200 * i), &tmp);
119 cx25821_i2c_write(&dev->i2c_bus[0],
120 HORIZ_TIM_CTRL + (0x200 * i), value);
123 cx25821_i2c_read(&dev->i2c_bus[0],
124 VERT_TIM_CTRL + (0x200 * i), &tmp);
126 value |= 0x1C1E001A; /* vblank_cnt + 2 to get camera ID */
128 cx25821_i2c_write(&dev->i2c_bus[0],
129 VERT_TIM_CTRL + (0x200 * i), value);
131 /* chroma subcarrier step size */
133 cx25821_i2c_write(&dev->i2c_bus[0],
134 SC_STEP_SIZE + (0x200 * i), 0x43E00000);
136 /* enable VIP optional active */
138 cx25821_i2c_read(&dev->i2c_bus[0],
139 OUT_CTRL_NS + (0x200 * i), &tmp);
143 cx25821_i2c_write(&dev->i2c_bus[0],
144 OUT_CTRL_NS + (0x200 * i), value);
146 /* enable VIP optional active (VIP_OPT_AL) for direct output. */
148 cx25821_i2c_read(&dev->i2c_bus[0], OUT_CTRL1 + (0x200 * i),
153 cx25821_i2c_write(&dev->i2c_bus[0], OUT_CTRL1 + (0x200 * i),
157 * clear VPRES_VERT_EN bit, fixes the chroma run away problem
158 * when the input switching rate < 16 fields
161 cx25821_i2c_read(&dev->i2c_bus[0],
162 MISC_TIM_CTRL + (0x200 * i), &tmp);
163 /* disable special play detection */
164 value = setBitAtPos(value, 14);
165 value = clearBitAtPos(value, 15);
167 cx25821_i2c_write(&dev->i2c_bus[0],
168 MISC_TIM_CTRL + (0x200 * i), value);
170 /* set vbi_gate_en to 0 */
172 cx25821_i2c_read(&dev->i2c_bus[0], DFE_CTRL1 + (0x200 * i),
174 value = clearBitAtPos(value, 29);
176 cx25821_i2c_write(&dev->i2c_bus[0], DFE_CTRL1 + (0x200 * i),
179 /* Enable the generation of blue field output if no video */
180 medusa_enable_bluefield_output(dev, i, 1);
183 for (i = 0; i < MAX_ENCODERS; i++) {
186 cx25821_i2c_read(&dev->i2c_bus[0],
187 DENC_A_REG_1 + (0x100 * i), &tmp);
191 cx25821_i2c_write(&dev->i2c_bus[0],
192 DENC_A_REG_1 + (0x100 * i), value);
194 /* burst begin and burst end */
196 cx25821_i2c_read(&dev->i2c_bus[0],
197 DENC_A_REG_2 + (0x100 * i), &tmp);
201 cx25821_i2c_write(&dev->i2c_bus[0],
202 DENC_A_REG_2 + (0x100 * i), value);
205 cx25821_i2c_read(&dev->i2c_bus[0],
206 DENC_A_REG_3 + (0x100 * i), &tmp);
210 cx25821_i2c_write(&dev->i2c_bus[0],
211 DENC_A_REG_3 + (0x100 * i), value);
213 /* set NTSC vblank, no phase alternation, 7.5 IRE pedestal */
215 cx25821_i2c_read(&dev->i2c_bus[0],
216 DENC_A_REG_4 + (0x100 * i), &tmp);
220 cx25821_i2c_write(&dev->i2c_bus[0],
221 DENC_A_REG_4 + (0x100 * i), value);
224 cx25821_i2c_read(&dev->i2c_bus[0],
225 DENC_A_REG_5 + (0x100 * i), &tmp);
229 cx25821_i2c_write(&dev->i2c_bus[0],
230 DENC_A_REG_5 + (0x100 * i), value);
233 cx25821_i2c_write(&dev->i2c_bus[0],
234 DENC_A_REG_6 + (0x100 * i), 0x009A89C1);
236 /* Subcarrier Increment */
238 cx25821_i2c_write(&dev->i2c_bus[0],
239 DENC_A_REG_7 + (0x100 * i), 0x21F07C1F);
242 /* set picture resolutions */
244 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], HSCALE_CTRL, 0x0);
246 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], VSCALE_CTRL, 0x0);
248 /* set Bypass input format to NTSC 525 lines */
249 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp);
251 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value);
253 mutex_unlock(&dev->lock);
258 static int medusa_PALCombInit(struct cx25821_dev *dev, int dec)
261 u32 value = 0, tmp = 0;
263 /* Setup for 2D threshold */
265 cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_HFS_CFG + (0x200 * dec),
268 cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_HFD_CFG + (0x200 * dec),
271 cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_LF_CFG + (0x200 * dec),
274 /* Setup flat chroma and luma thresholds */
276 cx25821_i2c_read(&dev->i2c_bus[0],
277 COMB_FLAT_THRESH_CTRL + (0x200 * dec), &tmp);
280 cx25821_i2c_write(&dev->i2c_bus[0],
281 COMB_FLAT_THRESH_CTRL + (0x200 * dec), value);
283 /* set comb 2D blend */
285 cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_BLEND + (0x200 * dec),
288 /* COMB MISC CONTROL */
290 cx25821_i2c_write(&dev->i2c_bus[0], COMB_MISC_CTRL + (0x200 * dec),
296 static int medusa_initialize_pal(struct cx25821_dev *dev)
303 mutex_lock(&dev->lock);
305 for (i = 0; i < MAX_DECODERS; i++) {
306 /* set video format PAL-BDGHI */
308 cx25821_i2c_read(&dev->i2c_bus[0], MODE_CTRL + (0x200 * i),
311 /* enable the fast locking mode bit[16] */
314 cx25821_i2c_write(&dev->i2c_bus[0], MODE_CTRL + (0x200 * i),
317 /* resolution PAL 720x576 */
319 cx25821_i2c_read(&dev->i2c_bus[0],
320 HORIZ_TIM_CTRL + (0x200 * i), &tmp);
324 cx25821_i2c_write(&dev->i2c_bus[0],
325 HORIZ_TIM_CTRL + (0x200 * i), value);
327 /* vblank656_cnt=x26, vactive_cnt=240h, vblank_cnt=x24 */
329 cx25821_i2c_read(&dev->i2c_bus[0],
330 VERT_TIM_CTRL + (0x200 * i), &tmp);
332 value |= 0x28240026; /* vblank_cnt + 2 to get camera ID */
334 cx25821_i2c_write(&dev->i2c_bus[0],
335 VERT_TIM_CTRL + (0x200 * i), value);
337 /* chroma subcarrier step size */
339 cx25821_i2c_write(&dev->i2c_bus[0],
340 SC_STEP_SIZE + (0x200 * i), 0x5411E2D0);
342 /* enable VIP optional active */
344 cx25821_i2c_read(&dev->i2c_bus[0],
345 OUT_CTRL_NS + (0x200 * i), &tmp);
349 cx25821_i2c_write(&dev->i2c_bus[0],
350 OUT_CTRL_NS + (0x200 * i), value);
352 /* enable VIP optional active (VIP_OPT_AL) for direct output. */
354 cx25821_i2c_read(&dev->i2c_bus[0], OUT_CTRL1 + (0x200 * i),
359 cx25821_i2c_write(&dev->i2c_bus[0], OUT_CTRL1 + (0x200 * i),
363 * clear VPRES_VERT_EN bit, fixes the chroma run away problem
364 * when the input switching rate < 16 fields
367 cx25821_i2c_read(&dev->i2c_bus[0],
368 MISC_TIM_CTRL + (0x200 * i), &tmp);
369 /* disable special play detection */
370 value = setBitAtPos(value, 14);
371 value = clearBitAtPos(value, 15);
373 cx25821_i2c_write(&dev->i2c_bus[0],
374 MISC_TIM_CTRL + (0x200 * i), value);
376 /* set vbi_gate_en to 0 */
378 cx25821_i2c_read(&dev->i2c_bus[0], DFE_CTRL1 + (0x200 * i),
380 value = clearBitAtPos(value, 29);
382 cx25821_i2c_write(&dev->i2c_bus[0], DFE_CTRL1 + (0x200 * i),
385 medusa_PALCombInit(dev, i);
387 /* Enable the generation of blue field output if no video */
388 medusa_enable_bluefield_output(dev, i, 1);
391 for (i = 0; i < MAX_ENCODERS; i++) {
394 cx25821_i2c_read(&dev->i2c_bus[0],
395 DENC_A_REG_1 + (0x100 * i), &tmp);
399 cx25821_i2c_write(&dev->i2c_bus[0],
400 DENC_A_REG_1 + (0x100 * i), value);
402 /* burst begin and burst end */
404 cx25821_i2c_read(&dev->i2c_bus[0],
405 DENC_A_REG_2 + (0x100 * i), &tmp);
409 cx25821_i2c_write(&dev->i2c_bus[0],
410 DENC_A_REG_2 + (0x100 * i), value);
412 /* hblank and vactive */
414 cx25821_i2c_read(&dev->i2c_bus[0],
415 DENC_A_REG_3 + (0x100 * i), &tmp);
419 cx25821_i2c_write(&dev->i2c_bus[0],
420 DENC_A_REG_3 + (0x100 * i), value);
422 /* set PAL vblank, phase alternation, 0 IRE pedestal */
424 cx25821_i2c_read(&dev->i2c_bus[0],
425 DENC_A_REG_4 + (0x100 * i), &tmp);
429 cx25821_i2c_write(&dev->i2c_bus[0],
430 DENC_A_REG_4 + (0x100 * i), value);
433 cx25821_i2c_read(&dev->i2c_bus[0],
434 DENC_A_REG_5 + (0x100 * i), &tmp);
438 cx25821_i2c_write(&dev->i2c_bus[0],
439 DENC_A_REG_5 + (0x100 * i), value);
442 cx25821_i2c_write(&dev->i2c_bus[0],
443 DENC_A_REG_6 + (0x100 * i), 0x00A493CF);
445 /* Subcarrier Increment */
447 cx25821_i2c_write(&dev->i2c_bus[0],
448 DENC_A_REG_7 + (0x100 * i), 0x2A098ACB);
451 /* set picture resolutions */
453 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], HSCALE_CTRL, 0x0);
455 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], VSCALE_CTRL, 0x0);
457 /* set Bypass input format to PAL 625 lines */
458 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp);
460 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value);
462 mutex_unlock(&dev->lock);
467 int medusa_set_videostandard(struct cx25821_dev *dev)
469 int status = STATUS_SUCCESS;
470 u32 value = 0, tmp = 0;
472 if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK)
473 status = medusa_initialize_pal(dev);
475 status = medusa_initialize_ntsc(dev);
477 /* Enable DENC_A output */
478 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_A_REG_4, &tmp);
479 value = setBitAtPos(value, 4);
480 status = cx25821_i2c_write(&dev->i2c_bus[0], DENC_A_REG_4, value);
482 /* Enable DENC_B output */
483 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_B_REG_4, &tmp);
484 value = setBitAtPos(value, 4);
485 status = cx25821_i2c_write(&dev->i2c_bus[0], DENC_B_REG_4, value);
490 void medusa_set_resolution(struct cx25821_dev *dev, int width,
494 int decoder_count = 0;
498 const int MAX_WIDTH = 720;
500 mutex_lock(&dev->lock);
502 /* validate the width - cannot be negative */
503 if (width > MAX_WIDTH) {
504 pr_info("%s(): width %d > MAX_WIDTH %d ! resetting to MAX_WIDTH\n",
505 __func__, width, MAX_WIDTH);
509 if (decoder_select <= 7 && decoder_select >= 0) {
510 decoder = decoder_select;
511 decoder_count = decoder_select + 1;
514 decoder_count = _num_decoders;
544 for (; decoder < decoder_count; decoder++) {
545 /* write scaling values for each decoder */
547 cx25821_i2c_write(&dev->i2c_bus[0],
548 HSCALE_CTRL + (0x200 * decoder), hscale);
550 cx25821_i2c_write(&dev->i2c_bus[0],
551 VSCALE_CTRL + (0x200 * decoder), vscale);
554 mutex_unlock(&dev->lock);
557 static void medusa_set_decoderduration(struct cx25821_dev *dev, int decoder,
563 u32 disp_cnt_reg = DISP_AB_CNT;
565 mutex_lock(&dev->lock);
568 if (decoder < VDEC_A && decoder > VDEC_H) {
569 mutex_unlock(&dev->lock);
578 disp_cnt_reg = DISP_CD_CNT;
582 disp_cnt_reg = DISP_EF_CNT;
586 disp_cnt_reg = DISP_GH_CNT;
590 _display_field_cnt[decoder] = duration;
592 /* update hardware */
593 fld_cnt = cx25821_i2c_read(&dev->i2c_bus[0], disp_cnt_reg, &tmp);
595 if (!(decoder % 2)) { /* EVEN decoder */
596 fld_cnt &= 0xFFFF0000;
599 fld_cnt &= 0x0000FFFF;
600 fld_cnt |= ((u32) duration) << 16;
603 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], disp_cnt_reg, fld_cnt);
605 mutex_unlock(&dev->lock);
608 /* Map to Medusa register setting */
609 static int mapM(int srcMin,
610 int srcMax, int srcVal, int dstMin, int dstMax, int *dstVal)
616 if ((srcMin == srcMax) || (srcVal < srcMin) || (srcVal > srcMax))
619 * This is the overall expression used:
621 * (srcVal - srcMin)*(dstMax - dstMin) / (srcMax - srcMin) + dstMin;
622 * but we need to account for rounding so below we use the modulus
623 * operator to find the remainder and increment if necessary.
625 numerator = (srcVal - srcMin) * (dstMax - dstMin);
626 denominator = srcMax - srcMin;
627 quotient = numerator / denominator;
629 if (2 * (numerator % denominator) >= denominator)
632 *dstVal = quotient + dstMin;
637 static unsigned long convert_to_twos(long numeric, unsigned long bits_len)
644 temp = ~(abs(numeric) & 0xFF);
650 int medusa_set_brightness(struct cx25821_dev *dev, int brightness, int decoder)
654 u32 val = 0, tmp = 0;
656 mutex_lock(&dev->lock);
657 if ((brightness > VIDEO_PROCAMP_MAX)
658 || (brightness < VIDEO_PROCAMP_MIN)) {
659 mutex_unlock(&dev->lock);
663 mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, brightness,
664 SIGNED_BYTE_MIN, SIGNED_BYTE_MAX, &value);
665 value = convert_to_twos(value, 8);
667 cx25821_i2c_read(&dev->i2c_bus[0],
668 VDEC_A_BRITE_CTRL + (0x200 * decoder), &tmp);
671 cx25821_i2c_write(&dev->i2c_bus[0],
672 VDEC_A_BRITE_CTRL + (0x200 * decoder),
674 mutex_unlock(&dev->lock);
678 int medusa_set_contrast(struct cx25821_dev *dev, int contrast, int decoder)
682 u32 val = 0, tmp = 0;
684 mutex_lock(&dev->lock);
686 if ((contrast > VIDEO_PROCAMP_MAX) || (contrast < VIDEO_PROCAMP_MIN)) {
687 mutex_unlock(&dev->lock);
692 mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, contrast,
693 UNSIGNED_BYTE_MIN, UNSIGNED_BYTE_MAX, &value);
695 cx25821_i2c_read(&dev->i2c_bus[0],
696 VDEC_A_CNTRST_CTRL + (0x200 * decoder), &tmp);
699 cx25821_i2c_write(&dev->i2c_bus[0],
700 VDEC_A_CNTRST_CTRL + (0x200 * decoder),
703 mutex_unlock(&dev->lock);
707 int medusa_set_hue(struct cx25821_dev *dev, int hue, int decoder)
711 u32 val = 0, tmp = 0;
713 mutex_lock(&dev->lock);
715 if ((hue > VIDEO_PROCAMP_MAX) || (hue < VIDEO_PROCAMP_MIN)) {
716 mutex_unlock(&dev->lock);
721 mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, hue, SIGNED_BYTE_MIN,
722 SIGNED_BYTE_MAX, &value);
724 value = convert_to_twos(value, 8);
726 cx25821_i2c_read(&dev->i2c_bus[0],
727 VDEC_A_HUE_CTRL + (0x200 * decoder), &tmp);
731 cx25821_i2c_write(&dev->i2c_bus[0],
732 VDEC_A_HUE_CTRL + (0x200 * decoder), val | value);
734 mutex_unlock(&dev->lock);
738 int medusa_set_saturation(struct cx25821_dev *dev, int saturation, int decoder)
742 u32 val = 0, tmp = 0;
744 mutex_lock(&dev->lock);
746 if ((saturation > VIDEO_PROCAMP_MAX)
747 || (saturation < VIDEO_PROCAMP_MIN)) {
748 mutex_unlock(&dev->lock);
753 mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, saturation,
754 UNSIGNED_BYTE_MIN, UNSIGNED_BYTE_MAX, &value);
757 cx25821_i2c_read(&dev->i2c_bus[0],
758 VDEC_A_USAT_CTRL + (0x200 * decoder), &tmp);
761 cx25821_i2c_write(&dev->i2c_bus[0],
762 VDEC_A_USAT_CTRL + (0x200 * decoder),
766 cx25821_i2c_read(&dev->i2c_bus[0],
767 VDEC_A_VSAT_CTRL + (0x200 * decoder), &tmp);
770 cx25821_i2c_write(&dev->i2c_bus[0],
771 VDEC_A_VSAT_CTRL + (0x200 * decoder),
774 mutex_unlock(&dev->lock);
778 /* Program the display sequence and monitor output. */
780 int medusa_video_init(struct cx25821_dev *dev)
782 u32 value = 0, tmp = 0;
786 mutex_lock(&dev->lock);
788 _num_decoders = dev->_max_num_decoders;
790 /* disable Auto source selection on all video decoders */
791 value = cx25821_i2c_read(&dev->i2c_bus[0], MON_A_CTRL, &tmp);
793 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MON_A_CTRL, value);
798 /* Turn off Master source switch enable */
799 value = cx25821_i2c_read(&dev->i2c_bus[0], MON_A_CTRL, &tmp);
801 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MON_A_CTRL, value);
806 mutex_unlock(&dev->lock);
808 for (i = 0; i < _num_decoders; i++)
809 medusa_set_decoderduration(dev, i, _display_field_cnt[i]);
811 mutex_lock(&dev->lock);
813 /* Select monitor as DENC A input, power up the DAC */
814 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_AB_CTRL, &tmp);
816 value |= 0x00090008; /* set en_active */
817 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], DENC_AB_CTRL, value);
822 /* enable input is VIP/656 */
823 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp);
824 value |= 0x00040100; /* enable VIP */
825 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value);
830 /* select AFE clock to output mode */
831 value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp);
834 cx25821_i2c_write(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL,
840 /* Turn on all of the data out and control output pins. */
841 value = cx25821_i2c_read(&dev->i2c_bus[0], PIN_OE_CTRL, &tmp);
843 if (_num_decoders == MAX_DECODERS) {
845 * Note: The octal board does not support control pins(bit16-19)
846 * These bits are ignored in the octal board.
848 * disable VDEC A-C port, default to Mobilygen Interface
852 /* disable VDEC A-C port, default to Mobilygen Interface */
857 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], PIN_OE_CTRL, value);
863 mutex_unlock(&dev->lock);
865 ret_val = medusa_set_videostandard(dev);
870 mutex_unlock(&dev->lock);