drivers/media/video/cx231xx/cx231xx-avcore.c

   1 /*
   2    cx231xx_avcore.c - driver for Conexant Cx23100/101/102
   3                       USB video capture devices
   4
   5    Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
   6
   7    This program contains the specific code to control the avdecoder chip and
   8    other related usb control functions for cx231xx based chipset.
   9
  10    This program is free software; you can redistribute it and/or modify
  11    it under the terms of the GNU General Public License as published by
  12    the Free Software Foundation; either version 2 of the License, or
  13    (at your option) any later version.
  14
  15    This program is distributed in the hope that it will be useful,
  16    but WITHOUT ANY WARRANTY; without even the implied warranty of
  17    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18    GNU General Public License for more details.
  19
  20    You should have received a copy of the GNU General Public License
  21    along with this program; if not, write to the Free Software
  22    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23  */
  24
  25 #include <linux/init.h>
  26 #include <linux/list.h>
  27 #include <linux/module.h>
  28 #include <linux/kernel.h>
  29 #include <linux/bitmap.h>
  30 #include <linux/usb.h>
  31 #include <linux/i2c.h>
  32 #include <linux/mm.h>
  33 #include <linux/mutex.h>
  34 #include <media/tuner.h>
  35
  36 #include <media/v4l2-common.h>
  37 #include <media/v4l2-ioctl.h>
  38 #include <media/v4l2-chip-ident.h>
  39
  40 #include "cx231xx.h"
  41 #include "cx231xx-dif.h"
  42
  43 #define TUNER_MODE_FM_RADIO 0
  44 /******************************************************************************
  45                         -: BLOCK ARRANGEMENT :-
  46         I2S block ----------------------|
  47         [I2S audio]                     |
  48                                         |
  49         Analog Front End --> Direct IF -|-> Cx25840 --> Audio
  50         [video & audio]                 |   [Audio]
  51                                         |
  52                                         |-> Cx25840 --> Video
  53                                             [Video]
  54
  55 *******************************************************************************/
  56 /******************************************************************************
  57  *                    VERVE REGISTER                                          *
  58         *                                                                     *
  59  ******************************************************************************/
  60 static int verve_write_byte(struct cx231xx *dev, u8 saddr, u8 data)
  61 {
  62         return cx231xx_write_i2c_data(dev, VERVE_I2C_ADDRESS,
  63                                         saddr, 1, data, 1);
  64 }
  65
  66 static int verve_read_byte(struct cx231xx *dev, u8 saddr, u8 *data)
  67 {
  68         int status;
  69         u32 temp = 0;
  70
  71         status = cx231xx_read_i2c_data(dev, VERVE_I2C_ADDRESS,
  72                                         saddr, 1, &temp, 1);
  73         *data = (u8) temp;
  74         return status;
  75 }
  76 void initGPIO(struct cx231xx *dev)
  77 {
  78         u32 _gpio_direction = 0;
  79         u32 value = 0;
  80         u8 val = 0;
  81
  82         _gpio_direction = _gpio_direction & 0xFC0003FF;
  83         _gpio_direction = _gpio_direction | 0x03FDFC00;
  84         cx231xx_send_gpio_cmd(dev, _gpio_direction, (u8 *)&value, 4, 0, 0);
  85
  86         verve_read_byte(dev, 0x07, &val);
  87         cx231xx_info(" verve_read_byte address0x07=0x%x\n", val);
  88         verve_write_byte(dev, 0x07, 0xF4);
  89         verve_read_byte(dev, 0x07, &val);
  90         cx231xx_info(" verve_read_byte address0x07=0x%x\n", val);
  91
  92         cx231xx_capture_start(dev, 1, 2);
  93
  94         cx231xx_mode_register(dev, EP_MODE_SET, 0x0500FE00);
  95         cx231xx_mode_register(dev, GBULK_BIT_EN, 0xFFFDFFFF);
  96
  97 }
  98 void uninitGPIO(struct cx231xx *dev)
  99 {
 100         u8 value[4] = { 0, 0, 0, 0 };
 101
 102         cx231xx_capture_start(dev, 0, 2);
 103         verve_write_byte(dev, 0x07, 0x14);
 104         cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
 105                         0x68, value, 4);
 106 }
 107
 108 /******************************************************************************
 109  *                    A F E - B L O C K    C O N T R O L   functions          *
 110  *                              [ANALOG FRONT END]                            *
 111  ******************************************************************************/
 112 static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
 113 {
 114         return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS,
 115                                         saddr, 2, data, 1);
 116 }
 117
 118 static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
 119 {
 120         int status;
 121         u32 temp = 0;
 122
 123         status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS,
 124                                         saddr, 2, &temp, 1);
 125         *data = (u8) temp;
 126         return status;
 127 }
 128
 129 int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count)
 130 {
 131         int status = 0;
 132         u8 temp = 0;
 133         u8 afe_power_status = 0;
 134         int i = 0;
 135
 136         /* super block initialize */
 137         temp = (u8) (ref_count & 0xff);
 138         status = afe_write_byte(dev, SUP_BLK_TUNE2, temp);
 139         if (status < 0)
 140                 return status;
 141
 142         status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status);
 143         if (status < 0)
 144                 return status;
 145
 146         temp = (u8) ((ref_count & 0x300) >> 8);
 147         temp |= 0x40;
 148         status = afe_write_byte(dev, SUP_BLK_TUNE1, temp);
 149         if (status < 0)
 150                 return status;
 151
 152         status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f);
 153         if (status < 0)
 154                 return status;
 155
 156         /* enable pll     */
 157         while (afe_power_status != 0x18) {
 158                 status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18);
 159                 if (status < 0) {
 160                         cx231xx_info(
 161                         ": Init Super Block failed in send cmd\n");
 162                         break;
 163                 }
 164
 165                 status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status);
 166                 afe_power_status &= 0xff;
 167                 if (status < 0) {
 168                         cx231xx_info(
 169                         ": Init Super Block failed in receive cmd\n");
 170                         break;
 171                 }
 172                 i++;
 173                 if (i == 10) {
 174                         cx231xx_info(
 175                         ": Init Super Block force break in loop !!!!\n");
 176                         status = -1;
 177                         break;
 178                 }
 179         }
 180
 181         if (status < 0)
 182                 return status;
 183
 184         /* start tuning filter */
 185         status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40);
 186         if (status < 0)
 187                 return status;
 188
 189         msleep(5);
 190
 191         /* exit tuning */
 192         status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00);
 193
 194         return status;
 195 }
 196
 197 int cx231xx_afe_init_channels(struct cx231xx *dev)
 198 {
 199         int status = 0;
 200
 201         /* power up all 3 channels, clear pd_buffer */
 202         status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00);
 203         status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00);
 204         status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00);
 205
 206         /* Enable quantizer calibration */
 207         status = afe_write_byte(dev, ADC_COM_QUANT, 0x02);
 208
 209         /* channel initialize, force modulator (fb) reset */
 210         status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17);
 211         status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17);
 212         status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17);
 213
 214         /* start quantilizer calibration  */
 215         status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10);
 216         status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10);
 217         status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10);
 218         msleep(5);
 219
 220         /* exit modulator (fb) reset */
 221         status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07);
 222         status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07);
 223         status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07);
 224
 225         /* enable the pre_clamp in each channel for single-ended input */
 226         status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0);
 227         status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0);
 228         status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0);
 229
 230         /* use diode instead of resistor, so set term_en to 0, res_en to 0  */
 231         status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
 232                                    ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00);
 233         status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
 234                                    ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00);
 235         status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
 236                                    ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00);
 237
 238         /* dynamic element matching off */
 239         status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03);
 240         status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03);
 241         status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03);
 242
 243         return status;
 244 }
 245
 246 int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev)
 247 {
 248         u8 c_value = 0;
 249         int status = 0;
 250
 251         status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value);
 252         c_value &= (~(0x50));
 253         status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value);
 254
 255         return status;
 256 }
 257
 258 /*
 259         The Analog Front End in Cx231xx has 3 channels. These
 260         channels are used to share between different inputs
 261         like tuner, s-video and composite inputs.
 262
 263         channel 1 ----- pin 1  to pin4(in reg is 1-4)
 264         channel 2 ----- pin 5  to pin8(in reg is 5-8)
 265         channel 3 ----- pin 9 to pin 12(in reg is 9-11)
 266 */
 267 int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux)
 268 {
 269         u8 ch1_setting = (u8) input_mux;
 270         u8 ch2_setting = (u8) (input_mux >> 8);
 271         u8 ch3_setting = (u8) (input_mux >> 16);
 272         int status = 0;
 273         u8 value = 0;
 274
 275         if (ch1_setting != 0) {
 276                 status = afe_read_byte(dev, ADC_INPUT_CH1, &value);
 277                 value &= (!INPUT_SEL_MASK);
 278                 value |= (ch1_setting - 1) << 4;
 279                 value &= 0xff;
 280                 status = afe_write_byte(dev, ADC_INPUT_CH1, value);
 281         }
 282
 283         if (ch2_setting != 0) {
 284                 status = afe_read_byte(dev, ADC_INPUT_CH2, &value);
 285                 value &= (!INPUT_SEL_MASK);
 286                 value |= (ch2_setting - 1) << 4;
 287                 value &= 0xff;
 288                 status = afe_write_byte(dev, ADC_INPUT_CH2, value);
 289         }
 290
 291         /* For ch3_setting, the value to put in the register is
 292            7 less than the input number */
 293         if (ch3_setting != 0) {
 294                 status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
 295                 value &= (!INPUT_SEL_MASK);
 296                 value |= (ch3_setting - 1) << 4;
 297                 value &= 0xff;
 298                 status = afe_write_byte(dev, ADC_INPUT_CH3, value);
 299         }
 300
 301         return status;
 302 }
 303
 304 int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
 305 {
 306         int status = 0;
 307
 308         /*
 309         * FIXME: We need to implement the AFE code for LOW IF and for HI IF.
 310         * Currently, only baseband works.
 311         */
 312
 313         switch (mode) {
 314         case AFE_MODE_LOW_IF:
 315                 cx231xx_Setup_AFE_for_LowIF(dev);
 316                 break;
 317         case AFE_MODE_BASEBAND:
 318                 status = cx231xx_afe_setup_AFE_for_baseband(dev);
 319                 break;
 320         case AFE_MODE_EU_HI_IF:
 321                 /* SetupAFEforEuHiIF(); */
 322                 break;
 323         case AFE_MODE_US_HI_IF:
 324                 /* SetupAFEforUsHiIF(); */
 325                 break;
 326         case AFE_MODE_JAPAN_HI_IF:
 327                 /* SetupAFEforJapanHiIF(); */
 328                 break;
 329         }
 330
 331         if ((mode != dev->afe_mode) &&
 332                 (dev->video_input == CX231XX_VMUX_TELEVISION))
 333                 status = cx231xx_afe_adjust_ref_count(dev,
 334                                                      CX231XX_VMUX_TELEVISION);
 335
 336         dev->afe_mode = mode;
 337
 338         return status;
 339 }
 340
 341 int cx231xx_afe_update_power_control(struct cx231xx *dev,
 342                                         enum AV_MODE avmode)
 343 {
 344         u8 afe_power_status = 0;
 345         int status = 0;
 346
 347         switch (dev->model) {
 348         case CX231XX_BOARD_CNXT_CARRAERA:
 349         case CX231XX_BOARD_CNXT_RDE_250:
 350         case CX231XX_BOARD_CNXT_SHELBY:
 351         case CX231XX_BOARD_CNXT_RDU_250:
 352         case CX231XX_BOARD_CNXT_RDE_253S:
 353         case CX231XX_BOARD_CNXT_RDU_253S:
 354         case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
 355                 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
 356                         while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
 357                                                 FLD_PWRDN_ENABLE_PLL)) {
 358                                 status = afe_write_byte(dev, SUP_BLK_PWRDN,
 359                                                         FLD_PWRDN_TUNING_BIAS |
 360                                                         FLD_PWRDN_ENABLE_PLL);
 361                                 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
 362                                                         &afe_power_status);
 363                                 if (status < 0)
 364                                         break;
 365                         }
 366
 367                         status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
 368                                                         0x00);
 369                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
 370                                                         0x00);
 371                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
 372                                                         0x00);
 373                 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
 374                         status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
 375                                                         0x70);
 376                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
 377                                                         0x70);
 378                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
 379                                                         0x70);
 380
 381                         status |= afe_read_byte(dev, SUP_BLK_PWRDN,
 382                                                   &afe_power_status);
 383                         afe_power_status |= FLD_PWRDN_PD_BANDGAP |
 384                                                 FLD_PWRDN_PD_BIAS |
 385                                                 FLD_PWRDN_PD_TUNECK;
 386                         status |= afe_write_byte(dev, SUP_BLK_PWRDN,
 387                                                    afe_power_status);
 388                 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
 389                         while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
 390                                                 FLD_PWRDN_ENABLE_PLL)) {
 391                                 status = afe_write_byte(dev, SUP_BLK_PWRDN,
 392                                                         FLD_PWRDN_TUNING_BIAS |
 393                                                         FLD_PWRDN_ENABLE_PLL);
 394                                 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
 395                                                         &afe_power_status);
 396                                 if (status < 0)
 397                                         break;
 398                         }
 399
 400                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
 401                                                 0x00);
 402                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
 403                                                 0x00);
 404                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
 405                                                 0x00);
 406                 } else {
 407                         cx231xx_info("Invalid AV mode input\n");
 408                         status = -1;
 409                 }
 410                 break;
 411         default:
 412                 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
 413                         while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
 414                                                 FLD_PWRDN_ENABLE_PLL)) {
 415                                 status = afe_write_byte(dev, SUP_BLK_PWRDN,
 416                                                         FLD_PWRDN_TUNING_BIAS |
 417                                                         FLD_PWRDN_ENABLE_PLL);
 418                                 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
 419                                                         &afe_power_status);
 420                                 if (status < 0)
 421                                         break;
 422                         }
 423
 424                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
 425                                                         0x40);
 426                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
 427                                                         0x40);
 428                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
 429                                                         0x00);
 430                 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
 431                         status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
 432                                                         0x70);
 433                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
 434                                                         0x70);
 435                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
 436                                                         0x70);
 437
 438                         status |= afe_read_byte(dev, SUP_BLK_PWRDN,
 439                                                        &afe_power_status);
 440                         afe_power_status |= FLD_PWRDN_PD_BANDGAP |
 441                                                 FLD_PWRDN_PD_BIAS |
 442                                                 FLD_PWRDN_PD_TUNECK;
 443                         status |= afe_write_byte(dev, SUP_BLK_PWRDN,
 444                                                         afe_power_status);
 445                 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
 446                         while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
 447                                                 FLD_PWRDN_ENABLE_PLL)) {
 448                                 status = afe_write_byte(dev, SUP_BLK_PWRDN,
 449                                                         FLD_PWRDN_TUNING_BIAS |
 450                                                         FLD_PWRDN_ENABLE_PLL);
 451                                 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
 452                                                         &afe_power_status);
 453                                 if (status < 0)
 454                                         break;
 455                         }
 456
 457                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
 458                                                         0x00);
 459                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
 460                                                         0x00);
 461                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
 462                                                         0x40);
 463                 } else {
 464                         cx231xx_info("Invalid AV mode input\n");
 465                         status = -1;
 466                 }
 467         }                       /* switch  */
 468
 469         return status;
 470 }
 471
 472 int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input)
 473 {
 474         u8 input_mode = 0;
 475         u8 ntf_mode = 0;
 476         int status = 0;
 477
 478         dev->video_input = video_input;
 479
 480         if (video_input == CX231XX_VMUX_TELEVISION) {
 481                 status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode);
 482                 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3,
 483                                         &ntf_mode);
 484         } else {
 485                 status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode);
 486                 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1,
 487                                         &ntf_mode);
 488         }
 489
 490         input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1);
 491
 492         switch (input_mode) {
 493         case SINGLE_ENDED:
 494                 dev->afe_ref_count = 0x23C;
 495                 break;
 496         case LOW_IF:
 497                 dev->afe_ref_count = 0x24C;
 498                 break;
 499         case EU_IF:
 500                 dev->afe_ref_count = 0x258;
 501                 break;
 502         case US_IF:
 503                 dev->afe_ref_count = 0x260;
 504                 break;
 505         default:
 506                 break;
 507         }
 508
 509         status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count);
 510
 511         return status;
 512 }
 513
 514 /******************************************************************************
 515  *     V I D E O / A U D I O    D E C O D E R    C O N T R O L   functions    *
 516  ******************************************************************************/
 517 static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
 518 {
 519         return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
 520                                         saddr, 2, data, 1);
 521 }
 522
 523 static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
 524 {
 525         int status;
 526         u32 temp = 0;
 527
 528         status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
 529                                         saddr, 2, &temp, 1);
 530         *data = (u8) temp;
 531         return status;
 532 }
 533
 534 static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data)
 535 {
 536         return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
 537                                         saddr, 2, data, 4);
 538 }
 539
 540 static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data)
 541 {
 542         return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
 543                                         saddr, 2, data, 4);
 544 }
 545 int cx231xx_check_fw(struct cx231xx *dev)
 546 {
 547         u8 temp = 0;
 548         int status = 0;
 549         status = vid_blk_read_byte(dev, DL_CTL_ADDRESS_LOW, &temp);
 550         if (status < 0)
 551                 return status;
 552         else
 553                 return temp;
 554
 555 }
 556
 557 int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input)
 558 {
 559         int status = 0;
 560
 561         switch (INPUT(input)->type) {
 562         case CX231XX_VMUX_COMPOSITE1:
 563         case CX231XX_VMUX_SVIDEO:
 564                 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
 565                     (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) {
 566                         /* External AV */
 567                         status = cx231xx_set_power_mode(dev,
 568                                         POLARIS_AVMODE_ENXTERNAL_AV);
 569                         if (status < 0) {
 570                                 cx231xx_errdev("%s: set_power_mode : Failed to"
 571                                                 " set Power - errCode [%d]!\n",
 572                                                 __func__, status);
 573                                 return status;
 574                         }
 575                 }
 576                 status = cx231xx_set_decoder_video_input(dev,
 577                                                          INPUT(input)->type,
 578                                                          INPUT(input)->vmux);
 579                 break;
 580         case CX231XX_VMUX_TELEVISION:
 581         case CX231XX_VMUX_CABLE:
 582                 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
 583                     (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) {
 584                         /* Tuner */
 585                         status = cx231xx_set_power_mode(dev,
 586                                                 POLARIS_AVMODE_ANALOGT_TV);
 587                         if (status < 0) {
 588                                 cx231xx_errdev("%s: set_power_mode:Failed"
 589                                         " to set Power - errCode [%d]!\n",
 590                                         __func__, status);
 591                                 return status;
 592                         }
 593                 }
 594                 if (dev->tuner_type == TUNER_NXP_TDA18271)
 595                         status = cx231xx_set_decoder_video_input(dev,
 596                                                         CX231XX_VMUX_TELEVISION,
 597                                                         INPUT(input)->vmux);
 598                 else
 599                         status = cx231xx_set_decoder_video_input(dev,
 600                                                         CX231XX_VMUX_COMPOSITE1,
 601                                                         INPUT(input)->vmux);
 602
 603                 break;
 604         default:
 605                 cx231xx_errdev("%s: set_power_mode : Unknown Input %d !\n",
 606                      __func__, INPUT(input)->type);
 607                 break;
 608         }
 609
 610         /* save the selection */
 611         dev->video_input = input;
 612
 613         return status;
 614 }
 615
 616 int cx231xx_set_decoder_video_input(struct cx231xx *dev,
 617                                 u8 pin_type, u8 input)
 618 {
 619         int status = 0;
 620         u32 value = 0;
 621
 622         if (pin_type != dev->video_input) {
 623                 status = cx231xx_afe_adjust_ref_count(dev, pin_type);
 624                 if (status < 0) {
 625                         cx231xx_errdev("%s: adjust_ref_count :Failed to set"
 626                                 "AFE input mux - errCode [%d]!\n",
 627                                 __func__, status);
 628                         return status;
 629                 }
 630         }
 631
 632         /* call afe block to set video inputs */
 633         status = cx231xx_afe_set_input_mux(dev, input);
 634         if (status < 0) {
 635                 cx231xx_errdev("%s: set_input_mux :Failed to set"
 636                                 " AFE input mux - errCode [%d]!\n",
 637                                 __func__, status);
 638                 return status;
 639         }
 640
 641         switch (pin_type) {
 642         case CX231XX_VMUX_COMPOSITE1:
 643                 status = vid_blk_read_word(dev, AFE_CTRL, &value);
 644                 value |= (0 << 13) | (1 << 4);
 645                 value &= ~(1 << 5);
 646
 647                 /* set [24:23] [22:15] to 0  */
 648                 value &= (~(0x1ff8000));
 649                 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0  */
 650                 value |= 0x1000000;
 651                 status = vid_blk_write_word(dev, AFE_CTRL, value);
 652
 653                 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
 654                 value |= (1 << 7);
 655                 status = vid_blk_write_word(dev, OUT_CTRL1, value);
 656
 657                 /* Set vip 1.1 output mode */
 658                 status = cx231xx_read_modify_write_i2c_dword(dev,
 659                                                         VID_BLK_I2C_ADDRESS,
 660                                                         OUT_CTRL1,
 661                                                         FLD_OUT_MODE,
 662                                                         OUT_MODE_VIP11);
 663
 664                 /* Tell DIF object to go to baseband mode  */
 665                 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
 666                 if (status < 0) {
 667                         cx231xx_errdev("%s: cx231xx_dif set to By pass"
 668                                                    " mode- errCode [%d]!\n",
 669                                 __func__, status);
 670                         return status;
 671                 }
 672
 673                 /* Read the DFE_CTRL1 register */
 674                 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
 675
 676                 /* enable the VBI_GATE_EN */
 677                 value |= FLD_VBI_GATE_EN;
 678
 679                 /* Enable the auto-VGA enable */
 680                 value |= FLD_VGA_AUTO_EN;
 681
 682                 /* Write it back */
 683                 status = vid_blk_write_word(dev, DFE_CTRL1, value);
 684
 685                 /* Disable auto config of registers */
 686                 status = cx231xx_read_modify_write_i2c_dword(dev,
 687                                         VID_BLK_I2C_ADDRESS,
 688                                         MODE_CTRL, FLD_ACFG_DIS,
 689                                         cx231xx_set_field(FLD_ACFG_DIS, 1));
 690
 691                 /* Set CVBS input mode */
 692                 status = cx231xx_read_modify_write_i2c_dword(dev,
 693                         VID_BLK_I2C_ADDRESS,
 694                         MODE_CTRL, FLD_INPUT_MODE,
 695                         cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0));
 696                 break;
 697         case CX231XX_VMUX_SVIDEO:
 698                 /* Disable the use of  DIF */
 699
 700                 status = vid_blk_read_word(dev, AFE_CTRL, &value);
 701
 702                 /* set [24:23] [22:15] to 0 */
 703                 value &= (~(0x1ff8000));
 704                 /* set FUNC_MODE[24:23] = 2
 705                 IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */
 706                 value |= 0x1000010;
 707                 status = vid_blk_write_word(dev, AFE_CTRL, value);
 708
 709                 /* Tell DIF object to go to baseband mode */
 710                 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
 711                 if (status < 0) {
 712                         cx231xx_errdev("%s: cx231xx_dif set to By pass"
 713                                                    " mode- errCode [%d]!\n",
 714                                 __func__, status);
 715                         return status;
 716                 }
 717
 718                 /* Read the DFE_CTRL1 register */
 719                 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
 720
 721                 /* enable the VBI_GATE_EN */
 722                 value |= FLD_VBI_GATE_EN;
 723
 724                 /* Enable the auto-VGA enable */
 725                 value |= FLD_VGA_AUTO_EN;
 726
 727                 /* Write it back */
 728                 status = vid_blk_write_word(dev, DFE_CTRL1, value);
 729
 730                 /* Disable auto config of registers  */
 731                 status =  cx231xx_read_modify_write_i2c_dword(dev,
 732                                         VID_BLK_I2C_ADDRESS,
 733                                         MODE_CTRL, FLD_ACFG_DIS,
 734                                         cx231xx_set_field(FLD_ACFG_DIS, 1));
 735
 736                 /* Set YC input mode */
 737                 status = cx231xx_read_modify_write_i2c_dword(dev,
 738                         VID_BLK_I2C_ADDRESS,
 739                         MODE_CTRL,
 740                         FLD_INPUT_MODE,
 741                         cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1));
 742
 743                 /* Chroma to ADC2 */
 744                 status = vid_blk_read_word(dev, AFE_CTRL, &value);
 745                 value |= FLD_CHROMA_IN_SEL;     /* set the chroma in select */
 746
 747                 /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8)
 748                    This sets them to use video
 749                    rather than audio.  Only one of the two will be in use. */
 750                 value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3);
 751
 752                 status = vid_blk_write_word(dev, AFE_CTRL, value);
 753
 754                 status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND);
 755                 break;
 756         case CX231XX_VMUX_TELEVISION:
 757         case CX231XX_VMUX_CABLE:
 758         default:
 759                 switch (dev->model) {
 760                 case CX231XX_BOARD_CNXT_CARRAERA:
 761                 case CX231XX_BOARD_CNXT_RDE_250:
 762                 case CX231XX_BOARD_CNXT_SHELBY:
 763                 case CX231XX_BOARD_CNXT_RDU_250:
 764                         /* Disable the use of  DIF   */
 765
 766                         status = vid_blk_read_word(dev, AFE_CTRL, &value);
 767                         value |= (0 << 13) | (1 << 4);
 768                         value &= ~(1 << 5);
 769
 770                         /* set [24:23] [22:15] to 0 */
 771                         value &= (~(0x1FF8000));
 772                         /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
 773                         value |= 0x1000000;
 774                         status = vid_blk_write_word(dev, AFE_CTRL, value);
 775
 776                         status = vid_blk_read_word(dev, OUT_CTRL1, &value);
 777                         value |= (1 << 7);
 778                         status = vid_blk_write_word(dev, OUT_CTRL1, value);
 779
 780                         /* Set vip 1.1 output mode */
 781                         status = cx231xx_read_modify_write_i2c_dword(dev,
 782                                                         VID_BLK_I2C_ADDRESS,
 783                                                         OUT_CTRL1, FLD_OUT_MODE,
 784                                                         OUT_MODE_VIP11);
 785
 786                         /* Tell DIF object to go to baseband mode */
 787                         status = cx231xx_dif_set_standard(dev,
 788                                                           DIF_USE_BASEBAND);
 789                         if (status < 0) {
 790                                 cx231xx_errdev("%s: cx231xx_dif set to By pass"
 791                                                 " mode- errCode [%d]!\n",
 792                                                 __func__, status);
 793                                 return status;
 794                         }
 795
 796                         /* Read the DFE_CTRL1 register */
 797                         status = vid_blk_read_word(dev, DFE_CTRL1, &value);
 798
 799                         /* enable the VBI_GATE_EN */
 800                         value |= FLD_VBI_GATE_EN;
 801
 802                         /* Enable the auto-VGA enable */
 803                         value |= FLD_VGA_AUTO_EN;
 804
 805                         /* Write it back */
 806                         status = vid_blk_write_word(dev, DFE_CTRL1, value);
 807
 808                         /* Disable auto config of registers */
 809                         status = cx231xx_read_modify_write_i2c_dword(dev,
 810                                         VID_BLK_I2C_ADDRESS,
 811                                         MODE_CTRL, FLD_ACFG_DIS,
 812                                         cx231xx_set_field(FLD_ACFG_DIS, 1));
 813
 814                         /* Set CVBS input mode */
 815                         status = cx231xx_read_modify_write_i2c_dword(dev,
 816                                 VID_BLK_I2C_ADDRESS,
 817                                 MODE_CTRL, FLD_INPUT_MODE,
 818                                 cx231xx_set_field(FLD_INPUT_MODE,
 819                                                 INPUT_MODE_CVBS_0));
 820                         break;
 821                 default:
 822                         /* Enable the DIF for the tuner */
 823
 824                         /* Reinitialize the DIF */
 825                         status = cx231xx_dif_set_standard(dev, dev->norm);
 826                         if (status < 0) {
 827                                 cx231xx_errdev("%s: cx231xx_dif set to By pass"
 828                                                 " mode- errCode [%d]!\n",
 829                                                 __func__, status);
 830                                 return status;
 831                         }
 832
 833                         /* Make sure bypass is cleared */
 834                         status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value);
 835
 836                         /* Clear the bypass bit */
 837                         value &= ~FLD_DIF_DIF_BYPASS;
 838
 839                         /* Enable the use of the DIF block */
 840                         status = vid_blk_write_word(dev, DIF_MISC_CTRL, value);
 841
 842                         /* Read the DFE_CTRL1 register */
 843                         status = vid_blk_read_word(dev, DFE_CTRL1, &value);
 844
 845                         /* Disable the VBI_GATE_EN */
 846                         value &= ~FLD_VBI_GATE_EN;
 847
 848                         /* Enable the auto-VGA enable, AGC, and
 849                            set the skip count to 2 */
 850                         value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000;
 851
 852                         /* Write it back */
 853                         status = vid_blk_write_word(dev, DFE_CTRL1, value);
 854
 855                         /* Wait until AGC locks up */
 856                         msleep(1);
 857
 858                         /* Disable the auto-VGA enable AGC */
 859                         value &= ~(FLD_VGA_AUTO_EN);
 860
 861                         /* Write it back */
 862                         status = vid_blk_write_word(dev, DFE_CTRL1, value);
 863
 864                         /* Enable Polaris B0 AGC output */
 865                         status = vid_blk_read_word(dev, PIN_CTRL, &value);
 866                         value |= (FLD_OEF_AGC_RF) |
 867                                  (FLD_OEF_AGC_IFVGA) |
 868                                  (FLD_OEF_AGC_IF);
 869                         status = vid_blk_write_word(dev, PIN_CTRL, value);
 870
 871                         /* Set vip 1.1 output mode */
 872                         status = cx231xx_read_modify_write_i2c_dword(dev,
 873                                                 VID_BLK_I2C_ADDRESS,
 874                                                 OUT_CTRL1, FLD_OUT_MODE,
 875                                                 OUT_MODE_VIP11);
 876
 877                         /* Disable auto config of registers */
 878                         status = cx231xx_read_modify_write_i2c_dword(dev,
 879                                         VID_BLK_I2C_ADDRESS,
 880                                         MODE_CTRL, FLD_ACFG_DIS,
 881                                         cx231xx_set_field(FLD_ACFG_DIS, 1));
 882
 883                         /* Set CVBS input mode */
 884                         status = cx231xx_read_modify_write_i2c_dword(dev,
 885                                 VID_BLK_I2C_ADDRESS,
 886                                 MODE_CTRL, FLD_INPUT_MODE,
 887                                 cx231xx_set_field(FLD_INPUT_MODE,
 888                                                 INPUT_MODE_CVBS_0));
 889
 890                         /* Set some bits in AFE_CTRL so that channel 2 or 3
 891                          * is ready to receive audio */
 892                         /* Clear clamp for channels 2 and 3      (bit 16-17) */
 893                         /* Clear droop comp                      (bit 19-20) */
 894                         /* Set VGA_SEL (for audio control)       (bit 7-8) */
 895                         status = vid_blk_read_word(dev, AFE_CTRL, &value);
 896
 897                         /*Set Func mode:01-DIF 10-baseband 11-YUV*/
 898                         value &= (~(FLD_FUNC_MODE));
 899                         value |= 0x800000;
 900
 901                         value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2;
 902
 903                         status = vid_blk_write_word(dev, AFE_CTRL, value);
 904
 905                         if (dev->tuner_type == TUNER_NXP_TDA18271) {
 906                                 status = vid_blk_read_word(dev, PIN_CTRL,
 907                                  &value);
 908                                 status = vid_blk_write_word(dev, PIN_CTRL,
 909                                  (value & 0xFFFFFFEF));
 910                         }
 911
 912                         break;
 913
 914                 }
 915                 break;
 916         }
 917
 918         /* Set raw VBI mode */
 919         status = cx231xx_read_modify_write_i2c_dword(dev,
 920                                 VID_BLK_I2C_ADDRESS,
 921                                 OUT_CTRL1, FLD_VBIHACTRAW_EN,
 922                                 cx231xx_set_field(FLD_VBIHACTRAW_EN, 1));
 923
 924         status = vid_blk_read_word(dev, OUT_CTRL1, &value);
 925         if (value & 0x02) {
 926                 value |= (1 << 19);
 927                 status = vid_blk_write_word(dev, OUT_CTRL1, value);
 928         }
 929
 930         return status;
 931 }
 932
 933 void cx231xx_enable656(struct cx231xx *dev)
 934 {
 935         u8 temp = 0;
 936         int status;
 937     /*enable TS1 data[0:7] as output to export 656*/
 938
 939         status = vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF);
 940
 941     /*enable TS1 clock as output to export 656*/
 942
 943         status = vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
 944         temp = temp|0x04;
 945
 946         status = vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
 947
 948 }
 949 EXPORT_SYMBOL_GPL(cx231xx_enable656);
 950
 951 void cx231xx_disable656(struct cx231xx *dev)
 952 {
 953         u8 temp = 0;
 954         int status;
 955
 956
 957         status = vid_blk_write_byte(dev, TS1_PIN_CTL0, 0x00);
 958
 959         status = vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
 960         temp = temp&0xFB;
 961
 962         status = vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
 963 }
 964 EXPORT_SYMBOL_GPL(cx231xx_disable656);
 965
 966 /*
 967  * Handle any video-mode specific overrides that are different
 968  * on a per video standards basis after touching the MODE_CTRL
 969  * register which resets many values for autodetect
 970  */
 971 int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
 972 {
 973         int status = 0;
 974
 975         cx231xx_info("do_mode_ctrl_overrides : 0x%x\n",
 976                      (unsigned int)dev->norm);
 977
 978         /* Change the DFE_CTRL3 bp_percent to fix flagging */
 979         status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280);
 980
 981         if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) {
 982                 cx231xx_info("do_mode_ctrl_overrides NTSC\n");
 983
 984                 /* Move the close caption lines out of active video,
 985                    adjust the active video start point */
 986                 status = cx231xx_read_modify_write_i2c_dword(dev,
 987                                                         VID_BLK_I2C_ADDRESS,
 988                                                         VERT_TIM_CTRL,
 989                                                         FLD_VBLANK_CNT, 0x18);
 990                 status = cx231xx_read_modify_write_i2c_dword(dev,
 991                                                         VID_BLK_I2C_ADDRESS,
 992                                                         VERT_TIM_CTRL,
 993                                                         FLD_VACTIVE_CNT,
 994                                                         0x1E6000);
 995                 status = cx231xx_read_modify_write_i2c_dword(dev,
 996                                                         VID_BLK_I2C_ADDRESS,
 997                                                         VERT_TIM_CTRL,
 998                                                         FLD_V656BLANK_CNT,
 999                                                         0x1C000000);
1000
1001                 status = cx231xx_read_modify_write_i2c_dword(dev,
1002                                                         VID_BLK_I2C_ADDRESS,
1003                                                         HORIZ_TIM_CTRL,
1004                                                         FLD_HBLANK_CNT,
1005                                                         cx231xx_set_field
1006                                                         (FLD_HBLANK_CNT, 0x79));
1007
1008         } else if (dev->norm & V4L2_STD_SECAM) {
1009                 cx231xx_info("do_mode_ctrl_overrides SECAM\n");
1010                 status =  cx231xx_read_modify_write_i2c_dword(dev,
1011                                                         VID_BLK_I2C_ADDRESS,
1012                                                         VERT_TIM_CTRL,
1013                                                         FLD_VBLANK_CNT, 0x24);
1014                 status = cx231xx_read_modify_write_i2c_dword(dev,
1015                                                         VID_BLK_I2C_ADDRESS,
1016                                                         VERT_TIM_CTRL,
1017                                                         FLD_V656BLANK_CNT,
1018                                                         cx231xx_set_field
1019                                                         (FLD_V656BLANK_CNT,
1020                                                         0x28));
1021                 /* Adjust the active video horizontal start point */
1022                 status = cx231xx_read_modify_write_i2c_dword(dev,
1023                                                         VID_BLK_I2C_ADDRESS,
1024                                                         HORIZ_TIM_CTRL,
1025                                                         FLD_HBLANK_CNT,
1026                                                         cx231xx_set_field
1027                                                         (FLD_HBLANK_CNT, 0x85));
1028         } else {
1029                 cx231xx_info("do_mode_ctrl_overrides PAL\n");
1030                 status = cx231xx_read_modify_write_i2c_dword(dev,
1031                                                         VID_BLK_I2C_ADDRESS,
1032                                                         VERT_TIM_CTRL,
1033                                                         FLD_VBLANK_CNT, 0x24);
1034                 status = cx231xx_read_modify_write_i2c_dword(dev,
1035                                                         VID_BLK_I2C_ADDRESS,
1036                                                         VERT_TIM_CTRL,
1037                                                         FLD_V656BLANK_CNT,
1038                                                         cx231xx_set_field
1039                                                         (FLD_V656BLANK_CNT,
1040                                                         0x28));
1041                 /* Adjust the active video horizontal start point */
1042                 status = cx231xx_read_modify_write_i2c_dword(dev,
1043                                                         VID_BLK_I2C_ADDRESS,
1044                                                         HORIZ_TIM_CTRL,
1045                                                         FLD_HBLANK_CNT,
1046                                                         cx231xx_set_field
1047                                                         (FLD_HBLANK_CNT, 0x85));
1048
1049         }
1050
1051         return status;
1052 }
1053
1054 int cx231xx_unmute_audio(struct cx231xx *dev)
1055 {
1056         return vid_blk_write_byte(dev, PATH1_VOL_CTL, 0x24);
1057 }
1058 EXPORT_SYMBOL_GPL(cx231xx_unmute_audio);
1059
1060 int stopAudioFirmware(struct cx231xx *dev)
1061 {
1062         return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x03);
1063 }
1064
1065 int restartAudioFirmware(struct cx231xx *dev)
1066 {
1067         return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x13);
1068 }
1069
1070 int cx231xx_set_audio_input(struct cx231xx *dev, u8 input)
1071 {
1072         int status = 0;
1073         enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE;
1074
1075         switch (INPUT(input)->amux) {
1076         case CX231XX_AMUX_VIDEO:
1077                 ainput = AUDIO_INPUT_TUNER_TV;
1078                 break;
1079         case CX231XX_AMUX_LINE_IN:
1080                 status = cx231xx_i2s_blk_set_audio_input(dev, input);
1081                 ainput = AUDIO_INPUT_LINE;
1082                 break;
1083         default:
1084                 break;
1085         }
1086
1087         status = cx231xx_set_audio_decoder_input(dev, ainput);
1088
1089         return status;
1090 }
1091
1092 int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
1093                                     enum AUDIO_INPUT audio_input)
1094 {
1095         u32 dwval;
1096         int status;
1097         u8 gen_ctrl;
1098         u32 value = 0;
1099
1100         /* Put it in soft reset   */
1101         status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
1102         gen_ctrl |= 1;
1103         status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
1104
1105         switch (audio_input) {
1106         case AUDIO_INPUT_LINE:
1107                 /* setup AUD_IO control from Merlin paralle output */
1108                 value = cx231xx_set_field(FLD_AUD_CHAN1_SRC,
1109                                           AUD_CHAN_SRC_PARALLEL);
1110                 status = vid_blk_write_word(dev, AUD_IO_CTRL, value);
1111
1112                 /* setup input to Merlin, SRC2 connect to AC97
1113                    bypass upsample-by-2, slave mode, sony mode, left justify
1114                    adr 091c, dat 01000000 */
1115                 status = vid_blk_read_word(dev, AC97_CTL, &dwval);
1116
1117                 status = vid_blk_write_word(dev, AC97_CTL,
1118                                            (dwval | FLD_AC97_UP2X_BYPASS));
1119
1120                 /* select the parallel1 and SRC3 */
1121                 status = vid_blk_write_word(dev, BAND_OUT_SEL,
1122                                 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) |
1123                                 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) |
1124                                 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0));
1125
1126                 /* unmute all, AC97 in, independence mode
1127                    adr 08d0, data 0x00063073 */
1128                 status = vid_blk_write_word(dev, DL_CTL, 0x3000001);
1129                 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073);
1130
1131                 /* set AVC maximum threshold, adr 08d4, dat ffff0024 */
1132                 status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval);
1133                 status = vid_blk_write_word(dev, PATH1_VOL_CTL,
1134                                            (dwval | FLD_PATH1_AVC_THRESHOLD));
1135
1136                 /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */
1137                 status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval);
1138                 status = vid_blk_write_word(dev, PATH1_SC_CTL,
1139                                            (dwval | FLD_PATH1_SC_THRESHOLD));
1140                 break;
1141
1142         case AUDIO_INPUT_TUNER_TV:
1143         default:
1144                 status = stopAudioFirmware(dev);
1145                 /* Setup SRC sources and clocks */
1146                 status = vid_blk_write_word(dev, BAND_OUT_SEL,
1147                         cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00)         |
1148                         cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01)        |
1149                         cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00)         |
1150                         cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02)        |
1151                         cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02)         |
1152                         cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03)        |
1153                         cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00)         |
1154                         cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00)        |
1155                         cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) |
1156                         cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03)        |
1157                         cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00)         |
1158                         cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02)   |
1159                         cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01));
1160
1161                 /* Setup the AUD_IO control */
1162                 status = vid_blk_write_word(dev, AUD_IO_CTRL,
1163                         cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00)  |
1164                         cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00)   |
1165                         cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) |
1166                         cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) |
1167                         cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03));
1168
1169                 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870);
1170
1171                 /* setAudioStandard(_audio_standard); */
1172                 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870);
1173
1174                 status = restartAudioFirmware(dev);
1175
1176                 switch (dev->model) {
1177                 case CX231XX_BOARD_CNXT_CARRAERA:
1178                 case CX231XX_BOARD_CNXT_RDE_250:
1179                 case CX231XX_BOARD_CNXT_SHELBY:
1180                 case CX231XX_BOARD_CNXT_RDU_250:
1181                 case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
1182                         status = cx231xx_read_modify_write_i2c_dword(dev,
1183                                         VID_BLK_I2C_ADDRESS,
1184                                         CHIP_CTRL,
1185                                         FLD_SIF_EN,
1186                                         cx231xx_set_field(FLD_SIF_EN, 1));
1187                         break;
1188                 case CX231XX_BOARD_CNXT_RDE_253S:
1189                 case CX231XX_BOARD_CNXT_RDU_253S:
1190                         status = cx231xx_read_modify_write_i2c_dword(dev,
1191                                         VID_BLK_I2C_ADDRESS,
1192                                         CHIP_CTRL,
1193                                         FLD_SIF_EN,
1194                                         cx231xx_set_field(FLD_SIF_EN, 0));
1195                         break;
1196                 default:
1197                         break;
1198                 }
1199                 break;
1200
1201         case AUDIO_INPUT_TUNER_FM:
1202                 /*  use SIF for FM radio
1203                    setupFM();
1204                    setAudioStandard(_audio_standard);
1205                  */
1206                 break;
1207
1208         case AUDIO_INPUT_MUTE:
1209                 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012);
1210                 break;
1211         }
1212
1213         /* Take it out of soft reset */
1214         status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
1215         gen_ctrl &= ~1;
1216         status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
1217
1218         return status;
1219 }
1220
1221 /* Set resolution of the video */
1222 int cx231xx_resolution_set(struct cx231xx *dev)
1223 {
1224         /* set horzontal scale */
1225         int status = vid_blk_write_word(dev, HSCALE_CTRL, dev->hscale);
1226         if (status)
1227                 return status;
1228
1229         /* set vertical scale */
1230         status = vid_blk_write_word(dev, VSCALE_CTRL, dev->vscale);
1231
1232         return status;
1233 }
1234
1235 /******************************************************************************
1236  *                    C H I P Specific  C O N T R O L   functions             *
1237  ******************************************************************************/
1238 int cx231xx_init_ctrl_pin_status(struct cx231xx *dev)
1239 {
1240         u32 value;
1241         int status = 0;
1242
1243         status = vid_blk_read_word(dev, PIN_CTRL, &value);
1244         value |= (~dev->board.ctl_pin_status_mask);
1245         status = vid_blk_write_word(dev, PIN_CTRL, value);
1246
1247         return status;
1248 }
1249
1250 int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev,
1251                                               u8 analog_or_digital)
1252 {
1253         int status = 0;
1254
1255         /* first set the direction to output */
1256         status = cx231xx_set_gpio_direction(dev,
1257                                             dev->board.
1258                                             agc_analog_digital_select_gpio, 1);
1259
1260         /* 0 - demod ; 1 - Analog mode */
1261         status = cx231xx_set_gpio_value(dev,
1262                                    dev->board.agc_analog_digital_select_gpio,
1263                                    analog_or_digital);
1264
1265         return status;
1266 }
1267
1268 int cx231xx_enable_i2c_for_tuner(struct cx231xx *dev, u8 I2CIndex)
1269 {
1270         u8 value[4] = { 0, 0, 0, 0 };
1271         int status = 0;
1272
1273         cx231xx_info("Changing the i2c port for tuner to %d\n", I2CIndex);
1274
1275         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER,
1276                                        PWR_CTL_EN, value, 4);
1277         if (status < 0)
1278                 return status;
1279
1280         if (I2CIndex == I2C_1) {
1281                 if (value[0] & I2C_DEMOD_EN) {
1282                         value[0] &= ~I2C_DEMOD_EN;
1283                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1284                                                    PWR_CTL_EN, value, 4);
1285                 }
1286         } else {
1287                 if (!(value[0] & I2C_DEMOD_EN)) {
1288                         value[0] |= I2C_DEMOD_EN;
1289                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1290                                                    PWR_CTL_EN, value, 4);
1291                 }
1292         }
1293
1294         return status;
1295
1296 }
1297 EXPORT_SYMBOL_GPL(cx231xx_enable_i2c_for_tuner);
1298 void update_HH_register_after_set_DIF(struct cx231xx *dev)
1299 {
1300 /*
1301         u8 status = 0;
1302         u32 value = 0;
1303
1304         vid_blk_write_word(dev, PIN_CTRL, 0xA0FFF82F);
1305         vid_blk_write_word(dev, DIF_MISC_CTRL, 0x0A203F11);
1306         vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0x1BEFBF06);
1307
1308         status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1309         vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
1310         status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL,  &value);
1311 */
1312 }
1313
1314 void cx231xx_dump_HH_reg(struct cx231xx *dev)
1315 {
1316         u8 status = 0;
1317         u32 value = 0;
1318         u16  i = 0;
1319
1320         value = 0x45005390;
1321         status = vid_blk_write_word(dev, 0x104, value);
1322
1323         for (i = 0x100; i < 0x140; i++) {
1324                 status = vid_blk_read_word(dev, i, &value);
1325                 cx231xx_info("reg0x%x=0x%x\n", i, value);
1326                 i = i+3;
1327         }
1328
1329         for (i = 0x300; i < 0x400; i++) {
1330                 status = vid_blk_read_word(dev, i, &value);
1331                 cx231xx_info("reg0x%x=0x%x\n", i, value);
1332                 i = i+3;
1333         }
1334
1335         for (i = 0x400; i < 0x440; i++) {
1336                 status = vid_blk_read_word(dev, i,  &value);
1337                 cx231xx_info("reg0x%x=0x%x\n", i, value);
1338                 i = i+3;
1339         }
1340
1341    status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1342    cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
1343    vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
1344    status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1345    cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
1346
1347 }
1348 void cx231xx_dump_SC_reg(struct cx231xx *dev)
1349 {
1350         u8 value[4] = { 0, 0, 0, 0 };
1351         int status = 0;
1352         cx231xx_info("cx231xx_dump_SC_reg %s!\n", __TIME__);
1353
1354         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT,
1355                                  value, 4);
1356         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", BOARD_CFG_STAT, value[0],
1357                                  value[1], value[2], value[3]);
1358         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS_MODE_REG,
1359                                  value, 4);
1360         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS_MODE_REG, value[0],
1361                                  value[1], value[2], value[3]);
1362         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_CFG_REG,
1363                                  value, 4);
1364         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_CFG_REG, value[0],
1365                                  value[1], value[2], value[3]);
1366         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_LENGTH_REG,
1367                                  value, 4);
1368         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_LENGTH_REG, value[0],
1369                                  value[1], value[2], value[3]);
1370
1371         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_CFG_REG,
1372                                  value, 4);
1373         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_CFG_REG, value[0],
1374                                  value[1], value[2], value[3]);
1375         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_LENGTH_REG,
1376                                  value, 4);
1377         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_LENGTH_REG, value[0],
1378                                  value[1], value[2], value[3]);
1379         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
1380                                  value, 4);
1381         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", EP_MODE_SET, value[0],
1382                                  value[1], value[2], value[3]);
1383         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN1,
1384                                  value, 4);
1385         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN1, value[0],
1386                                  value[1], value[2], value[3]);
1387
1388         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN2,
1389                                  value, 4);
1390         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN2, value[0],
1391                                  value[1], value[2], value[3]);
1392         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN3,
1393                                  value, 4);
1394         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN3, value[0],
1395                                  value[1], value[2], value[3]);
1396         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK0,
1397                                  value, 4);
1398         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK0, value[0],
1399                                  value[1], value[2], value[3]);
1400         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK1,
1401                                  value, 4);
1402         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK1, value[0],
1403                                  value[1], value[2], value[3]);
1404
1405         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK2,
1406                                  value, 4);
1407         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK2, value[0],
1408                                  value[1], value[2], value[3]);
1409         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_GAIN,
1410                                  value, 4);
1411         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_GAIN, value[0],
1412                                  value[1], value[2], value[3]);
1413         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_CAR_REG,
1414                                  value, 4);
1415         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_CAR_REG, value[0],
1416                                  value[1], value[2], value[3]);
1417         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG1,
1418                                  value, 4);
1419         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG1, value[0],
1420                                  value[1], value[2], value[3]);
1421
1422         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG2,
1423                                  value, 4);
1424         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG2, value[0],
1425                                  value[1], value[2], value[3]);
1426         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
1427                                  value, 4);
1428         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN, value[0],
1429                                  value[1], value[2], value[3]);
1430
1431
1432 }
1433
1434 void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev)
1435
1436 {
1437         u8 status = 0;
1438         u8 value = 0;
1439
1440
1441
1442         status = afe_read_byte(dev, ADC_STATUS2_CH3, &value);
1443         value = (value & 0xFE)|0x01;
1444         status = afe_write_byte(dev, ADC_STATUS2_CH3, value);
1445
1446         status = afe_read_byte(dev, ADC_STATUS2_CH3, &value);
1447         value = (value & 0xFE)|0x00;
1448         status = afe_write_byte(dev, ADC_STATUS2_CH3, value);
1449
1450
1451 /*
1452      config colibri to lo-if mode
1453
1454      FIXME: ntf_mode = 2'b00 by default. But set 0x1 would reduce
1455          the diff IF input by half,
1456
1457             for low-if agc defect
1458 */
1459
1460         status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value);
1461         value = (value & 0xFC)|0x00;
1462         status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, value);
1463
1464         status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
1465         value = (value & 0xF9)|0x02;
1466         status = afe_write_byte(dev, ADC_INPUT_CH3, value);
1467
1468         status = afe_read_byte(dev, ADC_FB_FRCRST_CH3, &value);
1469         value = (value & 0xFB)|0x04;
1470         status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, value);
1471
1472         status = afe_read_byte(dev, ADC_DCSERVO_DEM_CH3, &value);
1473         value = (value & 0xFC)|0x03;
1474         status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, value);
1475
1476         status = afe_read_byte(dev, ADC_CTRL_DAC1_CH3, &value);
1477         value = (value & 0xFB)|0x04;
1478         status = afe_write_byte(dev, ADC_CTRL_DAC1_CH3, value);
1479
1480         status = afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
1481         value = (value & 0xF8)|0x06;
1482         status = afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
1483
1484         status = afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
1485         value = (value & 0x8F)|0x40;
1486         status = afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
1487
1488         status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH3, &value);
1489         value = (value & 0xDF)|0x20;
1490         status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, value);
1491 }
1492
1493 void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq,
1494                  u8 spectral_invert, u32 mode)
1495 {
1496
1497     u32 colibri_carrier_offset = 0;
1498     u8 status = 0;
1499     u32 func_mode = 0;
1500     u32 standard = 0;
1501         u8 value[4] = { 0, 0, 0, 0 };
1502
1503         switch (dev->model) {
1504         case CX231XX_BOARD_CNXT_CARRAERA:
1505         case CX231XX_BOARD_CNXT_RDE_250:
1506         case CX231XX_BOARD_CNXT_SHELBY:
1507         case CX231XX_BOARD_CNXT_RDU_250:
1508         case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
1509                 func_mode = 0x03;
1510                 break;
1511         case CX231XX_BOARD_CNXT_RDE_253S:
1512         case CX231XX_BOARD_CNXT_RDU_253S:
1513                 func_mode = 0x01;
1514                 break;
1515
1516         default:
1517                 func_mode = 0x01;
1518         }
1519
1520         cx231xx_info("Enter cx231xx_set_Colibri_For_LowIF()\n");
1521                 value[0] = (u8) 0x6F;
1522                 value[1] = (u8) 0x6F;
1523                 value[2] = (u8) 0x6F;
1524                 value[3] = (u8) 0x6F;
1525                 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1526                                                 PWR_CTL_EN, value, 4);
1527     if (1) {
1528
1529         /*Set colibri for low IF*/
1530         status = cx231xx_afe_set_mode(dev, AFE_MODE_LOW_IF);
1531
1532
1533         /* Set C2HH for low IF operation.*/
1534         standard = dev->norm;
1535         status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1536                                                   func_mode, standard);
1537
1538
1539         /* Get colibri offsets.*/
1540         colibri_carrier_offset = cx231xx_Get_Colibri_CarrierOffset(mode,
1541                                          standard);
1542
1543         cx231xx_info("colibri_carrier_offset=%d, standard=0x%x\n",
1544                                  colibri_carrier_offset, standard);
1545
1546         /* Set the band Pass filter for DIF*/
1547         cx231xx_set_DIF_bandpass(dev, (if_freq+colibri_carrier_offset)
1548                  , spectral_invert, mode);
1549     }
1550 }
1551
1552 u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd)
1553 {
1554     u32 colibri_carrier_offset = 0;
1555
1556
1557     if (mode == TUNER_MODE_FM_RADIO) {
1558                 colibri_carrier_offset = 1100000;
1559         } else if (standerd & (V4L2_STD_NTSC | V4L2_STD_NTSC_M_JP)) {
1560                 colibri_carrier_offset = 4832000;  /*4.83MHz    */
1561         } else if (standerd & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) {
1562                 colibri_carrier_offset = 2700000;  /*2.70MHz       */
1563         } else if (standerd & (V4L2_STD_PAL_D | V4L2_STD_PAL_I
1564                         | V4L2_STD_SECAM)) {
1565                 colibri_carrier_offset = 2100000;  /*2.10MHz    */
1566         }
1567
1568
1569     return colibri_carrier_offset;
1570 }
1571
1572 void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq,
1573                  u8 spectral_invert, u32 mode)
1574 {
1575
1576     unsigned long pll_freq_word;
1577     int status = 0;
1578     u32 dif_misc_ctrl_value = 0;
1579     u64 pll_freq_u64 = 0;
1580     u32 i = 0;
1581
1582
1583         cx231xx_info("if_freq=%d;spectral_invert=0x%x;mode=0x%x\n",
1584                          if_freq, spectral_invert, mode);
1585
1586
1587     if (mode == TUNER_MODE_FM_RADIO) {
1588         pll_freq_word = 0x905A1CAC;
1589         status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD,  pll_freq_word);
1590
1591     } else /*KSPROPERTY_TUNER_MODE_TV*/{
1592        /* Calculate the PLL frequency word based on the adjusted if_freq*/
1593         pll_freq_word = if_freq;
1594         pll_freq_u64 = (u64)pll_freq_word << 28L;
1595         do_div(pll_freq_u64, 50000000);
1596         pll_freq_word = (u32)pll_freq_u64;
1597         /*pll_freq_word = 0x3463497;*/
1598         status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD,  pll_freq_word);
1599
1600     if (spectral_invert) {
1601         if_freq -= 400000;
1602         /* Enable Spectral Invert*/
1603         status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1604                                  &dif_misc_ctrl_value);
1605         dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000;
1606         status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1607                                  dif_misc_ctrl_value);
1608     } else {
1609         if_freq += 400000;
1610         /* Disable Spectral Invert*/
1611         status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1612                                  &dif_misc_ctrl_value);
1613         dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF;
1614         status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1615                                  dif_misc_ctrl_value);
1616     }
1617
1618         if_freq = (if_freq/100000)*100000;
1619
1620     if (if_freq < 3000000)
1621         if_freq = 3000000;
1622
1623     if (if_freq > 16000000)
1624         if_freq = 16000000;
1625     }
1626
1627     cx231xx_info("Enter IF=%d\n",
1628                  sizeof(Dif_set_array)/sizeof(struct dif_settings));
1629     for (i = 0; i < sizeof(Dif_set_array)/sizeof(struct dif_settings); i++) {
1630         if (Dif_set_array[i].if_freq == if_freq) {
1631                 status = vid_blk_write_word(dev,
1632                  Dif_set_array[i].register_address, Dif_set_array[i].value);
1633         }
1634     }
1635
1636 }
1637
1638 /******************************************************************************
1639  *                 D I F - B L O C K    C O N T R O L   functions             *
1640  ******************************************************************************/
1641 int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
1642                                           u32 function_mode, u32 standard)
1643 {
1644         int status = 0;
1645
1646
1647         if (mode == V4L2_TUNER_RADIO) {
1648                 /* C2HH */
1649                 /* lo if big signal */
1650                 status = cx231xx_reg_mask_write(dev,
1651                                 VID_BLK_I2C_ADDRESS, 32,
1652                                 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1653                 /* FUNC_MODE = DIF */
1654                 status = cx231xx_reg_mask_write(dev,
1655                                 VID_BLK_I2C_ADDRESS, 32,
1656                                 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode);
1657                 /* IF_MODE */
1658                 status = cx231xx_reg_mask_write(dev,
1659                                 VID_BLK_I2C_ADDRESS, 32,
1660                                 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF);
1661                 /* no inv */
1662                 status = cx231xx_reg_mask_write(dev,
1663                                 VID_BLK_I2C_ADDRESS, 32,
1664                                 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1665         } else if (standard != DIF_USE_BASEBAND) {
1666                 if (standard & V4L2_STD_MN) {
1667                         /* lo if big signal */
1668                         status = cx231xx_reg_mask_write(dev,
1669                                         VID_BLK_I2C_ADDRESS, 32,
1670                                         AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1671                         /* FUNC_MODE = DIF */
1672                         status = cx231xx_reg_mask_write(dev,
1673                                         VID_BLK_I2C_ADDRESS, 32,
1674                                         AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1675                                         function_mode);
1676                         /* IF_MODE */
1677                         status = cx231xx_reg_mask_write(dev,
1678                                         VID_BLK_I2C_ADDRESS, 32,
1679                                         AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb);
1680                         /* no inv */
1681                         status = cx231xx_reg_mask_write(dev,
1682                                         VID_BLK_I2C_ADDRESS, 32,
1683                                         AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1684                         /* 0x124, AUD_CHAN1_SRC = 0x3 */
1685                         status = cx231xx_reg_mask_write(dev,
1686                                         VID_BLK_I2C_ADDRESS, 32,
1687                                         AUD_IO_CTRL, 0, 31, 0x00000003);
1688                 } else if ((standard == V4L2_STD_PAL_I) |
1689                         (standard & V4L2_STD_PAL_D) |
1690                         (standard & V4L2_STD_SECAM)) {
1691                         /* C2HH setup */
1692                         /* lo if big signal */
1693                         status = cx231xx_reg_mask_write(dev,
1694                                         VID_BLK_I2C_ADDRESS, 32,
1695                                         AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1696                         /* FUNC_MODE = DIF */
1697                         status = cx231xx_reg_mask_write(dev,
1698                                         VID_BLK_I2C_ADDRESS, 32,
1699                                         AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1700                                         function_mode);
1701                         /* IF_MODE */
1702                         status = cx231xx_reg_mask_write(dev,
1703                                         VID_BLK_I2C_ADDRESS, 32,
1704                                         AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF);
1705                         /* no inv */
1706                         status = cx231xx_reg_mask_write(dev,
1707                                         VID_BLK_I2C_ADDRESS, 32,
1708                                         AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1709                 } else {
1710                         /* default PAL BG */
1711                         /* C2HH setup */
1712                         /* lo if big signal */
1713                         status = cx231xx_reg_mask_write(dev,
1714                                         VID_BLK_I2C_ADDRESS, 32,
1715                                         AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1716                         /* FUNC_MODE = DIF */
1717                         status = cx231xx_reg_mask_write(dev,
1718                                         VID_BLK_I2C_ADDRESS, 32,
1719                                         AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1720                                         function_mode);
1721                         /* IF_MODE */
1722                         status = cx231xx_reg_mask_write(dev,
1723                                         VID_BLK_I2C_ADDRESS, 32,
1724                                         AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE);
1725                         /* no inv */
1726                         status = cx231xx_reg_mask_write(dev,
1727                                         VID_BLK_I2C_ADDRESS, 32,
1728                                         AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1729                 }
1730         }
1731
1732         return status;
1733 }
1734
1735 int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1736 {
1737         int status = 0;
1738         u32 dif_misc_ctrl_value = 0;
1739         u32 func_mode = 0;
1740
1741         cx231xx_info("%s: setStandard to %x\n", __func__, standard);
1742
1743         status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value);
1744         if (standard != DIF_USE_BASEBAND)
1745                 dev->norm = standard;
1746
1747         switch (dev->model) {
1748         case CX231XX_BOARD_CNXT_CARRAERA:
1749         case CX231XX_BOARD_CNXT_RDE_250:
1750         case CX231XX_BOARD_CNXT_SHELBY:
1751         case CX231XX_BOARD_CNXT_RDU_250:
1752         case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
1753                 func_mode = 0x03;
1754                 break;
1755         case CX231XX_BOARD_CNXT_RDE_253S:
1756         case CX231XX_BOARD_CNXT_RDU_253S:
1757                 func_mode = 0x01;
1758                 break;
1759         default:
1760                 func_mode = 0x01;
1761         }
1762
1763         status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1764                                                   func_mode, standard);
1765
1766         if (standard == DIF_USE_BASEBAND) {     /* base band */
1767                 /* There is a different SRC_PHASE_INC value
1768                    for baseband vs. DIF */
1769                 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83);
1770                 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1771                                                 &dif_misc_ctrl_value);
1772                 dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS;
1773                 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1774                                                 dif_misc_ctrl_value);
1775         } else if (standard & V4L2_STD_PAL_D) {
1776                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1777                                            DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1778                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1779                                            DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1780                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1781                                            DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1782                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1783                                            DIF_PLL_CTRL3, 0, 31, 0x00008800);
1784                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1785                                            DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1786                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1787                                            DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1788                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1789                                            DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1790                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1791                                            DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1792                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1793                                            DIF_AGC_IF_INT_CURRENT, 0, 31,
1794                                            0x26001700);
1795                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1796                                            DIF_AGC_RF_CURRENT, 0, 31,
1797                                            0x00002660);
1798                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1799                                            DIF_VIDEO_AGC_CTRL, 0, 31,
1800                                            0x72500800);
1801                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1802                                            DIF_VID_AUD_OVERRIDE, 0, 31,
1803                                            0x27000100);
1804                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1805                                            DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA);
1806                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1807                                            DIF_COMP_FLT_CTRL, 0, 31,
1808                                            0x00000000);
1809                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1810                                            DIF_SRC_PHASE_INC, 0, 31,
1811                                            0x1befbf06);
1812                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1813                                            DIF_SRC_GAIN_CONTROL, 0, 31,
1814                                            0x000035e8);
1815                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1816                                            DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1817                 /* Save the Spec Inversion value */
1818                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1819                 dif_misc_ctrl_value |= 0x3a023F11;
1820         } else if (standard & V4L2_STD_PAL_I) {
1821                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1822                                            DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1823                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1824                                            DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1825                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1826                                            DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1827                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1828                                            DIF_PLL_CTRL3, 0, 31, 0x00008800);
1829                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1830                                            DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1831                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1832                                            DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1833                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1834                                            DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1835                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1836                                            DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1837                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1838                                            DIF_AGC_IF_INT_CURRENT, 0, 31,
1839                                            0x26001700);
1840                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1841                                            DIF_AGC_RF_CURRENT, 0, 31,
1842                                            0x00002660);
1843                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1844                                            DIF_VIDEO_AGC_CTRL, 0, 31,
1845                                            0x72500800);
1846                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1847                                            DIF_VID_AUD_OVERRIDE, 0, 31,
1848                                            0x27000100);
1849                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1850                                            DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934);
1851                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1852                                            DIF_COMP_FLT_CTRL, 0, 31,
1853                                            0x00000000);
1854                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1855                                            DIF_SRC_PHASE_INC, 0, 31,
1856                                            0x1befbf06);
1857                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1858                                            DIF_SRC_GAIN_CONTROL, 0, 31,
1859                                            0x000035e8);
1860                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1861                                            DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1862                 /* Save the Spec Inversion value */
1863                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1864                 dif_misc_ctrl_value |= 0x3a033F11;
1865         } else if (standard & V4L2_STD_PAL_M) {
1866                 /* improved Low Frequency Phase Noise */
1867                 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1868                 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1869                 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1870                 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1871                 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1872                 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1873                                                 0x26001700);
1874                 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1875                                                 0x00002660);
1876                 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1877                                                 0x72500800);
1878                 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1879                                                 0x27000100);
1880                 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d);
1881                 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1882                                                 0x009f50c1);
1883                 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1884                                                 0x1befbf06);
1885                 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1886                                                 0x000035e8);
1887                 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1888                                                 0x00000000);
1889                 /* Save the Spec Inversion value */
1890                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1891                 dif_misc_ctrl_value |= 0x3A0A3F10;
1892         } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) {
1893                 /* improved Low Frequency Phase Noise */
1894                 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1895                 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1896                 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1897                 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1898                 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1899                 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1900                                                 0x26001700);
1901                 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1902                                                 0x00002660);
1903                 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1904                                                 0x72500800);
1905                 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1906                                                 0x27000100);
1907                 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL,
1908                                                 0x012c405d);
1909                 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1910                                                 0x009f50c1);
1911                 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1912                                                 0x1befbf06);
1913                 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1914                                                 0x000035e8);
1915                 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1916                                                 0x00000000);
1917                 /* Save the Spec Inversion value */
1918                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1919                 dif_misc_ctrl_value = 0x3A093F10;
1920         } else if (standard &
1921                   (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G |
1922                    V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) {
1923
1924                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1925                                            DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1926                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1927                                            DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1928                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1929                                            DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1930                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1931                                            DIF_PLL_CTRL3, 0, 31, 0x00008800);
1932                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1933                                            DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1934                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1935                                            DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1936                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1937                                            DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1938                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1939                                            DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1940                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1941                                            DIF_AGC_IF_INT_CURRENT, 0, 31,
1942                                            0x26001700);
1943                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1944                                            DIF_AGC_RF_CURRENT, 0, 31,
1945                                            0x00002660);
1946                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1947                                            DIF_VID_AUD_OVERRIDE, 0, 31,
1948                                            0x27000100);
1949                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1950                                            DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1951                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1952                                            DIF_COMP_FLT_CTRL, 0, 31,
1953                                            0x00000000);
1954                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1955                                            DIF_SRC_PHASE_INC, 0, 31,
1956                                            0x1befbf06);
1957                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1958                                            DIF_SRC_GAIN_CONTROL, 0, 31,
1959                                            0x000035e8);
1960                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1961                                            DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1962                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1963                                            DIF_VIDEO_AGC_CTRL, 0, 31,
1964                                            0xf4000000);
1965
1966                 /* Save the Spec Inversion value */
1967                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1968                 dif_misc_ctrl_value |= 0x3a023F11;
1969         } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) {
1970                 /* Is it SECAM_L1? */
1971                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1972                                            DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1973                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1974                                            DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1975                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1976                                            DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1977                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1978                                            DIF_PLL_CTRL3, 0, 31, 0x00008800);
1979                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1980                                            DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1981                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1982                                            DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1983                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1984                                            DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1985                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1986                                            DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1987                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1988                                            DIF_AGC_IF_INT_CURRENT, 0, 31,
1989                                            0x26001700);
1990                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1991                                            DIF_AGC_RF_CURRENT, 0, 31,
1992                                            0x00002660);
1993                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1994                                            DIF_VID_AUD_OVERRIDE, 0, 31,
1995                                            0x27000100);
1996                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1997                                            DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1998                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1999                                            DIF_COMP_FLT_CTRL, 0, 31,
2000                                            0x00000000);
2001                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2002                                            DIF_SRC_PHASE_INC, 0, 31,
2003                                            0x1befbf06);
2004                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2005                                            DIF_SRC_GAIN_CONTROL, 0, 31,
2006                                            0x000035e8);
2007                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2008                                            DIF_RPT_VARIANCE, 0, 31, 0x00000000);
2009                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2010                                            DIF_VIDEO_AGC_CTRL, 0, 31,
2011                                            0xf2560000);
2012
2013                 /* Save the Spec Inversion value */
2014                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
2015                 dif_misc_ctrl_value |= 0x3a023F11;
2016
2017         } else if (standard & V4L2_STD_NTSC_M) {
2018                 /* V4L2_STD_NTSC_M (75 IRE Setup) Or
2019                    V4L2_STD_NTSC_M_JP (Japan,  0 IRE Setup) */
2020
2021                 /* For NTSC the centre frequency of video coming out of
2022                    sidewinder is around 7.1MHz or 3.6MHz depending on the
2023                    spectral inversion. so for a non spectrally inverted channel
2024                    the pll freq word is 0x03420c49
2025                  */
2026
2027                 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C);
2028                 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85);
2029                 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A);
2030                 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
2031                 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380);
2032                 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
2033                                                 0x26001700);
2034                 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
2035                                                 0x00002660);
2036                 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
2037                                                 0x04000800);
2038                 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
2039                                                 0x27000100);
2040                 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f);
2041
2042                 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
2043                                                 0x009f50c1);
2044                 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
2045                                                 0x1befbf06);
2046                 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
2047                                                 0x000035e8);
2048
2049                 status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600);
2050                 status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT,
2051                                                 0xC2262600);
2052                 status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600);
2053
2054                 /* Save the Spec Inversion value */
2055                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
2056                 dif_misc_ctrl_value |= 0x3a003F10;
2057         } else {
2058                 /* default PAL BG */
2059                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2060                                            DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
2061                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2062                                            DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
2063                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2064                                            DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
2065                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2066                                            DIF_PLL_CTRL3, 0, 31, 0x00008800);
2067                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2068                                            DIF_AGC_IF_REF, 0, 31, 0x444C1380);
2069                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2070                                            DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
2071                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2072                                            DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
2073                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2074                                            DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
2075                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2076                                            DIF_AGC_IF_INT_CURRENT, 0, 31,
2077                                            0x26001700);
2078                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2079                                            DIF_AGC_RF_CURRENT, 0, 31,
2080                                            0x00002660);
2081                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2082                                            DIF_VIDEO_AGC_CTRL, 0, 31,
2083                                            0x72500800);
2084                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2085                                            DIF_VID_AUD_OVERRIDE, 0, 31,
2086                                            0x27000100);
2087                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2088                                            DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC);
2089                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2090                                            DIF_COMP_FLT_CTRL, 0, 31,
2091                                            0x00A653A8);
2092                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2093                                            DIF_SRC_PHASE_INC, 0, 31,
2094                                            0x1befbf06);
2095                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2096                                            DIF_SRC_GAIN_CONTROL, 0, 31,
2097                                            0x000035e8);
2098                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2099                                            DIF_RPT_VARIANCE, 0, 31, 0x00000000);
2100                 /* Save the Spec Inversion value */
2101                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
2102                 dif_misc_ctrl_value |= 0x3a013F11;
2103         }
2104
2105         /* The AGC values should be the same for all standards,
2106            AUD_SRC_SEL[19] should always be disabled    */
2107         dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL;
2108
2109         /* It is still possible to get Set Standard calls even when we
2110            are in FM mode.
2111            This is done to override the value for FM. */
2112         if (dev->active_mode == V4L2_TUNER_RADIO)
2113                 dif_misc_ctrl_value = 0x7a080000;
2114
2115         /* Write the calculated value for misc ontrol register      */
2116         status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value);
2117
2118         return status;
2119 }
2120
2121 int cx231xx_tuner_pre_channel_change(struct cx231xx *dev)
2122 {
2123         int status = 0;
2124         u32 dwval;
2125
2126         /* Set the RF and IF k_agc values to 3 */
2127         status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
2128         dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
2129         dwval |= 0x33000000;
2130
2131         status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
2132
2133         return status;
2134 }
2135
2136 int cx231xx_tuner_post_channel_change(struct cx231xx *dev)
2137 {
2138         int status = 0;
2139         u32 dwval;
2140    cx231xx_info("cx231xx_tuner_post_channel_change  dev->tuner_type =0%d\n",
2141                          dev->tuner_type);
2142         /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for
2143          * SECAM L/B/D standards */
2144         status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
2145         dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
2146
2147         if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B |
2148                          V4L2_STD_SECAM_D)) {
2149                         if (dev->tuner_type == TUNER_NXP_TDA18271) {
2150                                 dwval &= ~FLD_DIF_IF_REF;
2151                                 dwval |= 0x88000300;
2152                         } else
2153                                 dwval |= 0x88000000;
2154                 } else {
2155                         if (dev->tuner_type == TUNER_NXP_TDA18271) {
2156                                 dwval &= ~FLD_DIF_IF_REF;
2157                                 dwval |= 0xCC000300;
2158                         } else
2159                                 dwval |= 0x44000000;
2160                 }
2161
2162         status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
2163
2164         return status;
2165 }
2166
2167 /******************************************************************************
2168  *                  I 2 S - B L O C K    C O N T R O L   functions            *
2169  ******************************************************************************/
2170 int cx231xx_i2s_blk_initialize(struct cx231xx *dev)
2171 {
2172         int status = 0;
2173         u32 value;
2174
2175         status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2176                                        CH_PWR_CTRL1, 1, &value, 1);
2177         /* enables clock to delta-sigma and decimation filter */
2178         value |= 0x80;
2179         status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2180                                         CH_PWR_CTRL1, 1, value, 1);
2181         /* power up all channel */
2182         status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2183                                         CH_PWR_CTRL2, 1, 0x00, 1);
2184
2185         return status;
2186 }
2187
2188 int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev,
2189                                         enum AV_MODE avmode)
2190 {
2191         int status = 0;
2192         u32 value = 0;
2193
2194         if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) {
2195                 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2196                                           CH_PWR_CTRL2, 1, &value, 1);
2197                 value |= 0xfe;
2198                 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2199                                                 CH_PWR_CTRL2, 1, value, 1);
2200         } else {
2201                 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2202                                                 CH_PWR_CTRL2, 1, 0x00, 1);
2203         }
2204
2205         return status;
2206 }
2207
2208 /* set i2s_blk for audio input types */
2209 int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input)
2210 {
2211         int status = 0;
2212
2213         switch (audio_input) {
2214         case CX231XX_AMUX_LINE_IN:
2215                 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2216                                                 CH_PWR_CTRL2, 1, 0x00, 1);
2217                 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2218                                                 CH_PWR_CTRL1, 1, 0x80, 1);
2219                 break;
2220         case CX231XX_AMUX_VIDEO:
2221         default:
2222                 break;
2223         }
2224
2225         dev->ctl_ainput = audio_input;
2226
2227         return status;
2228 }
2229
2230 /******************************************************************************
2231  *                  P O W E R      C O N T R O L   functions                  *
2232  ******************************************************************************/
2233 int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode)
2234 {
2235         u8 value[4] = { 0, 0, 0, 0 };
2236         u32 tmp = 0;
2237         int status = 0;
2238
2239         if (dev->power_mode != mode)
2240                 dev->power_mode = mode;
2241         else {
2242                 cx231xx_info(" setPowerMode::mode = %d, No Change req.\n",
2243                              mode);
2244                 return 0;
2245         }
2246
2247         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
2248                                        4);
2249         if (status < 0)
2250                 return status;
2251
2252         tmp = *((u32 *) value);
2253
2254         switch (mode) {
2255         case POLARIS_AVMODE_ENXTERNAL_AV:
2256
2257                 tmp &= (~PWR_MODE_MASK);
2258
2259                 tmp |= PWR_AV_EN;
2260                 value[0] = (u8) tmp;
2261                 value[1] = (u8) (tmp >> 8);
2262                 value[2] = (u8) (tmp >> 16);
2263                 value[3] = (u8) (tmp >> 24);
2264                 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2265                                                 PWR_CTL_EN, value, 4);
2266                 msleep(PWR_SLEEP_INTERVAL);
2267
2268                 tmp |= PWR_ISO_EN;
2269                 value[0] = (u8) tmp;
2270                 value[1] = (u8) (tmp >> 8);
2271                 value[2] = (u8) (tmp >> 16);
2272                 value[3] = (u8) (tmp >> 24);
2273                 status =
2274                     cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2275                                            value, 4);
2276                 msleep(PWR_SLEEP_INTERVAL);
2277
2278                 tmp |= POLARIS_AVMODE_ENXTERNAL_AV;
2279                 value[0] = (u8) tmp;
2280                 value[1] = (u8) (tmp >> 8);
2281                 value[2] = (u8) (tmp >> 16);
2282                 value[3] = (u8) (tmp >> 24);
2283                 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2284                                                 PWR_CTL_EN, value, 4);
2285
2286                 /* reset state of xceive tuner */
2287                 dev->xc_fw_load_done = 0;
2288                 break;
2289
2290         case POLARIS_AVMODE_ANALOGT_TV:
2291
2292                 tmp |= PWR_DEMOD_EN;
2293                 tmp |= (I2C_DEMOD_EN);
2294                 value[0] = (u8) tmp;
2295                 value[1] = (u8) (tmp >> 8);
2296                 value[2] = (u8) (tmp >> 16);
2297                 value[3] = (u8) (tmp >> 24);
2298                 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2299                                                 PWR_CTL_EN, value, 4);
2300                 msleep(PWR_SLEEP_INTERVAL);
2301
2302                 if (!(tmp & PWR_TUNER_EN)) {
2303                         tmp |= (PWR_TUNER_EN);
2304                         value[0] = (u8) tmp;
2305                         value[1] = (u8) (tmp >> 8);
2306                         value[2] = (u8) (tmp >> 16);
2307                         value[3] = (u8) (tmp >> 24);
2308                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2309                                                         PWR_CTL_EN, value, 4);
2310                         msleep(PWR_SLEEP_INTERVAL);
2311                 }
2312
2313                 if (!(tmp & PWR_AV_EN)) {
2314                         tmp |= PWR_AV_EN;
2315                         value[0] = (u8) tmp;
2316                         value[1] = (u8) (tmp >> 8);
2317                         value[2] = (u8) (tmp >> 16);
2318                         value[3] = (u8) (tmp >> 24);
2319                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2320                                                         PWR_CTL_EN, value, 4);
2321                         msleep(PWR_SLEEP_INTERVAL);
2322                 }
2323                 if (!(tmp & PWR_ISO_EN)) {
2324                         tmp |= PWR_ISO_EN;
2325                         value[0] = (u8) tmp;
2326                         value[1] = (u8) (tmp >> 8);
2327                         value[2] = (u8) (tmp >> 16);
2328                         value[3] = (u8) (tmp >> 24);
2329                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2330                                                         PWR_CTL_EN, value, 4);
2331                         msleep(PWR_SLEEP_INTERVAL);
2332                 }
2333
2334                 if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) {
2335                         tmp |= POLARIS_AVMODE_ANALOGT_TV;
2336                         value[0] = (u8) tmp;
2337                         value[1] = (u8) (tmp >> 8);
2338                         value[2] = (u8) (tmp >> 16);
2339                         value[3] = (u8) (tmp >> 24);
2340                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2341                                                         PWR_CTL_EN, value, 4);
2342                         msleep(PWR_SLEEP_INTERVAL);
2343                 }
2344
2345                 if ((dev->model == CX231XX_BOARD_CNXT_CARRAERA) ||
2346                     (dev->model == CX231XX_BOARD_CNXT_RDE_250) ||
2347                     (dev->model == CX231XX_BOARD_CNXT_SHELBY) ||
2348                     (dev->model == CX231XX_BOARD_CNXT_RDU_250)) {
2349                         /* tuner path to channel 1 from port 3 */
2350                         cx231xx_enable_i2c_for_tuner(dev, I2C_3);
2351
2352                         /* reset the Tuner */
2353                         cx231xx_gpio_set(dev, dev->board.tuner_gpio);
2354
2355                         if (dev->cx231xx_reset_analog_tuner)
2356                                 dev->cx231xx_reset_analog_tuner(dev);
2357                 } else if ((dev->model == CX231XX_BOARD_CNXT_RDE_253S) ||
2358                     (dev->model == CX231XX_BOARD_CNXT_VIDEO_GRABBER) ||
2359                     (dev->model == CX231XX_BOARD_CNXT_RDU_253S)) {
2360                         /* tuner path to channel 1 from port 3 */
2361                         cx231xx_enable_i2c_for_tuner(dev, I2C_3);
2362                         if (dev->cx231xx_reset_analog_tuner)
2363                                 dev->cx231xx_reset_analog_tuner(dev);
2364                 }
2365
2366                 break;
2367
2368         case POLARIS_AVMODE_DIGITAL:
2369                 if (!(tmp & PWR_TUNER_EN)) {
2370                         tmp |= (PWR_TUNER_EN);
2371                         value[0] = (u8) tmp;
2372                         value[1] = (u8) (tmp >> 8);
2373                         value[2] = (u8) (tmp >> 16);
2374                         value[3] = (u8) (tmp >> 24);
2375                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2376                                                         PWR_CTL_EN, value, 4);
2377                         msleep(PWR_SLEEP_INTERVAL);
2378                 }
2379                 if (!(tmp & PWR_AV_EN)) {
2380                         tmp |= PWR_AV_EN;
2381                         value[0] = (u8) tmp;
2382                         value[1] = (u8) (tmp >> 8);
2383                         value[2] = (u8) (tmp >> 16);
2384                         value[3] = (u8) (tmp >> 24);
2385                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2386                                                         PWR_CTL_EN, value, 4);
2387                         msleep(PWR_SLEEP_INTERVAL);
2388                 }
2389                 if (!(tmp & PWR_ISO_EN)) {
2390                         tmp |= PWR_ISO_EN;
2391                         value[0] = (u8) tmp;
2392                         value[1] = (u8) (tmp >> 8);
2393                         value[2] = (u8) (tmp >> 16);
2394                         value[3] = (u8) (tmp >> 24);
2395                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2396                                                         PWR_CTL_EN, value, 4);
2397                         msleep(PWR_SLEEP_INTERVAL);
2398                 }
2399
2400                 tmp |= POLARIS_AVMODE_DIGITAL | I2C_DEMOD_EN;
2401                 value[0] = (u8) tmp;
2402                 value[1] = (u8) (tmp >> 8);
2403                 value[2] = (u8) (tmp >> 16);
2404                 value[3] = (u8) (tmp >> 24);
2405                 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2406                                                 PWR_CTL_EN, value, 4);
2407                 msleep(PWR_SLEEP_INTERVAL);
2408
2409                 if (!(tmp & PWR_DEMOD_EN)) {
2410                         tmp |= PWR_DEMOD_EN;
2411                         value[0] = (u8) tmp;
2412                         value[1] = (u8) (tmp >> 8);
2413                         value[2] = (u8) (tmp >> 16);
2414                         value[3] = (u8) (tmp >> 24);
2415                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2416                                                         PWR_CTL_EN, value, 4);
2417                         msleep(PWR_SLEEP_INTERVAL);
2418                 }
2419
2420                 if ((dev->model == CX231XX_BOARD_CNXT_CARRAERA) ||
2421                     (dev->model == CX231XX_BOARD_CNXT_RDE_250) ||
2422                     (dev->model == CX231XX_BOARD_CNXT_SHELBY) ||
2423                     (dev->model == CX231XX_BOARD_CNXT_RDU_250)) {
2424                         /* tuner path to channel 1 from port 3 */
2425                         cx231xx_enable_i2c_for_tuner(dev, I2C_3);
2426
2427                         /* reset the Tuner */
2428                         cx231xx_gpio_set(dev, dev->board.tuner_gpio);
2429
2430                         if (dev->cx231xx_reset_analog_tuner)
2431                                 dev->cx231xx_reset_analog_tuner(dev);
2432                 } else if ((dev->model == CX231XX_BOARD_CNXT_RDE_253S) ||
2433                     (dev->model == CX231XX_BOARD_CNXT_VIDEO_GRABBER) ||
2434                     (dev->model == CX231XX_BOARD_CNXT_RDU_253S)) {
2435                         /* tuner path to channel 1 from port 3 */
2436                         cx231xx_enable_i2c_for_tuner(dev, I2C_3);
2437                         if (dev->cx231xx_reset_analog_tuner)
2438                                 dev->cx231xx_reset_analog_tuner(dev);
2439                 }
2440
2441                 break;
2442
2443         default:
2444                 break;
2445         }
2446
2447         msleep(PWR_SLEEP_INTERVAL);
2448
2449         /* For power saving, only enable Pwr_resetout_n
2450            when digital TV is selected. */
2451         if (mode == POLARIS_AVMODE_DIGITAL) {
2452                 tmp |= PWR_RESETOUT_EN;
2453                 value[0] = (u8) tmp;
2454                 value[1] = (u8) (tmp >> 8);
2455                 value[2] = (u8) (tmp >> 16);
2456                 value[3] = (u8) (tmp >> 24);
2457                 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2458                                                 PWR_CTL_EN, value, 4);
2459                 msleep(PWR_SLEEP_INTERVAL);
2460         }
2461
2462         /* update power control for afe */
2463         status = cx231xx_afe_update_power_control(dev, mode);
2464
2465         /* update power control for i2s_blk */
2466         status = cx231xx_i2s_blk_update_power_control(dev, mode);
2467
2468         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
2469                                        4);
2470
2471         return status;
2472 }
2473
2474 int cx231xx_power_suspend(struct cx231xx *dev)
2475 {
2476         u8 value[4] = { 0, 0, 0, 0 };
2477         u32 tmp = 0;
2478         int status = 0;
2479
2480         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
2481                                        value, 4);
2482         if (status > 0)
2483                 return status;
2484
2485         tmp = *((u32 *) value);
2486         tmp &= (~PWR_MODE_MASK);
2487
2488         value[0] = (u8) tmp;
2489         value[1] = (u8) (tmp >> 8);
2490         value[2] = (u8) (tmp >> 16);
2491         value[3] = (u8) (tmp >> 24);
2492         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2493                                         value, 4);
2494
2495         return status;
2496 }
2497
2498 /******************************************************************************
2499  *                  S T R E A M    C O N T R O L   functions                  *
2500  ******************************************************************************/
2501 int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask)
2502 {
2503         u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
2504         u32 tmp = 0;
2505         int status = 0;
2506
2507         cx231xx_info("cx231xx_start_stream():: ep_mask = %x\n", ep_mask);
2508         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
2509                                        value, 4);
2510         if (status < 0)
2511                 return status;
2512
2513         tmp = *((u32 *) value);
2514         tmp |= ep_mask;
2515         value[0] = (u8) tmp;
2516         value[1] = (u8) (tmp >> 8);
2517         value[2] = (u8) (tmp >> 16);
2518         value[3] = (u8) (tmp >> 24);
2519
2520         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2521                                         value, 4);
2522
2523         return status;
2524 }
2525
2526 int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask)
2527 {
2528         u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
2529         u32 tmp = 0;
2530         int status = 0;
2531
2532         cx231xx_info("cx231xx_stop_stream():: ep_mask = %x\n", ep_mask);
2533         status =
2534             cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4);
2535         if (status < 0)
2536                 return status;
2537
2538         tmp = *((u32 *) value);
2539         tmp &= (~ep_mask);
2540         value[0] = (u8) tmp;
2541         value[1] = (u8) (tmp >> 8);
2542         value[2] = (u8) (tmp >> 16);
2543         value[3] = (u8) (tmp >> 24);
2544
2545         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2546                                         value, 4);
2547
2548         return status;
2549 }
2550
2551 int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type)
2552 {
2553         int status = 0;
2554         u32 value = 0;
2555         u8 val[4] = { 0, 0, 0, 0 };
2556
2557         if (dev->udev->speed == USB_SPEED_HIGH) {
2558                 switch (media_type) {
2559                 case 81: /* audio */
2560                         cx231xx_info("%s: Audio enter HANC\n", __func__);
2561                         status =
2562                             cx231xx_mode_register(dev, TS_MODE_REG, 0x9300);
2563                         break;
2564
2565                 case 2: /* vbi */
2566                         cx231xx_info("%s: set vanc registers\n", __func__);
2567                         status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300);
2568                         break;
2569
2570                 case 3: /* sliced cc */
2571                         cx231xx_info("%s: set hanc registers\n", __func__);
2572                         status =
2573                             cx231xx_mode_register(dev, TS_MODE_REG, 0x1300);
2574                         break;
2575
2576                 case 0: /* video */
2577                         cx231xx_info("%s: set video registers\n", __func__);
2578                         status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2579                         break;
2580
2581                 case 4: /* ts1 */
2582                         cx231xx_info("%s: set ts1 registers", __func__);
2583
2584                 if (dev->model == CX231XX_BOARD_CNXT_VIDEO_GRABBER) {
2585                         cx231xx_info(" MPEG\n");
2586                         value &= 0xFFFFFFFC;
2587                         value |= 0x3;
2588
2589                         status = cx231xx_mode_register(dev, TS_MODE_REG, value);
2590
2591                         val[0] = 0x04;
2592                         val[1] = 0xA3;
2593                         val[2] = 0x3B;
2594                         val[3] = 0x00;
2595                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2596                                  TS1_CFG_REG, val, 4);
2597
2598                         val[0] = 0x00;
2599                         val[1] = 0x08;
2600                         val[2] = 0x00;
2601                         val[3] = 0x08;
2602                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2603                                  TS1_LENGTH_REG, val, 4);
2604
2605                 } else {
2606                         cx231xx_info(" BDA\n");
2607                         status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2608                         status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x010);
2609                 }
2610                         break;
2611
2612                 case 6: /* ts1 parallel mode */
2613                         cx231xx_info("%s: set ts1 parrallel mode registers\n",
2614                                      __func__);
2615                         status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2616                         status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
2617                         break;
2618                 }
2619         } else {
2620                 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2621         }
2622
2623         return status;
2624 }
2625
2626 int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type)
2627 {
2628         int rc = -1;
2629         u32 ep_mask = -1;
2630         struct pcb_config *pcb_config;
2631
2632         /* get EP for media type */
2633         pcb_config = (struct pcb_config *)&dev->current_pcb_config;
2634
2635         if (pcb_config->config_num == 1) {
2636                 switch (media_type) {
2637                 case 0: /* Video */
2638                         ep_mask = ENABLE_EP4;   /* ep4  [00:1000] */
2639                         break;
2640                 case 1: /* Audio */
2641                         ep_mask = ENABLE_EP3;   /* ep3  [00:0100] */
2642                         break;
2643                 case 2: /* Vbi */
2644                         ep_mask = ENABLE_EP5;   /* ep5 [01:0000] */
2645                         break;
2646                 case 3: /* Sliced_cc */
2647                         ep_mask = ENABLE_EP6;   /* ep6 [10:0000] */
2648                         break;
2649                 case 4: /* ts1 */
2650                 case 6: /* ts1 parallel mode */
2651                         ep_mask = ENABLE_EP1;   /* ep1 [00:0001] */
2652                         break;
2653                 case 5: /* ts2 */
2654                         ep_mask = ENABLE_EP2;   /* ep2 [00:0010] */
2655                         break;
2656                 }
2657
2658         } else if (pcb_config->config_num > 1) {
2659                 switch (media_type) {
2660                 case 0: /* Video */
2661                         ep_mask = ENABLE_EP4;   /* ep4  [00:1000] */
2662                         break;
2663                 case 1: /* Audio */
2664                         ep_mask = ENABLE_EP3;   /* ep3  [00:0100] */
2665                         break;
2666                 case 2: /* Vbi */
2667                         ep_mask = ENABLE_EP5;   /* ep5 [01:0000] */
2668                         break;
2669                 case 3: /* Sliced_cc */
2670                         ep_mask = ENABLE_EP6;   /* ep6 [10:0000] */
2671                         break;
2672                 case 4: /* ts1 */
2673                 case 6: /* ts1 parallel mode */
2674                         ep_mask = ENABLE_EP1;   /* ep1 [00:0001] */
2675                         break;
2676                 case 5: /* ts2 */
2677                         ep_mask = ENABLE_EP2;   /* ep2 [00:0010] */
2678                         break;
2679                 }
2680
2681         }
2682
2683         if (start) {
2684                 rc = cx231xx_initialize_stream_xfer(dev, media_type);
2685
2686                 if (rc < 0)
2687                         return rc;
2688
2689                 /* enable video capture */
2690                 if (ep_mask > 0)
2691                         rc = cx231xx_start_stream(dev, ep_mask);
2692         } else {
2693                 /* disable video capture */
2694                 if (ep_mask > 0)
2695                         rc = cx231xx_stop_stream(dev, ep_mask);
2696         }
2697
2698         if (dev->mode == CX231XX_ANALOG_MODE)
2699                 ;/* do any in Analog mode */
2700         else
2701                 ;/* do any in digital mode */
2702
2703         return rc;
2704 }
2705 EXPORT_SYMBOL_GPL(cx231xx_capture_start);
2706
2707 /*****************************************************************************
2708 *                   G P I O   B I T control functions                        *
2709 ******************************************************************************/
2710 int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val)
2711 {
2712         int status = 0;
2713
2714         status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 0);
2715
2716         return status;
2717 }
2718
2719 int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val)
2720 {
2721         int status = 0;
2722
2723         status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 1);
2724
2725         return status;
2726 }
2727
2728 /*
2729 * cx231xx_set_gpio_direction
2730 *      Sets the direction of the GPIO pin to input or output
2731 *
2732 * Parameters :
2733 *      pin_number : The GPIO Pin number to program the direction for
2734 *                   from 0 to 31
2735 *      pin_value : The Direction of the GPIO Pin under reference.
2736 *                      0 = Input direction
2737 *                      1 = Output direction
2738 */
2739 int cx231xx_set_gpio_direction(struct cx231xx *dev,
2740                                int pin_number, int pin_value)
2741 {
2742         int status = 0;
2743         u32 value = 0;
2744
2745         /* Check for valid pin_number - if 32 , bail out */
2746         if (pin_number >= 32)
2747                 return -EINVAL;
2748
2749         /* input */
2750         if (pin_value == 0)
2751                 value = dev->gpio_dir & (~(1 << pin_number));   /* clear */
2752         else
2753                 value = dev->gpio_dir | (1 << pin_number);
2754
2755         status = cx231xx_set_gpio_bit(dev, value, (u8 *) &dev->gpio_val);
2756
2757         /* cache the value for future */
2758         dev->gpio_dir = value;
2759
2760         return status;
2761 }
2762
2763 /*
2764 * cx231xx_set_gpio_value
2765 *      Sets the value of the GPIO pin to Logic high or low. The Pin under
2766 *      reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!!
2767 *
2768 * Parameters :
2769 *      pin_number : The GPIO Pin number to program the direction for
2770 *      pin_value : The value of the GPIO Pin under reference.
2771 *                      0 = set it to 0
2772 *                      1 = set it to 1
2773 */
2774 int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value)
2775 {
2776         int status = 0;
2777         u32 value = 0;
2778
2779         /* Check for valid pin_number - if 0xFF , bail out */
2780         if (pin_number >= 32)
2781                 return -EINVAL;
2782
2783         /* first do a sanity check - if the Pin is not output, make it output */
2784         if ((dev->gpio_dir & (1 << pin_number)) == 0x00) {
2785                 /* It was in input mode */
2786                 value = dev->gpio_dir | (1 << pin_number);
2787                 dev->gpio_dir = value;
2788                 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2789                                               (u8 *) &dev->gpio_val);
2790                 value = 0;
2791         }
2792
2793         if (pin_value == 0)
2794                 value = dev->gpio_val & (~(1 << pin_number));
2795         else
2796                 value = dev->gpio_val | (1 << pin_number);
2797
2798         /* store the value */
2799         dev->gpio_val = value;
2800
2801         /* toggle bit0 of GP_IO */
2802         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2803
2804         return status;
2805 }
2806
2807 /*****************************************************************************
2808 *                      G P I O I2C related functions                         *
2809 ******************************************************************************/
2810 int cx231xx_gpio_i2c_start(struct cx231xx *dev)
2811 {
2812         int status = 0;
2813
2814         /* set SCL to output 1 ; set SDA to output 1 */
2815         dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2816         dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2817         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2818         dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2819
2820         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2821         if (status < 0)
2822                 return -EINVAL;
2823
2824         /* set SCL to output 1; set SDA to output 0 */
2825         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2826         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2827
2828         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2829         if (status < 0)
2830                 return -EINVAL;
2831
2832         /* set SCL to output 0; set SDA to output 0      */
2833         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2834         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2835
2836         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2837         if (status < 0)
2838                 return -EINVAL;
2839
2840         return status;
2841 }
2842
2843 int cx231xx_gpio_i2c_end(struct cx231xx *dev)
2844 {
2845         int status = 0;
2846
2847         /* set SCL to output 0; set SDA to output 0      */
2848         dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2849         dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2850
2851         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2852         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2853
2854         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2855         if (status < 0)
2856                 return -EINVAL;
2857
2858         /* set SCL to output 1; set SDA to output 0      */
2859         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2860         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2861
2862         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2863         if (status < 0)
2864                 return -EINVAL;
2865
2866         /* set SCL to input ,release SCL cable control
2867            set SDA to input ,release SDA cable control */
2868         dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2869         dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2870
2871         status =
2872             cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2873         if (status < 0)
2874                 return -EINVAL;
2875
2876         return status;
2877 }
2878
2879 int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data)
2880 {
2881         int status = 0;
2882         u8 i;
2883
2884         /* set SCL to output ; set SDA to output */
2885         dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2886         dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2887
2888         for (i = 0; i < 8; i++) {
2889                 if (((data << i) & 0x80) == 0) {
2890                         /* set SCL to output 0; set SDA to output 0     */
2891                         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2892                         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2893                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2894                                                       (u8 *)&dev->gpio_val);
2895
2896                         /* set SCL to output 1; set SDA to output 0     */
2897                         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2898                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2899                                                       (u8 *)&dev->gpio_val);
2900
2901                         /* set SCL to output 0; set SDA to output 0     */
2902                         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2903                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2904                                                       (u8 *)&dev->gpio_val);
2905                 } else {
2906                         /* set SCL to output 0; set SDA to output 1     */
2907                         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2908                         dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2909                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2910                                                       (u8 *)&dev->gpio_val);
2911
2912                         /* set SCL to output 1; set SDA to output 1     */
2913                         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2914                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2915                                                       (u8 *)&dev->gpio_val);
2916
2917                         /* set SCL to output 0; set SDA to output 1     */
2918                         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2919                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2920                                                       (u8 *)&dev->gpio_val);
2921                 }
2922         }
2923         return status;
2924 }
2925
2926 int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf)
2927 {
2928         u8 value = 0;
2929         int status = 0;
2930         u32 gpio_logic_value = 0;
2931         u8 i;
2932
2933         /* read byte */
2934         for (i = 0; i < 8; i++) {       /* send write I2c addr */
2935
2936                 /* set SCL to output 0; set SDA to input */
2937                 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2938                 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2939                                               (u8 *)&dev->gpio_val);
2940
2941                 /* set SCL to output 1; set SDA to input */
2942                 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2943                 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2944                                               (u8 *)&dev->gpio_val);
2945
2946                 /* get SDA data bit */
2947                 gpio_logic_value = dev->gpio_val;
2948                 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2949                                               (u8 *)&dev->gpio_val);
2950                 if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0)
2951                         value |= (1 << (8 - i - 1));
2952
2953                 dev->gpio_val = gpio_logic_value;
2954         }
2955
2956         /* set SCL to output 0,finish the read latest SCL signal.
2957            !!!set SDA to input, never to modify SDA direction at
2958            the same times */
2959         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2960         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2961
2962         /* store the value */
2963         *buf = value & 0xff;
2964
2965         return status;
2966 }
2967
2968 int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev)
2969 {
2970         int status = 0;
2971         u32 gpio_logic_value = 0;
2972         int nCnt = 10;
2973         int nInit = nCnt;
2974
2975         /* clock stretch; set SCL to input; set SDA to input;
2976            get SCL value till SCL = 1 */
2977         dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2978         dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2979
2980         gpio_logic_value = dev->gpio_val;
2981         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2982
2983         do {
2984                 msleep(2);
2985                 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2986                                               (u8 *)&dev->gpio_val);
2987                 nCnt--;
2988         } while (((dev->gpio_val &
2989                           (1 << dev->board.tuner_scl_gpio)) == 0) &&
2990                          (nCnt > 0));
2991
2992         if (nCnt == 0)
2993                 cx231xx_info("No ACK after %d msec -GPIO I2C failed!",
2994                              nInit * 10);
2995
2996         /*
2997          * readAck
2998          * through clock stretch, slave has given a SCL signal,
2999          * so the SDA data can be directly read.
3000          */
3001         status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3002
3003         if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) {
3004                 dev->gpio_val = gpio_logic_value;
3005                 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
3006                 status = 0;
3007         } else {
3008                 dev->gpio_val = gpio_logic_value;
3009                 dev->gpio_val |= (1 << dev->board.tuner_sda_gpio);
3010         }
3011
3012         /* read SDA end, set the SCL to output 0, after this operation,
3013            SDA direction can be changed. */
3014         dev->gpio_val = gpio_logic_value;
3015         dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio);
3016         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
3017         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3018
3019         return status;
3020 }
3021
3022 int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev)
3023 {
3024         int status = 0;
3025
3026         /* set SDA to ouput */
3027         dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
3028         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3029
3030         /* set SCL = 0 (output); set SDA = 0 (output) */
3031         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
3032         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
3033         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3034
3035         /* set SCL = 1 (output); set SDA = 0 (output) */
3036         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
3037         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3038
3039         /* set SCL = 0 (output); set SDA = 0 (output) */
3040         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
3041         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3042
3043         /* set SDA to input,and then the slave will read data from SDA. */
3044         dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
3045         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3046
3047         return status;
3048 }
3049
3050 int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev)
3051 {
3052         int status = 0;
3053
3054         /* set scl to output ; set sda to input */
3055         dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
3056         dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
3057         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3058
3059         /* set scl to output 0; set sda to input */
3060         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
3061         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3062
3063         /* set scl to output 1; set sda to input */
3064         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
3065         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3066
3067         return status;
3068 }
3069
3070 /*****************************************************************************
3071 *                      G P I O I2C related functions                         *
3072 ******************************************************************************/
3073 /* cx231xx_gpio_i2c_read
3074  * Function to read data from gpio based I2C interface
3075  */
3076 int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
3077 {
3078         int status = 0;
3079         int i = 0;
3080
3081         /* get the lock */
3082         mutex_lock(&dev->gpio_i2c_lock);
3083
3084         /* start */
3085         status = cx231xx_gpio_i2c_start(dev);
3086
3087         /* write dev_addr */
3088         status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1);
3089
3090         /* readAck */
3091         status = cx231xx_gpio_i2c_read_ack(dev);
3092
3093         /* read data */
3094         for (i = 0; i < len; i++) {
3095                 /* read data */
3096                 buf[i] = 0;
3097                 status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]);
3098
3099                 if ((i + 1) != len) {
3100                         /* only do write ack if we more length */
3101                         status = cx231xx_gpio_i2c_write_ack(dev);
3102                 }
3103         }
3104
3105         /* write NAK - inform reads are complete */
3106         status = cx231xx_gpio_i2c_write_nak(dev);
3107
3108         /* write end */
3109         status = cx231xx_gpio_i2c_end(dev);
3110
3111         /* release the lock */
3112         mutex_unlock(&dev->gpio_i2c_lock);
3113
3114         return status;
3115 }
3116
3117 /* cx231xx_gpio_i2c_write
3118  * Function to write data to gpio based I2C interface
3119  */
3120 int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
3121 {
3122         int status = 0;
3123         int i = 0;
3124
3125         /* get the lock */
3126         mutex_lock(&dev->gpio_i2c_lock);
3127
3128         /* start */
3129         status = cx231xx_gpio_i2c_start(dev);
3130
3131         /* write dev_addr */
3132         status = cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1);
3133
3134         /* read Ack */
3135         status = cx231xx_gpio_i2c_read_ack(dev);
3136
3137         for (i = 0; i < len; i++) {
3138                 /* Write data */
3139                 status = cx231xx_gpio_i2c_write_byte(dev, buf[i]);
3140
3141                 /* read Ack */
3142                 status = cx231xx_gpio_i2c_read_ack(dev);
3143         }
3144
3145         /* write End */
3146         status = cx231xx_gpio_i2c_end(dev);
3147
3148         /* release the lock */
3149         mutex_unlock(&dev->gpio_i2c_lock);
3150
3151         return 0;
3152 }