2 * Elonics E4000 silicon tuner driver
4 * Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 #include "e4000_priv.h"
23 /* Max transfer size done by I2C transfer functions */
24 #define MAX_XFER_SIZE 64
26 /* write multiple registers */
27 static int e4000_wr_regs(struct e4000_priv *priv, u8 reg, u8 *val, int len)
30 u8 buf[MAX_XFER_SIZE];
31 struct i2c_msg msg[1] = {
33 .addr = priv->cfg->i2c_addr,
40 if (1 + len > sizeof(buf)) {
41 dev_warn(&priv->i2c->dev,
42 "%s: i2c wr reg=%04x: len=%d is too big!\n",
43 KBUILD_MODNAME, reg, len);
48 memcpy(&buf[1], val, len);
50 ret = i2c_transfer(priv->i2c, msg, 1);
54 dev_warn(&priv->i2c->dev, "%s: i2c wr failed=%d reg=%02x " \
55 "len=%d\n", KBUILD_MODNAME, ret, reg, len);
61 /* read multiple registers */
62 static int e4000_rd_regs(struct e4000_priv *priv, u8 reg, u8 *val, int len)
65 u8 buf[MAX_XFER_SIZE];
66 struct i2c_msg msg[2] = {
68 .addr = priv->cfg->i2c_addr,
73 .addr = priv->cfg->i2c_addr,
80 if (len > sizeof(buf)) {
81 dev_warn(&priv->i2c->dev,
82 "%s: i2c rd reg=%04x: len=%d is too big!\n",
83 KBUILD_MODNAME, reg, len);
87 ret = i2c_transfer(priv->i2c, msg, 2);
89 memcpy(val, buf, len);
92 dev_warn(&priv->i2c->dev, "%s: i2c rd failed=%d reg=%02x " \
93 "len=%d\n", KBUILD_MODNAME, ret, reg, len);
100 /* write single register */
101 static int e4000_wr_reg(struct e4000_priv *priv, u8 reg, u8 val)
103 return e4000_wr_regs(priv, reg, &val, 1);
106 /* read single register */
107 static int e4000_rd_reg(struct e4000_priv *priv, u8 reg, u8 *val)
109 return e4000_rd_regs(priv, reg, val, 1);
112 static int e4000_init(struct dvb_frontend *fe)
114 struct e4000_priv *priv = fe->tuner_priv;
117 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
119 if (fe->ops.i2c_gate_ctrl)
120 fe->ops.i2c_gate_ctrl(fe, 1);
122 /* dummy I2C to ensure I2C wakes up */
123 ret = e4000_wr_reg(priv, 0x02, 0x40);
126 ret = e4000_wr_reg(priv, 0x00, 0x01);
130 /* disable output clock */
131 ret = e4000_wr_reg(priv, 0x06, 0x00);
135 ret = e4000_wr_reg(priv, 0x7a, 0x96);
139 /* configure gains */
140 ret = e4000_wr_regs(priv, 0x7e, "\x01\xfe", 2);
144 ret = e4000_wr_reg(priv, 0x82, 0x00);
148 ret = e4000_wr_reg(priv, 0x24, 0x05);
152 ret = e4000_wr_regs(priv, 0x87, "\x20\x01", 2);
156 ret = e4000_wr_regs(priv, 0x9f, "\x7f\x07", 2);
161 * TODO: Implement DC offset control correctly.
162 * DC offsets has quite much effect for received signal quality in case
163 * of direct conversion tuners (Zero-IF). Surely we will now lose few
164 * decimals or even decibels from SNR...
166 /* DC offset control */
167 ret = e4000_wr_reg(priv, 0x2d, 0x0c);
172 ret = e4000_wr_reg(priv, 0x1a, 0x17);
176 ret = e4000_wr_reg(priv, 0x1f, 0x1a);
180 if (fe->ops.i2c_gate_ctrl)
181 fe->ops.i2c_gate_ctrl(fe, 0);
185 if (fe->ops.i2c_gate_ctrl)
186 fe->ops.i2c_gate_ctrl(fe, 0);
188 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
192 static int e4000_sleep(struct dvb_frontend *fe)
194 struct e4000_priv *priv = fe->tuner_priv;
197 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
199 if (fe->ops.i2c_gate_ctrl)
200 fe->ops.i2c_gate_ctrl(fe, 1);
202 ret = e4000_wr_reg(priv, 0x00, 0x00);
206 if (fe->ops.i2c_gate_ctrl)
207 fe->ops.i2c_gate_ctrl(fe, 0);
211 if (fe->ops.i2c_gate_ctrl)
212 fe->ops.i2c_gate_ctrl(fe, 0);
214 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
218 static int e4000_set_params(struct dvb_frontend *fe)
220 struct e4000_priv *priv = fe->tuner_priv;
221 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
222 int ret, i, sigma_delta;
226 dev_dbg(&priv->i2c->dev, "%s: delivery_system=%d frequency=%d " \
227 "bandwidth_hz=%d\n", __func__,
228 c->delivery_system, c->frequency, c->bandwidth_hz);
230 if (fe->ops.i2c_gate_ctrl)
231 fe->ops.i2c_gate_ctrl(fe, 1);
233 /* gain control manual */
234 ret = e4000_wr_reg(priv, 0x1a, 0x00);
239 for (i = 0; i < ARRAY_SIZE(e4000_pll_lut); i++) {
240 if (c->frequency <= e4000_pll_lut[i].freq)
244 if (i == ARRAY_SIZE(e4000_pll_lut))
248 * Note: Currently f_VCO overflows when c->frequency is 1 073 741 824 Hz
251 f_VCO = c->frequency * e4000_pll_lut[i].mul;
252 sigma_delta = 0x10000UL * (f_VCO % priv->cfg->clock) / priv->cfg->clock;
253 buf[0] = f_VCO / priv->cfg->clock;
254 buf[1] = (sigma_delta >> 0) & 0xff;
255 buf[2] = (sigma_delta >> 8) & 0xff;
257 buf[4] = e4000_pll_lut[i].div;
259 dev_dbg(&priv->i2c->dev, "%s: f_VCO=%u pll div=%d sigma_delta=%04x\n",
260 __func__, f_VCO, buf[0], sigma_delta);
262 ret = e4000_wr_regs(priv, 0x09, buf, 5);
266 /* LNA filter (RF filter) */
267 for (i = 0; i < ARRAY_SIZE(e400_lna_filter_lut); i++) {
268 if (c->frequency <= e400_lna_filter_lut[i].freq)
272 if (i == ARRAY_SIZE(e400_lna_filter_lut))
275 ret = e4000_wr_reg(priv, 0x10, e400_lna_filter_lut[i].val);
280 for (i = 0; i < ARRAY_SIZE(e4000_if_filter_lut); i++) {
281 if (c->bandwidth_hz <= e4000_if_filter_lut[i].freq)
285 if (i == ARRAY_SIZE(e4000_if_filter_lut))
288 buf[0] = e4000_if_filter_lut[i].reg11_val;
289 buf[1] = e4000_if_filter_lut[i].reg12_val;
291 ret = e4000_wr_regs(priv, 0x11, buf, 2);
296 for (i = 0; i < ARRAY_SIZE(e4000_band_lut); i++) {
297 if (c->frequency <= e4000_band_lut[i].freq)
301 if (i == ARRAY_SIZE(e4000_band_lut))
304 ret = e4000_wr_reg(priv, 0x07, e4000_band_lut[i].reg07_val);
308 ret = e4000_wr_reg(priv, 0x78, e4000_band_lut[i].reg78_val);
312 /* gain control auto */
313 ret = e4000_wr_reg(priv, 0x1a, 0x17);
317 if (fe->ops.i2c_gate_ctrl)
318 fe->ops.i2c_gate_ctrl(fe, 0);
322 if (fe->ops.i2c_gate_ctrl)
323 fe->ops.i2c_gate_ctrl(fe, 0);
325 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
329 static int e4000_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
331 struct e4000_priv *priv = fe->tuner_priv;
333 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
335 *frequency = 0; /* Zero-IF */
340 static int e4000_release(struct dvb_frontend *fe)
342 struct e4000_priv *priv = fe->tuner_priv;
344 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
346 kfree(fe->tuner_priv);
351 static const struct dvb_tuner_ops e4000_tuner_ops = {
353 .name = "Elonics E4000",
354 .frequency_min = 174000000,
355 .frequency_max = 862000000,
358 .release = e4000_release,
361 .sleep = e4000_sleep,
362 .set_params = e4000_set_params,
364 .get_if_frequency = e4000_get_if_frequency,
367 struct dvb_frontend *e4000_attach(struct dvb_frontend *fe,
368 struct i2c_adapter *i2c, const struct e4000_config *cfg)
370 struct e4000_priv *priv;
374 if (fe->ops.i2c_gate_ctrl)
375 fe->ops.i2c_gate_ctrl(fe, 1);
377 priv = kzalloc(sizeof(struct e4000_priv), GFP_KERNEL);
380 dev_err(&i2c->dev, "%s: kzalloc() failed\n", KBUILD_MODNAME);
387 /* check if the tuner is there */
388 ret = e4000_rd_reg(priv, 0x02, &chip_id);
392 dev_dbg(&priv->i2c->dev, "%s: chip_id=%02x\n", __func__, chip_id);
397 /* put sleep as chip seems to be in normal mode by default */
398 ret = e4000_wr_reg(priv, 0x00, 0x00);
402 dev_info(&priv->i2c->dev,
403 "%s: Elonics E4000 successfully identified\n",
406 fe->tuner_priv = priv;
407 memcpy(&fe->ops.tuner_ops, &e4000_tuner_ops,
408 sizeof(struct dvb_tuner_ops));
410 if (fe->ops.i2c_gate_ctrl)
411 fe->ops.i2c_gate_ctrl(fe, 0);
415 if (fe->ops.i2c_gate_ctrl)
416 fe->ops.i2c_gate_ctrl(fe, 0);
418 dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret);
422 EXPORT_SYMBOL(e4000_attach);
424 MODULE_DESCRIPTION("Elonics E4000 silicon tuner driver");
425 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
426 MODULE_LICENSE("GPL");