2 * V4L2 Driver for i.MX27 camera host
4 * Copyright (C) 2008, Sascha Hauer, Pengutronix
5 * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography
6 * Copyright (C) 2012, Javier Martin, Vista Silicon S.L.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/module.h>
17 #include <linux/delay.h>
18 #include <linux/slab.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/errno.h>
22 #include <linux/gcd.h>
23 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/math64.h>
27 #include <linux/moduleparam.h>
28 #include <linux/time.h>
29 #include <linux/device.h>
30 #include <linux/platform_device.h>
31 #include <linux/clk.h>
33 #include <media/v4l2-common.h>
34 #include <media/v4l2-dev.h>
35 #include <media/videobuf2-core.h>
36 #include <media/videobuf2-dma-contig.h>
37 #include <media/soc_camera.h>
38 #include <media/soc_mediabus.h>
40 #include <linux/videodev2.h>
42 #include <linux/platform_data/camera-mx2.h>
46 #define MX2_CAM_DRV_NAME "mx2-camera"
47 #define MX2_CAM_VERSION "0.0.6"
48 #define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera"
51 #define CSICR1_RESET_VAL 0x40000800
52 #define CSICR2_RESET_VAL 0x0
53 #define CSICR3_RESET_VAL 0x0
55 /* csi control reg 1 */
56 #define CSICR1_SWAP16_EN (1 << 31)
57 #define CSICR1_EXT_VSYNC (1 << 30)
58 #define CSICR1_EOF_INTEN (1 << 29)
59 #define CSICR1_PRP_IF_EN (1 << 28)
60 #define CSICR1_CCIR_MODE (1 << 27)
61 #define CSICR1_COF_INTEN (1 << 26)
62 #define CSICR1_SF_OR_INTEN (1 << 25)
63 #define CSICR1_RF_OR_INTEN (1 << 24)
64 #define CSICR1_STATFF_LEVEL (3 << 22)
65 #define CSICR1_STATFF_INTEN (1 << 21)
66 #define CSICR1_RXFF_LEVEL(l) (((l) & 3) << 19)
67 #define CSICR1_RXFF_INTEN (1 << 18)
68 #define CSICR1_SOF_POL (1 << 17)
69 #define CSICR1_SOF_INTEN (1 << 16)
70 #define CSICR1_MCLKDIV(d) (((d) & 0xF) << 12)
71 #define CSICR1_HSYNC_POL (1 << 11)
72 #define CSICR1_CCIR_EN (1 << 10)
73 #define CSICR1_MCLKEN (1 << 9)
74 #define CSICR1_FCC (1 << 8)
75 #define CSICR1_PACK_DIR (1 << 7)
76 #define CSICR1_CLR_STATFIFO (1 << 6)
77 #define CSICR1_CLR_RXFIFO (1 << 5)
78 #define CSICR1_GCLK_MODE (1 << 4)
79 #define CSICR1_INV_DATA (1 << 3)
80 #define CSICR1_INV_PCLK (1 << 2)
81 #define CSICR1_REDGE (1 << 1)
82 #define CSICR1_FMT_MASK (CSICR1_PACK_DIR | CSICR1_SWAP16_EN)
84 #define SHIFT_STATFF_LEVEL 22
85 #define SHIFT_RXFF_LEVEL 19
86 #define SHIFT_MCLKDIV 12
88 #define SHIFT_FRMCNT 16
93 #define CSISTATFIFO 0x0c
97 #define CSIDMASA_STATFIFO 0x20
98 #define CSIDMATA_STATFIFO 0x24
99 #define CSIDMASA_FB1 0x28
100 #define CSIDMASA_FB2 0x2c
101 #define CSIFBUF_PARA 0x30
102 #define CSIIMAG_PARA 0x34
105 #define PRP_CNTL 0x00
106 #define PRP_INTR_CNTL 0x04
107 #define PRP_INTRSTATUS 0x08
108 #define PRP_SOURCE_Y_PTR 0x0c
109 #define PRP_SOURCE_CB_PTR 0x10
110 #define PRP_SOURCE_CR_PTR 0x14
111 #define PRP_DEST_RGB1_PTR 0x18
112 #define PRP_DEST_RGB2_PTR 0x1c
113 #define PRP_DEST_Y_PTR 0x20
114 #define PRP_DEST_CB_PTR 0x24
115 #define PRP_DEST_CR_PTR 0x28
116 #define PRP_SRC_FRAME_SIZE 0x2c
117 #define PRP_DEST_CH1_LINE_STRIDE 0x30
118 #define PRP_SRC_PIXEL_FORMAT_CNTL 0x34
119 #define PRP_CH1_PIXEL_FORMAT_CNTL 0x38
120 #define PRP_CH1_OUT_IMAGE_SIZE 0x3c
121 #define PRP_CH2_OUT_IMAGE_SIZE 0x40
122 #define PRP_SRC_LINE_STRIDE 0x44
123 #define PRP_CSC_COEF_012 0x48
124 #define PRP_CSC_COEF_345 0x4c
125 #define PRP_CSC_COEF_678 0x50
126 #define PRP_CH1_RZ_HORI_COEF1 0x54
127 #define PRP_CH1_RZ_HORI_COEF2 0x58
128 #define PRP_CH1_RZ_HORI_VALID 0x5c
129 #define PRP_CH1_RZ_VERT_COEF1 0x60
130 #define PRP_CH1_RZ_VERT_COEF2 0x64
131 #define PRP_CH1_RZ_VERT_VALID 0x68
132 #define PRP_CH2_RZ_HORI_COEF1 0x6c
133 #define PRP_CH2_RZ_HORI_COEF2 0x70
134 #define PRP_CH2_RZ_HORI_VALID 0x74
135 #define PRP_CH2_RZ_VERT_COEF1 0x78
136 #define PRP_CH2_RZ_VERT_COEF2 0x7c
137 #define PRP_CH2_RZ_VERT_VALID 0x80
139 #define PRP_CNTL_CH1EN (1 << 0)
140 #define PRP_CNTL_CH2EN (1 << 1)
141 #define PRP_CNTL_CSIEN (1 << 2)
142 #define PRP_CNTL_DATA_IN_YUV420 (0 << 3)
143 #define PRP_CNTL_DATA_IN_YUV422 (1 << 3)
144 #define PRP_CNTL_DATA_IN_RGB16 (2 << 3)
145 #define PRP_CNTL_DATA_IN_RGB32 (3 << 3)
146 #define PRP_CNTL_CH1_OUT_RGB8 (0 << 5)
147 #define PRP_CNTL_CH1_OUT_RGB16 (1 << 5)
148 #define PRP_CNTL_CH1_OUT_RGB32 (2 << 5)
149 #define PRP_CNTL_CH1_OUT_YUV422 (3 << 5)
150 #define PRP_CNTL_CH2_OUT_YUV420 (0 << 7)
151 #define PRP_CNTL_CH2_OUT_YUV422 (1 << 7)
152 #define PRP_CNTL_CH2_OUT_YUV444 (2 << 7)
153 #define PRP_CNTL_CH1_LEN (1 << 9)
154 #define PRP_CNTL_CH2_LEN (1 << 10)
155 #define PRP_CNTL_SKIP_FRAME (1 << 11)
156 #define PRP_CNTL_SWRST (1 << 12)
157 #define PRP_CNTL_CLKEN (1 << 13)
158 #define PRP_CNTL_WEN (1 << 14)
159 #define PRP_CNTL_CH1BYP (1 << 15)
160 #define PRP_CNTL_IN_TSKIP(x) ((x) << 16)
161 #define PRP_CNTL_CH1_TSKIP(x) ((x) << 19)
162 #define PRP_CNTL_CH2_TSKIP(x) ((x) << 22)
163 #define PRP_CNTL_INPUT_FIFO_LEVEL(x) ((x) << 25)
164 #define PRP_CNTL_RZ_FIFO_LEVEL(x) ((x) << 27)
165 #define PRP_CNTL_CH2B1EN (1 << 29)
166 #define PRP_CNTL_CH2B2EN (1 << 30)
167 #define PRP_CNTL_CH2FEN (1 << 31)
169 /* IRQ Enable and status register */
170 #define PRP_INTR_RDERR (1 << 0)
171 #define PRP_INTR_CH1WERR (1 << 1)
172 #define PRP_INTR_CH2WERR (1 << 2)
173 #define PRP_INTR_CH1FC (1 << 3)
174 #define PRP_INTR_CH2FC (1 << 5)
175 #define PRP_INTR_LBOVF (1 << 7)
176 #define PRP_INTR_CH2OVF (1 << 8)
178 /* Resizing registers */
179 #define PRP_RZ_VALID_TBL_LEN(x) ((x) << 24)
180 #define PRP_RZ_VALID_BILINEAR (1 << 31)
182 #define MAX_VIDEO_MEM 16
184 #define RESIZE_NUM_MIN 1
185 #define RESIZE_NUM_MAX 20
187 #define SZ_COEF (1 << BC_COEF)
189 #define RESIZE_DIR_H 0
190 #define RESIZE_DIR_V 1
192 #define RESIZE_ALGO_BILINEAR 0
193 #define RESIZE_ALGO_AVERAGING 1
205 /* prp resizing parameters */
206 struct emma_prp_resize {
207 int algo; /* type of algorithm used */
208 int len; /* number of coefficients */
209 unsigned char s[RESIZE_NUM_MAX]; /* table of coefficients */
212 /* prp configuration for a client-host fmt pair */
214 enum v4l2_mbus_pixelcode in_fmt;
216 struct mx2_prp_cfg cfg;
219 struct mx2_buf_internal {
220 struct list_head queue;
225 /* buffer for one video frame */
227 /* common v4l buffer stuff -- must be first */
228 struct vb2_buffer vb;
229 struct mx2_buf_internal internal;
232 enum mx2_camera_type {
236 struct mx2_camera_dev {
238 struct soc_camera_host soc_host;
239 struct soc_camera_device *icd;
240 struct clk *clk_emma_ahb, *clk_emma_ipg;
241 struct clk *clk_csi_ahb, *clk_csi_per;
243 void __iomem *base_csi, *base_emma;
245 struct mx2_camera_platform_data *pdata;
246 unsigned long platform_flags;
248 struct list_head capture;
249 struct list_head active_bufs;
250 struct list_head discard;
255 struct mx2_buffer *active;
256 struct mx2_buffer *fb1_active;
257 struct mx2_buffer *fb2_active;
260 enum mx2_camera_type devtype;
262 struct mx2_buf_internal buf_discard[2];
263 void *discard_buffer;
264 dma_addr_t discard_buffer_dma;
266 struct mx2_fmt_cfg *emma_prp;
267 struct emma_prp_resize resizing[2];
268 unsigned int s_width, s_height;
270 struct vb2_alloc_ctx *alloc_ctx;
273 static struct platform_device_id mx2_camera_devtype[] = {
275 .name = "imx27-camera",
276 .driver_data = IMX27_CAMERA,
281 MODULE_DEVICE_TABLE(platform, mx2_camera_devtype);
283 static struct mx2_buffer *mx2_ibuf_to_buf(struct mx2_buf_internal *int_buf)
285 return container_of(int_buf, struct mx2_buffer, internal);
288 static struct mx2_fmt_cfg mx27_emma_prp_table[] = {
290 * This is a generic configuration which is valid for most
291 * prp input-output format combinations.
292 * We set the incoming and outgoing pixelformat to a
293 * 16 Bit wide format and adjust the bytesperline
294 * accordingly. With this configuration the inputdata
295 * will not be changed by the emma and could be any type
296 * of 16 Bit Pixelformat.
303 .in_fmt = PRP_CNTL_DATA_IN_RGB16,
304 .out_fmt = PRP_CNTL_CH1_OUT_RGB16,
305 .src_pixel = 0x2ca00565, /* RGB565 */
306 .ch1_pixel = 0x2ca00565, /* RGB565 */
307 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
308 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
313 .in_fmt = V4L2_MBUS_FMT_UYVY8_2X8,
314 .out_fmt = V4L2_PIX_FMT_YUYV,
317 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
318 .out_fmt = PRP_CNTL_CH1_OUT_YUV422,
319 .src_pixel = 0x22000888, /* YUV422 (YUYV) */
320 .ch1_pixel = 0x62000888, /* YUV422 (YUYV) */
321 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
322 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
323 .csicr1 = CSICR1_SWAP16_EN,
327 .in_fmt = V4L2_MBUS_FMT_YUYV8_2X8,
328 .out_fmt = V4L2_PIX_FMT_YUYV,
331 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
332 .out_fmt = PRP_CNTL_CH1_OUT_YUV422,
333 .src_pixel = 0x22000888, /* YUV422 (YUYV) */
334 .ch1_pixel = 0x62000888, /* YUV422 (YUYV) */
335 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
336 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
337 .csicr1 = CSICR1_PACK_DIR,
341 .in_fmt = V4L2_MBUS_FMT_YUYV8_2X8,
342 .out_fmt = V4L2_PIX_FMT_YUV420,
345 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
346 .out_fmt = PRP_CNTL_CH2_OUT_YUV420,
347 .src_pixel = 0x22000888, /* YUV422 (YUYV) */
348 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH2WERR |
349 PRP_INTR_CH2FC | PRP_INTR_LBOVF |
351 .csicr1 = CSICR1_PACK_DIR,
355 .in_fmt = V4L2_MBUS_FMT_UYVY8_2X8,
356 .out_fmt = V4L2_PIX_FMT_YUV420,
359 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
360 .out_fmt = PRP_CNTL_CH2_OUT_YUV420,
361 .src_pixel = 0x22000888, /* YUV422 (YUYV) */
362 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH2WERR |
363 PRP_INTR_CH2FC | PRP_INTR_LBOVF |
365 .csicr1 = CSICR1_SWAP16_EN,
370 static struct mx2_fmt_cfg *mx27_emma_prp_get_format(
371 enum v4l2_mbus_pixelcode in_fmt,
376 for (i = 1; i < ARRAY_SIZE(mx27_emma_prp_table); i++)
377 if ((mx27_emma_prp_table[i].in_fmt == in_fmt) &&
378 (mx27_emma_prp_table[i].out_fmt == out_fmt)) {
379 return &mx27_emma_prp_table[i];
381 /* If no match return the most generic configuration */
382 return &mx27_emma_prp_table[0];
385 static void mx27_update_emma_buf(struct mx2_camera_dev *pcdev,
386 unsigned long phys, int bufnum)
388 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
390 if (prp->cfg.channel == 1) {
391 writel(phys, pcdev->base_emma +
392 PRP_DEST_RGB1_PTR + 4 * bufnum);
394 writel(phys, pcdev->base_emma +
395 PRP_DEST_Y_PTR - 0x14 * bufnum);
396 if (prp->out_fmt == V4L2_PIX_FMT_YUV420) {
397 u32 imgsize = pcdev->icd->user_height *
398 pcdev->icd->user_width;
400 writel(phys + imgsize, pcdev->base_emma +
401 PRP_DEST_CB_PTR - 0x14 * bufnum);
402 writel(phys + ((5 * imgsize) / 4), pcdev->base_emma +
403 PRP_DEST_CR_PTR - 0x14 * bufnum);
408 static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev)
410 clk_disable_unprepare(pcdev->clk_csi_ahb);
411 clk_disable_unprepare(pcdev->clk_csi_per);
412 writel(0, pcdev->base_csi + CSICR1);
413 writel(0, pcdev->base_emma + PRP_CNTL);
417 * The following two functions absolutely depend on the fact, that
418 * there can be only one camera on mx2 camera sensor interface
420 static int mx2_camera_add_device(struct soc_camera_device *icd)
422 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
423 struct mx2_camera_dev *pcdev = ici->priv;
430 ret = clk_prepare_enable(pcdev->clk_csi_ahb);
434 ret = clk_prepare_enable(pcdev->clk_csi_per);
438 csicr1 = CSICR1_MCLKEN | CSICR1_PRP_IF_EN | CSICR1_FCC |
439 CSICR1_RXFF_LEVEL(0);
441 pcdev->csicr1 = csicr1;
442 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
445 pcdev->frame_count = 0;
447 dev_info(icd->parent, "Camera driver attached to camera %d\n",
453 clk_disable_unprepare(pcdev->clk_csi_ahb);
458 static void mx2_camera_remove_device(struct soc_camera_device *icd)
460 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
461 struct mx2_camera_dev *pcdev = ici->priv;
463 BUG_ON(icd != pcdev->icd);
465 dev_info(icd->parent, "Camera driver detached from camera %d\n",
468 mx2_camera_deactivate(pcdev);
474 * Videobuf operations
476 static int mx2_videobuf_setup(struct vb2_queue *vq,
477 const struct v4l2_format *fmt,
478 unsigned int *count, unsigned int *num_planes,
479 unsigned int sizes[], void *alloc_ctxs[])
481 struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
482 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
483 struct mx2_camera_dev *pcdev = ici->priv;
485 dev_dbg(icd->parent, "count=%d, size=%d\n", *count, sizes[0]);
487 /* TODO: support for VIDIOC_CREATE_BUFS not ready */
491 alloc_ctxs[0] = pcdev->alloc_ctx;
493 sizes[0] = icd->sizeimage;
498 sizes[0] * *count > MAX_VIDEO_MEM * 1024 * 1024)
499 *count = (MAX_VIDEO_MEM * 1024 * 1024) / sizes[0];
506 static int mx2_videobuf_prepare(struct vb2_buffer *vb)
508 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
511 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
512 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
516 * This can be useful if you want to see if we actually fill
517 * the buffer with something
519 memset((void *)vb2_plane_vaddr(vb, 0),
520 0xaa, vb2_get_plane_payload(vb, 0));
523 vb2_set_plane_payload(vb, 0, icd->sizeimage);
524 if (vb2_plane_vaddr(vb, 0) &&
525 vb2_get_plane_payload(vb, 0) > vb2_plane_size(vb, 0)) {
536 static void mx2_videobuf_queue(struct vb2_buffer *vb)
538 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
539 struct soc_camera_host *ici =
540 to_soc_camera_host(icd->parent);
541 struct mx2_camera_dev *pcdev = ici->priv;
542 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
545 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
546 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
548 spin_lock_irqsave(&pcdev->lock, flags);
550 list_add_tail(&buf->internal.queue, &pcdev->capture);
552 spin_unlock_irqrestore(&pcdev->lock, flags);
555 static void mx27_camera_emma_buf_init(struct soc_camera_device *icd,
558 struct soc_camera_host *ici =
559 to_soc_camera_host(icd->parent);
560 struct mx2_camera_dev *pcdev = ici->priv;
561 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
563 writel((pcdev->s_width << 16) | pcdev->s_height,
564 pcdev->base_emma + PRP_SRC_FRAME_SIZE);
565 writel(prp->cfg.src_pixel,
566 pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL);
567 if (prp->cfg.channel == 1) {
568 writel((icd->user_width << 16) | icd->user_height,
569 pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE);
571 pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE);
572 writel(prp->cfg.ch1_pixel,
573 pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL);
574 } else { /* channel 2 */
575 writel((icd->user_width << 16) | icd->user_height,
576 pcdev->base_emma + PRP_CH2_OUT_IMAGE_SIZE);
579 /* Enable interrupts */
580 writel(prp->cfg.irq_flags, pcdev->base_emma + PRP_INTR_CNTL);
583 static void mx2_prp_resize_commit(struct mx2_camera_dev *pcdev)
587 for (dir = RESIZE_DIR_H; dir <= RESIZE_DIR_V; dir++) {
588 unsigned char *s = pcdev->resizing[dir].s;
589 int len = pcdev->resizing[dir].len;
590 unsigned int coeff[2] = {0, 0};
591 unsigned int valid = 0;
597 for (i = RESIZE_NUM_MAX - 1; i >= 0; i--) {
601 coeff[j] = (coeff[j] << BC_COEF) |
602 (s[i] & (SZ_COEF - 1));
604 if (i == 5 || i == 15)
607 valid = (valid << 1) | (s[i] >> BC_COEF);
610 valid |= PRP_RZ_VALID_TBL_LEN(len);
612 if (pcdev->resizing[dir].algo == RESIZE_ALGO_BILINEAR)
613 valid |= PRP_RZ_VALID_BILINEAR;
615 if (pcdev->emma_prp->cfg.channel == 1) {
616 if (dir == RESIZE_DIR_H) {
617 writel(coeff[0], pcdev->base_emma +
618 PRP_CH1_RZ_HORI_COEF1);
619 writel(coeff[1], pcdev->base_emma +
620 PRP_CH1_RZ_HORI_COEF2);
621 writel(valid, pcdev->base_emma +
622 PRP_CH1_RZ_HORI_VALID);
624 writel(coeff[0], pcdev->base_emma +
625 PRP_CH1_RZ_VERT_COEF1);
626 writel(coeff[1], pcdev->base_emma +
627 PRP_CH1_RZ_VERT_COEF2);
628 writel(valid, pcdev->base_emma +
629 PRP_CH1_RZ_VERT_VALID);
632 if (dir == RESIZE_DIR_H) {
633 writel(coeff[0], pcdev->base_emma +
634 PRP_CH2_RZ_HORI_COEF1);
635 writel(coeff[1], pcdev->base_emma +
636 PRP_CH2_RZ_HORI_COEF2);
637 writel(valid, pcdev->base_emma +
638 PRP_CH2_RZ_HORI_VALID);
640 writel(coeff[0], pcdev->base_emma +
641 PRP_CH2_RZ_VERT_COEF1);
642 writel(coeff[1], pcdev->base_emma +
643 PRP_CH2_RZ_VERT_COEF2);
644 writel(valid, pcdev->base_emma +
645 PRP_CH2_RZ_VERT_VALID);
651 static int mx2_start_streaming(struct vb2_queue *q, unsigned int count)
653 struct soc_camera_device *icd = soc_camera_from_vb2q(q);
654 struct soc_camera_host *ici =
655 to_soc_camera_host(icd->parent);
656 struct mx2_camera_dev *pcdev = ici->priv;
657 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
658 struct vb2_buffer *vb;
659 struct mx2_buffer *buf;
667 spin_lock_irqsave(&pcdev->lock, flags);
669 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
671 buf->internal.bufnum = 0;
674 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
675 mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum);
676 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
678 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
680 buf->internal.bufnum = 1;
683 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
684 mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum);
685 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
687 bytesperline = soc_mbus_bytes_per_line(icd->user_width,
688 icd->current_fmt->host_fmt);
689 if (bytesperline < 0) {
690 spin_unlock_irqrestore(&pcdev->lock, flags);
695 * I didn't manage to properly enable/disable the prp
696 * on a per frame basis during running transfers,
697 * thus we allocate a buffer here and use it to
698 * discard frames when no buffer is available.
699 * Feel free to work on this ;)
701 pcdev->discard_size = icd->user_height * bytesperline;
702 pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev,
704 &pcdev->discard_buffer_dma, GFP_ATOMIC);
705 if (!pcdev->discard_buffer) {
706 spin_unlock_irqrestore(&pcdev->lock, flags);
710 pcdev->buf_discard[0].discard = true;
711 list_add_tail(&pcdev->buf_discard[0].queue,
714 pcdev->buf_discard[1].discard = true;
715 list_add_tail(&pcdev->buf_discard[1].queue,
718 mx2_prp_resize_commit(pcdev);
720 mx27_camera_emma_buf_init(icd, bytesperline);
722 if (prp->cfg.channel == 1) {
723 writel(PRP_CNTL_CH1EN |
729 PRP_CNTL_CH1_TSKIP(0) |
730 PRP_CNTL_IN_TSKIP(0),
731 pcdev->base_emma + PRP_CNTL);
733 writel(PRP_CNTL_CH2EN |
738 PRP_CNTL_CH2_TSKIP(0) |
739 PRP_CNTL_IN_TSKIP(0),
740 pcdev->base_emma + PRP_CNTL);
742 spin_unlock_irqrestore(&pcdev->lock, flags);
747 static int mx2_stop_streaming(struct vb2_queue *q)
749 struct soc_camera_device *icd = soc_camera_from_vb2q(q);
750 struct soc_camera_host *ici =
751 to_soc_camera_host(icd->parent);
752 struct mx2_camera_dev *pcdev = ici->priv;
753 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
758 spin_lock_irqsave(&pcdev->lock, flags);
760 cntl = readl(pcdev->base_emma + PRP_CNTL);
761 if (prp->cfg.channel == 1) {
762 writel(cntl & ~PRP_CNTL_CH1EN,
763 pcdev->base_emma + PRP_CNTL);
765 writel(cntl & ~PRP_CNTL_CH2EN,
766 pcdev->base_emma + PRP_CNTL);
768 INIT_LIST_HEAD(&pcdev->capture);
769 INIT_LIST_HEAD(&pcdev->active_bufs);
770 INIT_LIST_HEAD(&pcdev->discard);
772 b = pcdev->discard_buffer;
773 pcdev->discard_buffer = NULL;
775 spin_unlock_irqrestore(&pcdev->lock, flags);
777 dma_free_coherent(ici->v4l2_dev.dev,
778 pcdev->discard_size, b, pcdev->discard_buffer_dma);
783 static struct vb2_ops mx2_videobuf_ops = {
784 .queue_setup = mx2_videobuf_setup,
785 .buf_prepare = mx2_videobuf_prepare,
786 .buf_queue = mx2_videobuf_queue,
787 .start_streaming = mx2_start_streaming,
788 .stop_streaming = mx2_stop_streaming,
791 static int mx2_camera_init_videobuf(struct vb2_queue *q,
792 struct soc_camera_device *icd)
794 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
795 q->io_modes = VB2_MMAP | VB2_USERPTR;
797 q->ops = &mx2_videobuf_ops;
798 q->mem_ops = &vb2_dma_contig_memops;
799 q->buf_struct_size = sizeof(struct mx2_buffer);
801 return vb2_queue_init(q);
804 #define MX2_BUS_FLAGS (V4L2_MBUS_MASTER | \
805 V4L2_MBUS_VSYNC_ACTIVE_HIGH | \
806 V4L2_MBUS_VSYNC_ACTIVE_LOW | \
807 V4L2_MBUS_HSYNC_ACTIVE_HIGH | \
808 V4L2_MBUS_HSYNC_ACTIVE_LOW | \
809 V4L2_MBUS_PCLK_SAMPLE_RISING | \
810 V4L2_MBUS_PCLK_SAMPLE_FALLING | \
811 V4L2_MBUS_DATA_ACTIVE_HIGH | \
812 V4L2_MBUS_DATA_ACTIVE_LOW)
814 static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev)
819 cntl = readl(pcdev->base_emma + PRP_CNTL);
820 writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL);
821 while (count++ < 100) {
822 if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST))
831 static int mx2_camera_set_bus_param(struct soc_camera_device *icd)
833 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
834 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
835 struct mx2_camera_dev *pcdev = ici->priv;
836 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
837 unsigned long common_flags;
840 u32 csicr1 = pcdev->csicr1;
842 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
844 common_flags = soc_mbus_config_compatible(&cfg, MX2_BUS_FLAGS);
846 dev_warn(icd->parent,
847 "Flags incompatible: camera 0x%x, host 0x%x\n",
848 cfg.flags, MX2_BUS_FLAGS);
851 } else if (ret != -ENOIOCTLCMD) {
854 common_flags = MX2_BUS_FLAGS;
857 if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
858 (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
859 if (pcdev->platform_flags & MX2_CAMERA_HSYNC_HIGH)
860 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
862 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
865 if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
866 (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
867 if (pcdev->platform_flags & MX2_CAMERA_PCLK_SAMPLE_RISING)
868 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
870 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
873 cfg.flags = common_flags;
874 ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg);
875 if (ret < 0 && ret != -ENOIOCTLCMD) {
876 dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n",
881 csicr1 = (csicr1 & ~CSICR1_FMT_MASK) | pcdev->emma_prp->cfg.csicr1;
883 if (common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
884 csicr1 |= CSICR1_REDGE;
885 if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
886 csicr1 |= CSICR1_SOF_POL;
887 if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
888 csicr1 |= CSICR1_HSYNC_POL;
889 if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC)
890 csicr1 |= CSICR1_EXT_VSYNC;
891 if (pcdev->platform_flags & MX2_CAMERA_CCIR)
892 csicr1 |= CSICR1_CCIR_EN;
893 if (pcdev->platform_flags & MX2_CAMERA_CCIR_INTERLACE)
894 csicr1 |= CSICR1_CCIR_MODE;
895 if (pcdev->platform_flags & MX2_CAMERA_GATED_CLOCK)
896 csicr1 |= CSICR1_GCLK_MODE;
897 if (pcdev->platform_flags & MX2_CAMERA_INV_DATA)
898 csicr1 |= CSICR1_INV_DATA;
900 pcdev->csicr1 = csicr1;
902 bytesperline = soc_mbus_bytes_per_line(icd->user_width,
903 icd->current_fmt->host_fmt);
904 if (bytesperline < 0)
907 ret = mx27_camera_emma_prp_reset(pcdev);
911 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
916 static int mx2_camera_set_crop(struct soc_camera_device *icd,
917 const struct v4l2_crop *a)
919 struct v4l2_crop a_writable = *a;
920 struct v4l2_rect *rect = &a_writable.c;
921 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
922 struct v4l2_mbus_framefmt mf;
925 soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096);
926 soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096);
928 ret = v4l2_subdev_call(sd, video, s_crop, a);
932 /* The capture device might have changed its output */
933 ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf);
937 dev_dbg(icd->parent, "Sensor cropped %dx%d\n",
938 mf.width, mf.height);
940 icd->user_width = mf.width;
941 icd->user_height = mf.height;
946 static int mx2_camera_get_formats(struct soc_camera_device *icd,
948 struct soc_camera_format_xlate *xlate)
950 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
951 const struct soc_mbus_pixelfmt *fmt;
952 struct device *dev = icd->parent;
953 enum v4l2_mbus_pixelcode code;
954 int ret, formats = 0;
956 ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code);
958 /* no more formats */
961 fmt = soc_mbus_get_fmtdesc(code);
963 dev_err(dev, "Invalid format code #%u: %d\n", idx, code);
967 if (code == V4L2_MBUS_FMT_YUYV8_2X8 ||
968 code == V4L2_MBUS_FMT_UYVY8_2X8) {
972 * CH2 can output YUV420 which is a standard format in
976 soc_mbus_get_fmtdesc(V4L2_MBUS_FMT_YUYV8_1_5X8);
978 dev_dbg(dev, "Providing host format %s for sensor code %d\n",
979 xlate->host_fmt->name, code);
984 if (code == V4L2_MBUS_FMT_UYVY8_2X8) {
988 soc_mbus_get_fmtdesc(V4L2_MBUS_FMT_YUYV8_2X8);
990 dev_dbg(dev, "Providing host format %s for sensor code %d\n",
991 xlate->host_fmt->name, code);
996 /* Generic pass-trough */
999 xlate->host_fmt = fmt;
1006 static int mx2_emmaprp_resize(struct mx2_camera_dev *pcdev,
1007 struct v4l2_mbus_framefmt *mf_in,
1008 struct v4l2_pix_format *pix_out, bool apply)
1014 for (dir = RESIZE_DIR_H; dir <= RESIZE_DIR_V; dir++) {
1015 struct emma_prp_resize tmprsz;
1016 unsigned char *s = tmprsz.s;
1020 if (dir == RESIZE_DIR_H) {
1022 out = pix_out->width;
1025 out = pix_out->height;
1033 /* Calculate ratio */
1037 if (num > RESIZE_NUM_MAX)
1040 if ((num >= 2 * den) && (den == 1) &&
1041 (num < 9) && (!(num & 0x01))) {
1045 /* Average scaling for >= 2:1 ratios */
1046 /* Support can be added for num >=9 and odd values */
1048 tmprsz.algo = RESIZE_ALGO_AVERAGING;
1051 for (i = 0; i < (len / 2); i++)
1055 for (i = 0; i < (len / 2); i++) {
1058 for (j = 0; j < (len / 2); j++)
1065 for (i = (len / 2); i < len; i++)
1066 s[i] = s[len - i - 1];
1068 s[len - 1] |= SZ_COEF;
1070 /* bilinear scaling for < 2:1 ratios */
1071 int v; /* overflow counter */
1072 int coeff, nxt; /* table output */
1073 int in_pos_inc = 2 * den;
1075 int out_pos_inc = 2 * num;
1076 int init_carry = num - den;
1077 int carry = init_carry;
1079 tmprsz.algo = RESIZE_ALGO_BILINEAR;
1080 v = den + in_pos_inc;
1082 coeff = v - out_pos;
1083 out_pos += out_pos_inc;
1084 carry += out_pos_inc;
1085 for (nxt = 0; v < out_pos; nxt++) {
1087 carry -= in_pos_inc;
1090 if (len > RESIZE_NUM_MAX)
1093 coeff = ((coeff << BC_COEF) +
1094 (in_pos_inc >> 1)) / in_pos_inc;
1096 if (coeff >= (SZ_COEF - 1))
1100 s[len] = (unsigned char)coeff;
1103 for (i = 1; i < nxt; i++) {
1104 if (len >= RESIZE_NUM_MAX)
1109 } while (carry != init_carry);
1112 if (dir == RESIZE_DIR_H)
1113 mf_in->width = pix_out->width;
1115 mf_in->height = pix_out->height;
1118 memcpy(&pcdev->resizing[dir], &tmprsz, sizeof(tmprsz));
1123 static int mx2_camera_set_fmt(struct soc_camera_device *icd,
1124 struct v4l2_format *f)
1126 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1127 struct mx2_camera_dev *pcdev = ici->priv;
1128 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1129 const struct soc_camera_format_xlate *xlate;
1130 struct v4l2_pix_format *pix = &f->fmt.pix;
1131 struct v4l2_mbus_framefmt mf;
1134 dev_dbg(icd->parent, "%s: requested params: width = %d, height = %d\n",
1135 __func__, pix->width, pix->height);
1137 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1139 dev_warn(icd->parent, "Format %x not found\n",
1144 mf.width = pix->width;
1145 mf.height = pix->height;
1146 mf.field = pix->field;
1147 mf.colorspace = pix->colorspace;
1148 mf.code = xlate->code;
1150 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
1151 if (ret < 0 && ret != -ENOIOCTLCMD)
1154 /* Store width and height returned by the sensor for resizing */
1155 pcdev->s_width = mf.width;
1156 pcdev->s_height = mf.height;
1157 dev_dbg(icd->parent, "%s: sensor params: width = %d, height = %d\n",
1158 __func__, pcdev->s_width, pcdev->s_height);
1160 pcdev->emma_prp = mx27_emma_prp_get_format(xlate->code,
1161 xlate->host_fmt->fourcc);
1163 memset(pcdev->resizing, 0, sizeof(pcdev->resizing));
1164 if ((mf.width != pix->width || mf.height != pix->height) &&
1165 pcdev->emma_prp->cfg.in_fmt == PRP_CNTL_DATA_IN_YUV422) {
1166 if (mx2_emmaprp_resize(pcdev, &mf, pix, true) < 0)
1167 dev_dbg(icd->parent, "%s: can't resize\n", __func__);
1170 if (mf.code != xlate->code)
1173 pix->width = mf.width;
1174 pix->height = mf.height;
1175 pix->field = mf.field;
1176 pix->colorspace = mf.colorspace;
1177 icd->current_fmt = xlate;
1179 dev_dbg(icd->parent, "%s: returned params: width = %d, height = %d\n",
1180 __func__, pix->width, pix->height);
1185 static int mx2_camera_try_fmt(struct soc_camera_device *icd,
1186 struct v4l2_format *f)
1188 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1189 const struct soc_camera_format_xlate *xlate;
1190 struct v4l2_pix_format *pix = &f->fmt.pix;
1191 struct v4l2_mbus_framefmt mf;
1192 __u32 pixfmt = pix->pixelformat;
1193 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1194 struct mx2_camera_dev *pcdev = ici->priv;
1195 struct mx2_fmt_cfg *emma_prp;
1198 dev_dbg(icd->parent, "%s: requested params: width = %d, height = %d\n",
1199 __func__, pix->width, pix->height);
1201 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1202 if (pixfmt && !xlate) {
1203 dev_warn(icd->parent, "Format %x not found\n", pixfmt);
1208 * limit to MX27 hardware capabilities: width must be a multiple of 8 as
1209 * requested by the CSI. (Table 39-2 in the i.MX27 Reference Manual).
1213 /* limit to sensor capabilities */
1214 mf.width = pix->width;
1215 mf.height = pix->height;
1216 mf.field = pix->field;
1217 mf.colorspace = pix->colorspace;
1218 mf.code = xlate->code;
1220 ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
1224 dev_dbg(icd->parent, "%s: sensor params: width = %d, height = %d\n",
1225 __func__, pcdev->s_width, pcdev->s_height);
1227 /* If the sensor does not support image size try PrP resizing */
1228 emma_prp = mx27_emma_prp_get_format(xlate->code,
1229 xlate->host_fmt->fourcc);
1231 if ((mf.width != pix->width || mf.height != pix->height) &&
1232 emma_prp->cfg.in_fmt == PRP_CNTL_DATA_IN_YUV422) {
1233 if (mx2_emmaprp_resize(pcdev, &mf, pix, false) < 0)
1234 dev_dbg(icd->parent, "%s: can't resize\n", __func__);
1237 if (mf.field == V4L2_FIELD_ANY)
1238 mf.field = V4L2_FIELD_NONE;
1240 * Driver supports interlaced images provided they have
1241 * both fields so that they can be processed as if they
1244 if (mf.field != V4L2_FIELD_NONE && !V4L2_FIELD_HAS_BOTH(mf.field)) {
1245 dev_err(icd->parent, "Field type %d unsupported.\n",
1250 pix->width = mf.width;
1251 pix->height = mf.height;
1252 pix->field = mf.field;
1253 pix->colorspace = mf.colorspace;
1255 dev_dbg(icd->parent, "%s: returned params: width = %d, height = %d\n",
1256 __func__, pix->width, pix->height);
1261 static int mx2_camera_querycap(struct soc_camera_host *ici,
1262 struct v4l2_capability *cap)
1264 /* cap->name is set by the friendly caller:-> */
1265 strlcpy(cap->card, MX2_CAM_DRIVER_DESCRIPTION, sizeof(cap->card));
1266 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1271 static unsigned int mx2_camera_poll(struct file *file, poll_table *pt)
1273 struct soc_camera_device *icd = file->private_data;
1275 return vb2_poll(&icd->vb2_vidq, file, pt);
1278 static struct soc_camera_host_ops mx2_soc_camera_host_ops = {
1279 .owner = THIS_MODULE,
1280 .add = mx2_camera_add_device,
1281 .remove = mx2_camera_remove_device,
1282 .set_fmt = mx2_camera_set_fmt,
1283 .set_crop = mx2_camera_set_crop,
1284 .get_formats = mx2_camera_get_formats,
1285 .try_fmt = mx2_camera_try_fmt,
1286 .init_videobuf2 = mx2_camera_init_videobuf,
1287 .poll = mx2_camera_poll,
1288 .querycap = mx2_camera_querycap,
1289 .set_bus_param = mx2_camera_set_bus_param,
1292 static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev,
1293 int bufnum, bool err)
1296 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
1298 struct mx2_buf_internal *ibuf;
1299 struct mx2_buffer *buf;
1300 struct vb2_buffer *vb;
1303 ibuf = list_first_entry(&pcdev->active_bufs, struct mx2_buf_internal,
1306 BUG_ON(ibuf->bufnum != bufnum);
1308 if (ibuf->discard) {
1310 * Discard buffer must not be returned to user space.
1311 * Just return it to the discard queue.
1313 list_move_tail(pcdev->active_bufs.next, &pcdev->discard);
1315 buf = mx2_ibuf_to_buf(ibuf);
1319 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
1320 if (prp->cfg.channel == 1) {
1321 if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR +
1322 4 * bufnum) != phys) {
1323 dev_err(pcdev->dev, "%lx != %x\n", phys,
1324 readl(pcdev->base_emma +
1325 PRP_DEST_RGB1_PTR + 4 * bufnum));
1328 if (readl(pcdev->base_emma + PRP_DEST_Y_PTR -
1329 0x14 * bufnum) != phys) {
1330 dev_err(pcdev->dev, "%lx != %x\n", phys,
1331 readl(pcdev->base_emma +
1332 PRP_DEST_Y_PTR - 0x14 * bufnum));
1336 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__, vb,
1337 vb2_plane_vaddr(vb, 0),
1338 vb2_get_plane_payload(vb, 0));
1340 list_del_init(&buf->internal.queue);
1341 v4l2_get_timestamp(&vb->v4l2_buf.timestamp);
1342 vb->v4l2_buf.sequence = pcdev->frame_count;
1344 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
1346 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
1349 pcdev->frame_count++;
1351 if (list_empty(&pcdev->capture)) {
1352 if (list_empty(&pcdev->discard)) {
1353 dev_warn(pcdev->dev, "%s: trying to access empty discard list\n",
1358 ibuf = list_first_entry(&pcdev->discard,
1359 struct mx2_buf_internal, queue);
1360 ibuf->bufnum = bufnum;
1362 list_move_tail(pcdev->discard.next, &pcdev->active_bufs);
1363 mx27_update_emma_buf(pcdev, pcdev->discard_buffer_dma, bufnum);
1367 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
1370 buf->internal.bufnum = bufnum;
1372 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
1376 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
1377 mx27_update_emma_buf(pcdev, phys, bufnum);
1380 static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data)
1382 struct mx2_camera_dev *pcdev = data;
1383 unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS);
1384 struct mx2_buf_internal *ibuf;
1386 spin_lock(&pcdev->lock);
1388 if (list_empty(&pcdev->active_bufs)) {
1389 dev_warn(pcdev->dev, "%s: called while active list is empty\n",
1393 spin_unlock(&pcdev->lock);
1398 if (status & (1 << 7)) { /* overflow */
1399 u32 cntl = readl(pcdev->base_emma + PRP_CNTL);
1400 writel(cntl & ~(PRP_CNTL_CH1EN | PRP_CNTL_CH2EN),
1401 pcdev->base_emma + PRP_CNTL);
1402 writel(cntl, pcdev->base_emma + PRP_CNTL);
1404 ibuf = list_first_entry(&pcdev->active_bufs,
1405 struct mx2_buf_internal, queue);
1406 mx27_camera_frame_done_emma(pcdev,
1407 ibuf->bufnum, true);
1409 status &= ~(1 << 7);
1410 } else if (((status & (3 << 5)) == (3 << 5)) ||
1411 ((status & (3 << 3)) == (3 << 3))) {
1413 * Both buffers have triggered, process the one we're expecting
1416 ibuf = list_first_entry(&pcdev->active_bufs,
1417 struct mx2_buf_internal, queue);
1418 mx27_camera_frame_done_emma(pcdev, ibuf->bufnum, false);
1419 status &= ~(1 << (6 - ibuf->bufnum)); /* mark processed */
1420 } else if ((status & (1 << 6)) || (status & (1 << 4))) {
1421 mx27_camera_frame_done_emma(pcdev, 0, false);
1422 } else if ((status & (1 << 5)) || (status & (1 << 3))) {
1423 mx27_camera_frame_done_emma(pcdev, 1, false);
1426 spin_unlock(&pcdev->lock);
1427 writel(status, pcdev->base_emma + PRP_INTRSTATUS);
1432 static int mx27_camera_emma_init(struct platform_device *pdev)
1434 struct mx2_camera_dev *pcdev = platform_get_drvdata(pdev);
1435 struct resource *res_emma;
1439 res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1440 irq_emma = platform_get_irq(pdev, 1);
1441 if (!res_emma || !irq_emma) {
1442 dev_err(pcdev->dev, "no EMMA resources\n");
1447 pcdev->base_emma = devm_ioremap_resource(pcdev->dev, res_emma);
1448 if (IS_ERR(pcdev->base_emma)) {
1449 err = PTR_ERR(pcdev->base_emma);
1453 err = devm_request_irq(pcdev->dev, irq_emma, mx27_camera_emma_irq, 0,
1454 MX2_CAM_DRV_NAME, pcdev);
1456 dev_err(pcdev->dev, "Camera EMMA interrupt register failed \n");
1460 pcdev->clk_emma_ipg = devm_clk_get(pcdev->dev, "emma-ipg");
1461 if (IS_ERR(pcdev->clk_emma_ipg)) {
1462 err = PTR_ERR(pcdev->clk_emma_ipg);
1466 clk_prepare_enable(pcdev->clk_emma_ipg);
1468 pcdev->clk_emma_ahb = devm_clk_get(pcdev->dev, "emma-ahb");
1469 if (IS_ERR(pcdev->clk_emma_ahb)) {
1470 err = PTR_ERR(pcdev->clk_emma_ahb);
1471 goto exit_clk_emma_ipg;
1474 clk_prepare_enable(pcdev->clk_emma_ahb);
1476 err = mx27_camera_emma_prp_reset(pcdev);
1478 goto exit_clk_emma_ahb;
1483 clk_disable_unprepare(pcdev->clk_emma_ahb);
1485 clk_disable_unprepare(pcdev->clk_emma_ipg);
1490 static int mx2_camera_probe(struct platform_device *pdev)
1492 struct mx2_camera_dev *pcdev;
1493 struct resource *res_csi;
1497 dev_dbg(&pdev->dev, "initialising\n");
1499 res_csi = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1500 irq_csi = platform_get_irq(pdev, 0);
1501 if (res_csi == NULL || irq_csi < 0) {
1502 dev_err(&pdev->dev, "Missing platform resources data\n");
1507 pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL);
1509 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1514 pcdev->clk_csi_ahb = devm_clk_get(&pdev->dev, "ahb");
1515 if (IS_ERR(pcdev->clk_csi_ahb)) {
1516 dev_err(&pdev->dev, "Could not get csi ahb clock\n");
1517 err = PTR_ERR(pcdev->clk_csi_ahb);
1521 pcdev->clk_csi_per = devm_clk_get(&pdev->dev, "per");
1522 if (IS_ERR(pcdev->clk_csi_per)) {
1523 dev_err(&pdev->dev, "Could not get csi per clock\n");
1524 err = PTR_ERR(pcdev->clk_csi_per);
1528 pcdev->pdata = pdev->dev.platform_data;
1532 pcdev->platform_flags = pcdev->pdata->flags;
1534 rate = clk_round_rate(pcdev->clk_csi_per,
1535 pcdev->pdata->clk * 2);
1540 err = clk_set_rate(pcdev->clk_csi_per, rate);
1545 INIT_LIST_HEAD(&pcdev->capture);
1546 INIT_LIST_HEAD(&pcdev->active_bufs);
1547 INIT_LIST_HEAD(&pcdev->discard);
1548 spin_lock_init(&pcdev->lock);
1550 pcdev->base_csi = devm_ioremap_resource(&pdev->dev, res_csi);
1551 if (IS_ERR(pcdev->base_csi)) {
1552 err = PTR_ERR(pcdev->base_csi);
1556 pcdev->dev = &pdev->dev;
1557 platform_set_drvdata(pdev, pcdev);
1559 err = mx27_camera_emma_init(pdev);
1564 * We're done with drvdata here. Clear the pointer so that
1565 * v4l2 core can start using drvdata on its purpose.
1567 platform_set_drvdata(pdev, NULL);
1569 pcdev->soc_host.drv_name = MX2_CAM_DRV_NAME,
1570 pcdev->soc_host.ops = &mx2_soc_camera_host_ops,
1571 pcdev->soc_host.priv = pcdev;
1572 pcdev->soc_host.v4l2_dev.dev = &pdev->dev;
1573 pcdev->soc_host.nr = pdev->id;
1575 pcdev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1576 if (IS_ERR(pcdev->alloc_ctx)) {
1577 err = PTR_ERR(pcdev->alloc_ctx);
1580 err = soc_camera_host_register(&pcdev->soc_host);
1582 goto exit_free_emma;
1584 dev_info(&pdev->dev, "MX2 Camera (CSI) driver probed, clock frequency: %ld\n",
1585 clk_get_rate(pcdev->clk_csi_per));
1590 vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx);
1592 clk_disable_unprepare(pcdev->clk_emma_ipg);
1593 clk_disable_unprepare(pcdev->clk_emma_ahb);
1598 static int mx2_camera_remove(struct platform_device *pdev)
1600 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1601 struct mx2_camera_dev *pcdev = container_of(soc_host,
1602 struct mx2_camera_dev, soc_host);
1604 soc_camera_host_unregister(&pcdev->soc_host);
1606 vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx);
1608 clk_disable_unprepare(pcdev->clk_emma_ipg);
1609 clk_disable_unprepare(pcdev->clk_emma_ahb);
1611 dev_info(&pdev->dev, "MX2 Camera driver unloaded\n");
1616 static struct platform_driver mx2_camera_driver = {
1618 .name = MX2_CAM_DRV_NAME,
1620 .id_table = mx2_camera_devtype,
1621 .remove = mx2_camera_remove,
1622 .probe = mx2_camera_probe,
1625 module_platform_driver(mx2_camera_driver);
1627 MODULE_DESCRIPTION("i.MX27 SoC Camera Host driver");
1628 MODULE_AUTHOR("Sascha Hauer <sha@pengutronix.de>");
1629 MODULE_LICENSE("GPL");
1630 MODULE_VERSION(MX2_CAM_VERSION);