drivers/media/platform/s5p-mfc/s5p_mfc.c

   1 /*
   2  * Samsung S5P Multi Format Codec v 5.1
   3  *
   4  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
   5  * Kamil Debski, <k.debski@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/delay.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <linux/module.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/sched.h>
  20 #include <linux/slab.h>
  21 #include <linux/videodev2.h>
  22 #include <media/v4l2-event.h>
  23 #include <linux/workqueue.h>
  24 #include <linux/of.h>
  25 #include <media/videobuf2-v4l2.h>
  26 #include "s5p_mfc_common.h"
  27 #include "s5p_mfc_ctrl.h"
  28 #include "s5p_mfc_debug.h"
  29 #include "s5p_mfc_dec.h"
  30 #include "s5p_mfc_enc.h"
  31 #include "s5p_mfc_intr.h"
  32 #include "s5p_mfc_opr.h"
  33 #include "s5p_mfc_cmd.h"
  34 #include "s5p_mfc_pm.h"
  35
  36 #define S5P_MFC_NAME            "s5p-mfc"
  37 #define S5P_MFC_DEC_NAME        "s5p-mfc-dec"
  38 #define S5P_MFC_ENC_NAME        "s5p-mfc-enc"
  39
  40 int mfc_debug_level;
  41 module_param_named(debug, mfc_debug_level, int, S_IRUGO | S_IWUSR);
  42 MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages");
  43
  44 /* Helper functions for interrupt processing */
  45
  46 /* Remove from hw execution round robin */
  47 void clear_work_bit(struct s5p_mfc_ctx *ctx)
  48 {
  49         struct s5p_mfc_dev *dev = ctx->dev;
  50
  51         spin_lock(&dev->condlock);
  52         __clear_bit(ctx->num, &dev->ctx_work_bits);
  53         spin_unlock(&dev->condlock);
  54 }
  55
  56 /* Add to hw execution round robin */
  57 void set_work_bit(struct s5p_mfc_ctx *ctx)
  58 {
  59         struct s5p_mfc_dev *dev = ctx->dev;
  60
  61         spin_lock(&dev->condlock);
  62         __set_bit(ctx->num, &dev->ctx_work_bits);
  63         spin_unlock(&dev->condlock);
  64 }
  65
  66 /* Remove from hw execution round robin */
  67 void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
  68 {
  69         struct s5p_mfc_dev *dev = ctx->dev;
  70         unsigned long flags;
  71
  72         spin_lock_irqsave(&dev->condlock, flags);
  73         __clear_bit(ctx->num, &dev->ctx_work_bits);
  74         spin_unlock_irqrestore(&dev->condlock, flags);
  75 }
  76
  77 /* Add to hw execution round robin */
  78 void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
  79 {
  80         struct s5p_mfc_dev *dev = ctx->dev;
  81         unsigned long flags;
  82
  83         spin_lock_irqsave(&dev->condlock, flags);
  84         __set_bit(ctx->num, &dev->ctx_work_bits);
  85         spin_unlock_irqrestore(&dev->condlock, flags);
  86 }
  87
  88 /* Wake up context wait_queue */
  89 static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason,
  90                         unsigned int err)
  91 {
  92         ctx->int_cond = 1;
  93         ctx->int_type = reason;
  94         ctx->int_err = err;
  95         wake_up(&ctx->queue);
  96 }
  97
  98 /* Wake up device wait_queue */
  99 static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason,
 100                         unsigned int err)
 101 {
 102         dev->int_cond = 1;
 103         dev->int_type = reason;
 104         dev->int_err = err;
 105         wake_up(&dev->queue);
 106 }
 107
 108 static void s5p_mfc_watchdog(unsigned long arg)
 109 {
 110         struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg;
 111
 112         if (test_bit(0, &dev->hw_lock))
 113                 atomic_inc(&dev->watchdog_cnt);
 114         if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) {
 115                 /* This means that hw is busy and no interrupts were
 116                  * generated by hw for the Nth time of running this
 117                  * watchdog timer. This usually means a serious hw
 118                  * error. Now it is time to kill all instances and
 119                  * reset the MFC. */
 120                 mfc_err("Time out during waiting for HW\n");
 121                 queue_work(dev->watchdog_workqueue, &dev->watchdog_work);
 122         }
 123         dev->watchdog_timer.expires = jiffies +
 124                                         msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
 125         add_timer(&dev->watchdog_timer);
 126 }
 127
 128 static void s5p_mfc_watchdog_worker(struct work_struct *work)
 129 {
 130         struct s5p_mfc_dev *dev;
 131         struct s5p_mfc_ctx *ctx;
 132         unsigned long flags;
 133         int mutex_locked;
 134         int i, ret;
 135
 136         dev = container_of(work, struct s5p_mfc_dev, watchdog_work);
 137
 138         mfc_err("Driver timeout error handling\n");
 139         /* Lock the mutex that protects open and release.
 140          * This is necessary as they may load and unload firmware. */
 141         mutex_locked = mutex_trylock(&dev->mfc_mutex);
 142         if (!mutex_locked)
 143                 mfc_err("Error: some instance may be closing/opening\n");
 144         spin_lock_irqsave(&dev->irqlock, flags);
 145
 146         s5p_mfc_clock_off();
 147
 148         for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
 149                 ctx = dev->ctx[i];
 150                 if (!ctx)
 151                         continue;
 152                 ctx->state = MFCINST_ERROR;
 153                 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
 154                                                 &ctx->dst_queue, &ctx->vq_dst);
 155                 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
 156                                                 &ctx->src_queue, &ctx->vq_src);
 157                 clear_work_bit(ctx);
 158                 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0);
 159         }
 160         clear_bit(0, &dev->hw_lock);
 161         spin_unlock_irqrestore(&dev->irqlock, flags);
 162
 163         /* De-init MFC */
 164         s5p_mfc_deinit_hw(dev);
 165
 166         /* Double check if there is at least one instance running.
 167          * If no instance is in memory than no firmware should be present */
 168         if (dev->num_inst > 0) {
 169                 ret = s5p_mfc_load_firmware(dev);
 170                 if (ret) {
 171                         mfc_err("Failed to reload FW\n");
 172                         goto unlock;
 173                 }
 174                 s5p_mfc_clock_on();
 175                 ret = s5p_mfc_init_hw(dev);
 176                 if (ret)
 177                         mfc_err("Failed to reinit FW\n");
 178         }
 179 unlock:
 180         if (mutex_locked)
 181                 mutex_unlock(&dev->mfc_mutex);
 182 }
 183
 184 static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
 185 {
 186         struct s5p_mfc_buf *dst_buf;
 187         struct s5p_mfc_dev *dev = ctx->dev;
 188
 189         ctx->state = MFCINST_FINISHED;
 190         ctx->sequence++;
 191         while (!list_empty(&ctx->dst_queue)) {
 192                 dst_buf = list_entry(ctx->dst_queue.next,
 193                                      struct s5p_mfc_buf, list);
 194                 mfc_debug(2, "Cleaning up buffer: %d\n",
 195                                           dst_buf->b->vb2_buf.index);
 196                 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0, 0);
 197                 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1, 0);
 198                 list_del(&dst_buf->list);
 199                 dst_buf->flags |= MFC_BUF_FLAG_EOS;
 200                 ctx->dst_queue_cnt--;
 201                 dst_buf->b->sequence = (ctx->sequence++);
 202
 203                 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) ==
 204                         s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx))
 205                         dst_buf->b->field = V4L2_FIELD_NONE;
 206                 else
 207                         dst_buf->b->field = V4L2_FIELD_INTERLACED;
 208                 dst_buf->b->flags |= V4L2_BUF_FLAG_LAST;
 209
 210                 ctx->dec_dst_flag &= ~(1 << dst_buf->b->vb2_buf.index);
 211                 vb2_buffer_done(&dst_buf->b->vb2_buf, VB2_BUF_STATE_DONE);
 212         }
 213 }
 214
 215 static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx)
 216 {
 217         struct s5p_mfc_dev *dev = ctx->dev;
 218         struct s5p_mfc_buf  *dst_buf, *src_buf;
 219         size_t dec_y_addr;
 220         unsigned int frame_type;
 221
 222         /* Make sure we actually have a new frame before continuing. */
 223         frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
 224         if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED)
 225                 return;
 226         dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev);
 227
 228         /* Copy timestamp / timecode from decoded src to dst and set
 229            appropriate flags. */
 230         src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
 231         list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
 232                 if (vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0)
 233                                 == dec_y_addr) {
 234                         dst_buf->b->timecode =
 235                                                 src_buf->b->timecode;
 236                         dst_buf->b->timestamp =
 237                                                 src_buf->b->timestamp;
 238                         dst_buf->b->flags &=
 239                                 ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
 240                         dst_buf->b->flags |=
 241                                 src_buf->b->flags
 242                                 & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
 243                         switch (frame_type) {
 244                         case S5P_FIMV_DECODE_FRAME_I_FRAME:
 245                                 dst_buf->b->flags |=
 246                                                 V4L2_BUF_FLAG_KEYFRAME;
 247                                 break;
 248                         case S5P_FIMV_DECODE_FRAME_P_FRAME:
 249                                 dst_buf->b->flags |=
 250                                                 V4L2_BUF_FLAG_PFRAME;
 251                                 break;
 252                         case S5P_FIMV_DECODE_FRAME_B_FRAME:
 253                                 dst_buf->b->flags |=
 254                                                 V4L2_BUF_FLAG_BFRAME;
 255                                 break;
 256                         default:
 257                                 /* Don't know how to handle
 258                                    S5P_FIMV_DECODE_FRAME_OTHER_FRAME. */
 259                                 mfc_debug(2, "Unexpected frame type: %d\n",
 260                                                 frame_type);
 261                         }
 262                         break;
 263                 }
 264         }
 265 }
 266
 267 static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
 268 {
 269         struct s5p_mfc_dev *dev = ctx->dev;
 270         struct s5p_mfc_buf  *dst_buf;
 271         size_t dspl_y_addr;
 272         unsigned int frame_type;
 273
 274         dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev);
 275         if (IS_MFCV6_PLUS(dev))
 276                 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
 277                         get_disp_frame_type, ctx);
 278         else
 279                 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
 280                         get_dec_frame_type, dev);
 281
 282         /* If frame is same as previous then skip and do not dequeue */
 283         if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) {
 284                 if (!ctx->after_packed_pb)
 285                         ctx->sequence++;
 286                 ctx->after_packed_pb = 0;
 287                 return;
 288         }
 289         ctx->sequence++;
 290         /* The MFC returns address of the buffer, now we have to
 291          * check which videobuf does it correspond to */
 292         list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
 293                 /* Check if this is the buffer we're looking for */
 294                 if (vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0)
 295                                 == dspl_y_addr) {
 296                         list_del(&dst_buf->list);
 297                         ctx->dst_queue_cnt--;
 298                         dst_buf->b->sequence = ctx->sequence;
 299                         if (s5p_mfc_hw_call(dev->mfc_ops,
 300                                         get_pic_type_top, ctx) ==
 301                                 s5p_mfc_hw_call(dev->mfc_ops,
 302                                         get_pic_type_bot, ctx))
 303                                 dst_buf->b->field = V4L2_FIELD_NONE;
 304                         else
 305                                 dst_buf->b->field =
 306                                                         V4L2_FIELD_INTERLACED;
 307                         vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0,
 308                                                 ctx->luma_size);
 309                         vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1,
 310                                                 ctx->chroma_size);
 311                         clear_bit(dst_buf->b->vb2_buf.index,
 312                                                         &ctx->dec_dst_flag);
 313
 314                         vb2_buffer_done(&dst_buf->b->vb2_buf, err ?
 315                                 VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
 316
 317                         break;
 318                 }
 319         }
 320 }
 321
 322 /* Handle frame decoding interrupt */
 323 static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
 324                                         unsigned int reason, unsigned int err)
 325 {
 326         struct s5p_mfc_dev *dev = ctx->dev;
 327         unsigned int dst_frame_status;
 328         unsigned int dec_frame_status;
 329         struct s5p_mfc_buf *src_buf;
 330         unsigned long flags;
 331         unsigned int res_change;
 332
 333         dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
 334                                 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
 335         dec_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dec_status, dev)
 336                                 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
 337         res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
 338                                 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK)
 339                                 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT;
 340         mfc_debug(2, "Frame Status: %x\n", dst_frame_status);
 341         if (ctx->state == MFCINST_RES_CHANGE_INIT)
 342                 ctx->state = MFCINST_RES_CHANGE_FLUSH;
 343         if (res_change == S5P_FIMV_RES_INCREASE ||
 344                 res_change == S5P_FIMV_RES_DECREASE) {
 345                 ctx->state = MFCINST_RES_CHANGE_INIT;
 346                 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
 347                 wake_up_ctx(ctx, reason, err);
 348                 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
 349                 s5p_mfc_clock_off();
 350                 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
 351                 return;
 352         }
 353         if (ctx->dpb_flush_flag)
 354                 ctx->dpb_flush_flag = 0;
 355
 356         spin_lock_irqsave(&dev->irqlock, flags);
 357         /* All frames remaining in the buffer have been extracted  */
 358         if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) {
 359                 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) {
 360                         static const struct v4l2_event ev_src_ch = {
 361                                 .type = V4L2_EVENT_SOURCE_CHANGE,
 362                                 .u.src_change.changes =
 363                                         V4L2_EVENT_SRC_CH_RESOLUTION,
 364                         };
 365
 366                         s5p_mfc_handle_frame_all_extracted(ctx);
 367                         ctx->state = MFCINST_RES_CHANGE_END;
 368                         v4l2_event_queue_fh(&ctx->fh, &ev_src_ch);
 369
 370                         goto leave_handle_frame;
 371                 } else {
 372                         s5p_mfc_handle_frame_all_extracted(ctx);
 373                 }
 374         }
 375
 376         if (dec_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY)
 377                 s5p_mfc_handle_frame_copy_time(ctx);
 378
 379         /* A frame has been decoded and is in the buffer  */
 380         if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
 381             dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) {
 382                 s5p_mfc_handle_frame_new(ctx, err);
 383         } else {
 384                 mfc_debug(2, "No frame decode\n");
 385         }
 386         /* Mark source buffer as complete */
 387         if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
 388                 && !list_empty(&ctx->src_queue)) {
 389                 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
 390                                                                 list);
 391                 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops,
 392                                                 get_consumed_stream, dev);
 393                 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC &&
 394                         ctx->codec_mode != S5P_MFC_CODEC_VP8_DEC &&
 395                         ctx->consumed_stream + STUFF_BYTE <
 396                         src_buf->b->vb2_buf.planes[0].bytesused) {
 397                         /* Run MFC again on the same buffer */
 398                         mfc_debug(2, "Running again the same buffer\n");
 399                         ctx->after_packed_pb = 1;
 400                 } else {
 401                         mfc_debug(2, "MFC needs next buffer\n");
 402                         ctx->consumed_stream = 0;
 403                         if (src_buf->flags & MFC_BUF_FLAG_EOS)
 404                                 ctx->state = MFCINST_FINISHING;
 405                         list_del(&src_buf->list);
 406                         ctx->src_queue_cnt--;
 407                         if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0)
 408                                 vb2_buffer_done(&src_buf->b->vb2_buf,
 409                                                 VB2_BUF_STATE_ERROR);
 410                         else
 411                                 vb2_buffer_done(&src_buf->b->vb2_buf,
 412                                                 VB2_BUF_STATE_DONE);
 413                 }
 414         }
 415 leave_handle_frame:
 416         spin_unlock_irqrestore(&dev->irqlock, flags);
 417         if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
 418                                     || ctx->dst_queue_cnt < ctx->pb_count)
 419                 clear_work_bit(ctx);
 420         s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
 421         wake_up_ctx(ctx, reason, err);
 422         WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
 423         s5p_mfc_clock_off();
 424         /* if suspending, wake up device and do not try_run again*/
 425         if (test_bit(0, &dev->enter_suspend))
 426                 wake_up_dev(dev, reason, err);
 427         else
 428                 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
 429 }
 430
 431 /* Error handling for interrupt */
 432 static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev,
 433                 struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err)
 434 {
 435         unsigned long flags;
 436
 437         mfc_err("Interrupt Error: %08x\n", err);
 438
 439         if (ctx != NULL) {
 440                 /* Error recovery is dependent on the state of context */
 441                 switch (ctx->state) {
 442                 case MFCINST_RES_CHANGE_INIT:
 443                 case MFCINST_RES_CHANGE_FLUSH:
 444                 case MFCINST_RES_CHANGE_END:
 445                 case MFCINST_FINISHING:
 446                 case MFCINST_FINISHED:
 447                 case MFCINST_RUNNING:
 448                         /* It is highly probable that an error occurred
 449                          * while decoding a frame */
 450                         clear_work_bit(ctx);
 451                         ctx->state = MFCINST_ERROR;
 452                         /* Mark all dst buffers as having an error */
 453                         spin_lock_irqsave(&dev->irqlock, flags);
 454                         s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
 455                                                 &ctx->dst_queue, &ctx->vq_dst);
 456                         /* Mark all src buffers as having an error */
 457                         s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
 458                                                 &ctx->src_queue, &ctx->vq_src);
 459                         spin_unlock_irqrestore(&dev->irqlock, flags);
 460                         wake_up_ctx(ctx, reason, err);
 461                         break;
 462                 default:
 463                         clear_work_bit(ctx);
 464                         ctx->state = MFCINST_ERROR;
 465                         wake_up_ctx(ctx, reason, err);
 466                         break;
 467                 }
 468         }
 469         WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
 470         s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
 471         s5p_mfc_clock_off();
 472         wake_up_dev(dev, reason, err);
 473         return;
 474 }
 475
 476 /* Header parsing interrupt handling */
 477 static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
 478                                  unsigned int reason, unsigned int err)
 479 {
 480         struct s5p_mfc_dev *dev;
 481
 482         if (ctx == NULL)
 483                 return;
 484         dev = ctx->dev;
 485         if (ctx->c_ops->post_seq_start) {
 486                 if (ctx->c_ops->post_seq_start(ctx))
 487                         mfc_err("post_seq_start() failed\n");
 488         } else {
 489                 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width,
 490                                 dev);
 491                 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height,
 492                                 dev);
 493
 494                 s5p_mfc_hw_call_void(dev->mfc_ops, dec_calc_dpb_size, ctx);
 495
 496                 ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count,
 497                                 dev);
 498                 ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count,
 499                                 dev);
 500                 if (ctx->img_width == 0 || ctx->img_height == 0)
 501                         ctx->state = MFCINST_ERROR;
 502                 else
 503                         ctx->state = MFCINST_HEAD_PARSED;
 504
 505                 if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
 506                         ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) &&
 507                                 !list_empty(&ctx->src_queue)) {
 508                         struct s5p_mfc_buf *src_buf;
 509                         src_buf = list_entry(ctx->src_queue.next,
 510                                         struct s5p_mfc_buf, list);
 511                         if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream,
 512                                                 dev) <
 513                                         src_buf->b->vb2_buf.planes[0].bytesused)
 514                                 ctx->head_processed = 0;
 515                         else
 516                                 ctx->head_processed = 1;
 517                 } else {
 518                         ctx->head_processed = 1;
 519                 }
 520         }
 521         s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
 522         clear_work_bit(ctx);
 523         WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
 524         s5p_mfc_clock_off();
 525         s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
 526         wake_up_ctx(ctx, reason, err);
 527 }
 528
 529 /* Header parsing interrupt handling */
 530 static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
 531                                  unsigned int reason, unsigned int err)
 532 {
 533         struct s5p_mfc_buf *src_buf;
 534         struct s5p_mfc_dev *dev;
 535         unsigned long flags;
 536
 537         if (ctx == NULL)
 538                 return;
 539         dev = ctx->dev;
 540         s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
 541         ctx->int_type = reason;
 542         ctx->int_err = err;
 543         ctx->int_cond = 1;
 544         clear_work_bit(ctx);
 545         if (err == 0) {
 546                 ctx->state = MFCINST_RUNNING;
 547                 if (!ctx->dpb_flush_flag && ctx->head_processed) {
 548                         spin_lock_irqsave(&dev->irqlock, flags);
 549                         if (!list_empty(&ctx->src_queue)) {
 550                                 src_buf = list_entry(ctx->src_queue.next,
 551                                              struct s5p_mfc_buf, list);
 552                                 list_del(&src_buf->list);
 553                                 ctx->src_queue_cnt--;
 554                                 vb2_buffer_done(&src_buf->b->vb2_buf,
 555                                                 VB2_BUF_STATE_DONE);
 556                         }
 557                         spin_unlock_irqrestore(&dev->irqlock, flags);
 558                 } else {
 559                         ctx->dpb_flush_flag = 0;
 560                 }
 561                 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
 562
 563                 s5p_mfc_clock_off();
 564
 565                 wake_up(&ctx->queue);
 566                 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
 567         } else {
 568                 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
 569
 570                 s5p_mfc_clock_off();
 571
 572                 wake_up(&ctx->queue);
 573         }
 574 }
 575
 576 static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx)
 577 {
 578         struct s5p_mfc_dev *dev = ctx->dev;
 579         struct s5p_mfc_buf *mb_entry;
 580
 581         mfc_debug(2, "Stream completed\n");
 582
 583         ctx->state = MFCINST_FINISHED;
 584
 585         spin_lock(&dev->irqlock);
 586         if (!list_empty(&ctx->dst_queue)) {
 587                 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
 588                                                                         list);
 589                 list_del(&mb_entry->list);
 590                 ctx->dst_queue_cnt--;
 591                 vb2_set_plane_payload(&mb_entry->b->vb2_buf, 0, 0);
 592                 vb2_buffer_done(&mb_entry->b->vb2_buf, VB2_BUF_STATE_DONE);
 593         }
 594         spin_unlock(&dev->irqlock);
 595
 596         clear_work_bit(ctx);
 597
 598         WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
 599
 600         s5p_mfc_clock_off();
 601         wake_up(&ctx->queue);
 602         s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
 603 }
 604
 605 /* Interrupt processing */
 606 static irqreturn_t s5p_mfc_irq(int irq, void *priv)
 607 {
 608         struct s5p_mfc_dev *dev = priv;
 609         struct s5p_mfc_ctx *ctx;
 610         unsigned int reason;
 611         unsigned int err;
 612
 613         mfc_debug_enter();
 614         /* Reset the timeout watchdog */
 615         atomic_set(&dev->watchdog_cnt, 0);
 616         ctx = dev->ctx[dev->curr_ctx];
 617         /* Get the reason of interrupt and the error code */
 618         reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev);
 619         err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev);
 620         mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err);
 621         switch (reason) {
 622         case S5P_MFC_R2H_CMD_ERR_RET:
 623                 /* An error has occurred */
 624                 if (ctx->state == MFCINST_RUNNING &&
 625                         s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >=
 626                                 dev->warn_start)
 627                         s5p_mfc_handle_frame(ctx, reason, err);
 628                 else
 629                         s5p_mfc_handle_error(dev, ctx, reason, err);
 630                 clear_bit(0, &dev->enter_suspend);
 631                 break;
 632
 633         case S5P_MFC_R2H_CMD_SLICE_DONE_RET:
 634         case S5P_MFC_R2H_CMD_FIELD_DONE_RET:
 635         case S5P_MFC_R2H_CMD_FRAME_DONE_RET:
 636                 if (ctx->c_ops->post_frame_start) {
 637                         if (ctx->c_ops->post_frame_start(ctx))
 638                                 mfc_err("post_frame_start() failed\n");
 639
 640                         if (ctx->state == MFCINST_FINISHING &&
 641                                                 list_empty(&ctx->ref_queue)) {
 642                                 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
 643                                 s5p_mfc_handle_stream_complete(ctx);
 644                                 break;
 645                         }
 646                         s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
 647                         wake_up_ctx(ctx, reason, err);
 648                         WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
 649                         s5p_mfc_clock_off();
 650                         s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
 651                 } else {
 652                         s5p_mfc_handle_frame(ctx, reason, err);
 653                 }
 654                 break;
 655
 656         case S5P_MFC_R2H_CMD_SEQ_DONE_RET:
 657                 s5p_mfc_handle_seq_done(ctx, reason, err);
 658                 break;
 659
 660         case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET:
 661                 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev);
 662                 ctx->state = MFCINST_GOT_INST;
 663                 clear_work_bit(ctx);
 664                 wake_up(&ctx->queue);
 665                 goto irq_cleanup_hw;
 666
 667         case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET:
 668                 clear_work_bit(ctx);
 669                 ctx->inst_no = MFC_NO_INSTANCE_SET;
 670                 ctx->state = MFCINST_FREE;
 671                 wake_up(&ctx->queue);
 672                 goto irq_cleanup_hw;
 673
 674         case S5P_MFC_R2H_CMD_SYS_INIT_RET:
 675         case S5P_MFC_R2H_CMD_FW_STATUS_RET:
 676         case S5P_MFC_R2H_CMD_SLEEP_RET:
 677         case S5P_MFC_R2H_CMD_WAKEUP_RET:
 678                 if (ctx)
 679                         clear_work_bit(ctx);
 680                 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
 681                 wake_up_dev(dev, reason, err);
 682                 clear_bit(0, &dev->hw_lock);
 683                 clear_bit(0, &dev->enter_suspend);
 684                 break;
 685
 686         case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET:
 687                 s5p_mfc_handle_init_buffers(ctx, reason, err);
 688                 break;
 689
 690         case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET:
 691                 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
 692                 ctx->int_type = reason;
 693                 ctx->int_err = err;
 694                 s5p_mfc_handle_stream_complete(ctx);
 695                 break;
 696
 697         case S5P_MFC_R2H_CMD_DPB_FLUSH_RET:
 698                 clear_work_bit(ctx);
 699                 ctx->state = MFCINST_RUNNING;
 700                 wake_up(&ctx->queue);
 701                 goto irq_cleanup_hw;
 702
 703         default:
 704                 mfc_debug(2, "Unknown int reason\n");
 705                 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
 706         }
 707         mfc_debug_leave();
 708         return IRQ_HANDLED;
 709 irq_cleanup_hw:
 710         s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
 711         ctx->int_type = reason;
 712         ctx->int_err = err;
 713         ctx->int_cond = 1;
 714         if (test_and_clear_bit(0, &dev->hw_lock) == 0)
 715                 mfc_err("Failed to unlock hw\n");
 716
 717         s5p_mfc_clock_off();
 718
 719         s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
 720         mfc_debug(2, "Exit via irq_cleanup_hw\n");
 721         return IRQ_HANDLED;
 722 }
 723
 724 /* Open an MFC node */
 725 static int s5p_mfc_open(struct file *file)
 726 {
 727         struct video_device *vdev = video_devdata(file);
 728         struct s5p_mfc_dev *dev = video_drvdata(file);
 729         struct s5p_mfc_ctx *ctx = NULL;
 730         struct vb2_queue *q;
 731         int ret = 0;
 732
 733         mfc_debug_enter();
 734         if (mutex_lock_interruptible(&dev->mfc_mutex))
 735                 return -ERESTARTSYS;
 736         dev->num_inst++;        /* It is guarded by mfc_mutex in vfd */
 737         /* Allocate memory for context */
 738         ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
 739         if (!ctx) {
 740                 mfc_err("Not enough memory\n");
 741                 ret = -ENOMEM;
 742                 goto err_alloc;
 743         }
 744         v4l2_fh_init(&ctx->fh, vdev);
 745         file->private_data = &ctx->fh;
 746         v4l2_fh_add(&ctx->fh);
 747         ctx->dev = dev;
 748         INIT_LIST_HEAD(&ctx->src_queue);
 749         INIT_LIST_HEAD(&ctx->dst_queue);
 750         ctx->src_queue_cnt = 0;
 751         ctx->dst_queue_cnt = 0;
 752         /* Get context number */
 753         ctx->num = 0;
 754         while (dev->ctx[ctx->num]) {
 755                 ctx->num++;
 756                 if (ctx->num >= MFC_NUM_CONTEXTS) {
 757                         mfc_err("Too many open contexts\n");
 758                         ret = -EBUSY;
 759                         goto err_no_ctx;
 760                 }
 761         }
 762         /* Mark context as idle */
 763         clear_work_bit_irqsave(ctx);
 764         dev->ctx[ctx->num] = ctx;
 765         if (vdev == dev->vfd_dec) {
 766                 ctx->type = MFCINST_DECODER;
 767                 ctx->c_ops = get_dec_codec_ops();
 768                 s5p_mfc_dec_init(ctx);
 769                 /* Setup ctrl handler */
 770                 ret = s5p_mfc_dec_ctrls_setup(ctx);
 771                 if (ret) {
 772                         mfc_err("Failed to setup mfc controls\n");
 773                         goto err_ctrls_setup;
 774                 }
 775         } else if (vdev == dev->vfd_enc) {
 776                 ctx->type = MFCINST_ENCODER;
 777                 ctx->c_ops = get_enc_codec_ops();
 778                 /* only for encoder */
 779                 INIT_LIST_HEAD(&ctx->ref_queue);
 780                 ctx->ref_queue_cnt = 0;
 781                 s5p_mfc_enc_init(ctx);
 782                 /* Setup ctrl handler */
 783                 ret = s5p_mfc_enc_ctrls_setup(ctx);
 784                 if (ret) {
 785                         mfc_err("Failed to setup mfc controls\n");
 786                         goto err_ctrls_setup;
 787                 }
 788         } else {
 789                 ret = -ENOENT;
 790                 goto err_bad_node;
 791         }
 792         ctx->fh.ctrl_handler = &ctx->ctrl_handler;
 793         ctx->inst_no = MFC_NO_INSTANCE_SET;
 794         /* Load firmware if this is the first instance */
 795         if (dev->num_inst == 1) {
 796                 dev->watchdog_timer.expires = jiffies +
 797                                         msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
 798                 add_timer(&dev->watchdog_timer);
 799                 ret = s5p_mfc_power_on();
 800                 if (ret < 0) {
 801                         mfc_err("power on failed\n");
 802                         goto err_pwr_enable;
 803                 }
 804                 s5p_mfc_clock_on();
 805                 ret = s5p_mfc_load_firmware(dev);
 806                 if (ret) {
 807                         s5p_mfc_clock_off();
 808                         goto err_load_fw;
 809                 }
 810                 /* Init the FW */
 811                 ret = s5p_mfc_init_hw(dev);
 812                 s5p_mfc_clock_off();
 813                 if (ret)
 814                         goto err_init_hw;
 815         }
 816         /* Init videobuf2 queue for CAPTURE */
 817         q = &ctx->vq_dst;
 818         q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
 819         q->drv_priv = &ctx->fh;
 820         q->lock = &dev->mfc_mutex;
 821         if (vdev == dev->vfd_dec) {
 822                 q->io_modes = VB2_MMAP;
 823                 q->ops = get_dec_queue_ops();
 824         } else if (vdev == dev->vfd_enc) {
 825                 q->io_modes = VB2_MMAP | VB2_USERPTR;
 826                 q->ops = get_enc_queue_ops();
 827         } else {
 828                 ret = -ENOENT;
 829                 goto err_queue_init;
 830         }
 831         q->mem_ops = &vb2_dma_contig_memops;
 832         q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
 833         ret = vb2_queue_init(q);
 834         if (ret) {
 835                 mfc_err("Failed to initialize videobuf2 queue(capture)\n");
 836                 goto err_queue_init;
 837         }
 838         /* Init videobuf2 queue for OUTPUT */
 839         q = &ctx->vq_src;
 840         q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
 841         q->io_modes = VB2_MMAP;
 842         q->drv_priv = &ctx->fh;
 843         q->lock = &dev->mfc_mutex;
 844         if (vdev == dev->vfd_dec) {
 845                 q->io_modes = VB2_MMAP;
 846                 q->ops = get_dec_queue_ops();
 847         } else if (vdev == dev->vfd_enc) {
 848                 q->io_modes = VB2_MMAP | VB2_USERPTR;
 849                 q->ops = get_enc_queue_ops();
 850         } else {
 851                 ret = -ENOENT;
 852                 goto err_queue_init;
 853         }
 854         /* One way to indicate end-of-stream for MFC is to set the
 855          * bytesused == 0. However by default videobuf2 handles bytesused
 856          * equal to 0 as a special case and changes its value to the size
 857          * of the buffer. Set the allow_zero_bytesused flag so that videobuf2
 858          * will keep the value of bytesused intact.
 859          */
 860         q->allow_zero_bytesused = 1;
 861         q->mem_ops = &vb2_dma_contig_memops;
 862         q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
 863         ret = vb2_queue_init(q);
 864         if (ret) {
 865                 mfc_err("Failed to initialize videobuf2 queue(output)\n");
 866                 goto err_queue_init;
 867         }
 868         init_waitqueue_head(&ctx->queue);
 869         mutex_unlock(&dev->mfc_mutex);
 870         mfc_debug_leave();
 871         return ret;
 872         /* Deinit when failure occurred */
 873 err_queue_init:
 874         if (dev->num_inst == 1)
 875                 s5p_mfc_deinit_hw(dev);
 876 err_init_hw:
 877 err_load_fw:
 878 err_pwr_enable:
 879         if (dev->num_inst == 1) {
 880                 if (s5p_mfc_power_off() < 0)
 881                         mfc_err("power off failed\n");
 882                 del_timer_sync(&dev->watchdog_timer);
 883         }
 884 err_ctrls_setup:
 885         s5p_mfc_dec_ctrls_delete(ctx);
 886 err_bad_node:
 887         dev->ctx[ctx->num] = NULL;
 888 err_no_ctx:
 889         v4l2_fh_del(&ctx->fh);
 890         v4l2_fh_exit(&ctx->fh);
 891         kfree(ctx);
 892 err_alloc:
 893         dev->num_inst--;
 894         mutex_unlock(&dev->mfc_mutex);
 895         mfc_debug_leave();
 896         return ret;
 897 }
 898
 899 /* Release MFC context */
 900 static int s5p_mfc_release(struct file *file)
 901 {
 902         struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
 903         struct s5p_mfc_dev *dev = ctx->dev;
 904
 905         mfc_debug_enter();
 906         mutex_lock(&dev->mfc_mutex);
 907         s5p_mfc_clock_on();
 908         vb2_queue_release(&ctx->vq_src);
 909         vb2_queue_release(&ctx->vq_dst);
 910         /* Mark context as idle */
 911         clear_work_bit_irqsave(ctx);
 912         /* If instance was initialised and not yet freed,
 913          * return instance and free resources */
 914         if (ctx->state != MFCINST_FREE && ctx->state != MFCINST_INIT) {
 915                 mfc_debug(2, "Has to free instance\n");
 916                 s5p_mfc_close_mfc_inst(dev, ctx);
 917         }
 918         /* hardware locking scheme */
 919         if (dev->curr_ctx == ctx->num)
 920                 clear_bit(0, &dev->hw_lock);
 921         dev->num_inst--;
 922         if (dev->num_inst == 0) {
 923                 mfc_debug(2, "Last instance\n");
 924                 s5p_mfc_deinit_hw(dev);
 925                 del_timer_sync(&dev->watchdog_timer);
 926                 if (s5p_mfc_power_off() < 0)
 927                         mfc_err("Power off failed\n");
 928         }
 929         mfc_debug(2, "Shutting down clock\n");
 930         s5p_mfc_clock_off();
 931         dev->ctx[ctx->num] = NULL;
 932         s5p_mfc_dec_ctrls_delete(ctx);
 933         v4l2_fh_del(&ctx->fh);
 934         v4l2_fh_exit(&ctx->fh);
 935         kfree(ctx);
 936         mfc_debug_leave();
 937         mutex_unlock(&dev->mfc_mutex);
 938         return 0;
 939 }
 940
 941 /* Poll */
 942 static unsigned int s5p_mfc_poll(struct file *file,
 943                                  struct poll_table_struct *wait)
 944 {
 945         struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
 946         struct s5p_mfc_dev *dev = ctx->dev;
 947         struct vb2_queue *src_q, *dst_q;
 948         struct vb2_buffer *src_vb = NULL, *dst_vb = NULL;
 949         unsigned int rc = 0;
 950         unsigned long flags;
 951
 952         mutex_lock(&dev->mfc_mutex);
 953         src_q = &ctx->vq_src;
 954         dst_q = &ctx->vq_dst;
 955         /*
 956          * There has to be at least one buffer queued on each queued_list, which
 957          * means either in driver already or waiting for driver to claim it
 958          * and start processing.
 959          */
 960         if ((!src_q->streaming || list_empty(&src_q->queued_list))
 961                 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) {
 962                 rc = POLLERR;
 963                 goto end;
 964         }
 965         mutex_unlock(&dev->mfc_mutex);
 966         poll_wait(file, &ctx->fh.wait, wait);
 967         poll_wait(file, &src_q->done_wq, wait);
 968         poll_wait(file, &dst_q->done_wq, wait);
 969         mutex_lock(&dev->mfc_mutex);
 970         if (v4l2_event_pending(&ctx->fh))
 971                 rc |= POLLPRI;
 972         spin_lock_irqsave(&src_q->done_lock, flags);
 973         if (!list_empty(&src_q->done_list))
 974                 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer,
 975                                                                 done_entry);
 976         if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE
 977                                 || src_vb->state == VB2_BUF_STATE_ERROR))
 978                 rc |= POLLOUT | POLLWRNORM;
 979         spin_unlock_irqrestore(&src_q->done_lock, flags);
 980         spin_lock_irqsave(&dst_q->done_lock, flags);
 981         if (!list_empty(&dst_q->done_list))
 982                 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer,
 983                                                                 done_entry);
 984         if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE
 985                                 || dst_vb->state == VB2_BUF_STATE_ERROR))
 986                 rc |= POLLIN | POLLRDNORM;
 987         spin_unlock_irqrestore(&dst_q->done_lock, flags);
 988 end:
 989         mutex_unlock(&dev->mfc_mutex);
 990         return rc;
 991 }
 992
 993 /* Mmap */
 994 static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
 995 {
 996         struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
 997         struct s5p_mfc_dev *dev = ctx->dev;
 998         unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
 999         int ret;
1000
1001         if (mutex_lock_interruptible(&dev->mfc_mutex))
1002                 return -ERESTARTSYS;
1003         if (offset < DST_QUEUE_OFF_BASE) {
1004                 mfc_debug(2, "mmaping source\n");
1005                 ret = vb2_mmap(&ctx->vq_src, vma);
1006         } else {                /* capture */
1007                 mfc_debug(2, "mmaping destination\n");
1008                 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
1009                 ret = vb2_mmap(&ctx->vq_dst, vma);
1010         }
1011         mutex_unlock(&dev->mfc_mutex);
1012         return ret;
1013 }
1014
1015 /* v4l2 ops */
1016 static const struct v4l2_file_operations s5p_mfc_fops = {
1017         .owner = THIS_MODULE,
1018         .open = s5p_mfc_open,
1019         .release = s5p_mfc_release,
1020         .poll = s5p_mfc_poll,
1021         .unlocked_ioctl = video_ioctl2,
1022         .mmap = s5p_mfc_mmap,
1023 };
1024
1025 static int match_child(struct device *dev, void *data)
1026 {
1027         if (!dev_name(dev))
1028                 return 0;
1029         return !strcmp(dev_name(dev), (char *)data);
1030 }
1031
1032 static void *mfc_get_drv_data(struct platform_device *pdev);
1033
1034 static int s5p_mfc_alloc_memdevs(struct s5p_mfc_dev *dev)
1035 {
1036         unsigned int mem_info[2] = { };
1037
1038         dev->mem_dev_l = devm_kzalloc(&dev->plat_dev->dev,
1039                         sizeof(struct device), GFP_KERNEL);
1040         if (!dev->mem_dev_l) {
1041                 mfc_err("Not enough memory\n");
1042                 return -ENOMEM;
1043         }
1044
1045         dev_set_name(dev->mem_dev_l, "%s", "s5p-mfc-l");
1046         device_initialize(dev->mem_dev_l);
1047         of_property_read_u32_array(dev->plat_dev->dev.of_node,
1048                         "samsung,mfc-l", mem_info, 2);
1049         if (dma_declare_coherent_memory(dev->mem_dev_l, mem_info[0],
1050                                 mem_info[0], mem_info[1],
1051                                 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) {
1052                 mfc_err("Failed to declare coherent memory for\n"
1053                 "MFC device\n");
1054                 return -ENOMEM;
1055         }
1056
1057         dev->mem_dev_r = devm_kzalloc(&dev->plat_dev->dev,
1058                         sizeof(struct device), GFP_KERNEL);
1059         if (!dev->mem_dev_r) {
1060                 mfc_err("Not enough memory\n");
1061                 return -ENOMEM;
1062         }
1063
1064         dev_set_name(dev->mem_dev_r, "%s", "s5p-mfc-r");
1065         device_initialize(dev->mem_dev_r);
1066         of_property_read_u32_array(dev->plat_dev->dev.of_node,
1067                         "samsung,mfc-r", mem_info, 2);
1068         if (dma_declare_coherent_memory(dev->mem_dev_r, mem_info[0],
1069                                 mem_info[0], mem_info[1],
1070                                 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) {
1071                 pr_err("Failed to declare coherent memory for\n"
1072                 "MFC device\n");
1073                 return -ENOMEM;
1074         }
1075         return 0;
1076 }
1077
1078 /* MFC probe function */
1079 static int s5p_mfc_probe(struct platform_device *pdev)
1080 {
1081         struct s5p_mfc_dev *dev;
1082         struct video_device *vfd;
1083         struct resource *res;
1084         int ret;
1085
1086         pr_debug("%s++\n", __func__);
1087         dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1088         if (!dev) {
1089                 dev_err(&pdev->dev, "Not enough memory for MFC device\n");
1090                 return -ENOMEM;
1091         }
1092
1093         spin_lock_init(&dev->irqlock);
1094         spin_lock_init(&dev->condlock);
1095         dev->plat_dev = pdev;
1096         if (!dev->plat_dev) {
1097                 dev_err(&pdev->dev, "No platform data specified\n");
1098                 return -ENODEV;
1099         }
1100
1101         dev->variant = mfc_get_drv_data(pdev);
1102
1103         ret = s5p_mfc_init_pm(dev);
1104         if (ret < 0) {
1105                 dev_err(&pdev->dev, "failed to get mfc clock source\n");
1106                 return ret;
1107         }
1108
1109         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1110
1111         dev->regs_base = devm_ioremap_resource(&pdev->dev, res);
1112         if (IS_ERR(dev->regs_base))
1113                 return PTR_ERR(dev->regs_base);
1114
1115         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1116         if (res == NULL) {
1117                 dev_err(&pdev->dev, "failed to get irq resource\n");
1118                 ret = -ENOENT;
1119                 goto err_res;
1120         }
1121         dev->irq = res->start;
1122         ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq,
1123                                         0, pdev->name, dev);
1124         if (ret) {
1125                 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
1126                 goto err_res;
1127         }
1128
1129         if (pdev->dev.of_node) {
1130                 ret = s5p_mfc_alloc_memdevs(dev);
1131                 if (ret < 0)
1132                         goto err_res;
1133         } else {
1134                 dev->mem_dev_l = device_find_child(&dev->plat_dev->dev,
1135                                 "s5p-mfc-l", match_child);
1136                 if (!dev->mem_dev_l) {
1137                         mfc_err("Mem child (L) device get failed\n");
1138                         ret = -ENODEV;
1139                         goto err_res;
1140                 }
1141                 dev->mem_dev_r = device_find_child(&dev->plat_dev->dev,
1142                                 "s5p-mfc-r", match_child);
1143                 if (!dev->mem_dev_r) {
1144                         mfc_err("Mem child (R) device get failed\n");
1145                         ret = -ENODEV;
1146                         goto err_res;
1147                 }
1148         }
1149
1150         dev->alloc_ctx[0] = vb2_dma_contig_init_ctx(dev->mem_dev_l);
1151         if (IS_ERR(dev->alloc_ctx[0])) {
1152                 ret = PTR_ERR(dev->alloc_ctx[0]);
1153                 goto err_res;
1154         }
1155         dev->alloc_ctx[1] = vb2_dma_contig_init_ctx(dev->mem_dev_r);
1156         if (IS_ERR(dev->alloc_ctx[1])) {
1157                 ret = PTR_ERR(dev->alloc_ctx[1]);
1158                 goto err_mem_init_ctx_1;
1159         }
1160
1161         mutex_init(&dev->mfc_mutex);
1162
1163         ret = s5p_mfc_alloc_firmware(dev);
1164         if (ret)
1165                 goto err_alloc_fw;
1166
1167         ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1168         if (ret)
1169                 goto err_v4l2_dev_reg;
1170         init_waitqueue_head(&dev->queue);
1171
1172         /* decoder */
1173         vfd = video_device_alloc();
1174         if (!vfd) {
1175                 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1176                 ret = -ENOMEM;
1177                 goto err_dec_alloc;
1178         }
1179         vfd->fops       = &s5p_mfc_fops;
1180         vfd->ioctl_ops  = get_dec_v4l2_ioctl_ops();
1181         vfd->release    = video_device_release;
1182         vfd->lock       = &dev->mfc_mutex;
1183         vfd->v4l2_dev   = &dev->v4l2_dev;
1184         vfd->vfl_dir    = VFL_DIR_M2M;
1185         snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME);
1186         dev->vfd_dec    = vfd;
1187         ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1188         if (ret) {
1189                 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1190                 video_device_release(vfd);
1191                 goto err_dec_reg;
1192         }
1193         v4l2_info(&dev->v4l2_dev,
1194                   "decoder registered as /dev/video%d\n", vfd->num);
1195         video_set_drvdata(vfd, dev);
1196
1197         /* encoder */
1198         vfd = video_device_alloc();
1199         if (!vfd) {
1200                 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1201                 ret = -ENOMEM;
1202                 goto err_enc_alloc;
1203         }
1204         vfd->fops       = &s5p_mfc_fops;
1205         vfd->ioctl_ops  = get_enc_v4l2_ioctl_ops();
1206         vfd->release    = video_device_release;
1207         vfd->lock       = &dev->mfc_mutex;
1208         vfd->v4l2_dev   = &dev->v4l2_dev;
1209         vfd->vfl_dir    = VFL_DIR_M2M;
1210         snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME);
1211         dev->vfd_enc    = vfd;
1212         ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1213         if (ret) {
1214                 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1215                 video_device_release(vfd);
1216                 goto err_enc_reg;
1217         }
1218         v4l2_info(&dev->v4l2_dev,
1219                   "encoder registered as /dev/video%d\n", vfd->num);
1220         video_set_drvdata(vfd, dev);
1221         platform_set_drvdata(pdev, dev);
1222
1223         dev->hw_lock = 0;
1224         dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME);
1225         INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker);
1226         atomic_set(&dev->watchdog_cnt, 0);
1227         init_timer(&dev->watchdog_timer);
1228         dev->watchdog_timer.data = (unsigned long)dev;
1229         dev->watchdog_timer.function = s5p_mfc_watchdog;
1230
1231         /* Initialize HW ops and commands based on MFC version */
1232         s5p_mfc_init_hw_ops(dev);
1233         s5p_mfc_init_hw_cmds(dev);
1234         s5p_mfc_init_regs(dev);
1235
1236         pr_debug("%s--\n", __func__);
1237         return 0;
1238
1239 /* Deinit MFC if probe had failed */
1240 err_enc_reg:
1241         video_device_release(dev->vfd_enc);
1242 err_enc_alloc:
1243         video_unregister_device(dev->vfd_dec);
1244 err_dec_reg:
1245         video_device_release(dev->vfd_dec);
1246 err_dec_alloc:
1247         v4l2_device_unregister(&dev->v4l2_dev);
1248 err_v4l2_dev_reg:
1249         s5p_mfc_release_firmware(dev);
1250 err_alloc_fw:
1251         vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
1252 err_mem_init_ctx_1:
1253         vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
1254 err_res:
1255         s5p_mfc_final_pm(dev);
1256
1257         pr_debug("%s-- with error\n", __func__);
1258         return ret;
1259
1260 }
1261
1262 /* Remove the driver */
1263 static int s5p_mfc_remove(struct platform_device *pdev)
1264 {
1265         struct s5p_mfc_dev *dev = platform_get_drvdata(pdev);
1266
1267         v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name);
1268
1269         del_timer_sync(&dev->watchdog_timer);
1270         flush_workqueue(dev->watchdog_workqueue);
1271         destroy_workqueue(dev->watchdog_workqueue);
1272
1273         video_unregister_device(dev->vfd_enc);
1274         video_unregister_device(dev->vfd_dec);
1275         v4l2_device_unregister(&dev->v4l2_dev);
1276         s5p_mfc_release_firmware(dev);
1277         vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
1278         vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
1279         if (pdev->dev.of_node) {
1280                 put_device(dev->mem_dev_l);
1281                 put_device(dev->mem_dev_r);
1282         }
1283
1284         s5p_mfc_final_pm(dev);
1285         return 0;
1286 }
1287
1288 #ifdef CONFIG_PM_SLEEP
1289
1290 static int s5p_mfc_suspend(struct device *dev)
1291 {
1292         struct platform_device *pdev = to_platform_device(dev);
1293         struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1294         int ret;
1295
1296         if (m_dev->num_inst == 0)
1297                 return 0;
1298
1299         if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) {
1300                 mfc_err("Error: going to suspend for a second time\n");
1301                 return -EIO;
1302         }
1303
1304         /* Check if we're processing then wait if it necessary. */
1305         while (test_and_set_bit(0, &m_dev->hw_lock) != 0) {
1306                 /* Try and lock the HW */
1307                 /* Wait on the interrupt waitqueue */
1308                 ret = wait_event_interruptible_timeout(m_dev->queue,
1309                         m_dev->int_cond, msecs_to_jiffies(MFC_INT_TIMEOUT));
1310                 if (ret == 0) {
1311                         mfc_err("Waiting for hardware to finish timed out\n");
1312                         clear_bit(0, &m_dev->enter_suspend);
1313                         return -EIO;
1314                 }
1315         }
1316
1317         ret = s5p_mfc_sleep(m_dev);
1318         if (ret) {
1319                 clear_bit(0, &m_dev->enter_suspend);
1320                 clear_bit(0, &m_dev->hw_lock);
1321         }
1322         return ret;
1323 }
1324
1325 static int s5p_mfc_resume(struct device *dev)
1326 {
1327         struct platform_device *pdev = to_platform_device(dev);
1328         struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1329
1330         if (m_dev->num_inst == 0)
1331                 return 0;
1332         return s5p_mfc_wakeup(m_dev);
1333 }
1334 #endif
1335
1336 #ifdef CONFIG_PM
1337 static int s5p_mfc_runtime_suspend(struct device *dev)
1338 {
1339         struct platform_device *pdev = to_platform_device(dev);
1340         struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1341
1342         atomic_set(&m_dev->pm.power, 0);
1343         return 0;
1344 }
1345
1346 static int s5p_mfc_runtime_resume(struct device *dev)
1347 {
1348         struct platform_device *pdev = to_platform_device(dev);
1349         struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1350
1351         atomic_set(&m_dev->pm.power, 1);
1352         return 0;
1353 }
1354 #endif
1355
1356 /* Power management */
1357 static const struct dev_pm_ops s5p_mfc_pm_ops = {
1358         SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume)
1359         SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume,
1360                            NULL)
1361 };
1362
1363 static struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = {
1364         .h264_ctx       = MFC_H264_CTX_BUF_SIZE,
1365         .non_h264_ctx   = MFC_CTX_BUF_SIZE,
1366         .dsc            = DESC_BUF_SIZE,
1367         .shm            = SHARED_BUF_SIZE,
1368 };
1369
1370 static struct s5p_mfc_buf_size buf_size_v5 = {
1371         .fw     = MAX_FW_SIZE,
1372         .cpb    = MAX_CPB_SIZE,
1373         .priv   = &mfc_buf_size_v5,
1374 };
1375
1376 static struct s5p_mfc_buf_align mfc_buf_align_v5 = {
1377         .base = MFC_BASE_ALIGN_ORDER,
1378 };
1379
1380 static struct s5p_mfc_variant mfc_drvdata_v5 = {
1381         .version        = MFC_VERSION,
1382         .version_bit    = MFC_V5_BIT,
1383         .port_num       = MFC_NUM_PORTS,
1384         .buf_size       = &buf_size_v5,
1385         .buf_align      = &mfc_buf_align_v5,
1386         .fw_name[0]     = "s5p-mfc.fw",
1387 };
1388
1389 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = {
1390         .dev_ctx        = MFC_CTX_BUF_SIZE_V6,
1391         .h264_dec_ctx   = MFC_H264_DEC_CTX_BUF_SIZE_V6,
1392         .other_dec_ctx  = MFC_OTHER_DEC_CTX_BUF_SIZE_V6,
1393         .h264_enc_ctx   = MFC_H264_ENC_CTX_BUF_SIZE_V6,
1394         .other_enc_ctx  = MFC_OTHER_ENC_CTX_BUF_SIZE_V6,
1395 };
1396
1397 static struct s5p_mfc_buf_size buf_size_v6 = {
1398         .fw     = MAX_FW_SIZE_V6,
1399         .cpb    = MAX_CPB_SIZE_V6,
1400         .priv   = &mfc_buf_size_v6,
1401 };
1402
1403 static struct s5p_mfc_buf_align mfc_buf_align_v6 = {
1404         .base = 0,
1405 };
1406
1407 static struct s5p_mfc_variant mfc_drvdata_v6 = {
1408         .version        = MFC_VERSION_V6,
1409         .version_bit    = MFC_V6_BIT,
1410         .port_num       = MFC_NUM_PORTS_V6,
1411         .buf_size       = &buf_size_v6,
1412         .buf_align      = &mfc_buf_align_v6,
1413         .fw_name[0]     = "s5p-mfc-v6.fw",
1414         /*
1415          * v6-v2 firmware contains bug fixes and interface change
1416          * for init buffer command
1417          */
1418         .fw_name[1]     = "s5p-mfc-v6-v2.fw",
1419 };
1420
1421 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = {
1422         .dev_ctx        = MFC_CTX_BUF_SIZE_V7,
1423         .h264_dec_ctx   = MFC_H264_DEC_CTX_BUF_SIZE_V7,
1424         .other_dec_ctx  = MFC_OTHER_DEC_CTX_BUF_SIZE_V7,
1425         .h264_enc_ctx   = MFC_H264_ENC_CTX_BUF_SIZE_V7,
1426         .other_enc_ctx  = MFC_OTHER_ENC_CTX_BUF_SIZE_V7,
1427 };
1428
1429 static struct s5p_mfc_buf_size buf_size_v7 = {
1430         .fw     = MAX_FW_SIZE_V7,
1431         .cpb    = MAX_CPB_SIZE_V7,
1432         .priv   = &mfc_buf_size_v7,
1433 };
1434
1435 static struct s5p_mfc_buf_align mfc_buf_align_v7 = {
1436         .base = 0,
1437 };
1438
1439 static struct s5p_mfc_variant mfc_drvdata_v7 = {
1440         .version        = MFC_VERSION_V7,
1441         .version_bit    = MFC_V7_BIT,
1442         .port_num       = MFC_NUM_PORTS_V7,
1443         .buf_size       = &buf_size_v7,
1444         .buf_align      = &mfc_buf_align_v7,
1445         .fw_name[0]     = "s5p-mfc-v7.fw",
1446 };
1447
1448 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v8 = {
1449         .dev_ctx        = MFC_CTX_BUF_SIZE_V8,
1450         .h264_dec_ctx   = MFC_H264_DEC_CTX_BUF_SIZE_V8,
1451         .other_dec_ctx  = MFC_OTHER_DEC_CTX_BUF_SIZE_V8,
1452         .h264_enc_ctx   = MFC_H264_ENC_CTX_BUF_SIZE_V8,
1453         .other_enc_ctx  = MFC_OTHER_ENC_CTX_BUF_SIZE_V8,
1454 };
1455
1456 static struct s5p_mfc_buf_size buf_size_v8 = {
1457         .fw     = MAX_FW_SIZE_V8,
1458         .cpb    = MAX_CPB_SIZE_V8,
1459         .priv   = &mfc_buf_size_v8,
1460 };
1461
1462 static struct s5p_mfc_buf_align mfc_buf_align_v8 = {
1463         .base = 0,
1464 };
1465
1466 static struct s5p_mfc_variant mfc_drvdata_v8 = {
1467         .version        = MFC_VERSION_V8,
1468         .version_bit    = MFC_V8_BIT,
1469         .port_num       = MFC_NUM_PORTS_V8,
1470         .buf_size       = &buf_size_v8,
1471         .buf_align      = &mfc_buf_align_v8,
1472         .fw_name[0]     = "s5p-mfc-v8.fw",
1473 };
1474
1475 static const struct platform_device_id mfc_driver_ids[] = {
1476         {
1477                 .name = "s5p-mfc",
1478                 .driver_data = (unsigned long)&mfc_drvdata_v5,
1479         }, {
1480                 .name = "s5p-mfc-v5",
1481                 .driver_data = (unsigned long)&mfc_drvdata_v5,
1482         }, {
1483                 .name = "s5p-mfc-v6",
1484                 .driver_data = (unsigned long)&mfc_drvdata_v6,
1485         }, {
1486                 .name = "s5p-mfc-v7",
1487                 .driver_data = (unsigned long)&mfc_drvdata_v7,
1488         }, {
1489                 .name = "s5p-mfc-v8",
1490                 .driver_data = (unsigned long)&mfc_drvdata_v8,
1491         },
1492         {},
1493 };
1494 MODULE_DEVICE_TABLE(platform, mfc_driver_ids);
1495
1496 static const struct of_device_id exynos_mfc_match[] = {
1497         {
1498                 .compatible = "samsung,mfc-v5",
1499                 .data = &mfc_drvdata_v5,
1500         }, {
1501                 .compatible = "samsung,mfc-v6",
1502                 .data = &mfc_drvdata_v6,
1503         }, {
1504                 .compatible = "samsung,mfc-v7",
1505                 .data = &mfc_drvdata_v7,
1506         }, {
1507                 .compatible = "samsung,mfc-v8",
1508                 .data = &mfc_drvdata_v8,
1509         },
1510         {},
1511 };
1512 MODULE_DEVICE_TABLE(of, exynos_mfc_match);
1513
1514 static void *mfc_get_drv_data(struct platform_device *pdev)
1515 {
1516         struct s5p_mfc_variant *driver_data = NULL;
1517
1518         if (pdev->dev.of_node) {
1519                 const struct of_device_id *match;
1520                 match = of_match_node(exynos_mfc_match,
1521                                 pdev->dev.of_node);
1522                 if (match)
1523                         driver_data = (struct s5p_mfc_variant *)match->data;
1524         } else {
1525                 driver_data = (struct s5p_mfc_variant *)
1526                         platform_get_device_id(pdev)->driver_data;
1527         }
1528         return driver_data;
1529 }
1530
1531 static struct platform_driver s5p_mfc_driver = {
1532         .probe          = s5p_mfc_probe,
1533         .remove         = s5p_mfc_remove,
1534         .id_table       = mfc_driver_ids,
1535         .driver = {
1536                 .name   = S5P_MFC_NAME,
1537                 .pm     = &s5p_mfc_pm_ops,
1538                 .of_match_table = exynos_mfc_match,
1539         },
1540 };
1541
1542 module_platform_driver(s5p_mfc_driver);
1543
1544 MODULE_LICENSE("GPL");
1545 MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1546 MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");
1547