2 * Samsung S5P Multi Format Codec v 5.1
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Kamil Debski, <k.debski@samsung.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/interrupt.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/videodev2.h>
22 #include <media/v4l2-event.h>
23 #include <linux/workqueue.h>
25 #include <media/videobuf2-core.h>
26 #include "s5p_mfc_common.h"
27 #include "s5p_mfc_ctrl.h"
28 #include "s5p_mfc_debug.h"
29 #include "s5p_mfc_dec.h"
30 #include "s5p_mfc_enc.h"
31 #include "s5p_mfc_intr.h"
32 #include "s5p_mfc_opr.h"
33 #include "s5p_mfc_cmd.h"
34 #include "s5p_mfc_pm.h"
36 #define S5P_MFC_NAME "s5p-mfc"
37 #define S5P_MFC_DEC_NAME "s5p-mfc-dec"
38 #define S5P_MFC_ENC_NAME "s5p-mfc-enc"
41 module_param(debug, int, S_IRUGO | S_IWUSR);
42 MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages");
44 /* Helper functions for interrupt processing */
46 /* Remove from hw execution round robin */
47 void clear_work_bit(struct s5p_mfc_ctx *ctx)
49 struct s5p_mfc_dev *dev = ctx->dev;
51 spin_lock(&dev->condlock);
52 __clear_bit(ctx->num, &dev->ctx_work_bits);
53 spin_unlock(&dev->condlock);
56 /* Add to hw execution round robin */
57 void set_work_bit(struct s5p_mfc_ctx *ctx)
59 struct s5p_mfc_dev *dev = ctx->dev;
61 spin_lock(&dev->condlock);
62 __set_bit(ctx->num, &dev->ctx_work_bits);
63 spin_unlock(&dev->condlock);
66 /* Remove from hw execution round robin */
67 void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
69 struct s5p_mfc_dev *dev = ctx->dev;
72 spin_lock_irqsave(&dev->condlock, flags);
73 __clear_bit(ctx->num, &dev->ctx_work_bits);
74 spin_unlock_irqrestore(&dev->condlock, flags);
77 /* Add to hw execution round robin */
78 void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
80 struct s5p_mfc_dev *dev = ctx->dev;
83 spin_lock_irqsave(&dev->condlock, flags);
84 __set_bit(ctx->num, &dev->ctx_work_bits);
85 spin_unlock_irqrestore(&dev->condlock, flags);
88 /* Wake up context wait_queue */
89 static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason,
93 ctx->int_type = reason;
98 /* Wake up device wait_queue */
99 static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason,
103 dev->int_type = reason;
105 wake_up(&dev->queue);
108 static void s5p_mfc_watchdog(unsigned long arg)
110 struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg;
112 if (test_bit(0, &dev->hw_lock))
113 atomic_inc(&dev->watchdog_cnt);
114 if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) {
115 /* This means that hw is busy and no interrupts were
116 * generated by hw for the Nth time of running this
117 * watchdog timer. This usually means a serious hw
118 * error. Now it is time to kill all instances and
120 mfc_err("Time out during waiting for HW\n");
121 queue_work(dev->watchdog_workqueue, &dev->watchdog_work);
123 dev->watchdog_timer.expires = jiffies +
124 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
125 add_timer(&dev->watchdog_timer);
128 static void s5p_mfc_watchdog_worker(struct work_struct *work)
130 struct s5p_mfc_dev *dev;
131 struct s5p_mfc_ctx *ctx;
136 dev = container_of(work, struct s5p_mfc_dev, watchdog_work);
138 mfc_err("Driver timeout error handling\n");
139 /* Lock the mutex that protects open and release.
140 * This is necessary as they may load and unload firmware. */
141 mutex_locked = mutex_trylock(&dev->mfc_mutex);
143 mfc_err("Error: some instance may be closing/opening\n");
144 spin_lock_irqsave(&dev->irqlock, flags);
148 for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
152 ctx->state = MFCINST_ERROR;
153 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue,
155 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue,
158 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0);
160 clear_bit(0, &dev->hw_lock);
161 spin_unlock_irqrestore(&dev->irqlock, flags);
162 /* Double check if there is at least one instance running.
163 * If no instance is in memory than no firmware should be present */
164 if (dev->num_inst > 0) {
165 ret = s5p_mfc_reload_firmware(dev);
167 mfc_err("Failed to reload FW\n");
171 ret = s5p_mfc_init_hw(dev);
173 mfc_err("Failed to reinit FW\n");
177 mutex_unlock(&dev->mfc_mutex);
180 static enum s5p_mfc_node_type s5p_mfc_get_node_type(struct file *file)
182 struct video_device *vdev = video_devdata(file);
185 mfc_err("failed to get video_device");
186 return MFCNODE_INVALID;
188 if (vdev->index == 0)
189 return MFCNODE_DECODER;
190 else if (vdev->index == 1)
191 return MFCNODE_ENCODER;
192 return MFCNODE_INVALID;
195 static void s5p_mfc_clear_int_flags(struct s5p_mfc_dev *dev)
197 mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT);
198 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
199 mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID);
202 static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
204 struct s5p_mfc_buf *dst_buf;
205 struct s5p_mfc_dev *dev = ctx->dev;
207 ctx->state = MFCINST_FINISHED;
209 while (!list_empty(&ctx->dst_queue)) {
210 dst_buf = list_entry(ctx->dst_queue.next,
211 struct s5p_mfc_buf, list);
212 mfc_debug(2, "Cleaning up buffer: %d\n",
213 dst_buf->b->v4l2_buf.index);
214 vb2_set_plane_payload(dst_buf->b, 0, 0);
215 vb2_set_plane_payload(dst_buf->b, 1, 0);
216 list_del(&dst_buf->list);
217 ctx->dst_queue_cnt--;
218 dst_buf->b->v4l2_buf.sequence = (ctx->sequence++);
220 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) ==
221 s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx))
222 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE;
224 dst_buf->b->v4l2_buf.field = V4L2_FIELD_INTERLACED;
226 ctx->dec_dst_flag &= ~(1 << dst_buf->b->v4l2_buf.index);
227 vb2_buffer_done(dst_buf->b, VB2_BUF_STATE_DONE);
231 static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx)
233 struct s5p_mfc_dev *dev = ctx->dev;
234 struct s5p_mfc_buf *dst_buf, *src_buf;
236 unsigned int frame_type;
238 dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev);
239 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
241 /* Copy timestamp / timecode from decoded src to dst and set
243 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
244 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
245 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dec_y_addr) {
246 memcpy(&dst_buf->b->v4l2_buf.timecode,
247 &src_buf->b->v4l2_buf.timecode,
248 sizeof(struct v4l2_timecode));
249 memcpy(&dst_buf->b->v4l2_buf.timestamp,
250 &src_buf->b->v4l2_buf.timestamp,
251 sizeof(struct timeval));
252 switch (frame_type) {
253 case S5P_FIMV_DECODE_FRAME_I_FRAME:
254 dst_buf->b->v4l2_buf.flags |=
255 V4L2_BUF_FLAG_KEYFRAME;
257 case S5P_FIMV_DECODE_FRAME_P_FRAME:
258 dst_buf->b->v4l2_buf.flags |=
259 V4L2_BUF_FLAG_PFRAME;
261 case S5P_FIMV_DECODE_FRAME_B_FRAME:
262 dst_buf->b->v4l2_buf.flags |=
263 V4L2_BUF_FLAG_BFRAME;
271 static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
273 struct s5p_mfc_dev *dev = ctx->dev;
274 struct s5p_mfc_buf *dst_buf;
276 unsigned int frame_type;
278 dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev);
279 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_disp_frame_type, ctx);
281 /* If frame is same as previous then skip and do not dequeue */
282 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) {
283 if (!ctx->after_packed_pb)
285 ctx->after_packed_pb = 0;
289 /* The MFC returns address of the buffer, now we have to
290 * check which videobuf does it correspond to */
291 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
292 /* Check if this is the buffer we're looking for */
293 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dspl_y_addr) {
294 list_del(&dst_buf->list);
295 ctx->dst_queue_cnt--;
296 dst_buf->b->v4l2_buf.sequence = ctx->sequence;
297 if (s5p_mfc_hw_call(dev->mfc_ops,
298 get_pic_type_top, ctx) ==
299 s5p_mfc_hw_call(dev->mfc_ops,
300 get_pic_type_bot, ctx))
301 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE;
303 dst_buf->b->v4l2_buf.field =
304 V4L2_FIELD_INTERLACED;
305 vb2_set_plane_payload(dst_buf->b, 0, ctx->luma_size);
306 vb2_set_plane_payload(dst_buf->b, 1, ctx->chroma_size);
307 clear_bit(dst_buf->b->v4l2_buf.index,
310 vb2_buffer_done(dst_buf->b,
311 err ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
318 /* Handle frame decoding interrupt */
319 static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
320 unsigned int reason, unsigned int err)
322 struct s5p_mfc_dev *dev = ctx->dev;
323 unsigned int dst_frame_status;
324 struct s5p_mfc_buf *src_buf;
326 unsigned int res_change;
328 dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
329 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
330 res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
331 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK)
332 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT;
333 mfc_debug(2, "Frame Status: %x\n", dst_frame_status);
334 if (ctx->state == MFCINST_RES_CHANGE_INIT)
335 ctx->state = MFCINST_RES_CHANGE_FLUSH;
336 if (res_change == S5P_FIMV_RES_INCREASE ||
337 res_change == S5P_FIMV_RES_DECREASE) {
338 ctx->state = MFCINST_RES_CHANGE_INIT;
339 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
340 wake_up_ctx(ctx, reason, err);
341 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
344 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
347 if (ctx->dpb_flush_flag)
348 ctx->dpb_flush_flag = 0;
350 spin_lock_irqsave(&dev->irqlock, flags);
351 /* All frames remaining in the buffer have been extracted */
352 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) {
353 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) {
354 s5p_mfc_handle_frame_all_extracted(ctx);
355 ctx->state = MFCINST_RES_CHANGE_END;
356 goto leave_handle_frame;
358 s5p_mfc_handle_frame_all_extracted(ctx);
362 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY ||
363 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_ONLY)
364 s5p_mfc_handle_frame_copy_time(ctx);
366 /* A frame has been decoded and is in the buffer */
367 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
368 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) {
369 s5p_mfc_handle_frame_new(ctx, err);
371 mfc_debug(2, "No frame decode\n");
373 /* Mark source buffer as complete */
374 if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
375 && !list_empty(&ctx->src_queue)) {
376 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
378 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops,
379 get_consumed_stream, dev);
380 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC &&
381 ctx->consumed_stream + STUFF_BYTE <
382 src_buf->b->v4l2_planes[0].bytesused) {
383 /* Run MFC again on the same buffer */
384 mfc_debug(2, "Running again the same buffer\n");
385 ctx->after_packed_pb = 1;
387 mfc_debug(2, "MFC needs next buffer\n");
388 ctx->consumed_stream = 0;
389 list_del(&src_buf->list);
390 ctx->src_queue_cnt--;
391 if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0)
392 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_ERROR);
394 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_DONE);
398 spin_unlock_irqrestore(&dev->irqlock, flags);
399 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
400 || ctx->dst_queue_cnt < ctx->dpb_count)
402 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
403 wake_up_ctx(ctx, reason, err);
404 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
407 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
410 /* Error handling for interrupt */
411 static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev,
412 struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err)
416 mfc_err("Interrupt Error: %08x\n", err);
419 /* Error recovery is dependent on the state of context */
420 switch (ctx->state) {
421 case MFCINST_RES_CHANGE_INIT:
422 case MFCINST_RES_CHANGE_FLUSH:
423 case MFCINST_RES_CHANGE_END:
424 case MFCINST_FINISHING:
425 case MFCINST_FINISHED:
426 case MFCINST_RUNNING:
427 /* It is higly probable that an error occured
428 * while decoding a frame */
430 ctx->state = MFCINST_ERROR;
431 /* Mark all dst buffers as having an error */
432 spin_lock_irqsave(&dev->irqlock, flags);
433 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue,
434 &ctx->dst_queue, &ctx->vq_dst);
435 /* Mark all src buffers as having an error */
436 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue,
437 &ctx->src_queue, &ctx->vq_src);
438 spin_unlock_irqrestore(&dev->irqlock, flags);
439 wake_up_ctx(ctx, reason, err);
443 ctx->state = MFCINST_ERROR;
444 wake_up_ctx(ctx, reason, err);
448 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
450 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
452 wake_up_dev(dev, reason, err);
456 /* Header parsing interrupt handling */
457 static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
458 unsigned int reason, unsigned int err)
460 struct s5p_mfc_dev *dev;
465 if (ctx->c_ops->post_seq_start) {
466 if (ctx->c_ops->post_seq_start(ctx))
467 mfc_err("post_seq_start() failed\n");
469 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width,
471 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height,
474 s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx);
476 ctx->dpb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count,
478 ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count,
480 if (ctx->img_width == 0 || ctx->img_height == 0)
481 ctx->state = MFCINST_ERROR;
483 ctx->state = MFCINST_HEAD_PARSED;
485 if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
486 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) &&
487 !list_empty(&ctx->src_queue)) {
488 struct s5p_mfc_buf *src_buf;
489 src_buf = list_entry(ctx->src_queue.next,
490 struct s5p_mfc_buf, list);
491 if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream,
493 src_buf->b->v4l2_planes[0].bytesused)
494 ctx->head_processed = 0;
496 ctx->head_processed = 1;
498 ctx->head_processed = 1;
501 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
503 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
506 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
507 wake_up_ctx(ctx, reason, err);
510 /* Header parsing interrupt handling */
511 static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
512 unsigned int reason, unsigned int err)
514 struct s5p_mfc_buf *src_buf;
515 struct s5p_mfc_dev *dev;
521 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
522 ctx->int_type = reason;
527 ctx->state = MFCINST_RUNNING;
528 if (!ctx->dpb_flush_flag && ctx->head_processed) {
529 spin_lock_irqsave(&dev->irqlock, flags);
530 if (!list_empty(&ctx->src_queue)) {
531 src_buf = list_entry(ctx->src_queue.next,
532 struct s5p_mfc_buf, list);
533 list_del(&src_buf->list);
534 ctx->src_queue_cnt--;
535 vb2_buffer_done(src_buf->b,
538 spin_unlock_irqrestore(&dev->irqlock, flags);
540 ctx->dpb_flush_flag = 0;
542 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
547 wake_up(&ctx->queue);
548 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
550 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
555 wake_up(&ctx->queue);
559 static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx,
560 unsigned int reason, unsigned int err)
562 struct s5p_mfc_dev *dev = ctx->dev;
563 struct s5p_mfc_buf *mb_entry;
565 mfc_debug(2, "Stream completed");
567 s5p_mfc_clear_int_flags(dev);
568 ctx->int_type = reason;
570 ctx->state = MFCINST_FINISHED;
572 spin_lock(&dev->irqlock);
573 if (!list_empty(&ctx->dst_queue)) {
574 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
576 list_del(&mb_entry->list);
577 ctx->dst_queue_cnt--;
578 vb2_set_plane_payload(mb_entry->b, 0, 0);
579 vb2_buffer_done(mb_entry->b, VB2_BUF_STATE_DONE);
581 spin_unlock(&dev->irqlock);
585 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
588 wake_up(&ctx->queue);
589 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
592 /* Interrupt processing */
593 static irqreturn_t s5p_mfc_irq(int irq, void *priv)
595 struct s5p_mfc_dev *dev = priv;
596 struct s5p_mfc_ctx *ctx;
601 /* Reset the timeout watchdog */
602 atomic_set(&dev->watchdog_cnt, 0);
603 ctx = dev->ctx[dev->curr_ctx];
604 /* Get the reason of interrupt and the error code */
605 reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev);
606 err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev);
607 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err);
609 case S5P_MFC_R2H_CMD_ERR_RET:
610 /* An error has occured */
611 if (ctx->state == MFCINST_RUNNING &&
612 s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >=
614 s5p_mfc_handle_frame(ctx, reason, err);
616 s5p_mfc_handle_error(dev, ctx, reason, err);
617 clear_bit(0, &dev->enter_suspend);
620 case S5P_MFC_R2H_CMD_SLICE_DONE_RET:
621 case S5P_MFC_R2H_CMD_FIELD_DONE_RET:
622 case S5P_MFC_R2H_CMD_FRAME_DONE_RET:
623 if (ctx->c_ops->post_frame_start) {
624 if (ctx->c_ops->post_frame_start(ctx))
625 mfc_err("post_frame_start() failed\n");
626 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
627 wake_up_ctx(ctx, reason, err);
628 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
631 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
633 s5p_mfc_handle_frame(ctx, reason, err);
637 case S5P_MFC_R2H_CMD_SEQ_DONE_RET:
638 s5p_mfc_handle_seq_done(ctx, reason, err);
641 case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET:
642 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev);
643 ctx->state = MFCINST_GOT_INST;
645 wake_up(&ctx->queue);
648 case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET:
650 ctx->state = MFCINST_FREE;
651 wake_up(&ctx->queue);
654 case S5P_MFC_R2H_CMD_SYS_INIT_RET:
655 case S5P_MFC_R2H_CMD_FW_STATUS_RET:
656 case S5P_MFC_R2H_CMD_SLEEP_RET:
657 case S5P_MFC_R2H_CMD_WAKEUP_RET:
660 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
661 wake_up_dev(dev, reason, err);
662 clear_bit(0, &dev->hw_lock);
663 clear_bit(0, &dev->enter_suspend);
666 case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET:
667 s5p_mfc_handle_init_buffers(ctx, reason, err);
670 case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET:
671 s5p_mfc_handle_stream_complete(ctx, reason, err);
674 case S5P_MFC_R2H_CMD_DPB_FLUSH_RET:
676 ctx->state = MFCINST_RUNNING;
677 wake_up(&ctx->queue);
681 mfc_debug(2, "Unknown int reason\n");
682 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
687 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
688 ctx->int_type = reason;
691 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
692 mfc_err("Failed to unlock hw\n");
696 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
697 mfc_debug(2, "Exit via irq_cleanup_hw\n");
701 /* Open an MFC node */
702 static int s5p_mfc_open(struct file *file)
704 struct s5p_mfc_dev *dev = video_drvdata(file);
705 struct s5p_mfc_ctx *ctx = NULL;
710 if (mutex_lock_interruptible(&dev->mfc_mutex))
712 dev->num_inst++; /* It is guarded by mfc_mutex in vfd */
713 /* Allocate memory for context */
714 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
716 mfc_err("Not enough memory\n");
720 v4l2_fh_init(&ctx->fh, video_devdata(file));
721 file->private_data = &ctx->fh;
722 v4l2_fh_add(&ctx->fh);
724 INIT_LIST_HEAD(&ctx->src_queue);
725 INIT_LIST_HEAD(&ctx->dst_queue);
726 ctx->src_queue_cnt = 0;
727 ctx->dst_queue_cnt = 0;
728 /* Get context number */
730 while (dev->ctx[ctx->num]) {
732 if (ctx->num >= MFC_NUM_CONTEXTS) {
733 mfc_err("Too many open contexts\n");
738 /* Mark context as idle */
739 clear_work_bit_irqsave(ctx);
740 dev->ctx[ctx->num] = ctx;
741 if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) {
742 ctx->type = MFCINST_DECODER;
743 ctx->c_ops = get_dec_codec_ops();
744 s5p_mfc_dec_init(ctx);
745 /* Setup ctrl handler */
746 ret = s5p_mfc_dec_ctrls_setup(ctx);
748 mfc_err("Failed to setup mfc controls\n");
749 goto err_ctrls_setup;
751 } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) {
752 ctx->type = MFCINST_ENCODER;
753 ctx->c_ops = get_enc_codec_ops();
754 /* only for encoder */
755 INIT_LIST_HEAD(&ctx->ref_queue);
756 ctx->ref_queue_cnt = 0;
757 s5p_mfc_enc_init(ctx);
758 /* Setup ctrl handler */
759 ret = s5p_mfc_enc_ctrls_setup(ctx);
761 mfc_err("Failed to setup mfc controls\n");
762 goto err_ctrls_setup;
768 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
770 /* Load firmware if this is the first instance */
771 if (dev->num_inst == 1) {
772 dev->watchdog_timer.expires = jiffies +
773 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
774 add_timer(&dev->watchdog_timer);
775 ret = s5p_mfc_power_on();
777 mfc_err("power on failed\n");
781 ret = s5p_mfc_load_firmware(dev);
787 ret = s5p_mfc_init_hw(dev);
792 /* Init videobuf2 queue for CAPTURE */
794 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
795 q->drv_priv = &ctx->fh;
796 if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) {
797 q->io_modes = VB2_MMAP;
798 q->ops = get_dec_queue_ops();
799 } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) {
800 q->io_modes = VB2_MMAP | VB2_USERPTR;
801 q->ops = get_enc_queue_ops();
806 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops;
807 ret = vb2_queue_init(q);
809 mfc_err("Failed to initialize videobuf2 queue(capture)\n");
812 /* Init videobuf2 queue for OUTPUT */
814 q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
815 q->io_modes = VB2_MMAP;
816 q->drv_priv = &ctx->fh;
817 if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) {
818 q->io_modes = VB2_MMAP;
819 q->ops = get_dec_queue_ops();
820 } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) {
821 q->io_modes = VB2_MMAP | VB2_USERPTR;
822 q->ops = get_enc_queue_ops();
827 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops;
828 ret = vb2_queue_init(q);
830 mfc_err("Failed to initialize videobuf2 queue(output)\n");
833 init_waitqueue_head(&ctx->queue);
834 mutex_unlock(&dev->mfc_mutex);
837 /* Deinit when failure occured */
839 if (dev->num_inst == 1)
840 s5p_mfc_deinit_hw(dev);
844 if (dev->num_inst == 1) {
845 if (s5p_mfc_power_off() < 0)
846 mfc_err("power off failed\n");
847 del_timer_sync(&dev->watchdog_timer);
850 s5p_mfc_dec_ctrls_delete(ctx);
852 dev->ctx[ctx->num] = NULL;
854 v4l2_fh_del(&ctx->fh);
855 v4l2_fh_exit(&ctx->fh);
859 mutex_unlock(&dev->mfc_mutex);
864 /* Release MFC context */
865 static int s5p_mfc_release(struct file *file)
867 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
868 struct s5p_mfc_dev *dev = ctx->dev;
871 mutex_lock(&dev->mfc_mutex);
873 vb2_queue_release(&ctx->vq_src);
874 vb2_queue_release(&ctx->vq_dst);
875 /* Mark context as idle */
876 clear_work_bit_irqsave(ctx);
877 /* If instance was initialised then
878 * return instance and free reosurces */
879 if (ctx->inst_no != MFC_NO_INSTANCE_SET) {
880 mfc_debug(2, "Has to free instance\n");
881 ctx->state = MFCINST_RETURN_INST;
882 set_work_bit_irqsave(ctx);
883 s5p_mfc_clean_ctx_int_flags(ctx);
884 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
885 /* Wait until instance is returned or timeout occured */
886 if (s5p_mfc_wait_for_done_ctx
887 (ctx, S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET, 0)) {
889 mfc_err("Err returning instance\n");
891 mfc_debug(2, "After free instance\n");
893 s5p_mfc_hw_call(dev->mfc_ops, release_codec_buffers, ctx);
894 s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer, ctx);
895 if (ctx->type == MFCINST_DECODER)
896 s5p_mfc_hw_call(dev->mfc_ops, release_dec_desc_buffer,
899 ctx->inst_no = MFC_NO_INSTANCE_SET;
901 /* hardware locking scheme */
902 if (dev->curr_ctx == ctx->num)
903 clear_bit(0, &dev->hw_lock);
905 if (dev->num_inst == 0) {
906 mfc_debug(2, "Last instance\n");
907 s5p_mfc_deinit_hw(dev);
908 del_timer_sync(&dev->watchdog_timer);
909 if (s5p_mfc_power_off() < 0)
910 mfc_err("Power off failed\n");
912 mfc_debug(2, "Shutting down clock\n");
914 dev->ctx[ctx->num] = NULL;
915 s5p_mfc_dec_ctrls_delete(ctx);
916 v4l2_fh_del(&ctx->fh);
917 v4l2_fh_exit(&ctx->fh);
920 mutex_unlock(&dev->mfc_mutex);
925 static unsigned int s5p_mfc_poll(struct file *file,
926 struct poll_table_struct *wait)
928 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
929 struct s5p_mfc_dev *dev = ctx->dev;
930 struct vb2_queue *src_q, *dst_q;
931 struct vb2_buffer *src_vb = NULL, *dst_vb = NULL;
935 mutex_lock(&dev->mfc_mutex);
936 src_q = &ctx->vq_src;
937 dst_q = &ctx->vq_dst;
939 * There has to be at least one buffer queued on each queued_list, which
940 * means either in driver already or waiting for driver to claim it
941 * and start processing.
943 if ((!src_q->streaming || list_empty(&src_q->queued_list))
944 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) {
948 mutex_unlock(&dev->mfc_mutex);
949 poll_wait(file, &ctx->fh.wait, wait);
950 poll_wait(file, &src_q->done_wq, wait);
951 poll_wait(file, &dst_q->done_wq, wait);
952 mutex_lock(&dev->mfc_mutex);
953 if (v4l2_event_pending(&ctx->fh))
955 spin_lock_irqsave(&src_q->done_lock, flags);
956 if (!list_empty(&src_q->done_list))
957 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer,
959 if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE
960 || src_vb->state == VB2_BUF_STATE_ERROR))
961 rc |= POLLOUT | POLLWRNORM;
962 spin_unlock_irqrestore(&src_q->done_lock, flags);
963 spin_lock_irqsave(&dst_q->done_lock, flags);
964 if (!list_empty(&dst_q->done_list))
965 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer,
967 if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE
968 || dst_vb->state == VB2_BUF_STATE_ERROR))
969 rc |= POLLIN | POLLRDNORM;
970 spin_unlock_irqrestore(&dst_q->done_lock, flags);
972 mutex_unlock(&dev->mfc_mutex);
977 static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
979 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
980 struct s5p_mfc_dev *dev = ctx->dev;
981 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
984 if (mutex_lock_interruptible(&dev->mfc_mutex))
986 if (offset < DST_QUEUE_OFF_BASE) {
987 mfc_debug(2, "mmaping source\n");
988 ret = vb2_mmap(&ctx->vq_src, vma);
989 } else { /* capture */
990 mfc_debug(2, "mmaping destination\n");
991 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
992 ret = vb2_mmap(&ctx->vq_dst, vma);
994 mutex_unlock(&dev->mfc_mutex);
999 static const struct v4l2_file_operations s5p_mfc_fops = {
1000 .owner = THIS_MODULE,
1001 .open = s5p_mfc_open,
1002 .release = s5p_mfc_release,
1003 .poll = s5p_mfc_poll,
1004 .unlocked_ioctl = video_ioctl2,
1005 .mmap = s5p_mfc_mmap,
1008 static int match_child(struct device *dev, void *data)
1012 return !strcmp(dev_name(dev), (char *)data);
1015 static void *mfc_get_drv_data(struct platform_device *pdev);
1017 static int s5p_mfc_alloc_memdevs(struct s5p_mfc_dev *dev)
1019 unsigned int mem_info[2];
1021 dev->mem_dev_l = devm_kzalloc(&dev->plat_dev->dev,
1022 sizeof(struct device), GFP_KERNEL);
1023 if (!dev->mem_dev_l) {
1024 mfc_err("Not enough memory\n");
1027 device_initialize(dev->mem_dev_l);
1028 of_property_read_u32_array(dev->plat_dev->dev.of_node,
1029 "samsung,mfc-l", mem_info, 2);
1030 if (dma_declare_coherent_memory(dev->mem_dev_l, mem_info[0],
1031 mem_info[0], mem_info[1],
1032 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) {
1033 mfc_err("Failed to declare coherent memory for\n"
1038 dev->mem_dev_r = devm_kzalloc(&dev->plat_dev->dev,
1039 sizeof(struct device), GFP_KERNEL);
1040 if (!dev->mem_dev_r) {
1041 mfc_err("Not enough memory\n");
1044 device_initialize(dev->mem_dev_r);
1045 of_property_read_u32_array(dev->plat_dev->dev.of_node,
1046 "samsung,mfc-r", mem_info, 2);
1047 if (dma_declare_coherent_memory(dev->mem_dev_r, mem_info[0],
1048 mem_info[0], mem_info[1],
1049 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) {
1050 pr_err("Failed to declare coherent memory for\n"
1057 /* MFC probe function */
1058 static int s5p_mfc_probe(struct platform_device *pdev)
1060 struct s5p_mfc_dev *dev;
1061 struct video_device *vfd;
1062 struct resource *res;
1065 pr_debug("%s++\n", __func__);
1066 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1068 dev_err(&pdev->dev, "Not enough memory for MFC device\n");
1072 spin_lock_init(&dev->irqlock);
1073 spin_lock_init(&dev->condlock);
1074 dev->plat_dev = pdev;
1075 if (!dev->plat_dev) {
1076 dev_err(&pdev->dev, "No platform data specified\n");
1080 dev->variant = mfc_get_drv_data(pdev);
1082 ret = s5p_mfc_init_pm(dev);
1084 dev_err(&pdev->dev, "failed to get mfc clock source\n");
1088 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1090 dev->regs_base = devm_ioremap_resource(&pdev->dev, res);
1091 if (IS_ERR(dev->regs_base))
1092 return PTR_ERR(dev->regs_base);
1094 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1096 dev_err(&pdev->dev, "failed to get irq resource\n");
1100 dev->irq = res->start;
1101 ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq,
1102 IRQF_DISABLED, pdev->name, dev);
1104 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
1108 if (pdev->dev.of_node) {
1109 if (s5p_mfc_alloc_memdevs(dev) < 0)
1112 dev->mem_dev_l = device_find_child(&dev->plat_dev->dev,
1113 "s5p-mfc-l", match_child);
1114 if (!dev->mem_dev_l) {
1115 mfc_err("Mem child (L) device get failed\n");
1119 dev->mem_dev_r = device_find_child(&dev->plat_dev->dev,
1120 "s5p-mfc-r", match_child);
1121 if (!dev->mem_dev_r) {
1122 mfc_err("Mem child (R) device get failed\n");
1128 dev->alloc_ctx[0] = vb2_dma_contig_init_ctx(dev->mem_dev_l);
1129 if (IS_ERR(dev->alloc_ctx[0])) {
1130 ret = PTR_ERR(dev->alloc_ctx[0]);
1133 dev->alloc_ctx[1] = vb2_dma_contig_init_ctx(dev->mem_dev_r);
1134 if (IS_ERR(dev->alloc_ctx[1])) {
1135 ret = PTR_ERR(dev->alloc_ctx[1]);
1136 goto err_mem_init_ctx_1;
1139 mutex_init(&dev->mfc_mutex);
1141 ret = s5p_mfc_alloc_firmware(dev);
1145 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1147 goto err_v4l2_dev_reg;
1148 init_waitqueue_head(&dev->queue);
1151 vfd = video_device_alloc();
1153 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1157 vfd->fops = &s5p_mfc_fops,
1158 vfd->ioctl_ops = get_dec_v4l2_ioctl_ops();
1159 vfd->release = video_device_release,
1160 vfd->lock = &dev->mfc_mutex;
1161 vfd->v4l2_dev = &dev->v4l2_dev;
1162 vfd->vfl_dir = VFL_DIR_M2M;
1163 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME);
1165 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1167 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1168 video_device_release(vfd);
1171 v4l2_info(&dev->v4l2_dev,
1172 "decoder registered as /dev/video%d\n", vfd->num);
1173 video_set_drvdata(vfd, dev);
1176 vfd = video_device_alloc();
1178 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1182 vfd->fops = &s5p_mfc_fops,
1183 vfd->ioctl_ops = get_enc_v4l2_ioctl_ops();
1184 vfd->release = video_device_release,
1185 vfd->lock = &dev->mfc_mutex;
1186 vfd->v4l2_dev = &dev->v4l2_dev;
1187 vfd->vfl_dir = VFL_DIR_M2M;
1188 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME);
1190 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1192 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1193 video_device_release(vfd);
1196 v4l2_info(&dev->v4l2_dev,
1197 "encoder registered as /dev/video%d\n", vfd->num);
1198 video_set_drvdata(vfd, dev);
1199 platform_set_drvdata(pdev, dev);
1202 dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME);
1203 INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker);
1204 atomic_set(&dev->watchdog_cnt, 0);
1205 init_timer(&dev->watchdog_timer);
1206 dev->watchdog_timer.data = (unsigned long)dev;
1207 dev->watchdog_timer.function = s5p_mfc_watchdog;
1209 /* Initialize HW ops and commands based on MFC version */
1210 s5p_mfc_init_hw_ops(dev);
1211 s5p_mfc_init_hw_cmds(dev);
1213 pr_debug("%s--\n", __func__);
1216 /* Deinit MFC if probe had failed */
1218 video_device_release(dev->vfd_enc);
1220 video_unregister_device(dev->vfd_dec);
1222 video_device_release(dev->vfd_dec);
1224 v4l2_device_unregister(&dev->v4l2_dev);
1226 s5p_mfc_release_firmware(dev);
1228 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
1230 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
1232 s5p_mfc_final_pm(dev);
1234 pr_debug("%s-- with error\n", __func__);
1239 /* Remove the driver */
1240 static int s5p_mfc_remove(struct platform_device *pdev)
1242 struct s5p_mfc_dev *dev = platform_get_drvdata(pdev);
1244 v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name);
1246 del_timer_sync(&dev->watchdog_timer);
1247 flush_workqueue(dev->watchdog_workqueue);
1248 destroy_workqueue(dev->watchdog_workqueue);
1250 video_unregister_device(dev->vfd_enc);
1251 video_unregister_device(dev->vfd_dec);
1252 v4l2_device_unregister(&dev->v4l2_dev);
1253 s5p_mfc_release_firmware(dev);
1254 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
1255 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
1256 if (pdev->dev.of_node) {
1257 put_device(dev->mem_dev_l);
1258 put_device(dev->mem_dev_r);
1261 s5p_mfc_final_pm(dev);
1265 #ifdef CONFIG_PM_SLEEP
1267 static int s5p_mfc_suspend(struct device *dev)
1269 struct platform_device *pdev = to_platform_device(dev);
1270 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1273 if (m_dev->num_inst == 0)
1276 if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) {
1277 mfc_err("Error: going to suspend for a second time\n");
1281 /* Check if we're processing then wait if it necessary. */
1282 while (test_and_set_bit(0, &m_dev->hw_lock) != 0) {
1283 /* Try and lock the HW */
1284 /* Wait on the interrupt waitqueue */
1285 ret = wait_event_interruptible_timeout(m_dev->queue,
1286 m_dev->int_cond || m_dev->ctx[m_dev->curr_ctx]->int_cond,
1287 msecs_to_jiffies(MFC_INT_TIMEOUT));
1290 mfc_err("Waiting for hardware to finish timed out\n");
1295 return s5p_mfc_sleep(m_dev);
1298 static int s5p_mfc_resume(struct device *dev)
1300 struct platform_device *pdev = to_platform_device(dev);
1301 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1303 if (m_dev->num_inst == 0)
1305 return s5p_mfc_wakeup(m_dev);
1309 #ifdef CONFIG_PM_RUNTIME
1310 static int s5p_mfc_runtime_suspend(struct device *dev)
1312 struct platform_device *pdev = to_platform_device(dev);
1313 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1315 atomic_set(&m_dev->pm.power, 0);
1319 static int s5p_mfc_runtime_resume(struct device *dev)
1321 struct platform_device *pdev = to_platform_device(dev);
1322 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1325 if (!m_dev->alloc_ctx)
1327 pre_power = atomic_read(&m_dev->pm.power);
1328 atomic_set(&m_dev->pm.power, 1);
1333 /* Power management */
1334 static const struct dev_pm_ops s5p_mfc_pm_ops = {
1335 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume)
1336 SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume,
1340 struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = {
1341 .h264_ctx = MFC_H264_CTX_BUF_SIZE,
1342 .non_h264_ctx = MFC_CTX_BUF_SIZE,
1343 .dsc = DESC_BUF_SIZE,
1344 .shm = SHARED_BUF_SIZE,
1347 struct s5p_mfc_buf_size buf_size_v5 = {
1349 .cpb = MAX_CPB_SIZE,
1350 .priv = &mfc_buf_size_v5,
1353 struct s5p_mfc_buf_align mfc_buf_align_v5 = {
1354 .base = MFC_BASE_ALIGN_ORDER,
1357 static struct s5p_mfc_variant mfc_drvdata_v5 = {
1358 .version = MFC_VERSION,
1359 .port_num = MFC_NUM_PORTS,
1360 .buf_size = &buf_size_v5,
1361 .buf_align = &mfc_buf_align_v5,
1362 .mclk_name = "sclk_mfc",
1363 .fw_name = "s5p-mfc.fw",
1366 struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = {
1367 .dev_ctx = MFC_CTX_BUF_SIZE_V6,
1368 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6,
1369 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6,
1370 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6,
1371 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6,
1374 struct s5p_mfc_buf_size buf_size_v6 = {
1375 .fw = MAX_FW_SIZE_V6,
1376 .cpb = MAX_CPB_SIZE_V6,
1377 .priv = &mfc_buf_size_v6,
1380 struct s5p_mfc_buf_align mfc_buf_align_v6 = {
1384 static struct s5p_mfc_variant mfc_drvdata_v6 = {
1385 .version = MFC_VERSION_V6,
1386 .port_num = MFC_NUM_PORTS_V6,
1387 .buf_size = &buf_size_v6,
1388 .buf_align = &mfc_buf_align_v6,
1389 .mclk_name = "aclk_333",
1390 .fw_name = "s5p-mfc-v6.fw",
1393 static struct platform_device_id mfc_driver_ids[] = {
1396 .driver_data = (unsigned long)&mfc_drvdata_v5,
1398 .name = "s5p-mfc-v5",
1399 .driver_data = (unsigned long)&mfc_drvdata_v5,
1401 .name = "s5p-mfc-v6",
1402 .driver_data = (unsigned long)&mfc_drvdata_v6,
1406 MODULE_DEVICE_TABLE(platform, mfc_driver_ids);
1408 static const struct of_device_id exynos_mfc_match[] = {
1410 .compatible = "samsung,mfc-v5",
1411 .data = &mfc_drvdata_v5,
1413 .compatible = "samsung,mfc-v6",
1414 .data = &mfc_drvdata_v6,
1418 MODULE_DEVICE_TABLE(of, exynos_mfc_match);
1420 static void *mfc_get_drv_data(struct platform_device *pdev)
1422 struct s5p_mfc_variant *driver_data = NULL;
1424 if (pdev->dev.of_node) {
1425 const struct of_device_id *match;
1426 match = of_match_node(of_match_ptr(exynos_mfc_match),
1429 driver_data = (struct s5p_mfc_variant *)match->data;
1431 driver_data = (struct s5p_mfc_variant *)
1432 platform_get_device_id(pdev)->driver_data;
1437 static struct platform_driver s5p_mfc_driver = {
1438 .probe = s5p_mfc_probe,
1439 .remove = s5p_mfc_remove,
1440 .id_table = mfc_driver_ids,
1442 .name = S5P_MFC_NAME,
1443 .owner = THIS_MODULE,
1444 .pm = &s5p_mfc_pm_ops,
1445 .of_match_table = exynos_mfc_match,
1449 module_platform_driver(s5p_mfc_driver);
1451 MODULE_LICENSE("GPL");
1452 MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1453 MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");