2 * Rockchip RK3288 VPU codec driver
4 * Copyright (C) 2014 Google, Inc.
5 * Tomasz Figa <tfiga@chromium.org>
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #ifndef RK3288_VPU_REGS_H_
18 #define RK3288_VPU_REGS_H_
20 /* Encoder registers. */
21 #define VEPU_REG_INTERRUPT 0x004
22 #define VEPU_REG_INTERRUPT_DIS_BIT BIT(1)
23 #define VEPU_REG_INTERRUPT_BIT BIT(0)
24 #define VEPU_REG_AXI_CTRL 0x008
25 #define VEPU_REG_AXI_CTRL_OUTPUT_SWAP16 BIT(15)
26 #define VEPU_REG_AXI_CTRL_INPUT_SWAP16 BIT(14)
27 #define VEPU_REG_AXI_CTRL_BURST_LEN(x) ((x) << 8)
28 #define VEPU_REG_AXI_CTRL_GATE_BIT BIT(4)
29 #define VEPU_REG_AXI_CTRL_OUTPUT_SWAP32 BIT(3)
30 #define VEPU_REG_AXI_CTRL_INPUT_SWAP32 BIT(2)
31 #define VEPU_REG_AXI_CTRL_OUTPUT_SWAP8 BIT(1)
32 #define VEPU_REG_AXI_CTRL_INPUT_SWAP8 BIT(0)
33 #define VEPU_REG_ADDR_OUTPUT_STREAM 0x014
34 #define VEPU_REG_ADDR_OUTPUT_CTRL 0x018
35 #define VEPU_REG_ADDR_REF_LUMA 0x01c
36 #define VEPU_REG_ADDR_REF_CHROMA 0x020
37 #define VEPU_REG_ADDR_REC_LUMA 0x024
38 #define VEPU_REG_ADDR_REC_CHROMA 0x028
39 #define VEPU_REG_ADDR_IN_LUMA 0x02c
40 #define VEPU_REG_ADDR_IN_CB 0x030
41 #define VEPU_REG_ADDR_IN_CR 0x034
42 #define VEPU_REG_ENC_CTRL 0x038
43 #define VEPU_REG_ENC_CTRL_NAL_MODE_BIT BIT(29)
44 #define VEPU_REG_ENC_CTRL_WIDTH(w) ((w) << 19)
45 #define VEPU_REG_ENC_CTRL_HEIGHT(h) ((h) << 10)
46 #define VEPU_REG_ENC_CTRL_KEYFRAME_BIT BIT(3)
47 #define VEPU_REG_ENC_CTRL_ENC_MODE_VP8 (0x1 << 1)
48 #define VEPU_REG_ENC_CTRL_EN_BIT BIT(0)
49 #define VEPU_REG_IN_IMG_CTRL 0x03c
50 #define VEPU_REG_IN_IMG_CTRL_ROW_LEN(x) ((x) << 12)
51 #define VEPU_REG_IN_IMG_CTRL_OVRFLR_D4(x) ((x) << 10)
52 #define VEPU_REG_IN_IMG_CTRL_OVRFLB_D4(x) ((x) << 6)
53 #define VEPU_REG_IN_IMG_CTRL_FMT(x) ((x) << 2)
54 #define VEPU_REG_ENC_CTRL0 0x040
55 #define VEPU_REG_ENC_CTRL1 0x044
56 #define VEPU_REG_ENC_CTRL2 0x048
57 #define VEPU_REG_ENC_CTRL3 0x04c
58 #define VEPU_REG_ENC_CTRL5 0x050
59 #define VEPU_REG_ENC_CTRL4 0x054
60 #define VEPU_REG_STR_HDR_REM_MSB 0x058
61 #define VEPU_REG_STR_HDR_REM_LSB 0x05c
62 #define VEPU_REG_STR_BUF_LIMIT 0x060
63 #define VEPU_REG_MAD_CTRL 0x064
64 #define VEPU_REG_ADDR_VP8_PROB_CNT 0x068
65 #define VEPU_REG_QP_VAL 0x06c
66 #define VEPU_REG_VP8_QP_VAL(i) (0x06c + ((i) * 0x4))
67 #define VEPU_REG_CHECKPOINT(i) (0x070 + ((i) * 0x4))
68 #define VEPU_REG_CHKPT_WORD_ERR(i) (0x084 + ((i) * 0x4))
69 #define VEPU_REG_VP8_BOOL_ENC 0x08c
70 #define VEPU_REG_CHKPT_DELTA_QP 0x090
71 #define VEPU_REG_VP8_CTRL0 0x090
72 #define VEPU_REG_RLC_CTRL 0x094
73 #define VEPU_REG_RLC_CTRL_STR_OFFS_SHIFT 23
74 #define VEPU_REG_RLC_CTRL_STR_OFFS_MASK (0x3f << 23)
75 #define VEPU_REG_MB_CTRL 0x098
76 #define VEPU_REG_ADDR_CABAC_TBL 0x0cc
77 #define VEPU_REG_ADDR_MV_OUT 0x0d0
78 #define VEPU_REG_RGB_YUV_COEFF(i) (0x0d4 + ((i) * 0x4))
79 #define VEPU_REG_RGB_MASK_MSB 0x0dc
80 #define VEPU_REG_INTRA_AREA_CTRL 0x0e0
81 #define VEPU_REG_CIR_INTRA_CTRL 0x0e4
82 #define VEPU_REG_INTRA_SLICE_BITMAP(i) (0x0e8 + ((i) * 0x4))
83 #define VEPU_REG_ADDR_VP8_DCT_PART(i) (0x0e8 + ((i) * 0x4))
84 #define VEPU_REG_FIRST_ROI_AREA 0x0f0
85 #define VEPU_REG_SECOND_ROI_AREA 0x0f4
86 #define VEPU_REG_MVC_CTRL 0x0f8
87 #define VEPU_REG_VP8_INTRA_PENALTY(i) (0x100 + ((i) * 0x4))
88 #define VEPU_REG_ADDR_VP8_SEG_MAP 0x11c
89 #define VEPU_REG_VP8_SEG_QP(i) (0x120 + ((i) * 0x4))
90 #define VEPU_REG_DMV_4P_1P_PENALTY(i) (0x180 + ((i) * 0x4))
91 #define VEPU_REG_DMV_QPEL_PENALTY(i) (0x200 + ((i) * 0x4))
92 #define VEPU_REG_VP8_CTRL1 0x280
93 #define VEPU_REG_VP8_BIT_COST_GOLDEN 0x284
94 #define VEPU_REG_VP8_LOOP_FLT_DELTA(i) (0x288 + ((i) * 0x4))
96 /* Decoder registers. */
97 #define VDPU_REG_INTERRUPT 0x004
98 #define VDPU_REG_INTERRUPT_DEC_PIC_INF BIT(24)
99 #define VDPU_REG_INTERRUPT_DEC_TIMEOUT BIT(18)
100 #define VDPU_REG_INTERRUPT_DEC_SLICE_INT BIT(17)
101 #define VDPU_REG_INTERRUPT_DEC_ERROR_INT BIT(16)
102 #define VDPU_REG_INTERRUPT_DEC_ASO_INT BIT(15)
103 #define VDPU_REG_INTERRUPT_DEC_BUFFER_INT BIT(14)
104 #define VDPU_REG_INTERRUPT_DEC_BUS_INT BIT(13)
105 #define VDPU_REG_INTERRUPT_DEC_RDY_INT BIT(12)
106 #define VDPU_REG_INTERRUPT_DEC_IRQ BIT(8)
107 #define VDPU_REG_INTERRUPT_DEC_IRQ_DIS BIT(4)
108 #define VDPU_REG_INTERRUPT_DEC_E BIT(0)
109 #define VDPU_REG_CONFIG 0x008
110 #define VDPU_REG_CONFIG_DEC_AXI_RD_ID(x) (((x) & 0xff) << 24)
111 #define VDPU_REG_CONFIG_DEC_TIMEOUT_E BIT(23)
112 #define VDPU_REG_CONFIG_DEC_STRSWAP32_E BIT(22)
113 #define VDPU_REG_CONFIG_DEC_STRENDIAN_E BIT(21)
114 #define VDPU_REG_CONFIG_DEC_INSWAP32_E BIT(20)
115 #define VDPU_REG_CONFIG_DEC_OUTSWAP32_E BIT(19)
116 #define VDPU_REG_CONFIG_DEC_DATA_DISC_E BIT(18)
117 #define VDPU_REG_CONFIG_TILED_MODE_MSB BIT(17)
118 #define VDPU_REG_CONFIG_DEC_OUT_TILED_E BIT(17)
119 #define VDPU_REG_CONFIG_DEC_LATENCY(x) (((x) & 0x3f) << 11)
120 #define VDPU_REG_CONFIG_DEC_CLK_GATE_E BIT(10)
121 #define VDPU_REG_CONFIG_DEC_IN_ENDIAN BIT(9)
122 #define VDPU_REG_CONFIG_DEC_OUT_ENDIAN BIT(8)
123 #define VDPU_REG_CONFIG_PRIORITY_MODE(x) (((x) & 0x7) << 5)
124 #define VDPU_REG_CONFIG_TILED_MODE_LSB BIT(7)
125 #define VDPU_REG_CONFIG_DEC_ADV_PRE_DIS BIT(6)
126 #define VDPU_REG_CONFIG_DEC_SCMD_DIS BIT(5)
127 #define VDPU_REG_CONFIG_DEC_MAX_BURST(x) (((x) & 0x1f) << 0)
128 #define VDPU_REG_DEC_CTRL0 0x00c
129 #define VDPU_REG_DEC_CTRL0_DEC_MODE(x) (((x) & 0xf) << 28)
130 #define VDPU_REG_DEC_CTRL0_RLC_MODE_E BIT(27)
131 #define VDPU_REG_DEC_CTRL0_SKIP_MODE BIT(26)
132 #define VDPU_REG_DEC_CTRL0_DIVX3_E BIT(25)
133 #define VDPU_REG_DEC_CTRL0_PJPEG_E BIT(24)
134 #define VDPU_REG_DEC_CTRL0_PIC_INTERLACE_E BIT(23)
135 #define VDPU_REG_DEC_CTRL0_PIC_FIELDMODE_E BIT(22)
136 #define VDPU_REG_DEC_CTRL0_PIC_B_E BIT(21)
137 #define VDPU_REG_DEC_CTRL0_PIC_INTER_E BIT(20)
138 #define VDPU_REG_DEC_CTRL0_PIC_TOPFIELD_E BIT(19)
139 #define VDPU_REG_DEC_CTRL0_FWD_INTERLACE_E BIT(18)
140 #define VDPU_REG_DEC_CTRL0_SORENSON_E BIT(17)
141 #define VDPU_REG_DEC_CTRL0_REF_TOPFIELD_E BIT(16)
142 #define VDPU_REG_DEC_CTRL0_DEC_OUT_DIS BIT(15)
143 #define VDPU_REG_DEC_CTRL0_FILTERING_DIS BIT(14)
144 #define VDPU_REG_DEC_CTRL0_WEBP_E BIT(13)
145 #define VDPU_REG_DEC_CTRL0_MVC_E BIT(13)
146 #define VDPU_REG_DEC_CTRL0_PIC_FIXED_QUANT BIT(13)
147 #define VDPU_REG_DEC_CTRL0_WRITE_MVS_E BIT(12)
148 #define VDPU_REG_DEC_CTRL0_REFTOPFIRST_E BIT(11)
149 #define VDPU_REG_DEC_CTRL0_SEQ_MBAFF_E BIT(10)
150 #define VDPU_REG_DEC_CTRL0_PICORD_COUNT_E BIT(9)
151 #define VDPU_REG_DEC_CTRL0_DEC_AHB_HLOCK_E BIT(8)
152 #define VDPU_REG_DEC_CTRL0_DEC_AXI_WR_ID(x) (((x) & 0xff) << 0)
153 #define VDPU_REG_DEC_CTRL1 0x010
154 #define VDPU_REG_DEC_CTRL1_PIC_MB_WIDTH(x) (((x) & 0x1ff) << 23)
155 #define VDPU_REG_DEC_CTRL1_MB_WIDTH_OFF(x) (((x) & 0xf) << 19)
156 #define VDPU_REG_DEC_CTRL1_PIC_MB_HEIGHT_P(x) (((x) & 0xff) << 11)
157 #define VDPU_REG_DEC_CTRL1_MB_HEIGHT_OFF(x) (((x) & 0xf) << 7)
158 #define VDPU_REG_DEC_CTRL1_ALT_SCAN_E BIT(6)
159 #define VDPU_REG_DEC_CTRL1_TOPFIELDFIRST_E BIT(5)
160 #define VDPU_REG_DEC_CTRL1_REF_FRAMES(x) (((x) & 0x1f) << 0)
161 #define VDPU_REG_DEC_CTRL1_PIC_MB_W_EXT(x) (((x) & 0x7) << 3)
162 #define VDPU_REG_DEC_CTRL1_PIC_MB_H_EXT(x) (((x) & 0x7) << 0)
163 #define VDPU_REG_DEC_CTRL1_PIC_REFER_FLAG BIT(0)
164 #define VDPU_REG_DEC_CTRL2 0x014
165 #define VDPU_REG_DEC_CTRL2_STRM_START_BIT(x) (((x) & 0x3f) << 26)
166 #define VDPU_REG_DEC_CTRL2_SYNC_MARKER_E BIT(25)
167 #define VDPU_REG_DEC_CTRL2_TYPE1_QUANT_E BIT(24)
168 #define VDPU_REG_DEC_CTRL2_CH_QP_OFFSET(x) (((x) & 0x1f) << 19)
169 #define VDPU_REG_DEC_CTRL2_CH_QP_OFFSET2(x) (((x) & 0x1f) << 14)
170 #define VDPU_REG_DEC_CTRL2_FIELDPIC_FLAG_E BIT(0)
171 #define VDPU_REG_DEC_CTRL2_INTRADC_VLC_THR(x) (((x) & 0x7) << 16)
172 #define VDPU_REG_DEC_CTRL2_VOP_TIME_INCR(x) (((x) & 0xffff) << 0)
173 #define VDPU_REG_DEC_CTRL2_DQ_PROFILE BIT(24)
174 #define VDPU_REG_DEC_CTRL2_DQBI_LEVEL BIT(23)
175 #define VDPU_REG_DEC_CTRL2_RANGE_RED_FRM_E BIT(22)
176 #define VDPU_REG_DEC_CTRL2_FAST_UVMC_E BIT(20)
177 #define VDPU_REG_DEC_CTRL2_TRANSDCTAB BIT(17)
178 #define VDPU_REG_DEC_CTRL2_TRANSACFRM(x) (((x) & 0x3) << 15)
179 #define VDPU_REG_DEC_CTRL2_TRANSACFRM2(x) (((x) & 0x3) << 13)
180 #define VDPU_REG_DEC_CTRL2_MB_MODE_TAB(x) (((x) & 0x7) << 10)
181 #define VDPU_REG_DEC_CTRL2_MVTAB(x) (((x) & 0x7) << 7)
182 #define VDPU_REG_DEC_CTRL2_CBPTAB(x) (((x) & 0x7) << 4)
183 #define VDPU_REG_DEC_CTRL2_2MV_BLK_PAT_TAB(x) (((x) & 0x3) << 2)
184 #define VDPU_REG_DEC_CTRL2_4MV_BLK_PAT_TAB(x) (((x) & 0x3) << 0)
185 #define VDPU_REG_DEC_CTRL2_QSCALE_TYPE BIT(24)
186 #define VDPU_REG_DEC_CTRL2_CON_MV_E BIT(4)
187 #define VDPU_REG_DEC_CTRL2_INTRA_DC_PREC(x) (((x) & 0x3) << 2)
188 #define VDPU_REG_DEC_CTRL2_INTRA_VLC_TAB BIT(1)
189 #define VDPU_REG_DEC_CTRL2_FRAME_PRED_DCT BIT(0)
190 #define VDPU_REG_DEC_CTRL2_JPEG_QTABLES(x) (((x) & 0x3) << 11)
191 #define VDPU_REG_DEC_CTRL2_JPEG_MODE(x) (((x) & 0x7) << 8)
192 #define VDPU_REG_DEC_CTRL2_JPEG_FILRIGHT_E BIT(7)
193 #define VDPU_REG_DEC_CTRL2_JPEG_STREAM_ALL BIT(6)
194 #define VDPU_REG_DEC_CTRL2_CR_AC_VLCTABLE BIT(5)
195 #define VDPU_REG_DEC_CTRL2_CB_AC_VLCTABLE BIT(4)
196 #define VDPU_REG_DEC_CTRL2_CR_DC_VLCTABLE BIT(3)
197 #define VDPU_REG_DEC_CTRL2_CB_DC_VLCTABLE BIT(2)
198 #define VDPU_REG_DEC_CTRL2_CR_DC_VLCTABLE3 BIT(1)
199 #define VDPU_REG_DEC_CTRL2_CB_DC_VLCTABLE3 BIT(0)
200 #define VDPU_REG_DEC_CTRL2_STRM1_START_BIT(x) (((x) & 0x3f) << 18)
201 #define VDPU_REG_DEC_CTRL2_HUFFMAN_E BIT(17)
202 #define VDPU_REG_DEC_CTRL2_MULTISTREAM_E BIT(16)
203 #define VDPU_REG_DEC_CTRL2_BOOLEAN_VALUE(x) (((x) & 0xff) << 8)
204 #define VDPU_REG_DEC_CTRL2_BOOLEAN_RANGE(x) (((x) & 0xff) << 0)
205 #define VDPU_REG_DEC_CTRL2_ALPHA_OFFSET(x) (((x) & 0x1f) << 5)
206 #define VDPU_REG_DEC_CTRL2_BETA_OFFSET(x) (((x) & 0x1f) << 0)
207 #define VDPU_REG_DEC_CTRL3 0x018
208 #define VDPU_REG_DEC_CTRL3_START_CODE_E BIT(31)
209 #define VDPU_REG_DEC_CTRL3_INIT_QP(x) (((x) & 0x3f) << 25)
210 #define VDPU_REG_DEC_CTRL3_CH_8PIX_ILEAV_E BIT(24)
211 #define VDPU_REG_DEC_CTRL3_STREAM_LEN_EXT(x) (((x) & 0xff) << 24)
212 #define VDPU_REG_DEC_CTRL3_STREAM_LEN(x) (((x) & 0xffffff) << 0)
213 #define VDPU_REG_DEC_CTRL4 0x01c
214 #define VDPU_REG_DEC_CTRL4_CABAC_E BIT(31)
215 #define VDPU_REG_DEC_CTRL4_BLACKWHITE_E BIT(30)
216 #define VDPU_REG_DEC_CTRL4_DIR_8X8_INFER_E BIT(29)
217 #define VDPU_REG_DEC_CTRL4_WEIGHT_PRED_E BIT(28)
218 #define VDPU_REG_DEC_CTRL4_WEIGHT_BIPR_IDC(x) (((x) & 0x3) << 26)
219 #define VDPU_REG_DEC_CTRL4_AVS_H264_H_EXT BIT(25)
220 #define VDPU_REG_DEC_CTRL4_FRAMENUM_LEN(x) (((x) & 0x1f) << 16)
221 #define VDPU_REG_DEC_CTRL4_FRAMENUM(x) (((x) & 0xffff) << 0)
222 #define VDPU_REG_DEC_CTRL4_BITPLANE0_E BIT(31)
223 #define VDPU_REG_DEC_CTRL4_BITPLANE1_E BIT(30)
224 #define VDPU_REG_DEC_CTRL4_BITPLANE2_E BIT(29)
225 #define VDPU_REG_DEC_CTRL4_ALT_PQUANT(x) (((x) & 0x1f) << 24)
226 #define VDPU_REG_DEC_CTRL4_DQ_EDGES(x) (((x) & 0xf) << 20)
227 #define VDPU_REG_DEC_CTRL4_TTMBF BIT(19)
228 #define VDPU_REG_DEC_CTRL4_PQINDEX(x) (((x) & 0x1f) << 14)
229 #define VDPU_REG_DEC_CTRL4_VC1_HEIGHT_EXT BIT(13)
230 #define VDPU_REG_DEC_CTRL4_BILIN_MC_E BIT(12)
231 #define VDPU_REG_DEC_CTRL4_UNIQP_E BIT(11)
232 #define VDPU_REG_DEC_CTRL4_HALFQP_E BIT(10)
233 #define VDPU_REG_DEC_CTRL4_TTFRM(x) (((x) & 0x3) << 8)
234 #define VDPU_REG_DEC_CTRL4_2ND_BYTE_EMUL_E BIT(7)
235 #define VDPU_REG_DEC_CTRL4_DQUANT_E BIT(6)
236 #define VDPU_REG_DEC_CTRL4_VC1_ADV_E BIT(5)
237 #define VDPU_REG_DEC_CTRL4_PJPEG_FILDOWN_E BIT(26)
238 #define VDPU_REG_DEC_CTRL4_PJPEG_WDIV8 BIT(25)
239 #define VDPU_REG_DEC_CTRL4_PJPEG_HDIV8 BIT(24)
240 #define VDPU_REG_DEC_CTRL4_PJPEG_AH(x) (((x) & 0xf) << 20)
241 #define VDPU_REG_DEC_CTRL4_PJPEG_AL(x) (((x) & 0xf) << 16)
242 #define VDPU_REG_DEC_CTRL4_PJPEG_SS(x) (((x) & 0xff) << 8)
243 #define VDPU_REG_DEC_CTRL4_PJPEG_SE(x) (((x) & 0xff) << 0)
244 #define VDPU_REG_DEC_CTRL4_DCT1_START_BIT(x) (((x) & 0x3f) << 26)
245 #define VDPU_REG_DEC_CTRL4_DCT2_START_BIT(x) (((x) & 0x3f) << 20)
246 #define VDPU_REG_DEC_CTRL4_CH_MV_RES BIT(13)
247 #define VDPU_REG_DEC_CTRL4_INIT_DC_MATCH0(x) (((x) & 0x7) << 9)
248 #define VDPU_REG_DEC_CTRL4_INIT_DC_MATCH1(x) (((x) & 0x7) << 6)
249 #define VDPU_REG_DEC_CTRL4_VP7_VERSION BIT(5)
250 #define VDPU_REG_DEC_CTRL5 0x020
251 #define VDPU_REG_DEC_CTRL5_CONST_INTRA_E BIT(31)
252 #define VDPU_REG_DEC_CTRL5_FILT_CTRL_PRES BIT(30)
253 #define VDPU_REG_DEC_CTRL5_RDPIC_CNT_PRES BIT(29)
254 #define VDPU_REG_DEC_CTRL5_8X8TRANS_FLAG_E BIT(28)
255 #define VDPU_REG_DEC_CTRL5_REFPIC_MK_LEN(x) (((x) & 0x7ff) << 17)
256 #define VDPU_REG_DEC_CTRL5_IDR_PIC_E BIT(16)
257 #define VDPU_REG_DEC_CTRL5_IDR_PIC_ID(x) (((x) & 0xffff) << 0)
258 #define VDPU_REG_DEC_CTRL5_MV_SCALEFACTOR(x) (((x) & 0xff) << 24)
259 #define VDPU_REG_DEC_CTRL5_REF_DIST_FWD(x) (((x) & 0x1f) << 19)
260 #define VDPU_REG_DEC_CTRL5_REF_DIST_BWD(x) (((x) & 0x1f) << 14)
261 #define VDPU_REG_DEC_CTRL5_LOOP_FILT_LIMIT(x) (((x) & 0xf) << 14)
262 #define VDPU_REG_DEC_CTRL5_VARIANCE_TEST_E BIT(13)
263 #define VDPU_REG_DEC_CTRL5_MV_THRESHOLD(x) (((x) & 0x7) << 10)
264 #define VDPU_REG_DEC_CTRL5_VAR_THRESHOLD(x) (((x) & 0x3ff) << 0)
265 #define VDPU_REG_DEC_CTRL5_DIVX_IDCT_E BIT(8)
266 #define VDPU_REG_DEC_CTRL5_DIVX3_SLICE_SIZE(x) (((x) & 0xff) << 0)
267 #define VDPU_REG_DEC_CTRL5_PJPEG_REST_FREQ(x) (((x) & 0xffff) << 0)
268 #define VDPU_REG_DEC_CTRL5_RV_PROFILE(x) (((x) & 0x3) << 30)
269 #define VDPU_REG_DEC_CTRL5_RV_OSV_QUANT(x) (((x) & 0x3) << 28)
270 #define VDPU_REG_DEC_CTRL5_RV_FWD_SCALE(x) (((x) & 0x3fff) << 14)
271 #define VDPU_REG_DEC_CTRL5_RV_BWD_SCALE(x) (((x) & 0x3fff) << 0)
272 #define VDPU_REG_DEC_CTRL5_INIT_DC_COMP0(x) (((x) & 0xffff) << 16)
273 #define VDPU_REG_DEC_CTRL5_INIT_DC_COMP1(x) (((x) & 0xffff) << 0)
274 #define VDPU_REG_DEC_CTRL6 0x024
275 #define VDPU_REG_DEC_CTRL6_PPS_ID(x) (((x) & 0xff) << 24)
276 #define VDPU_REG_DEC_CTRL6_REFIDX1_ACTIVE(x) (((x) & 0x1f) << 19)
277 #define VDPU_REG_DEC_CTRL6_REFIDX0_ACTIVE(x) (((x) & 0x1f) << 14)
278 #define VDPU_REG_DEC_CTRL6_POC_LENGTH(x) (((x) & 0xff) << 0)
279 #define VDPU_REG_DEC_CTRL6_ICOMP0_E BIT(24)
280 #define VDPU_REG_DEC_CTRL6_ISCALE0(x) (((x) & 0xff) << 16)
281 #define VDPU_REG_DEC_CTRL6_ISHIFT0(x) (((x) & 0xffff) << 0)
282 #define VDPU_REG_DEC_CTRL6_STREAM1_LEN(x) (((x) & 0xffffff) << 0)
283 #define VDPU_REG_DEC_CTRL6_PIC_SLICE_AM(x) (((x) & 0x1fff) << 0)
284 #define VDPU_REG_DEC_CTRL6_COEFFS_PART_AM(x) (((x) & 0xf) << 24)
285 #define VDPU_REG_FWD_PIC(i) (0x028 + ((i) * 0x4))
286 #define VDPU_REG_FWD_PIC_PINIT_RLIST_F5(x) (((x) & 0x1f) << 25)
287 #define VDPU_REG_FWD_PIC_PINIT_RLIST_F4(x) (((x) & 0x1f) << 20)
288 #define VDPU_REG_FWD_PIC_PINIT_RLIST_F3(x) (((x) & 0x1f) << 15)
289 #define VDPU_REG_FWD_PIC_PINIT_RLIST_F2(x) (((x) & 0x1f) << 10)
290 #define VDPU_REG_FWD_PIC_PINIT_RLIST_F1(x) (((x) & 0x1f) << 5)
291 #define VDPU_REG_FWD_PIC_PINIT_RLIST_F0(x) (((x) & 0x1f) << 0)
292 #define VDPU_REG_FWD_PIC1_ICOMP1_E BIT(24)
293 #define VDPU_REG_FWD_PIC1_ISCALE1(x) (((x) & 0xff) << 16)
294 #define VDPU_REG_FWD_PIC1_ISHIFT1(x) (((x) & 0xffff) << 0)
295 #define VDPU_REG_FWD_PIC1_SEGMENT_BASE(x) ((x) << 0)
296 #define VDPU_REG_FWD_PIC1_SEGMENT_UPD_E BIT(1)
297 #define VDPU_REG_FWD_PIC1_SEGMENT_E BIT(0)
298 #define VDPU_REG_DEC_CTRL7 0x02c
299 #define VDPU_REG_DEC_CTRL7_PINIT_RLIST_F15(x) (((x) & 0x1f) << 25)
300 #define VDPU_REG_DEC_CTRL7_PINIT_RLIST_F14(x) (((x) & 0x1f) << 20)
301 #define VDPU_REG_DEC_CTRL7_PINIT_RLIST_F13(x) (((x) & 0x1f) << 15)
302 #define VDPU_REG_DEC_CTRL7_PINIT_RLIST_F12(x) (((x) & 0x1f) << 10)
303 #define VDPU_REG_DEC_CTRL7_PINIT_RLIST_F11(x) (((x) & 0x1f) << 5)
304 #define VDPU_REG_DEC_CTRL7_PINIT_RLIST_F10(x) (((x) & 0x1f) << 0)
305 #define VDPU_REG_DEC_CTRL7_ICOMP2_E BIT(24)
306 #define VDPU_REG_DEC_CTRL7_ISCALE2(x) (((x) & 0xff) << 16)
307 #define VDPU_REG_DEC_CTRL7_ISHIFT2(x) (((x) & 0xffff) << 0)
308 #define VDPU_REG_DEC_CTRL7_DCT3_START_BIT(x) (((x) & 0x3f) << 24)
309 #define VDPU_REG_DEC_CTRL7_DCT4_START_BIT(x) (((x) & 0x3f) << 18)
310 #define VDPU_REG_DEC_CTRL7_DCT5_START_BIT(x) (((x) & 0x3f) << 12)
311 #define VDPU_REG_DEC_CTRL7_DCT6_START_BIT(x) (((x) & 0x3f) << 6)
312 #define VDPU_REG_DEC_CTRL7_DCT7_START_BIT(x) (((x) & 0x3f) << 0)
313 #define VDPU_REG_ADDR_STR 0x030
314 #define VDPU_REG_ADDR_DST 0x034
315 #define VDPU_REG_ADDR_REF(i) (0x038 + ((i) * 0x4))
316 #define VDPU_REG_ADDR_REF_FIELD_E BIT(1)
317 #define VDPU_REG_ADDR_REF_TOPC_E BIT(0)
318 #define VDPU_REG_REF_PIC(i) (0x078 + ((i) * 0x4))
319 #define VDPU_REG_REF_PIC_FILT_TYPE_E BIT(31)
320 #define VDPU_REG_REF_PIC_FILT_SHARPNESS(x) (((x) & 0x7) << 28)
321 #define VDPU_REG_REF_PIC_MB_ADJ_0(x) (((x) & 0x7f) << 21)
322 #define VDPU_REG_REF_PIC_MB_ADJ_1(x) (((x) & 0x7f) << 14)
323 #define VDPU_REG_REF_PIC_MB_ADJ_2(x) (((x) & 0x7f) << 7)
324 #define VDPU_REG_REF_PIC_MB_ADJ_3(x) (((x) & 0x7f) << 0)
325 #define VDPU_REG_REF_PIC_REFER1_NBR(x) (((x) & 0xffff) << 16)
326 #define VDPU_REG_REF_PIC_REFER0_NBR(x) (((x) & 0xffff) << 0)
327 #define VDPU_REG_REF_PIC_LF_LEVEL_0(x) (((x) & 0x3f) << 18)
328 #define VDPU_REG_REF_PIC_LF_LEVEL_1(x) (((x) & 0x3f) << 12)
329 #define VDPU_REG_REF_PIC_LF_LEVEL_2(x) (((x) & 0x3f) << 6)
330 #define VDPU_REG_REF_PIC_LF_LEVEL_3(x) (((x) & 0x3f) << 0)
331 #define VDPU_REG_REF_PIC_QUANT_DELTA_0(x) (((x) & 0x1f) << 27)
332 #define VDPU_REG_REF_PIC_QUANT_DELTA_1(x) (((x) & 0x1f) << 22)
333 #define VDPU_REG_REF_PIC_QUANT_0(x) (((x) & 0x7ff) << 11)
334 #define VDPU_REG_REF_PIC_QUANT_1(x) (((x) & 0x7ff) << 0)
335 #define VDPU_REG_LT_REF 0x098
336 #define VDPU_REG_VALID_REF 0x09c
337 #define VDPU_REG_ADDR_QTABLE 0x0a0
338 #define VDPU_REG_ADDR_DIR_MV 0x0a4
339 #define VDPU_REG_BD_REF_PIC(i) (0x0a8 + ((i) * 0x4))
340 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B2(x) (((x) & 0x1f) << 25)
341 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F2(x) (((x) & 0x1f) << 20)
342 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B1(x) (((x) & 0x1f) << 15)
343 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F1(x) (((x) & 0x1f) << 10)
344 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B0(x) (((x) & 0x1f) << 5)
345 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F0(x) (((x) & 0x1f) << 0)
346 #define VDPU_REG_BD_REF_PIC_PRED_TAP_2_M1(x) (((x) & 0x3) << 10)
347 #define VDPU_REG_BD_REF_PIC_PRED_TAP_2_4(x) (((x) & 0x3) << 8)
348 #define VDPU_REG_BD_REF_PIC_PRED_TAP_4_M1(x) (((x) & 0x3) << 6)
349 #define VDPU_REG_BD_REF_PIC_PRED_TAP_4_4(x) (((x) & 0x3) << 4)
350 #define VDPU_REG_BD_REF_PIC_PRED_TAP_6_M1(x) (((x) & 0x3) << 2)
351 #define VDPU_REG_BD_REF_PIC_PRED_TAP_6_4(x) (((x) & 0x3) << 0)
352 #define VDPU_REG_BD_REF_PIC_QUANT_DELTA_2(x) (((x) & 0x1f) << 27)
353 #define VDPU_REG_BD_REF_PIC_QUANT_DELTA_3(x) (((x) & 0x1f) << 22)
354 #define VDPU_REG_BD_REF_PIC_QUANT_2(x) (((x) & 0x7ff) << 11)
355 #define VDPU_REG_BD_REF_PIC_QUANT_3(x) (((x) & 0x7ff) << 0)
356 #define VDPU_REG_BD_P_REF_PIC 0x0bc
357 #define VDPU_REG_BD_P_REF_PIC_QUANT_DELTA_4(x) (((x) & 0x1f) << 27)
358 #define VDPU_REG_BD_P_REF_PIC_PINIT_RLIST_F3(x) (((x) & 0x1f) << 25)
359 #define VDPU_REG_BD_P_REF_PIC_PINIT_RLIST_F2(x) (((x) & 0x1f) << 20)
360 #define VDPU_REG_BD_P_REF_PIC_PINIT_RLIST_F1(x) (((x) & 0x1f) << 15)
361 #define VDPU_REG_BD_P_REF_PIC_PINIT_RLIST_F0(x) (((x) & 0x1f) << 10)
362 #define VDPU_REG_BD_P_REF_PIC_BINIT_RLIST_B15(x) (((x) & 0x1f) << 5)
363 #define VDPU_REG_BD_P_REF_PIC_BINIT_RLIST_F15(x) (((x) & 0x1f) << 0)
364 #define VDPU_REG_ERR_CONC 0x0c0
365 #define VDPU_REG_ERR_CONC_STARTMB_X(x) (((x) & 0x1ff) << 23)
366 #define VDPU_REG_ERR_CONC_STARTMB_Y(x) (((x) & 0xff) << 15)
367 #define VDPU_REG_PRED_FLT 0x0c4
368 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_0_0(x) (((x) & 0x3ff) << 22)
369 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_0_1(x) (((x) & 0x3ff) << 12)
370 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_0_2(x) (((x) & 0x3ff) << 2)
371 #define VDPU_REG_REF_BUF_CTRL 0x0cc
372 #define VDPU_REG_REF_BUF_CTRL_REFBU_E BIT(31)
373 #define VDPU_REG_REF_BUF_CTRL_REFBU_THR(x) (((x) & 0xfff) << 19)
374 #define VDPU_REG_REF_BUF_CTRL_REFBU_PICID(x) (((x) & 0x1f) << 14)
375 #define VDPU_REG_REF_BUF_CTRL_REFBU_EVAL_E BIT(13)
376 #define VDPU_REG_REF_BUF_CTRL_REFBU_FPARMOD_E BIT(12)
377 #define VDPU_REG_REF_BUF_CTRL_REFBU_Y_OFFSET(x) (((x) & 0x1ff) << 0)
378 #define VDPU_REG_REF_BUF_CTRL2 0x0dc
379 #define VDPU_REG_REF_BUF_CTRL2_REFBU2_BUF_E BIT(31)
380 #define VDPU_REG_REF_BUF_CTRL2_REFBU2_THR(x) (((x) & 0xfff) << 19)
381 #define VDPU_REG_REF_BUF_CTRL2_REFBU2_PICID(x) (((x) & 0x1f) << 14)
382 #define VDPU_REG_REF_BUF_CTRL2_APF_THRESHOLD(x) (((x) & 0x3fff) << 0)
384 #endif /* RK3288_VPU_REGS_H_ */
projects / firefly-linux-kernel-4.4.55.git / blob