drivers/media/platform/rk3288-vpu/rk3288_vpu_hw_vp8e.c

   1 /*
   2  * Rockchip RK3288 VPU codec driver
   3  *
   4  * Copyright (C) 2014 Rockchip Electronics Co., Ltd.
   5  *      Alpha Lin <Alpha.Lin@rock-chips.com>
   6  *      Jeffy Chen <jeffy.chen@rock-chips.com>
   7  *
   8  * Copyright (C) 2014 Google, Inc.
   9  *      Tomasz Figa <tfiga@chromium.org>
  10  *
  11  * This software is licensed under the terms of the GNU General Public
  12  * License version 2, as published by the Free Software Foundation, and
  13  * may be copied, distributed, and modified under those terms.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  */
  20
  21 #include "rk3288_vpu_common.h"
  22
  23 #include <linux/types.h>
  24 #include <linux/sort.h>
  25
  26 #include "rk3288_vpu_regs.h"
  27 #include "rk3288_vpu_hw.h"
  28
  29 /* Various parameters specific to VP8 encoder. */
  30 #define VP8_CABAC_CTX_OFFSET                    192
  31 #define VP8_CABAC_CTX_SIZE                      ((55 + 96) << 3)
  32
  33 #define VP8_KEY_FRAME_HDR_SIZE                  10
  34 #define VP8_INTER_FRAME_HDR_SIZE                3
  35
  36 #define VP8_FRAME_TAG_KEY_FRAME_BIT             BIT(0)
  37 #define VP8_FRAME_TAG_LENGTH_SHIFT              5
  38 #define VP8_FRAME_TAG_LENGTH_MASK               (0x7ffff << 5)
  39
  40 /**
  41  * struct rk3288_vpu_vp8e_ctrl_buf - hardware control buffer layout
  42  * @ext_hdr_size:       Ext header size in bytes (written by hardware).
  43  * @dct_size:           DCT partition size (written by hardware).
  44  * @rsvd:               Reserved for hardware.
  45  */
  46 struct rk3288_vpu_vp8e_ctrl_buf {
  47         u32 ext_hdr_size;
  48         u32 dct_size;
  49         u8 rsvd[1016];
  50 };
  51
  52 /*
  53  * The hardware takes care only of ext hdr and dct partition. The software
  54  * must take care of frame header.
  55  *
  56  * Buffer layout as received from hardware:
  57  *   |<--gap-->|<--ext hdr-->|<-gap->|<---dct part---
  58  *   |<-------dct part offset------->|
  59  *
  60  * Required buffer layout:
  61  *   |<--hdr-->|<--ext hdr-->|<---dct part---
  62  */
  63 void rk3288_vpu_vp8e_assemble_bitstream(struct rk3288_vpu_ctx *ctx,
  64                                         struct rk3288_vpu_buf *dst_buf)
  65 {
  66         size_t ext_hdr_size = dst_buf->vp8e.ext_hdr_size;
  67         size_t dct_size = dst_buf->vp8e.dct_size;
  68         size_t hdr_size = dst_buf->vp8e.hdr_size;
  69         size_t dst_size;
  70         size_t tag_size;
  71         void *dst;
  72         u32 *tag;
  73
  74         dst_size = vb2_plane_size(&dst_buf->b, 0);
  75         dst = vb2_plane_vaddr(&dst_buf->b, 0);
  76         tag = dst; /* To access frame tag words. */
  77
  78         if (WARN_ON(hdr_size + ext_hdr_size + dct_size > dst_size))
  79                 return;
  80         if (WARN_ON(dst_buf->vp8e.dct_offset + dct_size > dst_size))
  81                 return;
  82
  83         vpu_debug(1, "%s: hdr_size = %u, ext_hdr_size = %u, dct_size = %u\n",
  84                         __func__, hdr_size, ext_hdr_size, dct_size);
  85
  86         memmove(dst + hdr_size + ext_hdr_size,
  87                 dst + dst_buf->vp8e.dct_offset, dct_size);
  88         memcpy(dst, dst_buf->vp8e.header, hdr_size);
  89
  90         /* Patch frame tag at first 32-bit word of the frame. */
  91         if (dst_buf->b.v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
  92                 tag_size = VP8_KEY_FRAME_HDR_SIZE;
  93                 tag[0] &= ~VP8_FRAME_TAG_KEY_FRAME_BIT;
  94         } else {
  95                 tag_size = VP8_INTER_FRAME_HDR_SIZE;
  96                 tag[0] |= VP8_FRAME_TAG_KEY_FRAME_BIT;
  97         }
  98
  99         tag[0] &= ~VP8_FRAME_TAG_LENGTH_MASK;
 100         tag[0] |= (hdr_size + ext_hdr_size - tag_size)
 101                                                 << VP8_FRAME_TAG_LENGTH_SHIFT;
 102
 103         vb2_set_plane_payload(&dst_buf->b, 0,
 104                                 hdr_size + ext_hdr_size + dct_size);
 105 }
 106
 107 static inline unsigned int ref_luma_size(unsigned int w, unsigned int h)
 108 {
 109         return round_up(w, MB_DIM) * round_up(h, MB_DIM);
 110 }
 111
 112 int rk3288_vpu_vp8e_init(struct rk3288_vpu_ctx *ctx)
 113 {
 114         struct rk3288_vpu_dev *vpu = ctx->dev;
 115         size_t height = ctx->src_fmt.height;
 116         size_t width = ctx->src_fmt.width;
 117         size_t ref_buf_size;
 118         size_t mv_size;
 119         int ret;
 120
 121         ret = rk3288_vpu_aux_buf_alloc(vpu, &ctx->hw.vp8e.ctrl_buf,
 122                                 sizeof(struct rk3288_vpu_vp8e_ctrl_buf));
 123         if (ret) {
 124                 vpu_err("failed to allocate ctrl buffer\n");
 125                 return ret;
 126         }
 127
 128         mv_size = DIV_ROUND_UP(width, 16) * DIV_ROUND_UP(height, 16) / 4;
 129         ret = rk3288_vpu_aux_buf_alloc(vpu, &ctx->hw.vp8e.mv_buf, mv_size);
 130         if (ret) {
 131                 vpu_err("failed to allocate MV buffer\n");
 132                 goto err_ctrl_buf;
 133         }
 134
 135         ref_buf_size = ref_luma_size(width, height) * 3 / 2;
 136         ret = rk3288_vpu_aux_buf_alloc(vpu, &ctx->hw.vp8e.ext_buf,
 137                                         2 * ref_buf_size);
 138         if (ret) {
 139                 vpu_err("failed to allocate ext buffer\n");
 140                 goto err_mv_buf;
 141         }
 142
 143         return 0;
 144
 145 err_mv_buf:
 146         rk3288_vpu_aux_buf_free(vpu, &ctx->hw.vp8e.mv_buf);
 147 err_ctrl_buf:
 148         rk3288_vpu_aux_buf_free(vpu, &ctx->hw.vp8e.ctrl_buf);
 149
 150         return ret;
 151 }
 152
 153 void rk3288_vpu_vp8e_exit(struct rk3288_vpu_ctx *ctx)
 154 {
 155         struct rk3288_vpu_dev *vpu = ctx->dev;
 156
 157         rk3288_vpu_aux_buf_free(vpu, &ctx->hw.vp8e.ext_buf);
 158         rk3288_vpu_aux_buf_free(vpu, &ctx->hw.vp8e.mv_buf);
 159         rk3288_vpu_aux_buf_free(vpu, &ctx->hw.vp8e.ctrl_buf);
 160 }
 161
 162 static inline u32 enc_in_img_ctrl(struct rk3288_vpu_ctx *ctx)
 163 {
 164         struct v4l2_pix_format_mplane *pix_fmt = &ctx->src_fmt;
 165         struct v4l2_rect *crop = &ctx->src_crop;
 166         unsigned bytes_per_line, overfill_r, overfill_b;
 167
 168         /*
 169          * The hardware needs only the value for luma plane, because
 170          * values of other planes are calculated internally based on
 171          * format setting.
 172          */
 173         bytes_per_line = pix_fmt->plane_fmt[0].bytesperline;
 174         overfill_r = (pix_fmt->width - crop->width) / 4;
 175         overfill_b = pix_fmt->height - crop->height;
 176
 177         return VEPU_REG_IN_IMG_CTRL_ROW_LEN(bytes_per_line)
 178                         | VEPU_REG_IN_IMG_CTRL_OVRFLR_D4(overfill_r)
 179                         | VEPU_REG_IN_IMG_CTRL_OVRFLB_D4(overfill_b)
 180                         | VEPU_REG_IN_IMG_CTRL_FMT(ctx->vpu_src_fmt->enc_fmt);
 181 }
 182
 183 static void rk3288_vpu_vp8e_set_buffers(struct rk3288_vpu_dev *vpu,
 184                                         struct rk3288_vpu_ctx *ctx)
 185 {
 186         const struct rk3288_vp8e_reg_params *params = ctx->run.vp8e.reg_params;
 187         dma_addr_t ref_buf_dma, rec_buf_dma;
 188         dma_addr_t stream_dma;
 189         size_t rounded_size;
 190         dma_addr_t dst_dma;
 191         u32 start_offset;
 192         size_t dst_size;
 193
 194         rounded_size = ref_luma_size(ctx->src_fmt.width,
 195                                                 ctx->src_fmt.height);
 196
 197         ref_buf_dma = rec_buf_dma = ctx->hw.vp8e.ext_buf.dma;
 198         if (ctx->hw.vp8e.ref_rec_ptr)
 199                 ref_buf_dma += rounded_size * 3 / 2;
 200         else
 201                 rec_buf_dma += rounded_size * 3 / 2;
 202         ctx->hw.vp8e.ref_rec_ptr ^= 1;
 203
 204         if (rk3288_vpu_ctx_is_dummy_encode(ctx)) {
 205                 dst_dma = vpu->dummy_encode_dst.dma;
 206                 dst_size = vpu->dummy_encode_dst.size;
 207         } else {
 208                 dst_dma = vb2_dma_contig_plane_dma_addr(&ctx->run.dst->b, 0);
 209                 dst_size = vb2_plane_size(&ctx->run.dst->b, 0);
 210         }
 211
 212         /*
 213          * stream addr-->|
 214          * align 64bits->|<-start offset->|
 215          * |<---------header size-------->|<---dst buf---
 216          */
 217         start_offset = (params->rlc_ctrl & VEPU_REG_RLC_CTRL_STR_OFFS_MASK)
 218                                         >> VEPU_REG_RLC_CTRL_STR_OFFS_SHIFT;
 219         stream_dma = dst_dma + params->hdr_len;
 220
 221         /**
 222          * Userspace will pass 8 bytes aligned size(round_down) to us,
 223          * so we need to plus start offset to get real header size.
 224          *
 225          * |<-aligned size->|<-start offset->|
 226          * |<----------header size---------->|
 227          */
 228         ctx->run.dst->vp8e.hdr_size = params->hdr_len + (start_offset >> 3);
 229
 230         if (params->enc_ctrl & VEPU_REG_ENC_CTRL_KEYFRAME_BIT)
 231                 ctx->run.dst->b.v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
 232         else
 233                 ctx->run.dst->b.v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
 234
 235         /*
 236          * We assume here that 1/10 of the buffer is enough for headers.
 237          * DCT partition will be placed in remaining 9/10 of the buffer.
 238          */
 239         ctx->run.dst->vp8e.dct_offset = round_up(dst_size / 10, 8);
 240
 241         /* Destination buffer. */
 242         vepu_write_relaxed(vpu, stream_dma, VEPU_REG_ADDR_OUTPUT_STREAM);
 243         vepu_write_relaxed(vpu, dst_dma + ctx->run.dst->vp8e.dct_offset,
 244                                 VEPU_REG_ADDR_VP8_DCT_PART(0));
 245         vepu_write_relaxed(vpu, dst_size - ctx->run.dst->vp8e.dct_offset,
 246                                 VEPU_REG_STR_BUF_LIMIT);
 247
 248         /* Auxilliary buffers. */
 249         vepu_write_relaxed(vpu, ctx->hw.vp8e.ctrl_buf.dma,
 250                                 VEPU_REG_ADDR_OUTPUT_CTRL);
 251         vepu_write_relaxed(vpu, ctx->hw.vp8e.mv_buf.dma,
 252                                 VEPU_REG_ADDR_MV_OUT);
 253         vepu_write_relaxed(vpu, ctx->run.priv_dst.dma,
 254                                 VEPU_REG_ADDR_VP8_PROB_CNT);
 255         vepu_write_relaxed(vpu, ctx->run.priv_src.dma + VP8_CABAC_CTX_OFFSET,
 256                                 VEPU_REG_ADDR_CABAC_TBL);
 257         vepu_write_relaxed(vpu, ctx->run.priv_src.dma
 258                                 + VP8_CABAC_CTX_OFFSET + VP8_CABAC_CTX_SIZE,
 259                                 VEPU_REG_ADDR_VP8_SEG_MAP);
 260
 261         /* Reference buffers. */
 262         vepu_write_relaxed(vpu, ref_buf_dma,
 263                                 VEPU_REG_ADDR_REF_LUMA);
 264         vepu_write_relaxed(vpu, ref_buf_dma + rounded_size,
 265                                 VEPU_REG_ADDR_REF_CHROMA);
 266
 267         /* Reconstruction buffers. */
 268         vepu_write_relaxed(vpu, rec_buf_dma,
 269                                 VEPU_REG_ADDR_REC_LUMA);
 270         vepu_write_relaxed(vpu, rec_buf_dma + rounded_size,
 271                                 VEPU_REG_ADDR_REC_CHROMA);
 272
 273         /* Source buffer. */
 274         if (rk3288_vpu_ctx_is_dummy_encode(ctx)) {
 275                 vepu_write_relaxed(vpu, vpu->dummy_encode_src[PLANE_Y].dma,
 276                                         VEPU_REG_ADDR_IN_LUMA);
 277                 vepu_write_relaxed(vpu, vpu->dummy_encode_src[PLANE_CB].dma,
 278                                         VEPU_REG_ADDR_IN_CB);
 279                 vepu_write_relaxed(vpu, vpu->dummy_encode_src[PLANE_CR].dma,
 280                                         VEPU_REG_ADDR_IN_CR);
 281         } else {
 282                 vepu_write_relaxed(vpu, vb2_dma_contig_plane_dma_addr(
 283                                         &ctx->run.src->b, PLANE_Y),
 284                                         VEPU_REG_ADDR_IN_LUMA);
 285                 vepu_write_relaxed(vpu, vb2_dma_contig_plane_dma_addr(
 286                                         &ctx->run.src->b, PLANE_CB),
 287                                         VEPU_REG_ADDR_IN_CB);
 288                 vepu_write_relaxed(vpu, vb2_dma_contig_plane_dma_addr(
 289                                         &ctx->run.src->b, PLANE_CR),
 290                                         VEPU_REG_ADDR_IN_CR);
 291         }
 292
 293         /* Source parameters. */
 294         vepu_write_relaxed(vpu, enc_in_img_ctrl(ctx), VEPU_REG_IN_IMG_CTRL);
 295 }
 296
 297 static void rk3288_vpu_vp8e_set_params(struct rk3288_vpu_dev *vpu,
 298                                        struct rk3288_vpu_ctx *ctx)
 299 {
 300         const struct rk3288_vp8e_reg_params *params = ctx->run.vp8e.reg_params;
 301         int i;
 302
 303         vepu_write_relaxed(vpu, params->enc_ctrl0, VEPU_REG_ENC_CTRL0);
 304         vepu_write_relaxed(vpu, params->enc_ctrl1, VEPU_REG_ENC_CTRL1);
 305         vepu_write_relaxed(vpu, params->enc_ctrl2, VEPU_REG_ENC_CTRL2);
 306         vepu_write_relaxed(vpu, params->enc_ctrl3, VEPU_REG_ENC_CTRL3);
 307         vepu_write_relaxed(vpu, params->enc_ctrl5, VEPU_REG_ENC_CTRL5);
 308         vepu_write_relaxed(vpu, params->enc_ctrl4, VEPU_REG_ENC_CTRL4);
 309         vepu_write_relaxed(vpu, params->str_hdr_rem_msb,
 310                                 VEPU_REG_STR_HDR_REM_MSB);
 311         vepu_write_relaxed(vpu, params->str_hdr_rem_lsb,
 312                                 VEPU_REG_STR_HDR_REM_LSB);
 313         vepu_write_relaxed(vpu, params->mad_ctrl, VEPU_REG_MAD_CTRL);
 314
 315         for (i = 0; i < ARRAY_SIZE(params->qp_val); ++i)
 316                 vepu_write_relaxed(vpu, params->qp_val[i],
 317                                         VEPU_REG_VP8_QP_VAL(i));
 318
 319         vepu_write_relaxed(vpu, params->bool_enc, VEPU_REG_VP8_BOOL_ENC);
 320         vepu_write_relaxed(vpu, params->vp8_ctrl0, VEPU_REG_VP8_CTRL0);
 321         vepu_write_relaxed(vpu, params->rlc_ctrl, VEPU_REG_RLC_CTRL);
 322         vepu_write_relaxed(vpu, params->mb_ctrl, VEPU_REG_MB_CTRL);
 323
 324         for (i = 0; i < ARRAY_SIZE(params->rgb_yuv_coeff); ++i)
 325                 vepu_write_relaxed(vpu, params->rgb_yuv_coeff[i],
 326                                         VEPU_REG_RGB_YUV_COEFF(i));
 327
 328         vepu_write_relaxed(vpu, params->rgb_mask_msb,
 329                                 VEPU_REG_RGB_MASK_MSB);
 330         vepu_write_relaxed(vpu, params->intra_area_ctrl,
 331                                 VEPU_REG_INTRA_AREA_CTRL);
 332         vepu_write_relaxed(vpu, params->cir_intra_ctrl,
 333                                 VEPU_REG_CIR_INTRA_CTRL);
 334         vepu_write_relaxed(vpu, params->first_roi_area,
 335                                 VEPU_REG_FIRST_ROI_AREA);
 336         vepu_write_relaxed(vpu, params->second_roi_area,
 337                                 VEPU_REG_SECOND_ROI_AREA);
 338         vepu_write_relaxed(vpu, params->mvc_ctrl,
 339                                 VEPU_REG_MVC_CTRL);
 340
 341         for (i = 0; i < ARRAY_SIZE(params->intra_penalty); ++i)
 342                 vepu_write_relaxed(vpu, params->intra_penalty[i],
 343                                         VEPU_REG_VP8_INTRA_PENALTY(i));
 344
 345         for (i = 0; i < ARRAY_SIZE(params->seg_qp); ++i)
 346                 vepu_write_relaxed(vpu, params->seg_qp[i],
 347                                         VEPU_REG_VP8_SEG_QP(i));
 348
 349         for (i = 0; i < ARRAY_SIZE(params->dmv_4p_1p_penalty); ++i)
 350                 vepu_write_relaxed(vpu, params->dmv_4p_1p_penalty[i],
 351                                         VEPU_REG_DMV_4P_1P_PENALTY(i));
 352
 353         for (i = 0; i < ARRAY_SIZE(params->dmv_qpel_penalty); ++i)
 354                 vepu_write_relaxed(vpu, params->dmv_qpel_penalty[i],
 355                                         VEPU_REG_DMV_QPEL_PENALTY(i));
 356
 357         vepu_write_relaxed(vpu, params->vp8_ctrl1, VEPU_REG_VP8_CTRL1);
 358         vepu_write_relaxed(vpu, params->bit_cost_golden,
 359                                 VEPU_REG_VP8_BIT_COST_GOLDEN);
 360
 361         for (i = 0; i < ARRAY_SIZE(params->loop_flt_delta); ++i)
 362                 vepu_write_relaxed(vpu, params->loop_flt_delta[i],
 363                                         VEPU_REG_VP8_LOOP_FLT_DELTA(i));
 364 }
 365
 366 void rk3288_vpu_vp8e_run(struct rk3288_vpu_ctx *ctx)
 367 {
 368         struct rk3288_vpu_dev *vpu = ctx->dev;
 369         u32 reg;
 370
 371         /* The hardware expects the control buffer to be zeroed. */
 372         memset(ctx->hw.vp8e.ctrl_buf.cpu, 0,
 373                 sizeof(struct rk3288_vpu_vp8e_ctrl_buf));
 374
 375         /*
 376          * Program the hardware.
 377          */
 378         rk3288_vpu_power_on(vpu);
 379
 380         vepu_write_relaxed(vpu, VEPU_REG_ENC_CTRL_ENC_MODE_VP8,
 381                                 VEPU_REG_ENC_CTRL);
 382
 383         rk3288_vpu_vp8e_set_params(vpu, ctx);
 384         rk3288_vpu_vp8e_set_buffers(vpu, ctx);
 385
 386         /* Make sure that all registers are written at this point. */
 387         wmb();
 388
 389         /* Set the watchdog. */
 390         schedule_delayed_work(&vpu->watchdog_work, msecs_to_jiffies(2000));
 391
 392         /* Start the hardware. */
 393         reg = VEPU_REG_AXI_CTRL_OUTPUT_SWAP16
 394                 | VEPU_REG_AXI_CTRL_INPUT_SWAP16
 395                 | VEPU_REG_AXI_CTRL_BURST_LEN(16)
 396                 | VEPU_REG_AXI_CTRL_GATE_BIT
 397                 | VEPU_REG_AXI_CTRL_OUTPUT_SWAP32
 398                 | VEPU_REG_AXI_CTRL_INPUT_SWAP32
 399                 | VEPU_REG_AXI_CTRL_OUTPUT_SWAP8
 400                 | VEPU_REG_AXI_CTRL_INPUT_SWAP8;
 401         vepu_write(vpu, reg, VEPU_REG_AXI_CTRL);
 402
 403         vepu_write(vpu, 0, VEPU_REG_INTERRUPT);
 404
 405         reg = VEPU_REG_ENC_CTRL_NAL_MODE_BIT
 406                 | VEPU_REG_ENC_CTRL_WIDTH(MB_WIDTH(ctx->src_fmt.width))
 407                 | VEPU_REG_ENC_CTRL_HEIGHT(MB_HEIGHT(ctx->src_fmt.height))
 408                 | VEPU_REG_ENC_CTRL_ENC_MODE_VP8
 409                 | VEPU_REG_ENC_CTRL_EN_BIT;
 410
 411         if (ctx->run.dst->b.v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME)
 412                 reg |= VEPU_REG_ENC_CTRL_KEYFRAME_BIT;
 413
 414         vepu_write(vpu, reg, VEPU_REG_ENC_CTRL);
 415 }
 416
 417 void rk3288_vpu_vp8e_done(struct rk3288_vpu_ctx *ctx,
 418                           enum vb2_buffer_state result)
 419 {
 420         struct rk3288_vpu_vp8e_ctrl_buf *ctrl_buf = ctx->hw.vp8e.ctrl_buf.cpu;
 421
 422         /* Read length information of this run from utility buffer. */
 423         ctx->run.dst->vp8e.ext_hdr_size = ctrl_buf->ext_hdr_size;
 424         ctx->run.dst->vp8e.dct_size = ctrl_buf->dct_size;
 425
 426         rk3288_vpu_run_done(ctx, result);
 427 }
 428
 429 /*
 430  * WAR for encoder state corruption after decoding
 431  */
 432
 433 static const struct rk3288_vp8e_reg_params dummy_encode_reg_params = {
 434         /* 00000014 */ .hdr_len = 0x00000000,
 435         /* 00000038 */ .enc_ctrl = VEPU_REG_ENC_CTRL_KEYFRAME_BIT,
 436         /* 00000040 */ .enc_ctrl0 = 0x00000000,
 437         /* 00000044 */ .enc_ctrl1 = 0x00000000,
 438         /* 00000048 */ .enc_ctrl2 = 0x00040014,
 439         /* 0000004c */ .enc_ctrl3 = 0x404083c0,
 440         /* 00000050 */ .enc_ctrl5 = 0x01006bff,
 441         /* 00000054 */ .enc_ctrl4 = 0x00000039,
 442         /* 00000058 */ .str_hdr_rem_msb = 0x85848805,
 443         /* 0000005c */ .str_hdr_rem_lsb = 0x02000000,
 444         /* 00000064 */ .mad_ctrl = 0x00000000,
 445         /* 0000006c */ .qp_val = {
 446                 /* 0000006c */ 0x020213b1,
 447                 /* 00000070 */ 0x02825249,
 448                 /* 00000074 */ 0x048409d8,
 449                 /* 00000078 */ 0x03834c30,
 450                 /* 0000007c */ 0x020213b1,
 451                 /* 00000080 */ 0x02825249,
 452                 /* 00000084 */ 0x00340e0d,
 453                 /* 00000088 */ 0x401c1a15,
 454         },
 455         /* 0000008c */ .bool_enc = 0x00018140,
 456         /* 00000090 */ .vp8_ctrl0 = 0x000695c0,
 457         /* 00000094 */ .rlc_ctrl = 0x14000000,
 458         /* 00000098 */ .mb_ctrl = 0x00000000,
 459         /* 000000d4 */ .rgb_yuv_coeff = {
 460                 /* 000000d4 */ 0x962b4c85,
 461                 /* 000000d8 */ 0x90901d50,
 462         },
 463         /* 000000dc */ .rgb_mask_msb = 0x0000b694,
 464         /* 000000e0 */ .intra_area_ctrl = 0xffffffff,
 465         /* 000000e4 */ .cir_intra_ctrl = 0x00000000,
 466         /* 000000f0 */ .first_roi_area = 0xffffffff,
 467         /* 000000f4 */ .second_roi_area = 0xffffffff,
 468         /* 000000f8 */ .mvc_ctrl = 0x01780000,
 469         /* 00000100 */ .intra_penalty = {
 470                 /* 00000100 */ 0x00010005,
 471                 /* 00000104 */ 0x00015011,
 472                 /* 00000108 */ 0x0000c005,
 473                 /* 0000010c */ 0x00016010,
 474                 /* 00000110 */ 0x0001a018,
 475                 /* 00000114 */ 0x00018015,
 476                 /* 00000118 */ 0x0001d01a,
 477         },
 478         /* 00000120 */ .seg_qp = {
 479                 /* 00000120 */ 0x020213b1,
 480                 /* 00000124 */ 0x02825249,
 481                 /* 00000128 */ 0x048409d8,
 482                 /* 0000012c */ 0x03834c30,
 483                 /* 00000130 */ 0x020213b1,
 484                 /* 00000134 */ 0x02825249,
 485                 /* 00000138 */ 0x00340e0d,
 486                 /* 0000013c */ 0x341c1a15,
 487                 /* 00000140 */ 0x020213b1,
 488                 /* 00000144 */ 0x02825249,
 489                 /* 00000148 */ 0x048409d8,
 490                 /* 0000014c */ 0x03834c30,
 491                 /* 00000150 */ 0x020213b1,
 492                 /* 00000154 */ 0x02825249,
 493                 /* 00000158 */ 0x00340e0d,
 494                 /* 0000015c */ 0x341c1a15,
 495                 /* 00000160 */ 0x020213b1,
 496                 /* 00000164 */ 0x02825249,
 497                 /* 00000168 */ 0x048409d8,
 498                 /* 0000016c */ 0x03834c30,
 499                 /* 00000170 */ 0x020213b1,
 500                 /* 00000174 */ 0x02825249,
 501                 /* 00000178 */ 0x00340e0d,
 502                 /* 0000017c */ 0x341c1a15,
 503         },
 504         /* 00000180 */ .dmv_4p_1p_penalty = {
 505                 /* 00000180 */ 0x00020406,
 506                 /* 00000184 */ 0x080a0c0e,
 507                 /* 00000188 */ 0x10121416,
 508                 /* 0000018c */ 0x181a1c1e,
 509                 /* 00000190 */ 0x20222426,
 510                 /* 00000194 */ 0x282a2c2e,
 511                 /* 00000198 */ 0x30323436,
 512                 /* 0000019c */ 0x383a3c3e,
 513                 /* 000001a0 */ 0x40424446,
 514                 /* 000001a4 */ 0x484a4c4e,
 515                 /* 000001a8 */ 0x50525456,
 516                 /* 000001ac */ 0x585a5c5e,
 517                 /* 000001b0 */ 0x60626466,
 518                 /* 000001b4 */ 0x686a6c6e,
 519                 /* 000001b8 */ 0x70727476,
 520                 /* NOTE: Further 17 registers set to 0. */
 521         },
 522         /*
 523          * NOTE: Following registers all set to 0:
 524          * - dmv_qpel_penalty,
 525          * - vp8_ctrl1,
 526          * - bit_cost_golden,
 527          * - loop_flt_delta.
 528          */
 529 };
 530
 531 const struct rk3288_vp8e_reg_params *rk3288_vpu_vp8e_get_dummy_params(void)
 532 {
 533         return &dummy_encode_reg_params;
 534 }