2 * Rockchip RK3288 VPU codec vp8 decode driver
4 * Copyright (C) 2014 Rockchip Electronics Co., Ltd.
5 * ZhiChao Yu <zhichao.yu@rock-chips.com>
7 * Copyright (C) 2014 Google, Inc.
8 * Tomasz Figa <tfiga@chromium.org>
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #include "rk3288_vpu_hw.h"
21 #include "rk3288_vpu_regs.h"
22 #include "rk3288_vpu_common.h"
24 #define DEC_8190_ALIGN_MASK 0x07U
27 * probs table with packed
29 struct vp8_prob_tbl_packed {
30 u8 prob_mb_skip_false;
37 u8 prob_luma_16x16_pred_mode[4];
38 u8 prob_chroma_pred_mode[3];
42 u8 prob_mv_context[2][19];
46 u8 prob_coeffs[4][8][3][11];
56 /* dct partiton base address regs */
57 static const struct vp8d_reg vp8d_dct_base[8] = {
58 { VDPU_REG_ADDR_STR, 0, 0xffffffff },
59 { VDPU_REG_ADDR_REF(8), 0, 0xffffffff },
60 { VDPU_REG_ADDR_REF(9), 0, 0xffffffff },
61 { VDPU_REG_ADDR_REF(10), 0, 0xffffffff },
62 { VDPU_REG_ADDR_REF(11), 0, 0xffffffff },
63 { VDPU_REG_ADDR_REF(12), 0, 0xffffffff },
64 { VDPU_REG_ADDR_REF(14), 0, 0xffffffff },
65 { VDPU_REG_ADDR_REF(15), 0, 0xffffffff },
68 /* loop filter level regs */
69 static const struct vp8d_reg vp8d_lf_level[4] = {
70 { VDPU_REG_REF_PIC(2), 18, 0x3f },
71 { VDPU_REG_REF_PIC(2), 12, 0x3f },
72 { VDPU_REG_REF_PIC(2), 6, 0x3f },
73 { VDPU_REG_REF_PIC(2), 0, 0x3f },
76 /* macroblock loop filter level adjustment regs */
77 static const struct vp8d_reg vp8d_mb_adj[4] = {
78 { VDPU_REG_REF_PIC(0), 21, 0x7f },
79 { VDPU_REG_REF_PIC(0), 14, 0x7f },
80 { VDPU_REG_REF_PIC(0), 7, 0x7f },
81 { VDPU_REG_REF_PIC(0), 0, 0x7f },
84 /* reference frame adjustment regs */
85 static const struct vp8d_reg vp8d_ref_adj[4] = {
86 { VDPU_REG_REF_PIC(1), 21, 0x7f },
87 { VDPU_REG_REF_PIC(1), 14, 0x7f },
88 { VDPU_REG_REF_PIC(1), 7, 0x7f },
89 { VDPU_REG_REF_PIC(1), 0, 0x7f },
93 static const struct vp8d_reg vp8d_quant[4] = {
94 { VDPU_REG_REF_PIC(3), 11, 0x7ff },
95 { VDPU_REG_REF_PIC(3), 0, 0x7ff },
96 { VDPU_REG_BD_REF_PIC(4), 11, 0x7ff },
97 { VDPU_REG_BD_REF_PIC(4), 0, 0x7ff },
100 /* quantizer delta regs */
101 static const struct vp8d_reg vp8d_quant_delta[5] = {
102 { VDPU_REG_REF_PIC(3), 27, 0x1f },
103 { VDPU_REG_REF_PIC(3), 22, 0x1f },
104 { VDPU_REG_BD_REF_PIC(4), 27, 0x1f },
105 { VDPU_REG_BD_REF_PIC(4), 22, 0x1f },
106 { VDPU_REG_BD_P_REF_PIC, 27, 0x1f },
109 /* dct partition start bits regs */
110 static const struct vp8d_reg vp8d_dct_start_bits[8] = {
111 { VDPU_REG_DEC_CTRL2, 26, 0x3f }, { VDPU_REG_DEC_CTRL4, 26, 0x3f },
112 { VDPU_REG_DEC_CTRL4, 20, 0x3f }, { VDPU_REG_DEC_CTRL7, 24, 0x3f },
113 { VDPU_REG_DEC_CTRL7, 18, 0x3f }, { VDPU_REG_DEC_CTRL7, 12, 0x3f },
114 { VDPU_REG_DEC_CTRL7, 6, 0x3f }, { VDPU_REG_DEC_CTRL7, 0, 0x3f },
117 /* precision filter tap regs */
118 static const struct vp8d_reg vp8d_pred_bc_tap[8][4] = {
120 { VDPU_REG_PRED_FLT, 22, 0x3ff },
121 { VDPU_REG_PRED_FLT, 12, 0x3ff },
122 { VDPU_REG_PRED_FLT, 2, 0x3ff },
123 { VDPU_REG_REF_PIC(4), 22, 0x3ff },
126 { VDPU_REG_REF_PIC(4), 12, 0x3ff },
127 { VDPU_REG_REF_PIC(4), 2, 0x3ff },
128 { VDPU_REG_REF_PIC(5), 22, 0x3ff },
129 { VDPU_REG_REF_PIC(5), 12, 0x3ff },
132 { VDPU_REG_REF_PIC(5), 2, 0x3ff },
133 { VDPU_REG_REF_PIC(6), 22, 0x3ff },
134 { VDPU_REG_REF_PIC(6), 12, 0x3ff },
135 { VDPU_REG_REF_PIC(6), 2, 0x3ff },
138 { VDPU_REG_REF_PIC(7), 22, 0x3ff },
139 { VDPU_REG_REF_PIC(7), 12, 0x3ff },
140 { VDPU_REG_REF_PIC(7), 2, 0x3ff },
141 { VDPU_REG_LT_REF, 22, 0x3ff },
144 { VDPU_REG_LT_REF, 12, 0x3ff },
145 { VDPU_REG_LT_REF, 2, 0x3ff },
146 { VDPU_REG_VALID_REF, 22, 0x3ff },
147 { VDPU_REG_VALID_REF, 12, 0x3ff },
150 { VDPU_REG_VALID_REF, 2, 0x3ff },
151 { VDPU_REG_BD_REF_PIC(0), 22, 0x3ff },
152 { VDPU_REG_BD_REF_PIC(0), 12, 0x3ff },
153 { VDPU_REG_BD_REF_PIC(0), 2, 0x3ff },
156 { VDPU_REG_BD_REF_PIC(1), 22, 0x3ff },
157 { VDPU_REG_BD_REF_PIC(1), 12, 0x3ff },
158 { VDPU_REG_BD_REF_PIC(1), 2, 0x3ff },
159 { VDPU_REG_BD_REF_PIC(2), 22, 0x3ff },
162 { VDPU_REG_BD_REF_PIC(2), 12, 0x3ff },
163 { VDPU_REG_BD_REF_PIC(2), 2, 0x3ff },
164 { VDPU_REG_BD_REF_PIC(3), 22, 0x3ff },
165 { VDPU_REG_BD_REF_PIC(3), 12, 0x3ff },
170 * filter taps taken to 7-bit precision,
171 * reference RFC6386#Page-16, filters[8][6]
173 static const u32 vp8d_mc_filter[8][6] = {
174 { 0, 0, 128, 0, 0, 0 },
175 { 0, -6, 123, 12, -1, 0 },
176 { 2, -11, 108, 36, -8, 1 },
177 { 0, -9, 93, 50, -6, 0 },
178 { 3, -16, 77, 77, -16, 3 },
179 { 0, -6, 50, 93, -9, 0 },
180 { 1, -8, 36, 108, -11, 2 },
181 { 0, -1, 12, 123, -6, 0 }
184 static inline void vp8d_reg_write(struct rk3288_vpu_dev *vpu,
185 const struct vp8d_reg *reg, u32 val)
189 v = vdpu_read(vpu, reg->base);
190 v &= ~(reg->mask << reg->shift);
191 v |= ((val & reg->mask) << reg->shift);
192 vdpu_write_relaxed(vpu, v, reg->base);
195 /* dump hw params for debug */
197 static void rk3288_vp8d_dump_hdr(struct rk3288_vpu_ctx *ctx)
199 const struct v4l2_ctrl_vp8_frame_hdr *hdr = ctx->run.vp8d.frame_hdr;
200 int dct_total_len = 0;
203 vpu_debug(4, "Frame tag: key_frame=0x%02x, version=0x%02x\n",
204 !hdr->key_frame, hdr->version);
206 vpu_debug(4, "Picture size: w=%d, h=%d\n", hdr->width, hdr->height);
208 /* stream addresses */
209 vpu_debug(4, "Addresses: segmap=0x%x, probs=0x%x\n",
210 ctx->hw.vp8d.segment_map.dma,
211 ctx->hw.vp8d.prob_tbl.dma);
213 /* reference frame info */
214 vpu_debug(4, "Ref frame: last=%d, golden=%d, alt=%d\n",
215 hdr->last_frame, hdr->golden_frame, hdr->alt_frame);
217 /* bool decoder info */
218 vpu_debug(4, "Bool decoder: range=0x%x, value=0x%x, count=0x%x\n",
219 hdr->bool_dec_range, hdr->bool_dec_value,
220 hdr->bool_dec_count);
222 /* control partition info */
223 vpu_debug(4, "Control Part: offset=0x%x, size=0x%x\n",
224 hdr->first_part_offset, hdr->first_part_size);
225 vpu_debug(2, "Macroblock Data: bits_offset=0x%x\n",
226 hdr->macroblock_bit_offset);
228 /* dct partition info */
229 for (i = 0; i < hdr->num_dct_parts; i++) {
230 dct_total_len += hdr->dct_part_sizes[i];
231 vpu_debug(4, "Dct Part%d Size: 0x%x\n",
232 i, hdr->dct_part_sizes[i]);
235 dct_total_len += (hdr->num_dct_parts - 1) * 3;
236 vpu_debug(4, "Dct Part Total Length: 0x%x\n", dct_total_len);
239 static inline void rk3288_vp8d_dump_hdr(struct rk3288_vpu_ctx *ctx) {}
242 static void rk3288_vp8d_prob_update(struct rk3288_vpu_ctx *ctx)
244 const struct v4l2_ctrl_vp8_frame_hdr *hdr = ctx->run.vp8d.frame_hdr;
245 const struct v4l2_vp8_entropy_hdr *entropy_hdr = &hdr->entropy_hdr;
250 dst = ctx->hw.vp8d.prob_tbl.cpu;
252 dst[0] = hdr->prob_skip_false;
253 dst[1] = hdr->prob_intra;
254 dst[2] = hdr->prob_last;
255 dst[3] = hdr->prob_gf;
256 dst[4] = hdr->sgmnt_hdr.segment_probs[0];
257 dst[5] = hdr->sgmnt_hdr.segment_probs[1];
258 dst[6] = hdr->sgmnt_hdr.segment_probs[2];
262 dst[0] = entropy_hdr->y_mode_probs[0];
263 dst[1] = entropy_hdr->y_mode_probs[1];
264 dst[2] = entropy_hdr->y_mode_probs[2];
265 dst[3] = entropy_hdr->y_mode_probs[3];
266 dst[4] = entropy_hdr->uv_mode_probs[0];
267 dst[5] = entropy_hdr->uv_mode_probs[1];
268 dst[6] = entropy_hdr->uv_mode_probs[2];
269 dst[7] = 0; /*unused */
273 dst[0] = entropy_hdr->mv_probs[0][0]; /* is short */
274 dst[1] = entropy_hdr->mv_probs[1][0];
275 dst[2] = entropy_hdr->mv_probs[0][1]; /* sign */
276 dst[3] = entropy_hdr->mv_probs[1][1];
277 dst[4] = entropy_hdr->mv_probs[0][8 + 9];
278 dst[5] = entropy_hdr->mv_probs[0][9 + 9];
279 dst[6] = entropy_hdr->mv_probs[1][8 + 9];
280 dst[7] = entropy_hdr->mv_probs[1][9 + 9];
282 for (i = 0; i < 2; ++i) {
283 for (j = 0; j < 8; j += 4) {
284 dst[0] = entropy_hdr->mv_probs[i][j + 9 + 0];
285 dst[1] = entropy_hdr->mv_probs[i][j + 9 + 1];
286 dst[2] = entropy_hdr->mv_probs[i][j + 9 + 2];
287 dst[3] = entropy_hdr->mv_probs[i][j + 9 + 3];
291 for (i = 0; i < 2; ++i) {
292 dst[0] = entropy_hdr->mv_probs[i][0 + 2];
293 dst[1] = entropy_hdr->mv_probs[i][1 + 2];
294 dst[2] = entropy_hdr->mv_probs[i][2 + 2];
295 dst[3] = entropy_hdr->mv_probs[i][3 + 2];
296 dst[4] = entropy_hdr->mv_probs[i][4 + 2];
297 dst[5] = entropy_hdr->mv_probs[i][5 + 2];
298 dst[6] = entropy_hdr->mv_probs[i][6 + 2];
299 dst[7] = 0; /*unused */
303 /* coeff probs (header part) */
304 dst = ctx->hw.vp8d.prob_tbl.cpu;
306 for (i = 0; i < 4; ++i) {
307 for (j = 0; j < 8; ++j) {
308 for (k = 0; k < 3; ++k) {
309 dst[0] = entropy_hdr->coeff_probs[i][j][k][0];
310 dst[1] = entropy_hdr->coeff_probs[i][j][k][1];
311 dst[2] = entropy_hdr->coeff_probs[i][j][k][2];
312 dst[3] = entropy_hdr->coeff_probs[i][j][k][3];
318 /* coeff probs (footer part) */
319 dst = ctx->hw.vp8d.prob_tbl.cpu;
321 for (i = 0; i < 4; ++i) {
322 for (j = 0; j < 8; ++j) {
323 for (k = 0; k < 3; ++k) {
324 dst[0] = entropy_hdr->coeff_probs[i][j][k][4];
325 dst[1] = entropy_hdr->coeff_probs[i][j][k][5];
326 dst[2] = entropy_hdr->coeff_probs[i][j][k][6];
327 dst[3] = entropy_hdr->coeff_probs[i][j][k][7];
328 dst[4] = entropy_hdr->coeff_probs[i][j][k][8];
329 dst[5] = entropy_hdr->coeff_probs[i][j][k][9];
330 dst[6] = entropy_hdr->coeff_probs[i][j][k][10];
331 dst[7] = 0; /*unused */
341 static void rk3288_vp8d_cfg_lf(struct rk3288_vpu_ctx *ctx)
343 const struct v4l2_ctrl_vp8_frame_hdr *hdr = ctx->run.vp8d.frame_hdr;
344 struct rk3288_vpu_dev *vpu = ctx->dev;
348 if (!(hdr->sgmnt_hdr.flags & V4L2_VP8_SEGMNT_HDR_FLAG_ENABLED)) {
349 vp8d_reg_write(vpu, &vp8d_lf_level[0], hdr->lf_hdr.level);
350 } else if (hdr->sgmnt_hdr.segment_feature_mode) {
352 for (i = 0; i < 4; i++)
353 vp8d_reg_write(vpu, &vp8d_lf_level[i],
354 hdr->sgmnt_hdr.lf_update[i]);
357 for (i = 0; i < 4; i++)
358 vp8d_reg_write(vpu, &vp8d_lf_level[i],
359 clamp(0, 63, hdr->lf_hdr.level
360 + hdr->sgmnt_hdr.lf_update[i]));
363 reg = VDPU_REG_REF_PIC_FILT_SHARPNESS(hdr->lf_hdr.sharpness_level);
364 if (hdr->lf_hdr.type)
365 reg |= VDPU_REG_REF_PIC_FILT_TYPE_E;
366 vdpu_write_relaxed(vpu, reg, VDPU_REG_REF_PIC(0));
368 if (hdr->lf_hdr.flags & V4L2_VP8_LF_HDR_ADJ_ENABLE) {
369 for (i = 0; i < 4; i++) {
370 vp8d_reg_write(vpu, &vp8d_mb_adj[i],
371 hdr->lf_hdr.mb_mode_delta_magnitude[i]);
372 vp8d_reg_write(vpu, &vp8d_ref_adj[i],
373 hdr->lf_hdr.ref_frm_delta_magnitude[i]);
379 * set quantization parameters
381 static void rk3288_vp8d_cfg_qp(struct rk3288_vpu_ctx *ctx)
383 const struct v4l2_ctrl_vp8_frame_hdr *hdr = ctx->run.vp8d.frame_hdr;
384 struct rk3288_vpu_dev *vpu = ctx->dev;
387 if (!(hdr->sgmnt_hdr.flags & V4L2_VP8_SEGMNT_HDR_FLAG_ENABLED)) {
388 vp8d_reg_write(vpu, &vp8d_quant[0], hdr->quant_hdr.y_ac_qi);
389 } else if (hdr->sgmnt_hdr.segment_feature_mode) {
391 for (i = 0; i < 4; i++)
392 vp8d_reg_write(vpu, &vp8d_quant[i],
393 hdr->sgmnt_hdr.quant_update[i]);
396 for (i = 0; i < 4; i++)
397 vp8d_reg_write(vpu, &vp8d_quant[i],
398 clamp(0, 127, hdr->quant_hdr.y_ac_qi
399 + hdr->sgmnt_hdr.quant_update[i]));
402 vp8d_reg_write(vpu, &vp8d_quant_delta[0], hdr->quant_hdr.y_dc_delta);
403 vp8d_reg_write(vpu, &vp8d_quant_delta[1], hdr->quant_hdr.y2_dc_delta);
404 vp8d_reg_write(vpu, &vp8d_quant_delta[2], hdr->quant_hdr.y2_ac_delta);
405 vp8d_reg_write(vpu, &vp8d_quant_delta[3], hdr->quant_hdr.uv_dc_delta);
406 vp8d_reg_write(vpu, &vp8d_quant_delta[4], hdr->quant_hdr.uv_ac_delta);
410 * set control partition and dct partition regs
412 * VP8 frame stream data layout:
414 * first_part_size parttion_sizes[0]
417 * ^ +--------+------+ +-----+-----+
418 * | | control part | | |
419 * +--------+----------------+------------------+-----------+-----+-----------+
420 * | tag 3B | extra 7B | hdr | mb_data | dct sz | dct part0 | ... | dct partn |
421 * +--------+-----------------------------------+-----------+-----+-----------+
424 * | mb_start | src_dma_end
426 * first_part_offset dct size part
429 * 1. only key frame has extra 7 bytes
430 * 2. all offsets are base on src_dma
431 * 3. number of dct parts is 1, 2, 4 or 8
432 * 4. the addresses set to vpu must be 64bits alignment
434 static void rk3288_vp8d_cfg_parts(struct rk3288_vpu_ctx *ctx)
436 const struct v4l2_ctrl_vp8_frame_hdr *hdr = ctx->run.vp8d.frame_hdr;
437 struct rk3288_vpu_dev *vpu = ctx->dev;
438 u32 dct_part_total_len = 0;
439 u32 dct_size_part_size = 0;
440 u32 dct_part_offset = 0;
441 u32 mb_offset_bytes = 0;
442 u32 mb_offset_bits = 0;
443 u32 mb_start_bits = 0;
450 src_dma = vb2_dma_contig_plane_dma_addr(&ctx->run.src->b, 0);
453 * Calculate control partition mb data info
454 * @macroblock_bit_offset: bits offset of mb data from first
456 * @mb_offset_bits: bits offset of mb data from src_dma
458 * @mb_offset_byte: bytes offset of mb data from src_dma
460 * @mb_start_bits: bits offset of mb data from mb data
461 * 64bits alignment addr
463 mb_offset_bits = hdr->first_part_offset * 8
464 + hdr->macroblock_bit_offset + 8;
465 mb_offset_bytes = mb_offset_bits / 8;
466 mb_start_bits = mb_offset_bits
467 - (mb_offset_bytes & (~DEC_8190_ALIGN_MASK)) * 8;
468 mb_size = hdr->first_part_size
469 - (mb_offset_bytes - hdr->first_part_offset)
470 + (mb_offset_bytes & DEC_8190_ALIGN_MASK);
472 /* mb data aligned base addr */
473 vdpu_write_relaxed(vpu, (mb_offset_bytes & (~DEC_8190_ALIGN_MASK))
474 + src_dma, VDPU_REG_ADDR_REF(13));
476 /* mb data start bits */
477 reg.base = VDPU_REG_DEC_CTRL2;
480 vp8d_reg_write(vpu, ®, mb_start_bits);
482 /* mb aligned data length */
483 reg.base = VDPU_REG_DEC_CTRL6;
486 vp8d_reg_write(vpu, ®, mb_size);
489 * Calculate dct partition info
490 * @dct_size_part_size: Containing sizes of dct part, every dct part
491 * has 3 bytes to store its size, except the last
493 * @dct_part_offset: bytes offset of dct parts from src_dma base addr
494 * @dct_part_total_len: total size of all dct parts
496 dct_size_part_size = (hdr->num_dct_parts - 1) * 3;
497 dct_part_offset = hdr->first_part_offset + hdr->first_part_size;
498 for (i = 0; i < hdr->num_dct_parts; i++)
499 dct_part_total_len += hdr->dct_part_sizes[i];
500 dct_part_total_len += dct_size_part_size;
501 dct_part_total_len += (dct_part_offset & DEC_8190_ALIGN_MASK);
503 /* number of dct partitions */
504 reg.base = VDPU_REG_DEC_CTRL6;
507 vp8d_reg_write(vpu, ®, hdr->num_dct_parts - 1);
509 /* dct partition length */
510 vdpu_write_relaxed(vpu,
511 VDPU_REG_DEC_CTRL3_STREAM_LEN(dct_part_total_len),
514 /* dct partitions base address */
515 for (i = 0; i < hdr->num_dct_parts; i++) {
516 u32 byte_offset = dct_part_offset + dct_size_part_size + count;
517 u32 base_addr = byte_offset + src_dma;
519 vp8d_reg_write(vpu, &vp8d_dct_base[i],
520 base_addr & (~DEC_8190_ALIGN_MASK));
522 vp8d_reg_write(vpu, &vp8d_dct_start_bits[i],
523 (byte_offset & DEC_8190_ALIGN_MASK) * 8);
525 count += hdr->dct_part_sizes[i];
530 * prediction filter taps
531 * normal 6-tap filters
533 static void rk3288_vp8d_cfg_tap(struct rk3288_vpu_ctx *ctx)
535 const struct v4l2_ctrl_vp8_frame_hdr *hdr = ctx->run.vp8d.frame_hdr;
536 struct rk3288_vpu_dev *vpu = ctx->dev;
541 reg.base = VDPU_REG_BD_REF_PIC(3);
544 if ((hdr->version & 0x03) != 0)
545 return; /* Tap filter not used. */
548 for (i = 0; i < 8; i++) {
549 val = (vp8d_mc_filter[i][0] << 2) | vp8d_mc_filter[i][5];
551 for (j = 0; j < 4; j++)
552 vp8d_reg_write(vpu, &vp8d_pred_bc_tap[i][j],
553 vp8d_mc_filter[i][j + 1]);
569 vp8d_reg_write(vpu, ®, val);
573 /* set reference frame */
574 static void rk3288_vp8d_cfg_ref(struct rk3288_vpu_ctx *ctx)
577 struct vb2_buffer *buf;
578 struct rk3288_vpu_dev *vpu = ctx->dev;
579 const struct v4l2_ctrl_vp8_frame_hdr *hdr = ctx->run.vp8d.frame_hdr;
581 /* set last frame address */
582 if (hdr->last_frame >= ctx->vq_dst.num_buffers)
583 buf = &ctx->run.dst->b;
585 buf = ctx->dst_bufs[hdr->last_frame];
588 vdpu_write_relaxed(vpu,
589 vb2_dma_contig_plane_dma_addr(&ctx->run.dst->b, 0),
590 VDPU_REG_ADDR_REF(0));
592 vdpu_write_relaxed(vpu, vb2_dma_contig_plane_dma_addr(buf, 0),
593 VDPU_REG_ADDR_REF(0));
595 /* set golden reference frame buffer address */
596 if (hdr->golden_frame >= ctx->vq_dst.num_buffers)
597 buf = &ctx->run.dst->b;
599 buf = ctx->dst_bufs[hdr->golden_frame];
601 reg = vb2_dma_contig_plane_dma_addr(buf, 0);
602 if (hdr->sign_bias_golden)
603 reg |= VDPU_REG_ADDR_REF_TOPC_E;
604 vdpu_write_relaxed(vpu, reg, VDPU_REG_ADDR_REF(4));
606 /* set alternate reference frame buffer address */
607 if (hdr->alt_frame >= ctx->vq_dst.num_buffers)
608 buf = &ctx->run.dst->b;
610 buf = ctx->dst_bufs[hdr->alt_frame];
612 reg = vb2_dma_contig_plane_dma_addr(buf, 0);
613 if (hdr->sign_bias_alternate)
614 reg |= VDPU_REG_ADDR_REF_TOPC_E;
615 vdpu_write_relaxed(vpu, reg, VDPU_REG_ADDR_REF(5));
618 static void rk3288_vp8d_cfg_buffers(struct rk3288_vpu_ctx *ctx)
620 const struct v4l2_ctrl_vp8_frame_hdr *hdr = ctx->run.vp8d.frame_hdr;
621 struct rk3288_vpu_dev *vpu = ctx->dev;
624 /* set probability table buffer address */
625 vdpu_write_relaxed(vpu, ctx->hw.vp8d.prob_tbl.dma,
626 VDPU_REG_ADDR_QTABLE);
628 /* set segment map address */
630 reg = VDPU_REG_FWD_PIC1_SEGMENT_BASE(ctx->hw.vp8d.segment_map.dma);
631 if (hdr->sgmnt_hdr.flags & V4L2_VP8_SEGMNT_HDR_FLAG_ENABLED)
632 reg |= VDPU_REG_FWD_PIC1_SEGMENT_E;
633 if (hdr->sgmnt_hdr.flags & V4L2_VP8_SEGMNT_HDR_FLAG_UPDATE_MAP)
634 reg |= VDPU_REG_FWD_PIC1_SEGMENT_UPD_E;
635 vdpu_write_relaxed(vpu, reg, VDPU_REG_FWD_PIC(0));
637 /* set output frame buffer address */
638 vdpu_write_relaxed(vpu,
639 vb2_dma_contig_plane_dma_addr(&ctx->run.dst->b, 0),
643 int rk3288_vpu_vp8d_init(struct rk3288_vpu_ctx *ctx)
645 struct rk3288_vpu_dev *vpu = ctx->dev;
646 unsigned int mb_width, mb_height;
647 size_t segment_map_size;
650 /* segment map table size calculation */
651 mb_width = MB_WIDTH(ctx->dst_fmt.width);
652 mb_height = MB_HEIGHT(ctx->dst_fmt.height);
653 segment_map_size = round_up(DIV_ROUND_UP(mb_width * mb_height, 4), 64);
656 * In context init the dma buffer for segment map must be allocated.
657 * And the data in segment map buffer must be set to all zero.
659 ret = rk3288_vpu_aux_buf_alloc(vpu, &ctx->hw.vp8d.segment_map,
662 vpu_err("allocate segment map mem failed\n");
665 memset(ctx->hw.vp8d.segment_map.cpu, 0, ctx->hw.vp8d.segment_map.size);
668 * Allocate probability table buffer,
669 * total 1208 bytes, 4K page is far enough.
671 ret = rk3288_vpu_aux_buf_alloc(vpu, &ctx->hw.vp8d.prob_tbl,
672 sizeof(struct vp8_prob_tbl_packed));
674 vpu_err("allocate prob table mem failed\n");
675 goto prob_table_failed;
681 rk3288_vpu_aux_buf_free(vpu, &ctx->hw.vp8d.segment_map);
686 void rk3288_vpu_vp8d_exit(struct rk3288_vpu_ctx *ctx)
688 struct rk3288_vpu_dev *vpu = ctx->dev;
690 rk3288_vpu_aux_buf_free(vpu, &ctx->hw.vp8d.segment_map);
691 rk3288_vpu_aux_buf_free(vpu, &ctx->hw.vp8d.prob_tbl);
694 void rk3288_vpu_vp8d_run(struct rk3288_vpu_ctx *ctx)
696 const struct v4l2_ctrl_vp8_frame_hdr *hdr = ctx->run.vp8d.frame_hdr;
697 struct rk3288_vpu_dev *vpu = ctx->dev;
698 size_t height = ctx->dst_fmt.height;
699 size_t width = ctx->dst_fmt.width;
700 u32 mb_width, mb_height;
703 rk3288_vp8d_dump_hdr(ctx);
705 /* reset segment_map buffer in keyframe */
706 if (!hdr->key_frame && ctx->hw.vp8d.segment_map.cpu)
707 memset(ctx->hw.vp8d.segment_map.cpu, 0,
708 ctx->hw.vp8d.segment_map.size);
710 rk3288_vp8d_prob_update(ctx);
712 rk3288_vpu_power_on(vpu);
714 reg = VDPU_REG_CONFIG_DEC_TIMEOUT_E
715 | VDPU_REG_CONFIG_DEC_STRENDIAN_E
716 | VDPU_REG_CONFIG_DEC_INSWAP32_E
717 | VDPU_REG_CONFIG_DEC_STRSWAP32_E
718 | VDPU_REG_CONFIG_DEC_OUTSWAP32_E
719 | VDPU_REG_CONFIG_DEC_CLK_GATE_E
720 | VDPU_REG_CONFIG_DEC_IN_ENDIAN
721 | VDPU_REG_CONFIG_DEC_OUT_ENDIAN
722 | VDPU_REG_CONFIG_DEC_MAX_BURST(16);
723 vdpu_write_relaxed(vpu, reg, VDPU_REG_CONFIG);
725 reg = VDPU_REG_DEC_CTRL0_DEC_MODE(10);
727 reg |= VDPU_REG_DEC_CTRL0_PIC_INTER_E;
728 if (!(hdr->flags & V4L2_VP8_FRAME_HDR_FLAG_MB_NO_SKIP_COEFF))
729 reg |= VDPU_REG_DEC_CTRL0_SKIP_MODE;
730 if (hdr->lf_hdr.level == 0)
731 reg |= VDPU_REG_DEC_CTRL0_FILTERING_DIS;
732 vdpu_write_relaxed(vpu, reg, VDPU_REG_DEC_CTRL0);
734 /* frame dimensions */
735 mb_width = MB_WIDTH(width);
736 mb_height = MB_HEIGHT(height);
737 reg = VDPU_REG_DEC_CTRL1_PIC_MB_WIDTH(mb_width)
738 | VDPU_REG_DEC_CTRL1_PIC_MB_HEIGHT_P(mb_height)
739 | VDPU_REG_DEC_CTRL1_PIC_MB_W_EXT(mb_width >> 9)
740 | VDPU_REG_DEC_CTRL1_PIC_MB_H_EXT(mb_height >> 8);
741 vdpu_write_relaxed(vpu, reg, VDPU_REG_DEC_CTRL1);
743 /* bool decode info */
744 reg = VDPU_REG_DEC_CTRL2_BOOLEAN_RANGE(hdr->bool_dec_range)
745 | VDPU_REG_DEC_CTRL2_BOOLEAN_VALUE(hdr->bool_dec_value);
746 vdpu_write_relaxed(vpu, reg, VDPU_REG_DEC_CTRL2);
749 if (hdr->version != 3)
750 reg |= VDPU_REG_DEC_CTRL4_VC1_HEIGHT_EXT;
751 if (hdr->version & 0x3)
752 reg |= VDPU_REG_DEC_CTRL4_BILIN_MC_E;
753 vdpu_write_relaxed(vpu, reg, VDPU_REG_DEC_CTRL4);
755 rk3288_vp8d_cfg_lf(ctx);
756 rk3288_vp8d_cfg_qp(ctx);
757 rk3288_vp8d_cfg_parts(ctx);
758 rk3288_vp8d_cfg_tap(ctx);
759 rk3288_vp8d_cfg_ref(ctx);
760 rk3288_vp8d_cfg_buffers(ctx);
762 schedule_delayed_work(&vpu->watchdog_work, msecs_to_jiffies(2000));
764 vdpu_write(vpu, VDPU_REG_INTERRUPT_DEC_E, VDPU_REG_INTERRUPT);