drivers/media/platform/rk3288-vpu/rk3288_vpu_hw_vp8d.c

   1 /*
   2  * Rockchip RK3288 VPU codec vp8 decode driver
   3  *
   4  * Copyright (C) 2014 Rockchip Electronics Co., Ltd.
   5  *      ZhiChao Yu <zhichao.yu@rock-chips.com>
   6  *
   7  * Copyright (C) 2014 Google, Inc.
   8  *      Tomasz Figa <tfiga@chromium.org>
   9  *
  10  * This software is licensed under the terms of the GNU General Public
  11  * License version 2, as published by the Free Software Foundation, and
  12  * may be copied, distributed, and modified under those terms.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  */
  19
  20 #include "rk3288_vpu_hw.h"
  21 #include "rk3288_vpu_regs.h"
  22 #include "rk3288_vpu_common.h"
  23
  24 #define DEC_8190_ALIGN_MASK     0x07U
  25
  26 /*
  27  * probs table with packed
  28  */
  29 struct vp8_prob_tbl_packed {
  30         u8 prob_mb_skip_false;
  31         u8 prob_intra;
  32         u8 prob_ref_last;
  33         u8 prob_ref_golden;
  34         u8 prob_segment[3];
  35         u8 packed0;
  36
  37         u8 prob_luma_16x16_pred_mode[4];
  38         u8 prob_chroma_pred_mode[3];
  39         u8 packed1;
  40
  41         /* mv prob */
  42         u8 prob_mv_context[2][19];
  43         u8 packed2[2];
  44
  45         /* coeff probs */
  46         u8 prob_coeffs[4][8][3][11];
  47         u8 packed3[96];
  48 };
  49
  50 struct vp8d_reg {
  51         u32 base;
  52         u32 shift;
  53         u32 mask;
  54 };
  55
  56 /* dct partiton base address regs */
  57 static const struct vp8d_reg vp8d_dct_base[8] = {
  58         { VDPU_REG_ADDR_STR, 0, 0xffffffff },
  59         { VDPU_REG_ADDR_REF(8), 0, 0xffffffff },
  60         { VDPU_REG_ADDR_REF(9), 0, 0xffffffff },
  61         { VDPU_REG_ADDR_REF(10), 0, 0xffffffff },
  62         { VDPU_REG_ADDR_REF(11), 0, 0xffffffff },
  63         { VDPU_REG_ADDR_REF(12), 0, 0xffffffff },
  64         { VDPU_REG_ADDR_REF(14), 0, 0xffffffff },
  65         { VDPU_REG_ADDR_REF(15), 0, 0xffffffff },
  66 };
  67
  68 /* loop filter level regs */
  69 static const struct vp8d_reg vp8d_lf_level[4] = {
  70         { VDPU_REG_REF_PIC(2), 18, 0x3f },
  71         { VDPU_REG_REF_PIC(2), 12, 0x3f },
  72         { VDPU_REG_REF_PIC(2), 6, 0x3f },
  73         { VDPU_REG_REF_PIC(2), 0, 0x3f },
  74 };
  75
  76 /* macroblock loop filter level adjustment regs */
  77 static const struct vp8d_reg vp8d_mb_adj[4] = {
  78         { VDPU_REG_REF_PIC(0), 21, 0x7f },
  79         { VDPU_REG_REF_PIC(0), 14, 0x7f },
  80         { VDPU_REG_REF_PIC(0), 7, 0x7f },
  81         { VDPU_REG_REF_PIC(0), 0, 0x7f },
  82 };
  83
  84 /* reference frame adjustment regs */
  85 static const struct vp8d_reg vp8d_ref_adj[4] = {
  86         { VDPU_REG_REF_PIC(1), 21, 0x7f },
  87         { VDPU_REG_REF_PIC(1), 14, 0x7f },
  88         { VDPU_REG_REF_PIC(1), 7, 0x7f },
  89         { VDPU_REG_REF_PIC(1), 0, 0x7f },
  90 };
  91
  92 /* quantizer regs */
  93 static const struct vp8d_reg vp8d_quant[4] = {
  94         { VDPU_REG_REF_PIC(3), 11, 0x7ff },
  95         { VDPU_REG_REF_PIC(3), 0, 0x7ff },
  96         { VDPU_REG_BD_REF_PIC(4), 11, 0x7ff },
  97         { VDPU_REG_BD_REF_PIC(4), 0, 0x7ff },
  98 };
  99
 100 /* quantizer delta regs */
 101 static const struct vp8d_reg vp8d_quant_delta[5] = {
 102         { VDPU_REG_REF_PIC(3), 27, 0x1f },
 103         { VDPU_REG_REF_PIC(3), 22, 0x1f },
 104         { VDPU_REG_BD_REF_PIC(4), 27, 0x1f },
 105         { VDPU_REG_BD_REF_PIC(4), 22, 0x1f },
 106         { VDPU_REG_BD_P_REF_PIC, 27, 0x1f },
 107 };
 108
 109 /* dct partition start bits regs */
 110 static const struct vp8d_reg vp8d_dct_start_bits[8] = {
 111         { VDPU_REG_DEC_CTRL2, 26, 0x3f }, { VDPU_REG_DEC_CTRL4, 26, 0x3f },
 112         { VDPU_REG_DEC_CTRL4, 20, 0x3f }, { VDPU_REG_DEC_CTRL7, 24, 0x3f },
 113         { VDPU_REG_DEC_CTRL7, 18, 0x3f }, { VDPU_REG_DEC_CTRL7, 12, 0x3f },
 114         { VDPU_REG_DEC_CTRL7, 6, 0x3f },  { VDPU_REG_DEC_CTRL7, 0, 0x3f },
 115 };
 116
 117 /* precision filter tap regs */
 118 static const struct vp8d_reg vp8d_pred_bc_tap[8][4] = {
 119         {
 120                 { VDPU_REG_PRED_FLT, 22, 0x3ff },
 121                 { VDPU_REG_PRED_FLT, 12, 0x3ff },
 122                 { VDPU_REG_PRED_FLT, 2, 0x3ff },
 123                 { VDPU_REG_REF_PIC(4), 22, 0x3ff },
 124         },
 125         {
 126                 { VDPU_REG_REF_PIC(4), 12, 0x3ff },
 127                 { VDPU_REG_REF_PIC(4), 2, 0x3ff },
 128                 { VDPU_REG_REF_PIC(5), 22, 0x3ff },
 129                 { VDPU_REG_REF_PIC(5), 12, 0x3ff },
 130         },
 131         {
 132                 { VDPU_REG_REF_PIC(5), 2, 0x3ff },
 133                 { VDPU_REG_REF_PIC(6), 22, 0x3ff },
 134                 { VDPU_REG_REF_PIC(6), 12, 0x3ff },
 135                 { VDPU_REG_REF_PIC(6), 2, 0x3ff },
 136         },
 137         {
 138                 { VDPU_REG_REF_PIC(7), 22, 0x3ff },
 139                 { VDPU_REG_REF_PIC(7), 12, 0x3ff },
 140                 { VDPU_REG_REF_PIC(7), 2, 0x3ff },
 141                 { VDPU_REG_LT_REF, 22, 0x3ff },
 142         },
 143         {
 144                 { VDPU_REG_LT_REF, 12, 0x3ff },
 145                 { VDPU_REG_LT_REF, 2, 0x3ff },
 146                 { VDPU_REG_VALID_REF, 22, 0x3ff },
 147                 { VDPU_REG_VALID_REF, 12, 0x3ff },
 148         },
 149         {
 150                 { VDPU_REG_VALID_REF, 2, 0x3ff },
 151                 { VDPU_REG_BD_REF_PIC(0), 22, 0x3ff },
 152                 { VDPU_REG_BD_REF_PIC(0), 12, 0x3ff },
 153                 { VDPU_REG_BD_REF_PIC(0), 2, 0x3ff },
 154         },
 155         {
 156                 { VDPU_REG_BD_REF_PIC(1), 22, 0x3ff },
 157                 { VDPU_REG_BD_REF_PIC(1), 12, 0x3ff },
 158                 { VDPU_REG_BD_REF_PIC(1), 2, 0x3ff },
 159                 { VDPU_REG_BD_REF_PIC(2), 22, 0x3ff },
 160         },
 161         {
 162                 { VDPU_REG_BD_REF_PIC(2), 12, 0x3ff },
 163                 { VDPU_REG_BD_REF_PIC(2), 2, 0x3ff },
 164                 { VDPU_REG_BD_REF_PIC(3), 22, 0x3ff },
 165                 { VDPU_REG_BD_REF_PIC(3), 12, 0x3ff },
 166         },
 167 };
 168
 169 /*
 170  * filter taps taken to 7-bit precision,
 171  * reference RFC6386#Page-16, filters[8][6]
 172  */
 173 static const u32 vp8d_mc_filter[8][6] = {
 174         { 0, 0, 128, 0, 0, 0 },
 175         { 0, -6, 123, 12, -1, 0 },
 176         { 2, -11, 108, 36, -8, 1 },
 177         { 0, -9, 93, 50, -6, 0 },
 178         { 3, -16, 77, 77, -16, 3 },
 179         { 0, -6, 50, 93, -9, 0 },
 180         { 1, -8, 36, 108, -11, 2 },
 181         { 0, -1, 12, 123, -6, 0 }
 182 };
 183
 184 static inline void vp8d_reg_write(struct rk3288_vpu_dev *vpu,
 185                                   const struct vp8d_reg *reg, u32 val)
 186 {
 187         u32 v;
 188
 189         v = vdpu_read(vpu, reg->base);
 190         v &= ~(reg->mask << reg->shift);
 191         v |= ((val & reg->mask) << reg->shift);
 192         vdpu_write_relaxed(vpu, v, reg->base);
 193 }
 194
 195 /* dump hw params for debug */
 196 #ifdef DEBUG
 197 static void rk3288_vp8d_dump_hdr(struct rk3288_vpu_ctx *ctx)
 198 {
 199         const struct v4l2_ctrl_vp8_frame_hdr *hdr = ctx->run.vp8d.frame_hdr;
 200         int dct_total_len = 0;
 201         int i;
 202
 203         vpu_debug(4, "Frame tag: key_frame=0x%02x, version=0x%02x\n",
 204                         !hdr->key_frame, hdr->version);
 205
 206         vpu_debug(4, "Picture size: w=%d, h=%d\n", hdr->width, hdr->height);
 207
 208         /* stream addresses */
 209         vpu_debug(4, "Addresses: segmap=0x%x, probs=0x%x\n",
 210                         ctx->hw.vp8d.segment_map.dma,
 211                         ctx->hw.vp8d.prob_tbl.dma);
 212
 213         /* reference frame info */
 214         vpu_debug(4, "Ref frame: last=%d, golden=%d, alt=%d\n",
 215                         hdr->last_frame, hdr->golden_frame, hdr->alt_frame);
 216
 217         /* bool decoder info */
 218         vpu_debug(4, "Bool decoder: range=0x%x, value=0x%x, count=0x%x\n",
 219                         hdr->bool_dec_range, hdr->bool_dec_value,
 220                         hdr->bool_dec_count);
 221
 222         /* control partition info */
 223         vpu_debug(4, "Control Part: offset=0x%x, size=0x%x\n",
 224                         hdr->first_part_offset, hdr->first_part_size);
 225         vpu_debug(2, "Macroblock Data: bits_offset=0x%x\n",
 226                         hdr->macroblock_bit_offset);
 227
 228         /* dct partition info */
 229         for (i = 0; i < hdr->num_dct_parts; i++) {
 230                 dct_total_len += hdr->dct_part_sizes[i];
 231                 vpu_debug(4, "Dct Part%d Size: 0x%x\n",
 232                                 i, hdr->dct_part_sizes[i]);
 233         }
 234
 235         dct_total_len += (hdr->num_dct_parts - 1) * 3;
 236         vpu_debug(4, "Dct Part Total Length: 0x%x\n", dct_total_len);
 237 }
 238 #else
 239 static inline void rk3288_vp8d_dump_hdr(struct rk3288_vpu_ctx *ctx) {}
 240 #endif
 241
 242 static void rk3288_vp8d_prob_update(struct rk3288_vpu_ctx *ctx)
 243 {
 244         const struct v4l2_ctrl_vp8_frame_hdr *hdr = ctx->run.vp8d.frame_hdr;
 245         const struct v4l2_vp8_entropy_hdr *entropy_hdr = &hdr->entropy_hdr;
 246         u32 i, j, k;
 247         u8 *dst;
 248
 249         /* first probs */
 250         dst = ctx->hw.vp8d.prob_tbl.cpu;
 251
 252         dst[0] = hdr->prob_skip_false;
 253         dst[1] = hdr->prob_intra;
 254         dst[2] = hdr->prob_last;
 255         dst[3] = hdr->prob_gf;
 256         dst[4] = hdr->sgmnt_hdr.segment_probs[0];
 257         dst[5] = hdr->sgmnt_hdr.segment_probs[1];
 258         dst[6] = hdr->sgmnt_hdr.segment_probs[2];
 259         dst[7] = 0;
 260
 261         dst += 8;
 262         dst[0] = entropy_hdr->y_mode_probs[0];
 263         dst[1] = entropy_hdr->y_mode_probs[1];
 264         dst[2] = entropy_hdr->y_mode_probs[2];
 265         dst[3] = entropy_hdr->y_mode_probs[3];
 266         dst[4] = entropy_hdr->uv_mode_probs[0];
 267         dst[5] = entropy_hdr->uv_mode_probs[1];
 268         dst[6] = entropy_hdr->uv_mode_probs[2];
 269         dst[7] = 0; /*unused */
 270
 271         /* mv probs */
 272         dst += 8;
 273         dst[0] = entropy_hdr->mv_probs[0][0]; /* is short */
 274         dst[1] = entropy_hdr->mv_probs[1][0];
 275         dst[2] = entropy_hdr->mv_probs[0][1]; /* sign */
 276         dst[3] = entropy_hdr->mv_probs[1][1];
 277         dst[4] = entropy_hdr->mv_probs[0][8 + 9];
 278         dst[5] = entropy_hdr->mv_probs[0][9 + 9];
 279         dst[6] = entropy_hdr->mv_probs[1][8 + 9];
 280         dst[7] = entropy_hdr->mv_probs[1][9 + 9];
 281         dst += 8;
 282         for (i = 0; i < 2; ++i) {
 283                 for (j = 0; j < 8; j += 4) {
 284                         dst[0] = entropy_hdr->mv_probs[i][j + 9 + 0];
 285                         dst[1] = entropy_hdr->mv_probs[i][j + 9 + 1];
 286                         dst[2] = entropy_hdr->mv_probs[i][j + 9 + 2];
 287                         dst[3] = entropy_hdr->mv_probs[i][j + 9 + 3];
 288                         dst += 4;
 289                 }
 290         }
 291         for (i = 0; i < 2; ++i) {
 292                 dst[0] = entropy_hdr->mv_probs[i][0 + 2];
 293                 dst[1] = entropy_hdr->mv_probs[i][1 + 2];
 294                 dst[2] = entropy_hdr->mv_probs[i][2 + 2];
 295                 dst[3] = entropy_hdr->mv_probs[i][3 + 2];
 296                 dst[4] = entropy_hdr->mv_probs[i][4 + 2];
 297                 dst[5] = entropy_hdr->mv_probs[i][5 + 2];
 298                 dst[6] = entropy_hdr->mv_probs[i][6 + 2];
 299                 dst[7] = 0;     /*unused */
 300                 dst += 8;
 301         }
 302
 303         /* coeff probs (header part) */
 304         dst = ctx->hw.vp8d.prob_tbl.cpu;
 305         dst += (8 * 7);
 306         for (i = 0; i < 4; ++i) {
 307                 for (j = 0; j < 8; ++j) {
 308                         for (k = 0; k < 3; ++k) {
 309                                 dst[0] = entropy_hdr->coeff_probs[i][j][k][0];
 310                                 dst[1] = entropy_hdr->coeff_probs[i][j][k][1];
 311                                 dst[2] = entropy_hdr->coeff_probs[i][j][k][2];
 312                                 dst[3] = entropy_hdr->coeff_probs[i][j][k][3];
 313                                 dst += 4;
 314                         }
 315                 }
 316         }
 317
 318         /* coeff probs (footer part) */
 319         dst = ctx->hw.vp8d.prob_tbl.cpu;
 320         dst += (8 * 55);
 321         for (i = 0; i < 4; ++i) {
 322                 for (j = 0; j < 8; ++j) {
 323                         for (k = 0; k < 3; ++k) {
 324                                 dst[0] = entropy_hdr->coeff_probs[i][j][k][4];
 325                                 dst[1] = entropy_hdr->coeff_probs[i][j][k][5];
 326                                 dst[2] = entropy_hdr->coeff_probs[i][j][k][6];
 327                                 dst[3] = entropy_hdr->coeff_probs[i][j][k][7];
 328                                 dst[4] = entropy_hdr->coeff_probs[i][j][k][8];
 329                                 dst[5] = entropy_hdr->coeff_probs[i][j][k][9];
 330                                 dst[6] = entropy_hdr->coeff_probs[i][j][k][10];
 331                                 dst[7] = 0;     /*unused */
 332                                 dst += 8;
 333                         }
 334                 }
 335         }
 336 }
 337
 338 /*
 339  * set loop filters
 340  */
 341 static void rk3288_vp8d_cfg_lf(struct rk3288_vpu_ctx *ctx)
 342 {
 343         const struct v4l2_ctrl_vp8_frame_hdr *hdr = ctx->run.vp8d.frame_hdr;
 344         struct rk3288_vpu_dev *vpu = ctx->dev;
 345         u32 reg;
 346         int i;
 347
 348         if (!(hdr->sgmnt_hdr.flags & V4L2_VP8_SEGMNT_HDR_FLAG_ENABLED)) {
 349                 vp8d_reg_write(vpu, &vp8d_lf_level[0], hdr->lf_hdr.level);
 350         } else if (hdr->sgmnt_hdr.segment_feature_mode) {
 351                 /* absolute mode */
 352                 for (i = 0; i < 4; i++)
 353                         vp8d_reg_write(vpu, &vp8d_lf_level[i],
 354                                         hdr->sgmnt_hdr.lf_update[i]);
 355         } else {
 356                 /* delta mode */
 357                 for (i = 0; i < 4; i++)
 358                         vp8d_reg_write(vpu, &vp8d_lf_level[i],
 359                                         clamp(hdr->lf_hdr.level
 360                                         + hdr->sgmnt_hdr.lf_update[i], 0, 63));
 361         }
 362
 363         reg = VDPU_REG_REF_PIC_FILT_SHARPNESS(hdr->lf_hdr.sharpness_level);
 364         if (hdr->lf_hdr.type)
 365                 reg |= VDPU_REG_REF_PIC_FILT_TYPE_E;
 366         vdpu_write_relaxed(vpu, reg, VDPU_REG_REF_PIC(0));
 367
 368         if (hdr->lf_hdr.flags & V4L2_VP8_LF_HDR_ADJ_ENABLE) {
 369                 for (i = 0; i < 4; i++) {
 370                         vp8d_reg_write(vpu, &vp8d_mb_adj[i],
 371                                 hdr->lf_hdr.mb_mode_delta_magnitude[i]);
 372                         vp8d_reg_write(vpu, &vp8d_ref_adj[i],
 373                                 hdr->lf_hdr.ref_frm_delta_magnitude[i]);
 374                 }
 375         }
 376 }
 377
 378 /*
 379  * set quantization parameters
 380  */
 381 static void rk3288_vp8d_cfg_qp(struct rk3288_vpu_ctx *ctx)
 382 {
 383         const struct v4l2_ctrl_vp8_frame_hdr *hdr = ctx->run.vp8d.frame_hdr;
 384         struct rk3288_vpu_dev *vpu = ctx->dev;
 385         int i;
 386
 387         if (!(hdr->sgmnt_hdr.flags & V4L2_VP8_SEGMNT_HDR_FLAG_ENABLED)) {
 388                 vp8d_reg_write(vpu, &vp8d_quant[0], hdr->quant_hdr.y_ac_qi);
 389         } else if (hdr->sgmnt_hdr.segment_feature_mode) {
 390                 /* absolute mode */
 391                 for (i = 0; i < 4; i++)
 392                         vp8d_reg_write(vpu, &vp8d_quant[i],
 393                                         hdr->sgmnt_hdr.quant_update[i]);
 394         } else {
 395                 /* delta mode */
 396                 for (i = 0; i < 4; i++)
 397                         vp8d_reg_write(vpu, &vp8d_quant[i],
 398                                         clamp(hdr->quant_hdr.y_ac_qi
 399                                         + hdr->sgmnt_hdr.quant_update[i],
 400                                         0, 127));
 401         }
 402
 403         vp8d_reg_write(vpu, &vp8d_quant_delta[0], hdr->quant_hdr.y_dc_delta);
 404         vp8d_reg_write(vpu, &vp8d_quant_delta[1], hdr->quant_hdr.y2_dc_delta);
 405         vp8d_reg_write(vpu, &vp8d_quant_delta[2], hdr->quant_hdr.y2_ac_delta);
 406         vp8d_reg_write(vpu, &vp8d_quant_delta[3], hdr->quant_hdr.uv_dc_delta);
 407         vp8d_reg_write(vpu, &vp8d_quant_delta[4], hdr->quant_hdr.uv_ac_delta);
 408 }
 409
 410 /*
 411  * set control partition and dct partition regs
 412  *
 413  * VP8 frame stream data layout:
 414  *
 415  *                           first_part_size          parttion_sizes[0]
 416  *                              ^                     ^
 417  * src_dma                      |                     |
 418  * ^                   +--------+------+        +-----+-----+
 419  * |                   | control part  |        |           |
 420  * +--------+----------------+------------------+-----------+-----+-----------+
 421  * | tag 3B | extra 7B | hdr | mb_data | dct sz | dct part0 | ... | dct partn |
 422  * +--------+-----------------------------------+-----------+-----+-----------+
 423  *                     |     |         |        |                             |
 424  *                     |     v         +----+---+                             v
 425  *                     |     mb_start       |                       src_dma_end
 426  *                     v                    v
 427  *             first_part_offset         dct size part
 428  *                                      (num_dct-1)*3B
 429  * Note:
 430  *   1. only key frame has extra 7 bytes
 431  *   2. all offsets are base on src_dma
 432  *   3. number of dct parts is 1, 2, 4 or 8
 433  *   4. the addresses set to vpu must be 64bits alignment
 434  */
 435 static void rk3288_vp8d_cfg_parts(struct rk3288_vpu_ctx *ctx)
 436 {
 437         const struct v4l2_ctrl_vp8_frame_hdr *hdr = ctx->run.vp8d.frame_hdr;
 438         struct rk3288_vpu_dev *vpu = ctx->dev;
 439         u32 dct_part_total_len = 0;
 440         u32 dct_size_part_size = 0;
 441         u32 dct_part_offset = 0;
 442         u32 mb_offset_bytes = 0;
 443         u32 mb_offset_bits = 0;
 444         u32 mb_start_bits = 0;
 445         struct vp8d_reg reg;
 446         dma_addr_t src_dma;
 447         u32 mb_size = 0;
 448         u32 count = 0;
 449         u32 i;
 450
 451         src_dma = vb2_dma_contig_plane_dma_addr(&ctx->run.src->b, 0);
 452
 453         /*
 454          * Calculate control partition mb data info
 455          * @macroblock_bit_offset:      bits offset of mb data from first
 456          *                              part start pos
 457          * @mb_offset_bits:             bits offset of mb data from src_dma
 458          *                              base addr
 459          * @mb_offset_byte:             bytes offset of mb data from src_dma
 460          *                              base addr
 461          * @mb_start_bits:              bits offset of mb data from mb data
 462          *                              64bits alignment addr
 463          */
 464         mb_offset_bits = hdr->first_part_offset * 8
 465                 + hdr->macroblock_bit_offset + 8;
 466         mb_offset_bytes = mb_offset_bits / 8;
 467         mb_start_bits = mb_offset_bits
 468                 - (mb_offset_bytes & (~DEC_8190_ALIGN_MASK)) * 8;
 469         mb_size = hdr->first_part_size
 470                 - (mb_offset_bytes - hdr->first_part_offset)
 471                 + (mb_offset_bytes & DEC_8190_ALIGN_MASK);
 472
 473         /* mb data aligned base addr */
 474         vdpu_write_relaxed(vpu, (mb_offset_bytes & (~DEC_8190_ALIGN_MASK))
 475                                 + src_dma, VDPU_REG_ADDR_REF(13));
 476
 477         /* mb data start bits */
 478         reg.base = VDPU_REG_DEC_CTRL2;
 479         reg.mask = 0x3f;
 480         reg.shift = 18;
 481         vp8d_reg_write(vpu, &reg, mb_start_bits);
 482
 483         /* mb aligned data length */
 484         reg.base = VDPU_REG_DEC_CTRL6;
 485         reg.mask = 0x3fffff;
 486         reg.shift = 0;
 487         vp8d_reg_write(vpu, &reg, mb_size);
 488
 489         /*
 490          * Calculate dct partition info
 491          * @dct_size_part_size: Containing sizes of dct part, every dct part
 492          *                      has 3 bytes to store its size, except the last
 493          *                      dct part
 494          * @dct_part_offset:    bytes offset of dct parts from src_dma base addr
 495          * @dct_part_total_len: total size of all dct parts
 496          */
 497         dct_size_part_size = (hdr->num_dct_parts - 1) * 3;
 498         dct_part_offset = hdr->first_part_offset + hdr->first_part_size;
 499         for (i = 0; i < hdr->num_dct_parts; i++)
 500                 dct_part_total_len += hdr->dct_part_sizes[i];
 501         dct_part_total_len += dct_size_part_size;
 502         dct_part_total_len += (dct_part_offset & DEC_8190_ALIGN_MASK);
 503
 504         /* number of dct partitions */
 505         reg.base = VDPU_REG_DEC_CTRL6;
 506         reg.mask = 0xf;
 507         reg.shift = 24;
 508         vp8d_reg_write(vpu, &reg, hdr->num_dct_parts - 1);
 509
 510         /* dct partition length */
 511         vdpu_write_relaxed(vpu,
 512                         VDPU_REG_DEC_CTRL3_STREAM_LEN(dct_part_total_len),
 513                         VDPU_REG_DEC_CTRL3);
 514
 515         /* dct partitions base address */
 516         for (i = 0; i < hdr->num_dct_parts; i++) {
 517                 u32 byte_offset = dct_part_offset + dct_size_part_size + count;
 518                 u32 base_addr = byte_offset + src_dma;
 519
 520                 vp8d_reg_write(vpu, &vp8d_dct_base[i],
 521                                 base_addr & (~DEC_8190_ALIGN_MASK));
 522
 523                 vp8d_reg_write(vpu, &vp8d_dct_start_bits[i],
 524                                 (byte_offset & DEC_8190_ALIGN_MASK) * 8);
 525
 526                 count += hdr->dct_part_sizes[i];
 527         }
 528 }
 529
 530 /*
 531  * prediction filter taps
 532  * normal 6-tap filters
 533  */
 534 static void rk3288_vp8d_cfg_tap(struct rk3288_vpu_ctx *ctx)
 535 {
 536         const struct v4l2_ctrl_vp8_frame_hdr *hdr = ctx->run.vp8d.frame_hdr;
 537         struct rk3288_vpu_dev *vpu = ctx->dev;
 538         struct vp8d_reg reg;
 539         u32 val = 0;
 540         int i, j;
 541
 542         reg.base = VDPU_REG_BD_REF_PIC(3);
 543         reg.mask = 0xf;
 544
 545         if ((hdr->version & 0x03) != 0)
 546                 return; /* Tap filter not used. */
 547
 548
 549         for (i = 0; i < 8; i++) {
 550                 val = (vp8d_mc_filter[i][0] << 2) | vp8d_mc_filter[i][5];
 551
 552                 for (j = 0; j < 4; j++)
 553                         vp8d_reg_write(vpu, &vp8d_pred_bc_tap[i][j],
 554                                         vp8d_mc_filter[i][j + 1]);
 555
 556                 switch (i) {
 557                 case 2:
 558                         reg.shift = 8;
 559                         break;
 560                 case 4:
 561                         reg.shift = 4;
 562                         break;
 563                 case 6:
 564                         reg.shift = 0;
 565                         break;
 566                 default:
 567                         continue;
 568                 }
 569
 570                 vp8d_reg_write(vpu, &reg, val);
 571         }
 572 }
 573
 574 /* set reference frame */
 575 static void rk3288_vp8d_cfg_ref(struct rk3288_vpu_ctx *ctx)
 576 {
 577         u32 reg;
 578         struct vb2_buffer *buf;
 579         struct rk3288_vpu_dev *vpu = ctx->dev;
 580         const struct v4l2_ctrl_vp8_frame_hdr *hdr = ctx->run.vp8d.frame_hdr;
 581
 582         /* set last frame address */
 583         if (hdr->last_frame >= ctx->vq_dst.num_buffers)
 584                 buf = &ctx->run.dst->b;
 585         else
 586                 buf = ctx->dst_bufs[hdr->last_frame];
 587
 588         if (!hdr->key_frame)
 589                 vdpu_write_relaxed(vpu,
 590                         vb2_dma_contig_plane_dma_addr(&ctx->run.dst->b, 0),
 591                         VDPU_REG_ADDR_REF(0));
 592         else
 593                 vdpu_write_relaxed(vpu, vb2_dma_contig_plane_dma_addr(buf, 0),
 594                         VDPU_REG_ADDR_REF(0));
 595
 596         /* set golden reference frame buffer address */
 597         if (hdr->golden_frame >= ctx->vq_dst.num_buffers)
 598                 buf = &ctx->run.dst->b;
 599         else
 600                 buf = ctx->dst_bufs[hdr->golden_frame];
 601
 602         reg = vb2_dma_contig_plane_dma_addr(buf, 0);
 603         if (hdr->sign_bias_golden)
 604                 reg |= VDPU_REG_ADDR_REF_TOPC_E;
 605         vdpu_write_relaxed(vpu, reg, VDPU_REG_ADDR_REF(4));
 606
 607         /* set alternate reference frame buffer address */
 608         if (hdr->alt_frame >= ctx->vq_dst.num_buffers)
 609                 buf = &ctx->run.dst->b;
 610         else
 611                 buf = ctx->dst_bufs[hdr->alt_frame];
 612
 613         reg = vb2_dma_contig_plane_dma_addr(buf, 0);
 614         if (hdr->sign_bias_alternate)
 615                 reg |= VDPU_REG_ADDR_REF_TOPC_E;
 616         vdpu_write_relaxed(vpu, reg, VDPU_REG_ADDR_REF(5));
 617 }
 618
 619 static void rk3288_vp8d_cfg_buffers(struct rk3288_vpu_ctx *ctx)
 620 {
 621         const struct v4l2_ctrl_vp8_frame_hdr *hdr = ctx->run.vp8d.frame_hdr;
 622         struct rk3288_vpu_dev *vpu = ctx->dev;
 623         u32 reg;
 624
 625         /* set probability table buffer address */
 626         vdpu_write_relaxed(vpu, ctx->hw.vp8d.prob_tbl.dma,
 627                                 VDPU_REG_ADDR_QTABLE);
 628
 629         /* set segment map address */
 630         reg = 0;
 631         reg = VDPU_REG_FWD_PIC1_SEGMENT_BASE(ctx->hw.vp8d.segment_map.dma);
 632         if (hdr->sgmnt_hdr.flags & V4L2_VP8_SEGMNT_HDR_FLAG_ENABLED) {
 633                 reg |= VDPU_REG_FWD_PIC1_SEGMENT_E;
 634                 if (hdr->sgmnt_hdr.flags & V4L2_VP8_SEGMNT_HDR_FLAG_UPDATE_MAP)
 635                         reg |= VDPU_REG_FWD_PIC1_SEGMENT_UPD_E;
 636         }
 637         vdpu_write_relaxed(vpu, reg, VDPU_REG_FWD_PIC(0));
 638
 639         /* set output frame buffer address */
 640         vdpu_write_relaxed(vpu,
 641                         vb2_dma_contig_plane_dma_addr(&ctx->run.dst->b, 0),
 642                         VDPU_REG_ADDR_DST);
 643 }
 644
 645 int rk3288_vpu_vp8d_init(struct rk3288_vpu_ctx *ctx)
 646 {
 647         struct rk3288_vpu_dev *vpu = ctx->dev;
 648         unsigned int mb_width, mb_height;
 649         size_t segment_map_size;
 650         int ret;
 651
 652         /* segment map table size calculation */
 653         mb_width = MB_WIDTH(ctx->dst_fmt.width);
 654         mb_height = MB_HEIGHT(ctx->dst_fmt.height);
 655         segment_map_size = round_up(DIV_ROUND_UP(mb_width * mb_height, 4), 64);
 656
 657         /*
 658          * In context init the dma buffer for segment map must be allocated.
 659          * And the data in segment map buffer must be set to all zero.
 660          */
 661         ret = rk3288_vpu_aux_buf_alloc(vpu, &ctx->hw.vp8d.segment_map,
 662                                         segment_map_size);
 663         if (ret) {
 664                 vpu_err("allocate segment map mem failed\n");
 665                 return ret;
 666         }
 667         memset(ctx->hw.vp8d.segment_map.cpu, 0, ctx->hw.vp8d.segment_map.size);
 668
 669         /*
 670          * Allocate probability table buffer,
 671          * total 1208 bytes, 4K page is far enough.
 672          */
 673         ret = rk3288_vpu_aux_buf_alloc(vpu, &ctx->hw.vp8d.prob_tbl,
 674                                         sizeof(struct vp8_prob_tbl_packed));
 675         if (ret) {
 676                 vpu_err("allocate prob table mem failed\n");
 677                 goto prob_table_failed;
 678         }
 679
 680         return 0;
 681
 682 prob_table_failed:
 683         rk3288_vpu_aux_buf_free(vpu, &ctx->hw.vp8d.segment_map);
 684
 685         return ret;
 686 }
 687
 688 void rk3288_vpu_vp8d_exit(struct rk3288_vpu_ctx *ctx)
 689 {
 690         struct rk3288_vpu_dev *vpu = ctx->dev;
 691
 692         rk3288_vpu_aux_buf_free(vpu, &ctx->hw.vp8d.segment_map);
 693         rk3288_vpu_aux_buf_free(vpu, &ctx->hw.vp8d.prob_tbl);
 694 }
 695
 696 void rk3288_vpu_vp8d_run(struct rk3288_vpu_ctx *ctx)
 697 {
 698         const struct v4l2_ctrl_vp8_frame_hdr *hdr = ctx->run.vp8d.frame_hdr;
 699         struct rk3288_vpu_dev *vpu = ctx->dev;
 700         size_t height = ctx->dst_fmt.height;
 701         size_t width = ctx->dst_fmt.width;
 702         u32 mb_width, mb_height;
 703         u32 reg;
 704
 705         rk3288_vp8d_dump_hdr(ctx);
 706
 707         /* reset segment_map buffer in keyframe */
 708         if (!hdr->key_frame && ctx->hw.vp8d.segment_map.cpu)
 709                 memset(ctx->hw.vp8d.segment_map.cpu, 0,
 710                         ctx->hw.vp8d.segment_map.size);
 711
 712         rk3288_vp8d_prob_update(ctx);
 713
 714         rk3288_vpu_power_on(vpu);
 715
 716         reg = VDPU_REG_CONFIG_DEC_TIMEOUT_E
 717                 | VDPU_REG_CONFIG_DEC_STRENDIAN_E
 718                 | VDPU_REG_CONFIG_DEC_INSWAP32_E
 719                 | VDPU_REG_CONFIG_DEC_STRSWAP32_E
 720                 | VDPU_REG_CONFIG_DEC_OUTSWAP32_E
 721                 | VDPU_REG_CONFIG_DEC_CLK_GATE_E
 722                 | VDPU_REG_CONFIG_DEC_IN_ENDIAN
 723                 | VDPU_REG_CONFIG_DEC_OUT_ENDIAN
 724                 | VDPU_REG_CONFIG_DEC_MAX_BURST(16);
 725         vdpu_write_relaxed(vpu, reg, VDPU_REG_CONFIG);
 726
 727         reg = VDPU_REG_DEC_CTRL0_DEC_MODE(10);
 728         if (hdr->key_frame)
 729                 reg |= VDPU_REG_DEC_CTRL0_PIC_INTER_E;
 730         if (!(hdr->flags & V4L2_VP8_FRAME_HDR_FLAG_MB_NO_SKIP_COEFF))
 731                 reg |= VDPU_REG_DEC_CTRL0_SKIP_MODE;
 732         if (hdr->lf_hdr.level == 0)
 733                 reg |= VDPU_REG_DEC_CTRL0_FILTERING_DIS;
 734         vdpu_write_relaxed(vpu, reg, VDPU_REG_DEC_CTRL0);
 735
 736         /* frame dimensions */
 737         mb_width = MB_WIDTH(width);
 738         mb_height = MB_HEIGHT(height);
 739         reg = VDPU_REG_DEC_CTRL1_PIC_MB_WIDTH(mb_width)
 740                 | VDPU_REG_DEC_CTRL1_PIC_MB_HEIGHT_P(mb_height)
 741                 | VDPU_REG_DEC_CTRL1_PIC_MB_W_EXT(mb_width >> 9)
 742                 | VDPU_REG_DEC_CTRL1_PIC_MB_H_EXT(mb_height >> 8);
 743         vdpu_write_relaxed(vpu, reg, VDPU_REG_DEC_CTRL1);
 744
 745         /* bool decode info */
 746         reg = VDPU_REG_DEC_CTRL2_BOOLEAN_RANGE(hdr->bool_dec_range)
 747                 | VDPU_REG_DEC_CTRL2_BOOLEAN_VALUE(hdr->bool_dec_value);
 748         vdpu_write_relaxed(vpu, reg, VDPU_REG_DEC_CTRL2);
 749
 750         reg = 0;
 751         if (hdr->version != 3)
 752                 reg |= VDPU_REG_DEC_CTRL4_VC1_HEIGHT_EXT;
 753         if (hdr->version & 0x3)
 754                 reg |= VDPU_REG_DEC_CTRL4_BILIN_MC_E;
 755         vdpu_write_relaxed(vpu, reg, VDPU_REG_DEC_CTRL4);
 756
 757         rk3288_vp8d_cfg_lf(ctx);
 758         rk3288_vp8d_cfg_qp(ctx);
 759         rk3288_vp8d_cfg_parts(ctx);
 760         rk3288_vp8d_cfg_tap(ctx);
 761         rk3288_vp8d_cfg_ref(ctx);
 762         rk3288_vp8d_cfg_buffers(ctx);
 763
 764         schedule_delayed_work(&vpu->watchdog_work, msecs_to_jiffies(2000));
 765
 766         vdpu_write(vpu, VDPU_REG_INTERRUPT_DEC_E, VDPU_REG_INTERRUPT);
 767 }