2 * Rockchip RK3288 VPU codec driver
4 * Copyright (C) 2014 Google, Inc.
5 * Tomasz Figa <tfiga@chromium.org>
7 * Based on s5p-mfc driver by Samsung Electronics Co., Ltd.
9 * Copyright (C) 2011 Samsung Electronics Co., Ltd.
11 * This software is licensed under the terms of the GNU General Public
12 * License version 2, as published by the Free Software Foundation, and
13 * may be copied, distributed, and modified under those terms.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
21 #ifndef RK3288_VPU_COMMON_H_
22 #define RK3288_VPU_COMMON_H_
24 /* Enable debugging by default for now. */
27 #include <linux/platform_device.h>
28 #include <linux/videodev2.h>
29 #include <linux/wait.h>
31 #include <media/v4l2-ctrls.h>
32 #include <media/v4l2-device.h>
33 #include <media/v4l2-ioctl.h>
34 #include <media/videobuf2-core.h>
35 #include <media/videobuf2-dma-contig.h>
37 #include "rk3288_vpu_hw.h"
39 #define RK3288_VPU_NAME "rk3288-vpu"
40 #define RK3288_VPU_DEC_NAME "rk3288-vpu-dec"
41 #define RK3288_VPU_ENC_NAME "rk3288-vpu-enc"
43 #define V4L2_CID_CUSTOM_BASE (V4L2_CID_USER_BASE | 0x1000)
45 #define DST_QUEUE_OFF_BASE (TASK_SIZE / 2)
47 #define RK3288_VPU_MAX_CTRLS 32
50 #define MB_WIDTH(x_size) DIV_ROUND_UP(x_size, MB_DIM)
51 #define MB_HEIGHT(y_size) DIV_ROUND_UP(y_size, MB_DIM)
53 struct rk3288_vpu_variant;
54 struct rk3288_vpu_ctx;
55 struct rk3288_vpu_codec_ops;
58 * enum rk3288_vpu_codec_mode - codec operating mode.
59 * @RK_VPU_CODEC_NONE: No operating mode. Used for RAW video formats.
60 * @RK_VPU_CODEC_H264D: H264 decoder.
61 * @RK_VPU_CODEC_VP8D: VP8 decoder.
62 * @RK_VPU_CODEC_H264E: H264 encoder.
63 * @RK_VPU_CODEC_VP8E: VP8 encoder.
65 enum rk3288_vpu_codec_mode {
66 RK_VPU_CODEC_NONE = -1,
74 * enum rk3288_vpu_plane - indices of planes inside a VB2 buffer.
75 * @PLANE_Y: Plane containing luminance data (also denoted as Y).
76 * @PLANE_CB_CR: Plane containing interleaved chrominance data (also
78 * @PLANE_CB: Plane containing CB part of chrominance data.
79 * @PLANE_CR: Plane containing CR part of chrominance data.
81 enum rk3288_vpu_plane {
89 * struct rk3288_vpu_vp8e_buf_data - mode-specific per-buffer data
90 * @dct_offset: Offset inside the buffer to DCT partition.
91 * @hdr_size: Size of header data in the buffer.
92 * @ext_hdr_size: Size of ext header data in the buffer.
93 * @dct_size: Size of DCT partition in the buffer.
94 * @header: Frame header to copy to destination buffer.
96 struct rk3288_vpu_vp8e_buf_data {
101 u8 header[RK3288_HEADER_SIZE];
105 * struct rk3288_vpu_buf - Private data related to each VB2 buffer.
106 * @list: List head for queuing in buffer queue.
107 * @b: Pointer to related VB2 buffer.
108 * @flags: Buffer state. See enum rk3288_vpu_buf_flags.
110 struct rk3288_vpu_buf {
112 struct list_head list;
114 /* Mode-specific data. */
116 struct rk3288_vpu_vp8e_buf_data vp8e;
121 * enum rk3288_vpu_state - bitwise flags indicating hardware state.
122 * @VPU_RUNNING: The hardware has been programmed for operation
123 * and is running at the moment.
124 * @VPU_SUSPENDED: System is entering sleep state and no more runs
125 * should be executed on hardware.
127 enum rk3288_vpu_state {
128 VPU_RUNNING = BIT(0),
129 VPU_SUSPENDED = BIT(1),
133 * struct rk3288_vpu_dev - driver data
134 * @v4l2_dev: V4L2 device to register video devices for.
135 * @vfd_dec: Video device for decoder.
136 * @vfd_enc: Video device for encoder.
137 * @pdev: Pointer to VPU platform device.
138 * @dev: Pointer to device for convenient logging using
140 * @alloc_ctx: VB2 allocator context
141 * (for allocations without kernel mapping).
142 * @alloc_ctx_vm: VB2 allocator context
143 * (for allocations with kernel mapping).
144 * @aclk_vcodec: Handle of ACLK clock.
145 * @hclk_vcodec: Handle of HCLK clock.
146 * @base: Mapped address of VPU registers.
147 * @enc_base: Mapped address of VPU encoder register for convenience.
148 * @dec_base: Mapped address of VPU decoder register for convenience.
149 * @mapping: DMA IOMMU mapping.
150 * @vpu_mutex: Mutex to synchronize V4L2 calls.
151 * @irqlock: Spinlock to synchronize access to data structures
152 * shared with interrupt handlers.
153 * @state: Device state.
154 * @ready_ctxs: List of contexts ready to run.
155 * @variant: Hardware variant-specfic parameters.
156 * @current_ctx: Context being currently processed by hardware.
157 * @run_wq: Wait queue to wait for run completion.
158 * @watchdog_work: Delayed work for hardware timeout handling.
160 struct rk3288_vpu_dev {
161 struct v4l2_device v4l2_dev;
162 struct video_device *vfd_dec;
163 struct video_device *vfd_enc;
164 struct platform_device *pdev;
168 struct clk *aclk_vcodec;
169 struct clk *hclk_vcodec;
171 void __iomem *enc_base;
172 void __iomem *dec_base;
173 struct dma_iommu_mapping *mapping;
175 struct mutex vpu_mutex; /* video_device lock */
178 struct list_head ready_ctxs;
179 const struct rk3288_vpu_variant *variant;
180 struct rk3288_vpu_ctx *current_ctx;
181 wait_queue_head_t run_wq;
182 struct delayed_work watchdog_work;
186 * struct rk3288_vpu_run_ops - per context operations on run data.
187 * @prepare_run: Called when the context was selected for running
188 * to prepare operating mode specific data.
189 * @run_done: Called when hardware completed the run to collect
190 * operating mode specific data from hardware and
191 * finalize the processing.
193 struct rk3288_vpu_run_ops {
194 void (*prepare_run)(struct rk3288_vpu_ctx *);
195 void (*run_done)(struct rk3288_vpu_ctx *, enum vb2_buffer_state);
199 * struct rk3288_vpu_vp8e_run - per-run data specific to VP8 encoding.
200 * @reg_params: Pointer to a buffer containing register values prepared
203 struct rk3288_vpu_vp8e_run {
204 const struct rk3288_vp8e_reg_params *reg_params;
208 * struct rk3288_vpu_vp8d_run - per-run data specific to VP8 decoding.
209 * @frame_hdr: Pointer to a buffer containing per-run frame data which
210 * is needed by setting vpu register.
212 struct rk3288_vpu_vp8d_run {
213 const struct v4l2_ctrl_vp8_frame_hdr *frame_hdr;
217 * struct rk3288_vpu_h264d_run - per-run data specific to H264 decoding.
218 * @sps: Pointer to a buffer containing H264 SPS.
219 * @pps: Pointer to a buffer containing H264 PPS.
220 * @scaling_matrix: Pointer to a buffer containing scaling matrix.
221 * @slice_param: Pointer to a buffer containing slice parameters array.
222 * @decode_param: Pointer to a buffer containing decode parameters.
223 * @dpb: Array of DPB entries reordered to keep POC order.
224 * @dpb_map: Map of indices used in ref_pic_list_* into indices to
225 * reordered DPB array.
227 struct rk3288_vpu_h264d_run {
228 const struct v4l2_ctrl_h264_sps *sps;
229 const struct v4l2_ctrl_h264_pps *pps;
230 const struct v4l2_ctrl_h264_scaling_matrix *scaling_matrix;
231 const struct v4l2_ctrl_h264_slice_param *slice_param;
232 const struct v4l2_ctrl_h264_decode_param *decode_param;
233 struct v4l2_h264_dpb_entry dpb[16];
238 * struct rk3288_vpu_run - per-run data for hardware code.
239 * @src: Source buffer to be processed.
240 * @dst: Destination buffer to be processed.
241 * @priv_src: Hardware private source buffer.
242 * @priv_dst: Hardware private destination buffer.
244 struct rk3288_vpu_run {
245 /* Generic for more than one operating mode. */
246 struct rk3288_vpu_buf *src;
247 struct rk3288_vpu_buf *dst;
249 struct rk3288_vpu_aux_buf priv_src;
250 struct rk3288_vpu_aux_buf priv_dst;
252 /* Specific for particular operating modes. */
254 struct rk3288_vpu_vp8e_run vp8e;
255 struct rk3288_vpu_vp8d_run vp8d;
256 struct rk3288_vpu_h264d_run h264d;
257 /* Other modes will need different data. */
262 * struct rk3288_vpu_ctx - Context (instance) private data.
264 * @dev: VPU driver data to which the context belongs.
265 * @fh: V4L2 file handler.
267 * @vpu_src_fmt: Descriptor of active source format.
268 * @src_fmt: V4L2 pixel format of active source format.
269 * @vpu_dst_fmt: Descriptor of active destination format.
270 * @dst_fmt: V4L2 pixel format of active destination format.
272 * @vq_src: Videobuf2 source queue.
273 * @src_queue: Internal source buffer queue.
274 * @src_crop: Configured source crop rectangle (encoder-only).
275 * @vq_dst: Videobuf2 destination queue
276 * @dst_queue: Internal destination buffer queue.
277 * @dst_bufs: Private buffers wrapping VB2 buffers (destination).
279 * @ctrls: Array containing pointer to registered controls.
280 * @ctrl_handler: Control handler used to register controls.
281 * @num_ctrls: Number of registered controls.
283 * @list: List head for queue of ready contexts.
285 * @run: Structure containing data about currently scheduled
287 * @run_ops: Set of operations related to currently scheduled run.
288 * @hw: Structure containing hardware-related context.
290 struct rk3288_vpu_ctx {
291 struct rk3288_vpu_dev *dev;
295 struct rk3288_vpu_fmt *vpu_src_fmt;
296 struct v4l2_pix_format_mplane src_fmt;
297 struct rk3288_vpu_fmt *vpu_dst_fmt;
298 struct v4l2_pix_format_mplane dst_fmt;
301 struct vb2_queue vq_src;
302 struct list_head src_queue;
303 struct v4l2_rect src_crop;
304 struct vb2_queue vq_dst;
305 struct list_head dst_queue;
306 struct vb2_buffer *dst_bufs[VIDEO_MAX_FRAME];
309 struct v4l2_ctrl *ctrls[RK3288_VPU_MAX_CTRLS];
310 struct v4l2_ctrl_handler ctrl_handler;
313 /* Various runtime data */
314 struct list_head list;
316 struct rk3288_vpu_run run;
317 const struct rk3288_vpu_run_ops *run_ops;
318 struct rk3288_vpu_hw_ctx hw;
322 * struct rk3288_vpu_fmt - information about supported video formats.
323 * @name: Human readable name of the format.
324 * @fourcc: FourCC code of the format. See V4L2_PIX_FMT_*.
325 * @codec_mode: Codec mode related to this format. See
326 * enum rk3288_vpu_codec_mode.
327 * @num_planes: Number of planes used by this format.
328 * @depth: Depth of each plane in bits per pixel.
329 * @enc_fmt: Format identifier for encoder registers.
331 struct rk3288_vpu_fmt {
334 enum rk3288_vpu_codec_mode codec_mode;
336 u8 depth[VIDEO_MAX_PLANES];
337 enum rk3288_vpu_enc_fmt enc_fmt;
341 * struct rk3288_vpu_control - information about controls to be registered.
343 * @type: Type of the control.
344 * @name: Human readable name of the control.
345 * @minimum: Minimum value of the control.
346 * @maximum: Maximum value of the control.
347 * @step: Control value increase step.
348 * @menu_skip_mask: Mask of invalid menu positions.
349 * @default_value: Initial value of the control.
350 * @max_stores: Maximum number of configration stores.
351 * @dims: Size of each dimension of compound control.
352 * @elem_size: Size of individual element of compound control.
353 * @is_volatile: Control is volatile.
354 * @is_read_only: Control is read-only.
355 * @can_store: Control uses configuration stores.
357 * See also struct v4l2_ctrl_config.
359 struct rk3288_vpu_control {
362 enum v4l2_ctrl_type type;
370 u32 dims[V4L2_CTRL_MAX_DIMS];
378 /* Logging helpers */
381 * debug - Module parameter to control level of debugging messages.
383 * Level of debugging messages can be controlled by bits of module parameter
384 * called "debug". Meaning of particular bits is as follows:
386 * bit 0 - global information: mode, size, init, release
387 * bit 1 - each run start/result information
388 * bit 2 - contents of small controls from userspace
389 * bit 3 - contents of big controls from userspace
390 * bit 4 - detail fmt, ctrl, buffer q/dq information
391 * bit 5 - detail function enter/leave trace information
392 * bit 6 - register write/read information
396 #define vpu_debug(level, fmt, args...) \
398 if (debug & BIT(level)) \
399 pr_debug("%s:%d: " fmt, \
400 __func__, __LINE__, ##args); \
403 #define vpu_debug_enter() vpu_debug(5, "enter\n")
404 #define vpu_debug_leave() vpu_debug(5, "leave\n")
406 #define vpu_err(fmt, args...) \
407 pr_err("%s:%d: " fmt, __func__, __LINE__, ##args)
409 static inline char *fmt2str(u32 fmt, char *str)
412 char b = (fmt >> 8) & 0xFF;
413 char c = (fmt >> 16) & 0xFF;
414 char d = (fmt >> 24) & 0xFF;
416 sprintf(str, "%c%c%c%c", a, b, c, d);
421 /* Structure access helpers. */
422 static inline struct rk3288_vpu_ctx *fh_to_ctx(struct v4l2_fh *fh)
424 return container_of(fh, struct rk3288_vpu_ctx, fh);
427 static inline struct rk3288_vpu_ctx *ctrl_to_ctx(struct v4l2_ctrl *ctrl)
429 return container_of(ctrl->handler, struct rk3288_vpu_ctx, ctrl_handler);
432 static inline struct rk3288_vpu_buf *vb_to_buf(struct vb2_buffer *vb)
434 return container_of(vb, struct rk3288_vpu_buf, b);
437 static inline bool rk3288_vpu_ctx_is_encoder(struct rk3288_vpu_ctx *ctx)
439 return ctx->vpu_dst_fmt->codec_mode != RK_VPU_CODEC_NONE;
442 int rk3288_vpu_ctrls_setup(struct rk3288_vpu_ctx *ctx,
443 const struct v4l2_ctrl_ops *ctrl_ops,
444 struct rk3288_vpu_control *controls,
446 const char *const *(*get_menu)(u32));
447 void rk3288_vpu_ctrls_delete(struct rk3288_vpu_ctx *ctx);
449 void rk3288_vpu_try_context(struct rk3288_vpu_dev *dev,
450 struct rk3288_vpu_ctx *ctx);
452 void rk3288_vpu_run_done(struct rk3288_vpu_ctx *ctx,
453 enum vb2_buffer_state result);
455 int rk3288_vpu_aux_buf_alloc(struct rk3288_vpu_dev *vpu,
456 struct rk3288_vpu_aux_buf *buf, size_t size);
457 void rk3288_vpu_aux_buf_free(struct rk3288_vpu_dev *vpu,
458 struct rk3288_vpu_aux_buf *buf);
460 /* Register accessors. */
461 static inline void vepu_write_relaxed(struct rk3288_vpu_dev *vpu,
464 vpu_debug(6, "MARK: set reg[%03d]: %08x\n", reg / 4, val);
465 writel_relaxed(val, vpu->enc_base + reg);
468 static inline void vepu_write(struct rk3288_vpu_dev *vpu, u32 val, u32 reg)
470 vpu_debug(6, "MARK: set reg[%03d]: %08x\n", reg / 4, val);
471 writel(val, vpu->enc_base + reg);
474 static inline u32 vepu_read(struct rk3288_vpu_dev *vpu, u32 reg)
476 u32 val = readl(vpu->enc_base + reg);
478 vpu_debug(6, "MARK: get reg[%03d]: %08x\n", reg / 4, val);
482 static inline void vdpu_write_relaxed(struct rk3288_vpu_dev *vpu,
485 vpu_debug(6, "MARK: set reg[%03d]: %08x\n", reg / 4, val);
486 writel_relaxed(val, vpu->dec_base + reg);
489 static inline void vdpu_write(struct rk3288_vpu_dev *vpu, u32 val, u32 reg)
491 vpu_debug(6, "MARK: set reg[%03d]: %08x\n", reg / 4, val);
492 writel(val, vpu->dec_base + reg);
495 static inline u32 vdpu_read(struct rk3288_vpu_dev *vpu, u32 reg)
497 u32 val = readl(vpu->dec_base + reg);
499 vpu_debug(6, "MARK: get reg[%03d]: %08x\n", reg / 4, val);
503 #endif /* RK3288_VPU_COMMON_H_ */