2 * The Marvell camera core. This device appears in a number of settings,
3 * so it needs platform-specific support outside of the core.
5 * Copyright 2011 Jonathan Corbet corbet@lwn.net
7 #include <linux/kernel.h>
8 #include <linux/module.h>
11 #include <linux/i2c.h>
12 #include <linux/interrupt.h>
13 #include <linux/spinlock.h>
14 #include <linux/slab.h>
15 #include <linux/device.h>
16 #include <linux/wait.h>
17 #include <linux/list.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/delay.h>
20 #include <linux/vmalloc.h>
22 #include <linux/clk.h>
23 #include <linux/videodev2.h>
24 #include <media/v4l2-device.h>
25 #include <media/v4l2-ioctl.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-event.h>
28 #include <media/ov7670.h>
29 #include <media/videobuf2-vmalloc.h>
30 #include <media/videobuf2-dma-contig.h>
31 #include <media/videobuf2-dma-sg.h>
33 #include "mcam-core.h"
35 #ifdef MCAM_MODE_VMALLOC
37 * Internal DMA buffer management. Since the controller cannot do S/G I/O,
38 * we must have physically contiguous buffers to bring frames into.
39 * These parameters control how many buffers we use, whether we
40 * allocate them at load time (better chance of success, but nails down
41 * memory) or when somebody tries to use the camera (riskier), and,
42 * for load-time allocation, how big they should be.
44 * The controller can cycle through three buffers. We could use
45 * more by flipping pointers around, but it probably makes little
49 static bool alloc_bufs_at_read;
50 module_param(alloc_bufs_at_read, bool, 0444);
51 MODULE_PARM_DESC(alloc_bufs_at_read,
52 "Non-zero value causes DMA buffers to be allocated when the "
53 "video capture device is read, rather than at module load "
54 "time. This saves memory, but decreases the chances of "
55 "successfully getting those buffers. This parameter is "
56 "only used in the vmalloc buffer mode");
58 static int n_dma_bufs = 3;
59 module_param(n_dma_bufs, uint, 0644);
60 MODULE_PARM_DESC(n_dma_bufs,
61 "The number of DMA buffers to allocate. Can be either two "
62 "(saves memory, makes timing tighter) or three.");
64 static int dma_buf_size = VGA_WIDTH * VGA_HEIGHT * 2; /* Worst case */
65 module_param(dma_buf_size, uint, 0444);
66 MODULE_PARM_DESC(dma_buf_size,
67 "The size of the allocated DMA buffers. If actual operating "
68 "parameters require larger buffers, an attempt to reallocate "
70 #else /* MCAM_MODE_VMALLOC */
71 static const bool alloc_bufs_at_read;
72 static const int n_dma_bufs = 3; /* Used by S/G_PARM */
73 #endif /* MCAM_MODE_VMALLOC */
76 module_param(flip, bool, 0444);
77 MODULE_PARM_DESC(flip,
78 "If set, the sensor will be instructed to flip the image "
81 static int buffer_mode = -1;
82 module_param(buffer_mode, int, 0444);
83 MODULE_PARM_DESC(buffer_mode,
84 "Set the buffer mode to be used; default is to go with what "
85 "the platform driver asks for. Set to 0 for vmalloc, 1 for "
89 * Status flags. Always manipulated with bit operations.
91 #define CF_BUF0_VALID 0 /* Buffers valid - first three */
92 #define CF_BUF1_VALID 1
93 #define CF_BUF2_VALID 2
94 #define CF_DMA_ACTIVE 3 /* A frame is incoming */
95 #define CF_CONFIG_NEEDED 4 /* Must configure hardware */
96 #define CF_SINGLE_BUFFER 5 /* Running with a single buffer */
97 #define CF_SG_RESTART 6 /* SG restart needed */
98 #define CF_FRAME_SOF0 7 /* Frame 0 started */
99 #define CF_FRAME_SOF1 8
100 #define CF_FRAME_SOF2 9
102 #define sensor_call(cam, o, f, args...) \
103 v4l2_subdev_call(cam->sensor, o, f, ##args)
105 static struct mcam_format_struct {
108 int bpp; /* Bytes per pixel */
113 .desc = "YUYV 4:2:2",
114 .pixelformat = V4L2_PIX_FMT_YUYV,
115 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
120 .desc = "UYVY 4:2:2",
121 .pixelformat = V4L2_PIX_FMT_UYVY,
122 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
127 .desc = "YUV 4:2:0 PLANAR",
128 .pixelformat = V4L2_PIX_FMT_YUV420,
129 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
134 .desc = "YVU 4:2:0 PLANAR",
135 .pixelformat = V4L2_PIX_FMT_YVU420,
136 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
142 .pixelformat = V4L2_PIX_FMT_RGB444,
143 .mbus_code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE,
149 .pixelformat = V4L2_PIX_FMT_RGB565,
150 .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE,
155 .desc = "Raw RGB Bayer",
156 .pixelformat = V4L2_PIX_FMT_SBGGR8,
157 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
162 #define N_MCAM_FMTS ARRAY_SIZE(mcam_formats)
164 static struct mcam_format_struct *mcam_find_format(u32 pixelformat)
168 for (i = 0; i < N_MCAM_FMTS; i++)
169 if (mcam_formats[i].pixelformat == pixelformat)
170 return mcam_formats + i;
171 /* Not found? Then return the first format. */
176 * The default format we use until somebody says otherwise.
178 static const struct v4l2_pix_format mcam_def_pix_format = {
180 .height = VGA_HEIGHT,
181 .pixelformat = V4L2_PIX_FMT_YUYV,
182 .field = V4L2_FIELD_NONE,
183 .bytesperline = VGA_WIDTH*2,
184 .sizeimage = VGA_WIDTH*VGA_HEIGHT*2,
185 .colorspace = V4L2_COLORSPACE_SRGB,
188 static const u32 mcam_def_mbus_code = MEDIA_BUS_FMT_YUYV8_2X8;
192 * The two-word DMA descriptor format used by the Armada 610 and like. There
193 * Is a three-word format as well (set C1_DESC_3WORD) where the third
194 * word is a pointer to the next descriptor, but we don't use it. Two-word
195 * descriptors have to be contiguous in memory.
197 struct mcam_dma_desc {
203 * Our buffer type for working with videobuf2. Note that the vb2
204 * developers have decreed that struct vb2_buffer must be at the
205 * beginning of this structure.
207 struct mcam_vb_buffer {
208 struct vb2_buffer vb_buf;
209 struct list_head queue;
210 struct mcam_dma_desc *dma_desc; /* Descriptor virtual address */
211 dma_addr_t dma_desc_pa; /* Descriptor physical address */
212 int dma_desc_nent; /* Number of mapped descriptors */
215 static inline struct mcam_vb_buffer *vb_to_mvb(struct vb2_buffer *vb)
217 return container_of(vb, struct mcam_vb_buffer, vb_buf);
221 * Hand a completed buffer back to user space.
223 static void mcam_buffer_done(struct mcam_camera *cam, int frame,
224 struct vb2_buffer *vbuf)
226 vbuf->v4l2_buf.bytesused = cam->pix_format.sizeimage;
227 vbuf->v4l2_buf.sequence = cam->buf_seq[frame];
228 vbuf->v4l2_buf.field = V4L2_FIELD_NONE;
229 v4l2_get_timestamp(&vbuf->v4l2_buf.timestamp);
230 vb2_set_plane_payload(vbuf, 0, cam->pix_format.sizeimage);
231 vb2_buffer_done(vbuf, VB2_BUF_STATE_DONE);
237 * Debugging and related.
239 #define cam_err(cam, fmt, arg...) \
240 dev_err((cam)->dev, fmt, ##arg);
241 #define cam_warn(cam, fmt, arg...) \
242 dev_warn((cam)->dev, fmt, ##arg);
243 #define cam_dbg(cam, fmt, arg...) \
244 dev_dbg((cam)->dev, fmt, ##arg);
248 * Flag manipulation helpers
250 static void mcam_reset_buffers(struct mcam_camera *cam)
255 for (i = 0; i < cam->nbufs; i++) {
256 clear_bit(i, &cam->flags);
257 clear_bit(CF_FRAME_SOF0 + i, &cam->flags);
261 static inline int mcam_needs_config(struct mcam_camera *cam)
263 return test_bit(CF_CONFIG_NEEDED, &cam->flags);
266 static void mcam_set_config_needed(struct mcam_camera *cam, int needed)
269 set_bit(CF_CONFIG_NEEDED, &cam->flags);
271 clear_bit(CF_CONFIG_NEEDED, &cam->flags);
274 /* ------------------------------------------------------------------- */
276 * Make the controller start grabbing images. Everything must
277 * be set up before doing this.
279 static void mcam_ctlr_start(struct mcam_camera *cam)
281 /* set_bit performs a read, so no other barrier should be
283 mcam_reg_set_bit(cam, REG_CTRL0, C0_ENABLE);
286 static void mcam_ctlr_stop(struct mcam_camera *cam)
288 mcam_reg_clear_bit(cam, REG_CTRL0, C0_ENABLE);
291 static void mcam_enable_mipi(struct mcam_camera *mcam)
293 /* Using MIPI mode and enable MIPI */
294 cam_dbg(mcam, "camera: DPHY3=0x%x, DPHY5=0x%x, DPHY6=0x%x\n",
295 mcam->dphy[0], mcam->dphy[1], mcam->dphy[2]);
296 mcam_reg_write(mcam, REG_CSI2_DPHY3, mcam->dphy[0]);
297 mcam_reg_write(mcam, REG_CSI2_DPHY5, mcam->dphy[1]);
298 mcam_reg_write(mcam, REG_CSI2_DPHY6, mcam->dphy[2]);
300 if (!mcam->mipi_enabled) {
301 if (mcam->lane > 4 || mcam->lane <= 0) {
302 cam_warn(mcam, "lane number error\n");
303 mcam->lane = 1; /* set the default value */
306 * 0x41 actives 1 lane
307 * 0x43 actives 2 lanes
308 * 0x45 actives 3 lanes (never happen)
309 * 0x47 actives 4 lanes
311 mcam_reg_write(mcam, REG_CSI2_CTRL0,
312 CSI2_C0_MIPI_EN | CSI2_C0_ACT_LANE(mcam->lane));
313 mcam_reg_write(mcam, REG_CLKCTRL,
314 (mcam->mclk_src << 29) | mcam->mclk_div);
316 mcam->mipi_enabled = true;
320 static void mcam_disable_mipi(struct mcam_camera *mcam)
322 /* Using Parallel mode or disable MIPI */
323 mcam_reg_write(mcam, REG_CSI2_CTRL0, 0x0);
324 mcam_reg_write(mcam, REG_CSI2_DPHY3, 0x0);
325 mcam_reg_write(mcam, REG_CSI2_DPHY5, 0x0);
326 mcam_reg_write(mcam, REG_CSI2_DPHY6, 0x0);
327 mcam->mipi_enabled = false;
330 static bool mcam_fmt_is_planar(__u32 pfmt)
332 struct mcam_format_struct *f;
334 f = mcam_find_format(pfmt);
338 static void mcam_write_yuv_bases(struct mcam_camera *cam,
339 unsigned frame, dma_addr_t base)
341 struct v4l2_pix_format *fmt = &cam->pix_format;
342 u32 pixel_count = fmt->width * fmt->height;
343 dma_addr_t y, u = 0, v = 0;
347 switch (fmt->pixelformat) {
348 case V4L2_PIX_FMT_YUV420:
350 v = u + pixel_count / 4;
352 case V4L2_PIX_FMT_YVU420:
354 u = v + pixel_count / 4;
360 mcam_reg_write(cam, REG_Y0BAR + frame * 4, y);
361 if (mcam_fmt_is_planar(fmt->pixelformat)) {
362 mcam_reg_write(cam, REG_U0BAR + frame * 4, u);
363 mcam_reg_write(cam, REG_V0BAR + frame * 4, v);
367 /* ------------------------------------------------------------------- */
369 #ifdef MCAM_MODE_VMALLOC
371 * Code specific to the vmalloc buffer mode.
375 * Allocate in-kernel DMA buffers for vmalloc mode.
377 static int mcam_alloc_dma_bufs(struct mcam_camera *cam, int loadtime)
381 mcam_set_config_needed(cam, 1);
383 cam->dma_buf_size = dma_buf_size;
385 cam->dma_buf_size = cam->pix_format.sizeimage;
390 for (i = 0; i < n_dma_bufs; i++) {
391 cam->dma_bufs[i] = dma_alloc_coherent(cam->dev,
392 cam->dma_buf_size, cam->dma_handles + i,
394 if (cam->dma_bufs[i] == NULL) {
395 cam_warn(cam, "Failed to allocate DMA buffer\n");
401 switch (cam->nbufs) {
403 dma_free_coherent(cam->dev, cam->dma_buf_size,
404 cam->dma_bufs[0], cam->dma_handles[0]);
407 cam_err(cam, "Insufficient DMA buffers, cannot operate\n");
412 cam_warn(cam, "Will limp along with only 2 buffers\n");
418 static void mcam_free_dma_bufs(struct mcam_camera *cam)
422 for (i = 0; i < cam->nbufs; i++) {
423 dma_free_coherent(cam->dev, cam->dma_buf_size,
424 cam->dma_bufs[i], cam->dma_handles[i]);
425 cam->dma_bufs[i] = NULL;
432 * Set up DMA buffers when operating in vmalloc mode
434 static void mcam_ctlr_dma_vmalloc(struct mcam_camera *cam)
437 * Store the first two YUV buffers. Then either
438 * set the third if it exists, or tell the controller
441 mcam_write_yuv_bases(cam, 0, cam->dma_handles[0]);
442 mcam_write_yuv_bases(cam, 1, cam->dma_handles[1]);
443 if (cam->nbufs > 2) {
444 mcam_write_yuv_bases(cam, 2, cam->dma_handles[2]);
445 mcam_reg_clear_bit(cam, REG_CTRL1, C1_TWOBUFS);
447 mcam_reg_set_bit(cam, REG_CTRL1, C1_TWOBUFS);
448 if (cam->chip_id == MCAM_CAFE)
449 mcam_reg_write(cam, REG_UBAR, 0); /* 32 bits only */
453 * Copy data out to user space in the vmalloc case
455 static void mcam_frame_tasklet(unsigned long data)
457 struct mcam_camera *cam = (struct mcam_camera *) data;
460 struct mcam_vb_buffer *buf;
462 spin_lock_irqsave(&cam->dev_lock, flags);
463 for (i = 0; i < cam->nbufs; i++) {
464 int bufno = cam->next_buf;
466 if (cam->state != S_STREAMING || bufno < 0)
467 break; /* I/O got stopped */
468 if (++(cam->next_buf) >= cam->nbufs)
470 if (!test_bit(bufno, &cam->flags))
472 if (list_empty(&cam->buffers)) {
473 cam->frame_state.singles++;
474 break; /* Leave it valid, hope for better later */
476 cam->frame_state.delivered++;
477 clear_bit(bufno, &cam->flags);
478 buf = list_first_entry(&cam->buffers, struct mcam_vb_buffer,
480 list_del_init(&buf->queue);
482 * Drop the lock during the big copy. This *should* be safe...
484 spin_unlock_irqrestore(&cam->dev_lock, flags);
485 memcpy(vb2_plane_vaddr(&buf->vb_buf, 0), cam->dma_bufs[bufno],
486 cam->pix_format.sizeimage);
487 mcam_buffer_done(cam, bufno, &buf->vb_buf);
488 spin_lock_irqsave(&cam->dev_lock, flags);
490 spin_unlock_irqrestore(&cam->dev_lock, flags);
495 * Make sure our allocated buffers are up to the task.
497 static int mcam_check_dma_buffers(struct mcam_camera *cam)
499 if (cam->nbufs > 0 && cam->dma_buf_size < cam->pix_format.sizeimage)
500 mcam_free_dma_bufs(cam);
502 return mcam_alloc_dma_bufs(cam, 0);
506 static void mcam_vmalloc_done(struct mcam_camera *cam, int frame)
508 tasklet_schedule(&cam->s_tasklet);
511 #else /* MCAM_MODE_VMALLOC */
513 static inline int mcam_alloc_dma_bufs(struct mcam_camera *cam, int loadtime)
518 static inline void mcam_free_dma_bufs(struct mcam_camera *cam)
523 static inline int mcam_check_dma_buffers(struct mcam_camera *cam)
530 #endif /* MCAM_MODE_VMALLOC */
533 #ifdef MCAM_MODE_DMA_CONTIG
534 /* ---------------------------------------------------------------------- */
536 * DMA-contiguous code.
540 * Set up a contiguous buffer for the given frame. Here also is where
541 * the underrun strategy is set: if there is no buffer available, reuse
542 * the buffer from the other BAR and set the CF_SINGLE_BUFFER flag to
543 * keep the interrupt handler from giving that buffer back to user
544 * space. In this way, we always have a buffer to DMA to and don't
545 * have to try to play games stopping and restarting the controller.
547 static void mcam_set_contig_buffer(struct mcam_camera *cam, int frame)
549 struct mcam_vb_buffer *buf;
550 dma_addr_t dma_handle;
551 struct vb2_buffer *vb;
554 * If there are no available buffers, go into single mode
556 if (list_empty(&cam->buffers)) {
557 buf = cam->vb_bufs[frame ^ 0x1];
558 set_bit(CF_SINGLE_BUFFER, &cam->flags);
559 cam->frame_state.singles++;
562 * OK, we have a buffer we can use.
564 buf = list_first_entry(&cam->buffers, struct mcam_vb_buffer,
566 list_del_init(&buf->queue);
567 clear_bit(CF_SINGLE_BUFFER, &cam->flags);
570 cam->vb_bufs[frame] = buf;
573 dma_handle = vb2_dma_contig_plane_dma_addr(vb, 0);
574 mcam_write_yuv_bases(cam, frame, dma_handle);
578 * Initial B_DMA_contig setup.
580 static void mcam_ctlr_dma_contig(struct mcam_camera *cam)
582 mcam_reg_set_bit(cam, REG_CTRL1, C1_TWOBUFS);
584 mcam_set_contig_buffer(cam, 0);
585 mcam_set_contig_buffer(cam, 1);
589 * Frame completion handling.
591 static void mcam_dma_contig_done(struct mcam_camera *cam, int frame)
593 struct mcam_vb_buffer *buf = cam->vb_bufs[frame];
595 if (!test_bit(CF_SINGLE_BUFFER, &cam->flags)) {
596 cam->frame_state.delivered++;
597 cam->vb_bufs[frame] = NULL;
598 mcam_buffer_done(cam, frame, &buf->vb_buf);
600 mcam_set_contig_buffer(cam, frame);
603 #endif /* MCAM_MODE_DMA_CONTIG */
605 #ifdef MCAM_MODE_DMA_SG
606 /* ---------------------------------------------------------------------- */
608 * Scatter/gather-specific code.
612 * Set up the next buffer for S/G I/O; caller should be sure that
613 * the controller is stopped and a buffer is available.
615 static void mcam_sg_next_buffer(struct mcam_camera *cam)
617 struct mcam_vb_buffer *buf;
619 buf = list_first_entry(&cam->buffers, struct mcam_vb_buffer, queue);
620 list_del_init(&buf->queue);
622 * Very Bad Not Good Things happen if you don't clear
623 * C1_DESC_ENA before making any descriptor changes.
625 mcam_reg_clear_bit(cam, REG_CTRL1, C1_DESC_ENA);
626 mcam_reg_write(cam, REG_DMA_DESC_Y, buf->dma_desc_pa);
627 mcam_reg_write(cam, REG_DESC_LEN_Y,
628 buf->dma_desc_nent*sizeof(struct mcam_dma_desc));
629 mcam_reg_write(cam, REG_DESC_LEN_U, 0);
630 mcam_reg_write(cam, REG_DESC_LEN_V, 0);
631 mcam_reg_set_bit(cam, REG_CTRL1, C1_DESC_ENA);
632 cam->vb_bufs[0] = buf;
636 * Initial B_DMA_sg setup
638 static void mcam_ctlr_dma_sg(struct mcam_camera *cam)
641 * The list-empty condition can hit us at resume time
642 * if the buffer list was empty when the system was suspended.
644 if (list_empty(&cam->buffers)) {
645 set_bit(CF_SG_RESTART, &cam->flags);
649 mcam_reg_clear_bit(cam, REG_CTRL1, C1_DESC_3WORD);
650 mcam_sg_next_buffer(cam);
656 * Frame completion with S/G is trickier. We can't muck with
657 * a descriptor chain on the fly, since the controller buffers it
658 * internally. So we have to actually stop and restart; Marvell
659 * says this is the way to do it.
661 * Of course, stopping is easier said than done; experience shows
662 * that the controller can start a frame *after* C0_ENABLE has been
663 * cleared. So when running in S/G mode, the controller is "stopped"
664 * on receipt of the start-of-frame interrupt. That means we can
665 * safely change the DMA descriptor array here and restart things
666 * (assuming there's another buffer waiting to go).
668 static void mcam_dma_sg_done(struct mcam_camera *cam, int frame)
670 struct mcam_vb_buffer *buf = cam->vb_bufs[0];
673 * If we're no longer supposed to be streaming, don't do anything.
675 if (cam->state != S_STREAMING)
678 * If we have another buffer available, put it in and
679 * restart the engine.
681 if (!list_empty(&cam->buffers)) {
682 mcam_sg_next_buffer(cam);
683 mcam_ctlr_start(cam);
685 * Otherwise set CF_SG_RESTART and the controller will
686 * be restarted once another buffer shows up.
689 set_bit(CF_SG_RESTART, &cam->flags);
690 cam->frame_state.singles++;
691 cam->vb_bufs[0] = NULL;
694 * Now we can give the completed frame back to user space.
696 cam->frame_state.delivered++;
697 mcam_buffer_done(cam, frame, &buf->vb_buf);
702 * Scatter/gather mode requires stopping the controller between
703 * frames so we can put in a new DMA descriptor array. If no new
704 * buffer exists at frame completion, the controller is left stopped;
705 * this function is charged with gettig things going again.
707 static void mcam_sg_restart(struct mcam_camera *cam)
709 mcam_ctlr_dma_sg(cam);
710 mcam_ctlr_start(cam);
711 clear_bit(CF_SG_RESTART, &cam->flags);
714 #else /* MCAM_MODE_DMA_SG */
716 static inline void mcam_sg_restart(struct mcam_camera *cam)
721 #endif /* MCAM_MODE_DMA_SG */
723 /* ---------------------------------------------------------------------- */
725 * Buffer-mode-independent controller code.
731 static void mcam_ctlr_image(struct mcam_camera *cam)
733 struct v4l2_pix_format *fmt = &cam->pix_format;
734 u32 widthy = 0, widthuv = 0, imgsz_h, imgsz_w;
736 cam_dbg(cam, "camera: bytesperline = %d; height = %d\n",
737 fmt->bytesperline, fmt->sizeimage / fmt->bytesperline);
738 imgsz_h = (fmt->height << IMGSZ_V_SHIFT) & IMGSZ_V_MASK;
739 imgsz_w = (fmt->width * 2) & IMGSZ_H_MASK;
741 switch (fmt->pixelformat) {
742 case V4L2_PIX_FMT_YUYV:
743 case V4L2_PIX_FMT_UYVY:
744 widthy = fmt->width * 2;
747 case V4L2_PIX_FMT_YUV420:
748 case V4L2_PIX_FMT_YVU420:
750 widthuv = fmt->width / 2;
753 widthy = fmt->bytesperline;
758 mcam_reg_write_mask(cam, REG_IMGPITCH, widthuv << 16 | widthy,
759 IMGP_YP_MASK | IMGP_UVP_MASK);
760 mcam_reg_write(cam, REG_IMGSIZE, imgsz_h | imgsz_w);
761 mcam_reg_write(cam, REG_IMGOFFSET, 0x0);
764 * Tell the controller about the image format we are using.
766 switch (fmt->pixelformat) {
767 case V4L2_PIX_FMT_YUV420:
768 case V4L2_PIX_FMT_YVU420:
769 mcam_reg_write_mask(cam, REG_CTRL0,
770 C0_DF_YUV | C0_YUV_420PL | C0_YUVE_YVYU, C0_DF_MASK);
772 case V4L2_PIX_FMT_YUYV:
773 mcam_reg_write_mask(cam, REG_CTRL0,
774 C0_DF_YUV | C0_YUV_PACKED | C0_YUVE_UYVY, C0_DF_MASK);
776 case V4L2_PIX_FMT_UYVY:
777 mcam_reg_write_mask(cam, REG_CTRL0,
778 C0_DF_YUV | C0_YUV_PACKED | C0_YUVE_YUYV, C0_DF_MASK);
780 case V4L2_PIX_FMT_RGB444:
781 mcam_reg_write_mask(cam, REG_CTRL0,
782 C0_DF_RGB | C0_RGBF_444 | C0_RGB4_XRGB, C0_DF_MASK);
785 case V4L2_PIX_FMT_RGB565:
786 mcam_reg_write_mask(cam, REG_CTRL0,
787 C0_DF_RGB | C0_RGBF_565 | C0_RGB5_BGGR, C0_DF_MASK);
789 case V4L2_PIX_FMT_SBGGR8:
790 mcam_reg_write_mask(cam, REG_CTRL0,
791 C0_DF_RGB | C0_RGB5_GRBG, C0_DF_MASK);
794 cam_err(cam, "camera: unknown format: %#x\n", fmt->pixelformat);
799 * Make sure it knows we want to use hsync/vsync.
801 mcam_reg_write_mask(cam, REG_CTRL0, C0_SIF_HVSYNC, C0_SIFM_MASK);
803 * This field controls the generation of EOF(DVP only)
805 if (cam->bus_type != V4L2_MBUS_CSI2)
806 mcam_reg_set_bit(cam, REG_CTRL0,
807 C0_EOF_VSYNC | C0_VEDGE_CTRL);
812 * Configure the controller for operation; caller holds the
815 static int mcam_ctlr_configure(struct mcam_camera *cam)
819 spin_lock_irqsave(&cam->dev_lock, flags);
820 clear_bit(CF_SG_RESTART, &cam->flags);
822 mcam_ctlr_image(cam);
823 mcam_set_config_needed(cam, 0);
824 spin_unlock_irqrestore(&cam->dev_lock, flags);
828 static void mcam_ctlr_irq_enable(struct mcam_camera *cam)
831 * Clear any pending interrupts, since we do not
832 * expect to have I/O active prior to enabling.
834 mcam_reg_write(cam, REG_IRQSTAT, FRAMEIRQS);
835 mcam_reg_set_bit(cam, REG_IRQMASK, FRAMEIRQS);
838 static void mcam_ctlr_irq_disable(struct mcam_camera *cam)
840 mcam_reg_clear_bit(cam, REG_IRQMASK, FRAMEIRQS);
845 static void mcam_ctlr_init(struct mcam_camera *cam)
849 spin_lock_irqsave(&cam->dev_lock, flags);
851 * Make sure it's not powered down.
853 mcam_reg_clear_bit(cam, REG_CTRL1, C1_PWRDWN);
855 * Turn off the enable bit. It sure should be off anyway,
856 * but it's good to be sure.
858 mcam_reg_clear_bit(cam, REG_CTRL0, C0_ENABLE);
860 * Clock the sensor appropriately. Controller clock should
861 * be 48MHz, sensor "typical" value is half that.
863 mcam_reg_write_mask(cam, REG_CLKCTRL, 2, CLK_DIV_MASK);
864 spin_unlock_irqrestore(&cam->dev_lock, flags);
869 * Stop the controller, and don't return until we're really sure that no
870 * further DMA is going on.
872 static void mcam_ctlr_stop_dma(struct mcam_camera *cam)
877 * Theory: stop the camera controller (whether it is operating
878 * or not). Delay briefly just in case we race with the SOF
879 * interrupt, then wait until no DMA is active.
881 spin_lock_irqsave(&cam->dev_lock, flags);
882 clear_bit(CF_SG_RESTART, &cam->flags);
885 spin_unlock_irqrestore(&cam->dev_lock, flags);
887 * This is a brutally long sleep, but experience shows that
888 * it can take the controller a while to get the message that
889 * it needs to stop grabbing frames. In particular, we can
890 * sometimes (on mmp) get a frame at the end WITHOUT the
891 * start-of-frame indication.
894 if (test_bit(CF_DMA_ACTIVE, &cam->flags))
895 cam_err(cam, "Timeout waiting for DMA to end\n");
896 /* This would be bad news - what now? */
897 spin_lock_irqsave(&cam->dev_lock, flags);
898 mcam_ctlr_irq_disable(cam);
899 spin_unlock_irqrestore(&cam->dev_lock, flags);
905 static int mcam_ctlr_power_up(struct mcam_camera *cam)
910 spin_lock_irqsave(&cam->dev_lock, flags);
911 ret = cam->plat_power_up(cam);
913 spin_unlock_irqrestore(&cam->dev_lock, flags);
916 mcam_reg_clear_bit(cam, REG_CTRL1, C1_PWRDWN);
917 spin_unlock_irqrestore(&cam->dev_lock, flags);
918 msleep(5); /* Just to be sure */
922 static void mcam_ctlr_power_down(struct mcam_camera *cam)
926 spin_lock_irqsave(&cam->dev_lock, flags);
928 * School of hard knocks department: be sure we do any register
929 * twiddling on the controller *before* calling the platform
930 * power down routine.
932 mcam_reg_set_bit(cam, REG_CTRL1, C1_PWRDWN);
933 cam->plat_power_down(cam);
934 spin_unlock_irqrestore(&cam->dev_lock, flags);
937 /* -------------------------------------------------------------------- */
939 * Communications with the sensor.
942 static int __mcam_cam_reset(struct mcam_camera *cam)
944 return sensor_call(cam, core, reset, 0);
948 * We have found the sensor on the i2c. Let's try to have a
951 static int mcam_cam_init(struct mcam_camera *cam)
955 if (cam->state != S_NOTREADY)
956 cam_warn(cam, "Cam init with device in funky state %d",
958 ret = __mcam_cam_reset(cam);
959 /* Get/set parameters? */
961 mcam_ctlr_power_down(cam);
966 * Configure the sensor to match the parameters we have. Caller should
969 static int mcam_cam_set_flip(struct mcam_camera *cam)
971 struct v4l2_control ctrl;
973 memset(&ctrl, 0, sizeof(ctrl));
974 ctrl.id = V4L2_CID_VFLIP;
976 return sensor_call(cam, core, s_ctrl, &ctrl);
980 static int mcam_cam_configure(struct mcam_camera *cam)
982 struct v4l2_mbus_framefmt mbus_fmt;
985 v4l2_fill_mbus_format(&mbus_fmt, &cam->pix_format, cam->mbus_code);
986 ret = sensor_call(cam, core, init, 0);
988 ret = sensor_call(cam, video, s_mbus_fmt, &mbus_fmt);
990 * OV7670 does weird things if flip is set *before* format...
992 ret += mcam_cam_set_flip(cam);
997 * Get everything ready, and start grabbing frames.
999 static int mcam_read_setup(struct mcam_camera *cam)
1002 unsigned long flags;
1005 * Configuration. If we still don't have DMA buffers,
1006 * make one last, desperate attempt.
1008 if (cam->buffer_mode == B_vmalloc && cam->nbufs == 0 &&
1009 mcam_alloc_dma_bufs(cam, 0))
1012 if (mcam_needs_config(cam)) {
1013 mcam_cam_configure(cam);
1014 ret = mcam_ctlr_configure(cam);
1022 spin_lock_irqsave(&cam->dev_lock, flags);
1023 clear_bit(CF_DMA_ACTIVE, &cam->flags);
1024 mcam_reset_buffers(cam);
1026 * Update CSI2_DPHY value
1029 cam->calc_dphy(cam);
1030 cam_dbg(cam, "camera: DPHY sets: dphy3=0x%x, dphy5=0x%x, dphy6=0x%x\n",
1031 cam->dphy[0], cam->dphy[1], cam->dphy[2]);
1032 if (cam->bus_type == V4L2_MBUS_CSI2)
1033 mcam_enable_mipi(cam);
1035 mcam_disable_mipi(cam);
1036 mcam_ctlr_irq_enable(cam);
1037 cam->state = S_STREAMING;
1038 if (!test_bit(CF_SG_RESTART, &cam->flags))
1039 mcam_ctlr_start(cam);
1040 spin_unlock_irqrestore(&cam->dev_lock, flags);
1044 /* ----------------------------------------------------------------------- */
1046 * Videobuf2 interface code.
1049 static int mcam_vb_queue_setup(struct vb2_queue *vq,
1050 const struct v4l2_format *fmt, unsigned int *nbufs,
1051 unsigned int *num_planes, unsigned int sizes[],
1054 struct mcam_camera *cam = vb2_get_drv_priv(vq);
1055 int minbufs = (cam->buffer_mode == B_DMA_contig) ? 3 : 2;
1057 if (fmt && fmt->fmt.pix.sizeimage < cam->pix_format.sizeimage)
1059 sizes[0] = fmt ? fmt->fmt.pix.sizeimage : cam->pix_format.sizeimage;
1060 *num_planes = 1; /* Someday we have to support planar formats... */
1061 if (*nbufs < minbufs)
1063 if (cam->buffer_mode == B_DMA_contig)
1064 alloc_ctxs[0] = cam->vb_alloc_ctx;
1065 else if (cam->buffer_mode == B_DMA_sg)
1066 alloc_ctxs[0] = cam->vb_alloc_ctx_sg;
1071 static void mcam_vb_buf_queue(struct vb2_buffer *vb)
1073 struct mcam_vb_buffer *mvb = vb_to_mvb(vb);
1074 struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
1075 unsigned long flags;
1078 spin_lock_irqsave(&cam->dev_lock, flags);
1079 start = (cam->state == S_BUFWAIT) && !list_empty(&cam->buffers);
1080 list_add(&mvb->queue, &cam->buffers);
1081 if (cam->state == S_STREAMING && test_bit(CF_SG_RESTART, &cam->flags))
1082 mcam_sg_restart(cam);
1083 spin_unlock_irqrestore(&cam->dev_lock, flags);
1085 mcam_read_setup(cam);
1088 static void mcam_vb_requeue_bufs(struct vb2_queue *vq,
1089 enum vb2_buffer_state state)
1091 struct mcam_camera *cam = vb2_get_drv_priv(vq);
1092 struct mcam_vb_buffer *buf, *node;
1093 unsigned long flags;
1096 spin_lock_irqsave(&cam->dev_lock, flags);
1097 list_for_each_entry_safe(buf, node, &cam->buffers, queue) {
1098 vb2_buffer_done(&buf->vb_buf, state);
1099 list_del(&buf->queue);
1101 for (i = 0; i < MAX_DMA_BUFS; i++) {
1102 buf = cam->vb_bufs[i];
1105 vb2_buffer_done(&buf->vb_buf, state);
1106 cam->vb_bufs[i] = NULL;
1109 spin_unlock_irqrestore(&cam->dev_lock, flags);
1113 * These need to be called with the mutex held from vb2
1115 static int mcam_vb_start_streaming(struct vb2_queue *vq, unsigned int count)
1117 struct mcam_camera *cam = vb2_get_drv_priv(vq);
1121 if (cam->state != S_IDLE) {
1122 mcam_vb_requeue_bufs(vq, VB2_BUF_STATE_QUEUED);
1125 cam->frame_state.frames = 0;
1126 cam->frame_state.singles = 0;
1127 cam->frame_state.delivered = 0;
1130 * Videobuf2 sneakily hoards all the buffers and won't
1131 * give them to us until *after* streaming starts. But
1132 * we can't actually start streaming until we have a
1133 * destination. So go into a wait state and hope they
1134 * give us buffers soon.
1136 if (cam->buffer_mode != B_vmalloc && list_empty(&cam->buffers)) {
1137 cam->state = S_BUFWAIT;
1142 * Ensure clear the left over frame flags
1143 * before every really start streaming
1145 for (frame = 0; frame < cam->nbufs; frame++)
1146 clear_bit(CF_FRAME_SOF0 + frame, &cam->flags);
1148 ret = mcam_read_setup(cam);
1150 mcam_vb_requeue_bufs(vq, VB2_BUF_STATE_QUEUED);
1154 static void mcam_vb_stop_streaming(struct vb2_queue *vq)
1156 struct mcam_camera *cam = vb2_get_drv_priv(vq);
1158 cam_dbg(cam, "stop_streaming: %d frames, %d singles, %d delivered\n",
1159 cam->frame_state.frames, cam->frame_state.singles,
1160 cam->frame_state.delivered);
1161 if (cam->state == S_BUFWAIT) {
1162 /* They never gave us buffers */
1163 cam->state = S_IDLE;
1166 if (cam->state != S_STREAMING)
1168 mcam_ctlr_stop_dma(cam);
1170 * Reset the CCIC PHY after stopping streaming,
1171 * otherwise, the CCIC may be unstable.
1173 if (cam->ctlr_reset)
1174 cam->ctlr_reset(cam);
1176 * VB2 reclaims the buffers, so we need to forget
1179 mcam_vb_requeue_bufs(vq, VB2_BUF_STATE_ERROR);
1183 static const struct vb2_ops mcam_vb2_ops = {
1184 .queue_setup = mcam_vb_queue_setup,
1185 .buf_queue = mcam_vb_buf_queue,
1186 .start_streaming = mcam_vb_start_streaming,
1187 .stop_streaming = mcam_vb_stop_streaming,
1188 .wait_prepare = vb2_ops_wait_prepare,
1189 .wait_finish = vb2_ops_wait_finish,
1193 #ifdef MCAM_MODE_DMA_SG
1195 * Scatter/gather mode uses all of the above functions plus a
1196 * few extras to deal with DMA mapping.
1198 static int mcam_vb_sg_buf_init(struct vb2_buffer *vb)
1200 struct mcam_vb_buffer *mvb = vb_to_mvb(vb);
1201 struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
1202 int ndesc = cam->pix_format.sizeimage/PAGE_SIZE + 1;
1204 mvb->dma_desc = dma_alloc_coherent(cam->dev,
1205 ndesc * sizeof(struct mcam_dma_desc),
1206 &mvb->dma_desc_pa, GFP_KERNEL);
1207 if (mvb->dma_desc == NULL) {
1208 cam_err(cam, "Unable to get DMA descriptor array\n");
1214 static int mcam_vb_sg_buf_prepare(struct vb2_buffer *vb)
1216 struct mcam_vb_buffer *mvb = vb_to_mvb(vb);
1217 struct sg_table *sg_table = vb2_dma_sg_plane_desc(vb, 0);
1218 struct mcam_dma_desc *desc = mvb->dma_desc;
1219 struct scatterlist *sg;
1222 for_each_sg(sg_table->sgl, sg, sg_table->nents, i) {
1223 desc->dma_addr = sg_dma_address(sg);
1224 desc->segment_len = sg_dma_len(sg);
1230 static void mcam_vb_sg_buf_cleanup(struct vb2_buffer *vb)
1232 struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
1233 struct mcam_vb_buffer *mvb = vb_to_mvb(vb);
1234 int ndesc = cam->pix_format.sizeimage/PAGE_SIZE + 1;
1236 dma_free_coherent(cam->dev, ndesc * sizeof(struct mcam_dma_desc),
1237 mvb->dma_desc, mvb->dma_desc_pa);
1241 static const struct vb2_ops mcam_vb2_sg_ops = {
1242 .queue_setup = mcam_vb_queue_setup,
1243 .buf_init = mcam_vb_sg_buf_init,
1244 .buf_prepare = mcam_vb_sg_buf_prepare,
1245 .buf_queue = mcam_vb_buf_queue,
1246 .buf_cleanup = mcam_vb_sg_buf_cleanup,
1247 .start_streaming = mcam_vb_start_streaming,
1248 .stop_streaming = mcam_vb_stop_streaming,
1249 .wait_prepare = vb2_ops_wait_prepare,
1250 .wait_finish = vb2_ops_wait_finish,
1253 #endif /* MCAM_MODE_DMA_SG */
1255 static int mcam_setup_vb2(struct mcam_camera *cam)
1257 struct vb2_queue *vq = &cam->vb_queue;
1259 memset(vq, 0, sizeof(*vq));
1260 vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1262 vq->lock = &cam->s_mutex;
1263 vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1264 vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;
1265 vq->buf_struct_size = sizeof(struct mcam_vb_buffer);
1266 INIT_LIST_HEAD(&cam->buffers);
1267 switch (cam->buffer_mode) {
1269 #ifdef MCAM_MODE_DMA_CONTIG
1270 vq->ops = &mcam_vb2_ops;
1271 vq->mem_ops = &vb2_dma_contig_memops;
1272 cam->dma_setup = mcam_ctlr_dma_contig;
1273 cam->frame_complete = mcam_dma_contig_done;
1274 cam->vb_alloc_ctx = vb2_dma_contig_init_ctx(cam->dev);
1275 if (IS_ERR(cam->vb_alloc_ctx))
1276 return PTR_ERR(cam->vb_alloc_ctx);
1280 #ifdef MCAM_MODE_DMA_SG
1281 vq->ops = &mcam_vb2_sg_ops;
1282 vq->mem_ops = &vb2_dma_sg_memops;
1283 cam->dma_setup = mcam_ctlr_dma_sg;
1284 cam->frame_complete = mcam_dma_sg_done;
1285 cam->vb_alloc_ctx_sg = vb2_dma_sg_init_ctx(cam->dev);
1286 if (IS_ERR(cam->vb_alloc_ctx_sg))
1287 return PTR_ERR(cam->vb_alloc_ctx_sg);
1291 #ifdef MCAM_MODE_VMALLOC
1292 tasklet_init(&cam->s_tasklet, mcam_frame_tasklet,
1293 (unsigned long) cam);
1294 vq->ops = &mcam_vb2_ops;
1295 vq->mem_ops = &vb2_vmalloc_memops;
1296 cam->dma_setup = mcam_ctlr_dma_vmalloc;
1297 cam->frame_complete = mcam_vmalloc_done;
1301 return vb2_queue_init(vq);
1304 static void mcam_cleanup_vb2(struct mcam_camera *cam)
1306 #ifdef MCAM_MODE_DMA_CONTIG
1307 if (cam->buffer_mode == B_DMA_contig)
1308 vb2_dma_contig_cleanup_ctx(cam->vb_alloc_ctx);
1310 #ifdef MCAM_MODE_DMA_SG
1311 if (cam->buffer_mode == B_DMA_sg)
1312 vb2_dma_sg_cleanup_ctx(cam->vb_alloc_ctx_sg);
1317 /* ---------------------------------------------------------------------- */
1319 * The long list of V4L2 ioctl() operations.
1322 static int mcam_vidioc_querycap(struct file *file, void *priv,
1323 struct v4l2_capability *cap)
1325 struct mcam_camera *cam = video_drvdata(file);
1327 strcpy(cap->driver, "marvell_ccic");
1328 strcpy(cap->card, "marvell_ccic");
1329 strlcpy(cap->bus_info, cam->bus_info, sizeof(cap->bus_info));
1330 cap->device_caps = V4L2_CAP_VIDEO_CAPTURE |
1331 V4L2_CAP_READWRITE | V4L2_CAP_STREAMING;
1332 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
1337 static int mcam_vidioc_enum_fmt_vid_cap(struct file *filp,
1338 void *priv, struct v4l2_fmtdesc *fmt)
1340 if (fmt->index >= N_MCAM_FMTS)
1342 strlcpy(fmt->description, mcam_formats[fmt->index].desc,
1343 sizeof(fmt->description));
1344 fmt->pixelformat = mcam_formats[fmt->index].pixelformat;
1348 static int mcam_vidioc_try_fmt_vid_cap(struct file *filp, void *priv,
1349 struct v4l2_format *fmt)
1351 struct mcam_camera *cam = video_drvdata(filp);
1352 struct mcam_format_struct *f;
1353 struct v4l2_pix_format *pix = &fmt->fmt.pix;
1354 struct v4l2_subdev_pad_config pad_cfg;
1355 struct v4l2_subdev_format format = {
1356 .which = V4L2_SUBDEV_FORMAT_TRY,
1360 f = mcam_find_format(pix->pixelformat);
1361 pix->pixelformat = f->pixelformat;
1362 v4l2_fill_mbus_format(&format.format, pix, f->mbus_code);
1363 ret = sensor_call(cam, pad, set_fmt, &pad_cfg, &format);
1364 v4l2_fill_pix_format(pix, &format.format);
1365 pix->bytesperline = pix->width * f->bpp;
1366 switch (f->pixelformat) {
1367 case V4L2_PIX_FMT_YUV420:
1368 case V4L2_PIX_FMT_YVU420:
1369 pix->sizeimage = pix->height * pix->bytesperline * 3 / 2;
1372 pix->sizeimage = pix->height * pix->bytesperline;
1375 pix->colorspace = V4L2_COLORSPACE_SRGB;
1379 static int mcam_vidioc_s_fmt_vid_cap(struct file *filp, void *priv,
1380 struct v4l2_format *fmt)
1382 struct mcam_camera *cam = video_drvdata(filp);
1383 struct mcam_format_struct *f;
1387 * Can't do anything if the device is not idle
1388 * Also can't if there are streaming buffers in place.
1390 if (cam->state != S_IDLE || vb2_is_busy(&cam->vb_queue))
1393 f = mcam_find_format(fmt->fmt.pix.pixelformat);
1396 * See if the formatting works in principle.
1398 ret = mcam_vidioc_try_fmt_vid_cap(filp, priv, fmt);
1402 * Now we start to change things for real, so let's do it
1405 cam->pix_format = fmt->fmt.pix;
1406 cam->mbus_code = f->mbus_code;
1409 * Make sure we have appropriate DMA buffers.
1411 if (cam->buffer_mode == B_vmalloc) {
1412 ret = mcam_check_dma_buffers(cam);
1416 mcam_set_config_needed(cam, 1);
1422 * Return our stored notion of how the camera is/should be configured.
1423 * The V4l2 spec wants us to be smarter, and actually get this from
1424 * the camera (and not mess with it at open time). Someday.
1426 static int mcam_vidioc_g_fmt_vid_cap(struct file *filp, void *priv,
1427 struct v4l2_format *f)
1429 struct mcam_camera *cam = video_drvdata(filp);
1431 f->fmt.pix = cam->pix_format;
1436 * We only have one input - the sensor - so minimize the nonsense here.
1438 static int mcam_vidioc_enum_input(struct file *filp, void *priv,
1439 struct v4l2_input *input)
1441 if (input->index != 0)
1444 input->type = V4L2_INPUT_TYPE_CAMERA;
1445 strcpy(input->name, "Camera");
1449 static int mcam_vidioc_g_input(struct file *filp, void *priv, unsigned int *i)
1455 static int mcam_vidioc_s_input(struct file *filp, void *priv, unsigned int i)
1463 * G/S_PARM. Most of this is done by the sensor, but we are
1464 * the level which controls the number of read buffers.
1466 static int mcam_vidioc_g_parm(struct file *filp, void *priv,
1467 struct v4l2_streamparm *parms)
1469 struct mcam_camera *cam = video_drvdata(filp);
1472 ret = sensor_call(cam, video, g_parm, parms);
1473 parms->parm.capture.readbuffers = n_dma_bufs;
1477 static int mcam_vidioc_s_parm(struct file *filp, void *priv,
1478 struct v4l2_streamparm *parms)
1480 struct mcam_camera *cam = video_drvdata(filp);
1483 ret = sensor_call(cam, video, s_parm, parms);
1484 parms->parm.capture.readbuffers = n_dma_bufs;
1488 static int mcam_vidioc_enum_framesizes(struct file *filp, void *priv,
1489 struct v4l2_frmsizeenum *sizes)
1491 struct mcam_camera *cam = video_drvdata(filp);
1492 struct mcam_format_struct *f;
1493 struct v4l2_subdev_frame_size_enum fse = {
1494 .index = sizes->index,
1495 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1499 f = mcam_find_format(sizes->pixel_format);
1500 if (f->pixelformat != sizes->pixel_format)
1502 fse.code = f->mbus_code;
1503 ret = sensor_call(cam, pad, enum_frame_size, NULL, &fse);
1506 if (fse.min_width == fse.max_width &&
1507 fse.min_height == fse.max_height) {
1508 sizes->type = V4L2_FRMSIZE_TYPE_DISCRETE;
1509 sizes->discrete.width = fse.min_width;
1510 sizes->discrete.height = fse.min_height;
1513 sizes->type = V4L2_FRMSIZE_TYPE_CONTINUOUS;
1514 sizes->stepwise.min_width = fse.min_width;
1515 sizes->stepwise.max_width = fse.max_width;
1516 sizes->stepwise.min_height = fse.min_height;
1517 sizes->stepwise.max_height = fse.max_height;
1518 sizes->stepwise.step_width = 1;
1519 sizes->stepwise.step_height = 1;
1523 static int mcam_vidioc_enum_frameintervals(struct file *filp, void *priv,
1524 struct v4l2_frmivalenum *interval)
1526 struct mcam_camera *cam = video_drvdata(filp);
1527 struct mcam_format_struct *f;
1528 struct v4l2_subdev_frame_interval_enum fie = {
1529 .index = interval->index,
1530 .width = interval->width,
1531 .height = interval->height,
1532 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1536 f = mcam_find_format(interval->pixel_format);
1537 if (f->pixelformat != interval->pixel_format)
1539 fie.code = f->mbus_code;
1540 ret = sensor_call(cam, pad, enum_frame_interval, NULL, &fie);
1543 interval->type = V4L2_FRMIVAL_TYPE_DISCRETE;
1544 interval->discrete = fie.interval;
1548 #ifdef CONFIG_VIDEO_ADV_DEBUG
1549 static int mcam_vidioc_g_register(struct file *file, void *priv,
1550 struct v4l2_dbg_register *reg)
1552 struct mcam_camera *cam = video_drvdata(file);
1554 if (reg->reg > cam->regs_size - 4)
1556 reg->val = mcam_reg_read(cam, reg->reg);
1561 static int mcam_vidioc_s_register(struct file *file, void *priv,
1562 const struct v4l2_dbg_register *reg)
1564 struct mcam_camera *cam = video_drvdata(file);
1566 if (reg->reg > cam->regs_size - 4)
1568 mcam_reg_write(cam, reg->reg, reg->val);
1573 static const struct v4l2_ioctl_ops mcam_v4l_ioctl_ops = {
1574 .vidioc_querycap = mcam_vidioc_querycap,
1575 .vidioc_enum_fmt_vid_cap = mcam_vidioc_enum_fmt_vid_cap,
1576 .vidioc_try_fmt_vid_cap = mcam_vidioc_try_fmt_vid_cap,
1577 .vidioc_s_fmt_vid_cap = mcam_vidioc_s_fmt_vid_cap,
1578 .vidioc_g_fmt_vid_cap = mcam_vidioc_g_fmt_vid_cap,
1579 .vidioc_enum_input = mcam_vidioc_enum_input,
1580 .vidioc_g_input = mcam_vidioc_g_input,
1581 .vidioc_s_input = mcam_vidioc_s_input,
1582 .vidioc_reqbufs = vb2_ioctl_reqbufs,
1583 .vidioc_create_bufs = vb2_ioctl_create_bufs,
1584 .vidioc_querybuf = vb2_ioctl_querybuf,
1585 .vidioc_qbuf = vb2_ioctl_qbuf,
1586 .vidioc_dqbuf = vb2_ioctl_dqbuf,
1587 .vidioc_expbuf = vb2_ioctl_expbuf,
1588 .vidioc_streamon = vb2_ioctl_streamon,
1589 .vidioc_streamoff = vb2_ioctl_streamoff,
1590 .vidioc_g_parm = mcam_vidioc_g_parm,
1591 .vidioc_s_parm = mcam_vidioc_s_parm,
1592 .vidioc_enum_framesizes = mcam_vidioc_enum_framesizes,
1593 .vidioc_enum_frameintervals = mcam_vidioc_enum_frameintervals,
1594 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1595 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1596 #ifdef CONFIG_VIDEO_ADV_DEBUG
1597 .vidioc_g_register = mcam_vidioc_g_register,
1598 .vidioc_s_register = mcam_vidioc_s_register,
1602 /* ---------------------------------------------------------------------- */
1604 * Our various file operations.
1606 static int mcam_v4l_open(struct file *filp)
1608 struct mcam_camera *cam = video_drvdata(filp);
1611 mutex_lock(&cam->s_mutex);
1612 ret = v4l2_fh_open(filp);
1615 if (v4l2_fh_is_singular_file(filp)) {
1616 ret = mcam_ctlr_power_up(cam);
1619 __mcam_cam_reset(cam);
1620 mcam_set_config_needed(cam, 1);
1623 mutex_unlock(&cam->s_mutex);
1625 v4l2_fh_release(filp);
1630 static int mcam_v4l_release(struct file *filp)
1632 struct mcam_camera *cam = video_drvdata(filp);
1635 mutex_lock(&cam->s_mutex);
1636 last_open = v4l2_fh_is_singular_file(filp);
1637 _vb2_fop_release(filp, NULL);
1639 mcam_disable_mipi(cam);
1640 mcam_ctlr_power_down(cam);
1641 if (cam->buffer_mode == B_vmalloc && alloc_bufs_at_read)
1642 mcam_free_dma_bufs(cam);
1645 mutex_unlock(&cam->s_mutex);
1649 static const struct v4l2_file_operations mcam_v4l_fops = {
1650 .owner = THIS_MODULE,
1651 .open = mcam_v4l_open,
1652 .release = mcam_v4l_release,
1653 .read = vb2_fop_read,
1654 .poll = vb2_fop_poll,
1655 .mmap = vb2_fop_mmap,
1656 .unlocked_ioctl = video_ioctl2,
1661 * This template device holds all of those v4l2 methods; we
1662 * clone it for specific real devices.
1664 static struct video_device mcam_v4l_template = {
1666 .fops = &mcam_v4l_fops,
1667 .ioctl_ops = &mcam_v4l_ioctl_ops,
1668 .release = video_device_release_empty,
1671 /* ---------------------------------------------------------------------- */
1673 * Interrupt handler stuff
1675 static void mcam_frame_complete(struct mcam_camera *cam, int frame)
1678 * Basic frame housekeeping.
1680 set_bit(frame, &cam->flags);
1681 clear_bit(CF_DMA_ACTIVE, &cam->flags);
1682 cam->next_buf = frame;
1683 cam->buf_seq[frame] = cam->sequence++;
1684 cam->frame_state.frames++;
1686 * "This should never happen"
1688 if (cam->state != S_STREAMING)
1691 * Process the frame and set up the next one.
1693 cam->frame_complete(cam, frame);
1698 * The interrupt handler; this needs to be called from the
1699 * platform irq handler with the lock held.
1701 int mccic_irq(struct mcam_camera *cam, unsigned int irqs)
1703 unsigned int frame, handled = 0;
1705 mcam_reg_write(cam, REG_IRQSTAT, FRAMEIRQS); /* Clear'em all */
1707 * Handle any frame completions. There really should
1708 * not be more than one of these, or we have fallen
1711 * When running in S/G mode, the frame number lacks any
1712 * real meaning - there's only one descriptor array - but
1713 * the controller still picks a different one to signal
1716 for (frame = 0; frame < cam->nbufs; frame++)
1717 if (irqs & (IRQ_EOF0 << frame) &&
1718 test_bit(CF_FRAME_SOF0 + frame, &cam->flags)) {
1719 mcam_frame_complete(cam, frame);
1721 clear_bit(CF_FRAME_SOF0 + frame, &cam->flags);
1722 if (cam->buffer_mode == B_DMA_sg)
1726 * If a frame starts, note that we have DMA active. This
1727 * code assumes that we won't get multiple frame interrupts
1728 * at once; may want to rethink that.
1730 for (frame = 0; frame < cam->nbufs; frame++) {
1731 if (irqs & (IRQ_SOF0 << frame)) {
1732 set_bit(CF_FRAME_SOF0 + frame, &cam->flags);
1733 handled = IRQ_HANDLED;
1737 if (handled == IRQ_HANDLED) {
1738 set_bit(CF_DMA_ACTIVE, &cam->flags);
1739 if (cam->buffer_mode == B_DMA_sg)
1740 mcam_ctlr_stop(cam);
1745 /* ---------------------------------------------------------------------- */
1747 * Registration and such.
1749 static struct ov7670_config sensor_cfg = {
1751 * Exclude QCIF mode, because it only captures a tiny portion
1759 int mccic_register(struct mcam_camera *cam)
1761 struct i2c_board_info ov7670_info = {
1764 .platform_data = &sensor_cfg,
1769 * Validate the requested buffer mode.
1771 if (buffer_mode >= 0)
1772 cam->buffer_mode = buffer_mode;
1773 if (cam->buffer_mode == B_DMA_sg &&
1774 cam->chip_id == MCAM_CAFE) {
1775 printk(KERN_ERR "marvell-cam: Cafe can't do S/G I/O, "
1776 "attempting vmalloc mode instead\n");
1777 cam->buffer_mode = B_vmalloc;
1779 if (!mcam_buffer_mode_supported(cam->buffer_mode)) {
1780 printk(KERN_ERR "marvell-cam: buffer mode %d unsupported\n",
1787 ret = v4l2_device_register(cam->dev, &cam->v4l2_dev);
1791 mutex_init(&cam->s_mutex);
1792 cam->state = S_NOTREADY;
1793 mcam_set_config_needed(cam, 1);
1794 cam->pix_format = mcam_def_pix_format;
1795 cam->mbus_code = mcam_def_mbus_code;
1796 mcam_ctlr_init(cam);
1799 * Get the v4l2 setup done.
1801 ret = v4l2_ctrl_handler_init(&cam->ctrl_handler, 10);
1803 goto out_unregister;
1804 cam->v4l2_dev.ctrl_handler = &cam->ctrl_handler;
1807 * Try to find the sensor.
1809 sensor_cfg.clock_speed = cam->clock_speed;
1810 sensor_cfg.use_smbus = cam->use_smbus;
1811 cam->sensor_addr = ov7670_info.addr;
1812 cam->sensor = v4l2_i2c_new_subdev_board(&cam->v4l2_dev,
1813 cam->i2c_adapter, &ov7670_info, NULL);
1814 if (cam->sensor == NULL) {
1816 goto out_unregister;
1819 ret = mcam_cam_init(cam);
1821 goto out_unregister;
1823 ret = mcam_setup_vb2(cam);
1825 goto out_unregister;
1827 mutex_lock(&cam->s_mutex);
1828 cam->vdev = mcam_v4l_template;
1829 cam->vdev.v4l2_dev = &cam->v4l2_dev;
1830 cam->vdev.lock = &cam->s_mutex;
1831 cam->vdev.queue = &cam->vb_queue;
1832 video_set_drvdata(&cam->vdev, cam);
1833 ret = video_register_device(&cam->vdev, VFL_TYPE_GRABBER, -1);
1835 mutex_unlock(&cam->s_mutex);
1836 goto out_unregister;
1840 * If so requested, try to get our DMA buffers now.
1842 if (cam->buffer_mode == B_vmalloc && !alloc_bufs_at_read) {
1843 if (mcam_alloc_dma_bufs(cam, 1))
1844 cam_warn(cam, "Unable to alloc DMA buffers at load"
1845 " will try again later.");
1848 mutex_unlock(&cam->s_mutex);
1852 v4l2_ctrl_handler_free(&cam->ctrl_handler);
1853 v4l2_device_unregister(&cam->v4l2_dev);
1858 void mccic_shutdown(struct mcam_camera *cam)
1861 * If we have no users (and we really, really should have no
1862 * users) the device will already be powered down. Trying to
1863 * take it down again will wedge the machine, which is frowned
1866 if (!list_empty(&cam->vdev.fh_list)) {
1867 cam_warn(cam, "Removing a device with users!\n");
1868 mcam_ctlr_power_down(cam);
1870 mcam_cleanup_vb2(cam);
1871 if (cam->buffer_mode == B_vmalloc)
1872 mcam_free_dma_bufs(cam);
1873 video_unregister_device(&cam->vdev);
1874 v4l2_ctrl_handler_free(&cam->ctrl_handler);
1875 v4l2_device_unregister(&cam->v4l2_dev);
1883 void mccic_suspend(struct mcam_camera *cam)
1885 mutex_lock(&cam->s_mutex);
1886 if (!list_empty(&cam->vdev.fh_list)) {
1887 enum mcam_state cstate = cam->state;
1889 mcam_ctlr_stop_dma(cam);
1890 mcam_ctlr_power_down(cam);
1891 cam->state = cstate;
1893 mutex_unlock(&cam->s_mutex);
1896 int mccic_resume(struct mcam_camera *cam)
1900 mutex_lock(&cam->s_mutex);
1901 if (!list_empty(&cam->vdev.fh_list)) {
1902 ret = mcam_ctlr_power_up(cam);
1904 mutex_unlock(&cam->s_mutex);
1907 __mcam_cam_reset(cam);
1909 mcam_ctlr_power_down(cam);
1911 mutex_unlock(&cam->s_mutex);
1913 set_bit(CF_CONFIG_NEEDED, &cam->flags);
1914 if (cam->state == S_STREAMING) {
1916 * If there was a buffer in the DMA engine at suspend
1917 * time, put it back on the queue or we'll forget about it.
1919 if (cam->buffer_mode == B_DMA_sg && cam->vb_bufs[0])
1920 list_add(&cam->vb_bufs[0]->queue, &cam->buffers);
1921 ret = mcam_read_setup(cam);
1925 #endif /* CONFIG_PM */