2 * A driver for the CMOS camera controller in the Marvell 88ALP01 "cafe"
3 * multifunction chip. Currently works with the Omnivision OV7670
6 * The data sheet for this device can be found at:
7 * http://www.marvell.com/products/pc_connectivity/88alp01/
9 * Copyright 2006-11 One Laptop Per Child Association, Inc.
10 * Copyright 2006-11 Jonathan Corbet <corbet@lwn.net>
12 * Written by Jonathan Corbet, corbet@lwn.net.
14 * v4l2_device/v4l2_subdev conversion by:
15 * Copyright (C) 2009 Hans Verkuil <hverkuil@xs4all.nl>
17 * This file may be distributed under the terms of the GNU General
18 * Public License, version 2.
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/pci.h>
24 #include <linux/i2c.h>
25 #include <linux/interrupt.h>
26 #include <linux/spinlock.h>
27 #include <linux/slab.h>
28 #include <linux/videodev2.h>
29 #include <media/v4l2-device.h>
30 #include <linux/device.h>
31 #include <linux/wait.h>
32 #include <linux/delay.h>
35 #include "mcam-core.h"
37 #define CAFE_VERSION 0x000002
43 MODULE_AUTHOR("Jonathan Corbet <corbet@lwn.net>");
44 MODULE_DESCRIPTION("Marvell 88ALP01 CMOS Camera Controller driver");
45 MODULE_LICENSE("GPL");
46 MODULE_SUPPORTED_DEVICE("Video");
52 int registered; /* Fully initialized? */
53 struct mcam_camera mcam;
55 wait_queue_head_t smbus_wait; /* Waiting on i2c events */
59 * Most of the camera controller registers are defined in mcam-core.h,
60 * but the Cafe platform has some additional registers of its own;
61 * they are described here.
65 * "General purpose register" has a couple of GPIOs used for sensor
66 * power and reset on OLPC XO 1.0 systems.
69 #define GPR_C1EN 0x00000020 /* Pad 1 (power down) enable */
70 #define GPR_C0EN 0x00000010 /* Pad 0 (reset) enable */
71 #define GPR_C1 0x00000002 /* Control 1 value */
73 * Control 0 is wired to reset on OLPC machines. For ov7x sensors,
76 #define GPR_C0 0x00000001 /* Control 0 value */
79 * These registers control the SMBUS module for communicating
82 #define REG_TWSIC0 0xb8 /* TWSI (smbus) control 0 */
83 #define TWSIC0_EN 0x00000001 /* TWSI enable */
84 #define TWSIC0_MODE 0x00000002 /* 1 = 16-bit, 0 = 8-bit */
85 #define TWSIC0_SID 0x000003fc /* Slave ID */
87 * Subtle trickery: the slave ID field starts with bit 2. But the
88 * Linux i2c stack wants to treat the bottommost bit as a separate
89 * read/write bit, which is why slave ID's are usually presented
90 * >>1. For consistency with that behavior, we shift over three
91 * bits instead of two.
93 #define TWSIC0_SID_SHIFT 3
94 #define TWSIC0_CLKDIV 0x0007fc00 /* Clock divider */
95 #define TWSIC0_MASKACK 0x00400000 /* Mask ack from sensor */
96 #define TWSIC0_OVMAGIC 0x00800000 /* Make it work on OV sensors */
98 #define REG_TWSIC1 0xbc /* TWSI control 1 */
99 #define TWSIC1_DATA 0x0000ffff /* Data to/from camchip */
100 #define TWSIC1_ADDR 0x00ff0000 /* Address (register) */
101 #define TWSIC1_ADDR_SHIFT 16
102 #define TWSIC1_READ 0x01000000 /* Set for read op */
103 #define TWSIC1_WSTAT 0x02000000 /* Write status */
104 #define TWSIC1_RVALID 0x04000000 /* Read data valid */
105 #define TWSIC1_ERROR 0x08000000 /* Something screwed up */
108 * Here's the weird global control registers
110 #define REG_GL_CSR 0x3004 /* Control/status register */
111 #define GCSR_SRS 0x00000001 /* SW Reset set */
112 #define GCSR_SRC 0x00000002 /* SW Reset clear */
113 #define GCSR_MRS 0x00000004 /* Master reset set */
114 #define GCSR_MRC 0x00000008 /* HW Reset clear */
115 #define GCSR_CCIC_EN 0x00004000 /* CCIC Clock enable */
116 #define REG_GL_IMASK 0x300c /* Interrupt mask register */
117 #define GIMSK_CCIC_EN 0x00000004 /* CCIC Interrupt enable */
119 #define REG_GL_FCR 0x3038 /* GPIO functional control register */
120 #define GFCR_GPIO_ON 0x08 /* Camera GPIO enabled */
121 #define REG_GL_GPIOR 0x315c /* GPIO register */
122 #define GGPIO_OUT 0x80000 /* GPIO output */
123 #define GGPIO_VAL 0x00008 /* Output pin value */
125 #define REG_LEN (REG_GL_IMASK + 4)
129 * Debugging and related.
131 #define cam_err(cam, fmt, arg...) \
132 dev_err(&(cam)->pdev->dev, fmt, ##arg);
133 #define cam_warn(cam, fmt, arg...) \
134 dev_warn(&(cam)->pdev->dev, fmt, ##arg);
136 /* -------------------------------------------------------------------- */
138 * The I2C/SMBUS interface to the camera itself starts here. The
139 * controller handles SMBUS itself, presenting a relatively simple register
140 * interface; all we have to do is to tell it where to route the data.
142 #define CAFE_SMBUS_TIMEOUT (HZ) /* generous */
144 static inline struct cafe_camera *to_cam(struct v4l2_device *dev)
146 struct mcam_camera *m = container_of(dev, struct mcam_camera, v4l2_dev);
147 return container_of(m, struct cafe_camera, mcam);
151 static int cafe_smbus_write_done(struct mcam_camera *mcam)
157 * We must delay after the interrupt, or the controller gets confused
158 * and never does give us good status. Fortunately, we don't do this
162 spin_lock_irqsave(&mcam->dev_lock, flags);
163 c1 = mcam_reg_read(mcam, REG_TWSIC1);
164 spin_unlock_irqrestore(&mcam->dev_lock, flags);
165 return (c1 & (TWSIC1_WSTAT|TWSIC1_ERROR)) != TWSIC1_WSTAT;
168 static int cafe_smbus_write_data(struct cafe_camera *cam,
169 u16 addr, u8 command, u8 value)
173 struct mcam_camera *mcam = &cam->mcam;
175 spin_lock_irqsave(&mcam->dev_lock, flags);
176 rval = TWSIC0_EN | ((addr << TWSIC0_SID_SHIFT) & TWSIC0_SID);
177 rval |= TWSIC0_OVMAGIC; /* Make OV sensors work */
179 * Marvell sez set clkdiv to all 1's for now.
181 rval |= TWSIC0_CLKDIV;
182 mcam_reg_write(mcam, REG_TWSIC0, rval);
183 (void) mcam_reg_read(mcam, REG_TWSIC1); /* force write */
184 rval = value | ((command << TWSIC1_ADDR_SHIFT) & TWSIC1_ADDR);
185 mcam_reg_write(mcam, REG_TWSIC1, rval);
186 spin_unlock_irqrestore(&mcam->dev_lock, flags);
188 /* Unfortunately, reading TWSIC1 too soon after sending a command
189 * causes the device to die.
190 * Use a busy-wait because we often send a large quantity of small
191 * commands at-once; using msleep() would cause a lot of context
192 * switches which take longer than 2ms, resulting in a noticeable
193 * boot-time and capture-start delays.
198 * Another sad fact is that sometimes, commands silently complete but
199 * cafe_smbus_write_done() never becomes aware of this.
200 * This happens at random and appears to possible occur with any
202 * We don't understand why this is. We work around this issue
203 * with the timeout in the wait below, assuming that all commands
204 * complete within the timeout.
206 wait_event_timeout(cam->smbus_wait, cafe_smbus_write_done(mcam),
209 spin_lock_irqsave(&mcam->dev_lock, flags);
210 rval = mcam_reg_read(mcam, REG_TWSIC1);
211 spin_unlock_irqrestore(&mcam->dev_lock, flags);
213 if (rval & TWSIC1_WSTAT) {
214 cam_err(cam, "SMBUS write (%02x/%02x/%02x) timed out\n", addr,
218 if (rval & TWSIC1_ERROR) {
219 cam_err(cam, "SMBUS write (%02x/%02x/%02x) error\n", addr,
228 static int cafe_smbus_read_done(struct mcam_camera *mcam)
234 * We must delay after the interrupt, or the controller gets confused
235 * and never does give us good status. Fortunately, we don't do this
239 spin_lock_irqsave(&mcam->dev_lock, flags);
240 c1 = mcam_reg_read(mcam, REG_TWSIC1);
241 spin_unlock_irqrestore(&mcam->dev_lock, flags);
242 return c1 & (TWSIC1_RVALID|TWSIC1_ERROR);
247 static int cafe_smbus_read_data(struct cafe_camera *cam,
248 u16 addr, u8 command, u8 *value)
252 struct mcam_camera *mcam = &cam->mcam;
254 spin_lock_irqsave(&mcam->dev_lock, flags);
255 rval = TWSIC0_EN | ((addr << TWSIC0_SID_SHIFT) & TWSIC0_SID);
256 rval |= TWSIC0_OVMAGIC; /* Make OV sensors work */
258 * Marvel sez set clkdiv to all 1's for now.
260 rval |= TWSIC0_CLKDIV;
261 mcam_reg_write(mcam, REG_TWSIC0, rval);
262 (void) mcam_reg_read(mcam, REG_TWSIC1); /* force write */
263 rval = TWSIC1_READ | ((command << TWSIC1_ADDR_SHIFT) & TWSIC1_ADDR);
264 mcam_reg_write(mcam, REG_TWSIC1, rval);
265 spin_unlock_irqrestore(&mcam->dev_lock, flags);
267 wait_event_timeout(cam->smbus_wait,
268 cafe_smbus_read_done(mcam), CAFE_SMBUS_TIMEOUT);
269 spin_lock_irqsave(&mcam->dev_lock, flags);
270 rval = mcam_reg_read(mcam, REG_TWSIC1);
271 spin_unlock_irqrestore(&mcam->dev_lock, flags);
273 if (rval & TWSIC1_ERROR) {
274 cam_err(cam, "SMBUS read (%02x/%02x) error\n", addr, command);
277 if (!(rval & TWSIC1_RVALID)) {
278 cam_err(cam, "SMBUS read (%02x/%02x) timed out\n", addr,
282 *value = rval & 0xff;
287 * Perform a transfer over SMBUS. This thing is called under
288 * the i2c bus lock, so we shouldn't race with ourselves...
290 static int cafe_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
291 unsigned short flags, char rw, u8 command,
292 int size, union i2c_smbus_data *data)
294 struct cafe_camera *cam = i2c_get_adapdata(adapter);
298 * This interface would appear to only do byte data ops. OK
299 * it can do word too, but the cam chip has no use for that.
301 if (size != I2C_SMBUS_BYTE_DATA) {
302 cam_err(cam, "funky xfer size %d\n", size);
306 if (rw == I2C_SMBUS_WRITE)
307 ret = cafe_smbus_write_data(cam, addr, command, data->byte);
308 else if (rw == I2C_SMBUS_READ)
309 ret = cafe_smbus_read_data(cam, addr, command, &data->byte);
314 static void cafe_smbus_enable_irq(struct cafe_camera *cam)
318 spin_lock_irqsave(&cam->mcam.dev_lock, flags);
319 mcam_reg_set_bit(&cam->mcam, REG_IRQMASK, TWSIIRQS);
320 spin_unlock_irqrestore(&cam->mcam.dev_lock, flags);
323 static u32 cafe_smbus_func(struct i2c_adapter *adapter)
325 return I2C_FUNC_SMBUS_READ_BYTE_DATA |
326 I2C_FUNC_SMBUS_WRITE_BYTE_DATA;
329 static struct i2c_algorithm cafe_smbus_algo = {
330 .smbus_xfer = cafe_smbus_xfer,
331 .functionality = cafe_smbus_func
334 static int cafe_smbus_setup(struct cafe_camera *cam)
336 struct i2c_adapter *adap;
339 adap = kzalloc(sizeof(*adap), GFP_KERNEL);
342 cam->mcam.i2c_adapter = adap;
343 cafe_smbus_enable_irq(cam);
344 adap->owner = THIS_MODULE;
345 adap->algo = &cafe_smbus_algo;
346 strcpy(adap->name, "cafe_ccic");
347 adap->dev.parent = &cam->pdev->dev;
348 i2c_set_adapdata(adap, cam);
349 ret = i2c_add_adapter(adap);
351 printk(KERN_ERR "Unable to register cafe i2c adapter\n");
355 static void cafe_smbus_shutdown(struct cafe_camera *cam)
357 i2c_del_adapter(cam->mcam.i2c_adapter);
358 kfree(cam->mcam.i2c_adapter);
363 * Controller-level stuff
366 static void cafe_ctlr_init(struct mcam_camera *mcam)
370 spin_lock_irqsave(&mcam->dev_lock, flags);
372 * Added magic to bring up the hardware on the B-Test board
374 mcam_reg_write(mcam, 0x3038, 0x8);
375 mcam_reg_write(mcam, 0x315c, 0x80008);
377 * Go through the dance needed to wake the device up.
378 * Note that these registers are global and shared
379 * with the NAND and SD devices. Interaction between the
380 * three still needs to be examined.
382 mcam_reg_write(mcam, REG_GL_CSR, GCSR_SRS|GCSR_MRS); /* Needed? */
383 mcam_reg_write(mcam, REG_GL_CSR, GCSR_SRC|GCSR_MRC);
384 mcam_reg_write(mcam, REG_GL_CSR, GCSR_SRC|GCSR_MRS);
386 * Here we must wait a bit for the controller to come around.
388 spin_unlock_irqrestore(&mcam->dev_lock, flags);
390 spin_lock_irqsave(&mcam->dev_lock, flags);
392 mcam_reg_write(mcam, REG_GL_CSR, GCSR_CCIC_EN|GCSR_SRC|GCSR_MRC);
393 mcam_reg_set_bit(mcam, REG_GL_IMASK, GIMSK_CCIC_EN);
395 * Mask all interrupts.
397 mcam_reg_write(mcam, REG_IRQMASK, 0);
398 spin_unlock_irqrestore(&mcam->dev_lock, flags);
402 static int cafe_ctlr_power_up(struct mcam_camera *mcam)
405 * Part one of the sensor dance: turn the global
408 mcam_reg_write(mcam, REG_GL_FCR, GFCR_GPIO_ON);
409 mcam_reg_write(mcam, REG_GL_GPIOR, GGPIO_OUT|GGPIO_VAL);
411 * Put the sensor into operational mode (assumes OLPC-style
412 * wiring). Control 0 is reset - set to 1 to operate.
413 * Control 1 is power down, set to 0 to operate.
415 mcam_reg_write(mcam, REG_GPR, GPR_C1EN|GPR_C0EN); /* pwr up, reset */
416 mcam_reg_write(mcam, REG_GPR, GPR_C1EN|GPR_C0EN|GPR_C0);
421 static void cafe_ctlr_power_down(struct mcam_camera *mcam)
423 mcam_reg_write(mcam, REG_GPR, GPR_C1EN|GPR_C0EN|GPR_C1);
424 mcam_reg_write(mcam, REG_GL_FCR, GFCR_GPIO_ON);
425 mcam_reg_write(mcam, REG_GL_GPIOR, GGPIO_OUT);
431 * The platform interrupt handler.
433 static irqreturn_t cafe_irq(int irq, void *data)
435 struct cafe_camera *cam = data;
436 struct mcam_camera *mcam = &cam->mcam;
437 unsigned int irqs, handled;
439 spin_lock(&mcam->dev_lock);
440 irqs = mcam_reg_read(mcam, REG_IRQSTAT);
441 handled = cam->registered && mccic_irq(mcam, irqs);
442 if (irqs & TWSIIRQS) {
443 mcam_reg_write(mcam, REG_IRQSTAT, TWSIIRQS);
444 wake_up(&cam->smbus_wait);
447 spin_unlock(&mcam->dev_lock);
448 return IRQ_RETVAL(handled);
452 /* -------------------------------------------------------------------------- */
454 * PCI interface stuff.
457 static int cafe_pci_probe(struct pci_dev *pdev,
458 const struct pci_device_id *id)
461 struct cafe_camera *cam;
462 struct mcam_camera *mcam;
465 * Start putting together one of our big camera structures.
468 cam = kzalloc(sizeof(struct cafe_camera), GFP_KERNEL);
473 mcam->chip_id = MCAM_CAFE;
474 spin_lock_init(&mcam->dev_lock);
475 init_waitqueue_head(&cam->smbus_wait);
476 mcam->plat_power_up = cafe_ctlr_power_up;
477 mcam->plat_power_down = cafe_ctlr_power_down;
478 mcam->dev = &pdev->dev;
480 * Set the clock speed for the XO 1; I don't believe this
481 * driver has ever run anywhere else.
483 mcam->clock_speed = 45;
486 * Vmalloc mode for buffers is traditional with this driver.
487 * We *might* be able to run DMA_contig, especially on a system
490 mcam->buffer_mode = B_vmalloc;
492 * Get set up on the PCI bus.
494 ret = pci_enable_device(pdev);
497 pci_set_master(pdev);
500 mcam->regs = pci_iomap(pdev, 0, 0);
502 printk(KERN_ERR "Unable to ioremap cafe-ccic regs\n");
505 mcam->regs_size = pci_resource_len(pdev, 0);
506 ret = request_irq(pdev->irq, cafe_irq, IRQF_SHARED, "cafe-ccic", cam);
511 * Initialize the controller and leave it powered up. It will
512 * stay that way until the sensor driver shows up.
514 cafe_ctlr_init(mcam);
515 cafe_ctlr_power_up(mcam);
517 * Set up I2C/SMBUS communications. We have to drop the mutex here
518 * because the sensor could attach in this call chain, leading to
519 * unsightly deadlocks.
521 ret = cafe_smbus_setup(cam);
525 ret = mccic_register(mcam);
531 cafe_smbus_shutdown(cam);
533 cafe_ctlr_power_down(mcam);
534 free_irq(pdev->irq, cam);
536 pci_iounmap(pdev, mcam->regs);
538 pci_disable_device(pdev);
547 * Shut down an initialized device
549 static void cafe_shutdown(struct cafe_camera *cam)
551 mccic_shutdown(&cam->mcam);
552 cafe_smbus_shutdown(cam);
553 free_irq(cam->pdev->irq, cam);
554 pci_iounmap(cam->pdev, cam->mcam.regs);
558 static void cafe_pci_remove(struct pci_dev *pdev)
560 struct v4l2_device *v4l2_dev = dev_get_drvdata(&pdev->dev);
561 struct cafe_camera *cam = to_cam(v4l2_dev);
564 printk(KERN_WARNING "pci_remove on unknown pdev %p\n", pdev);
574 * Basic power management.
576 static int cafe_pci_suspend(struct pci_dev *pdev, pm_message_t state)
578 struct v4l2_device *v4l2_dev = dev_get_drvdata(&pdev->dev);
579 struct cafe_camera *cam = to_cam(v4l2_dev);
582 ret = pci_save_state(pdev);
585 mccic_suspend(&cam->mcam);
586 pci_disable_device(pdev);
591 static int cafe_pci_resume(struct pci_dev *pdev)
593 struct v4l2_device *v4l2_dev = dev_get_drvdata(&pdev->dev);
594 struct cafe_camera *cam = to_cam(v4l2_dev);
597 pci_restore_state(pdev);
598 ret = pci_enable_device(pdev);
601 cam_warn(cam, "Unable to re-enable device on resume!\n");
604 cafe_ctlr_init(&cam->mcam);
605 return mccic_resume(&cam->mcam);
608 #endif /* CONFIG_PM */
610 static struct pci_device_id cafe_ids[] = {
611 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL,
612 PCI_DEVICE_ID_MARVELL_88ALP01_CCIC) },
616 MODULE_DEVICE_TABLE(pci, cafe_ids);
618 static struct pci_driver cafe_pci_driver = {
619 .name = "cafe1000-ccic",
620 .id_table = cafe_ids,
621 .probe = cafe_pci_probe,
622 .remove = cafe_pci_remove,
624 .suspend = cafe_pci_suspend,
625 .resume = cafe_pci_resume,
632 static int __init cafe_init(void)
636 printk(KERN_NOTICE "Marvell M88ALP01 'CAFE' Camera Controller version %d\n",
638 ret = pci_register_driver(&cafe_pci_driver);
640 printk(KERN_ERR "Unable to register cafe_ccic driver\n");
650 static void __exit cafe_exit(void)
652 pci_unregister_driver(&cafe_pci_driver);
655 module_init(cafe_init);
656 module_exit(cafe_exit);