drivers/media/platform/exynos4-is/fimc-is.c

   1 /*
   2  * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
   3  *
   4  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
   5  *
   6  * Authors: Sylwester Nawrocki <s.nawrocki@samsung.com>
   7  *          Younghwan Joo <yhwan.joo@samsung.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13 #define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
  14
  15 #include <linux/device.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/delay.h>
  18 #include <linux/dma-contiguous.h>
  19 #include <linux/errno.h>
  20 #include <linux/firmware.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/i2c.h>
  25 #include <linux/of_irq.h>
  26 #include <linux/of_address.h>
  27 #include <linux/of_graph.h>
  28 #include <linux/of_platform.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/slab.h>
  32 #include <linux/types.h>
  33 #include <linux/videodev2.h>
  34 #include <media/videobuf2-dma-contig.h>
  35
  36 #include "media-dev.h"
  37 #include "fimc-is.h"
  38 #include "fimc-is-command.h"
  39 #include "fimc-is-errno.h"
  40 #include "fimc-is-i2c.h"
  41 #include "fimc-is-param.h"
  42 #include "fimc-is-regs.h"
  43
  44
  45 static char *fimc_is_clocks[ISS_CLKS_MAX] = {
  46         [ISS_CLK_PPMUISPX]              = "ppmuispx",
  47         [ISS_CLK_PPMUISPMX]             = "ppmuispmx",
  48         [ISS_CLK_LITE0]                 = "lite0",
  49         [ISS_CLK_LITE1]                 = "lite1",
  50         [ISS_CLK_MPLL]                  = "mpll",
  51         [ISS_CLK_ISP]                   = "isp",
  52         [ISS_CLK_DRC]                   = "drc",
  53         [ISS_CLK_FD]                    = "fd",
  54         [ISS_CLK_MCUISP]                = "mcuisp",
  55         [ISS_CLK_UART]                  = "uart",
  56         [ISS_CLK_ISP_DIV0]              = "ispdiv0",
  57         [ISS_CLK_ISP_DIV1]              = "ispdiv1",
  58         [ISS_CLK_MCUISP_DIV0]           = "mcuispdiv0",
  59         [ISS_CLK_MCUISP_DIV1]           = "mcuispdiv1",
  60         [ISS_CLK_ACLK200]               = "aclk200",
  61         [ISS_CLK_ACLK200_DIV]           = "div_aclk200",
  62         [ISS_CLK_ACLK400MCUISP]         = "aclk400mcuisp",
  63         [ISS_CLK_ACLK400MCUISP_DIV]     = "div_aclk400mcuisp",
  64 };
  65
  66 static void fimc_is_put_clocks(struct fimc_is *is)
  67 {
  68         int i;
  69
  70         for (i = 0; i < ISS_CLKS_MAX; i++) {
  71                 if (IS_ERR(is->clocks[i]))
  72                         continue;
  73                 clk_put(is->clocks[i]);
  74                 is->clocks[i] = ERR_PTR(-EINVAL);
  75         }
  76 }
  77
  78 static int fimc_is_get_clocks(struct fimc_is *is)
  79 {
  80         int i, ret;
  81
  82         for (i = 0; i < ISS_CLKS_MAX; i++)
  83                 is->clocks[i] = ERR_PTR(-EINVAL);
  84
  85         for (i = 0; i < ISS_CLKS_MAX; i++) {
  86                 is->clocks[i] = clk_get(&is->pdev->dev, fimc_is_clocks[i]);
  87                 if (IS_ERR(is->clocks[i])) {
  88                         ret = PTR_ERR(is->clocks[i]);
  89                         goto err;
  90                 }
  91         }
  92
  93         return 0;
  94 err:
  95         fimc_is_put_clocks(is);
  96         dev_err(&is->pdev->dev, "failed to get clock: %s\n",
  97                 fimc_is_clocks[i]);
  98         return ret;
  99 }
 100
 101 static int fimc_is_setup_clocks(struct fimc_is *is)
 102 {
 103         int ret;
 104
 105         ret = clk_set_parent(is->clocks[ISS_CLK_ACLK200],
 106                                         is->clocks[ISS_CLK_ACLK200_DIV]);
 107         if (ret < 0)
 108                 return ret;
 109
 110         ret = clk_set_parent(is->clocks[ISS_CLK_ACLK400MCUISP],
 111                                         is->clocks[ISS_CLK_ACLK400MCUISP_DIV]);
 112         if (ret < 0)
 113                 return ret;
 114
 115         ret = clk_set_rate(is->clocks[ISS_CLK_ISP_DIV0], ACLK_AXI_FREQUENCY);
 116         if (ret < 0)
 117                 return ret;
 118
 119         ret = clk_set_rate(is->clocks[ISS_CLK_ISP_DIV1], ACLK_AXI_FREQUENCY);
 120         if (ret < 0)
 121                 return ret;
 122
 123         ret = clk_set_rate(is->clocks[ISS_CLK_MCUISP_DIV0],
 124                                         ATCLK_MCUISP_FREQUENCY);
 125         if (ret < 0)
 126                 return ret;
 127
 128         return clk_set_rate(is->clocks[ISS_CLK_MCUISP_DIV1],
 129                                         ATCLK_MCUISP_FREQUENCY);
 130 }
 131
 132 static int fimc_is_enable_clocks(struct fimc_is *is)
 133 {
 134         int i, ret;
 135
 136         for (i = 0; i < ISS_GATE_CLKS_MAX; i++) {
 137                 if (IS_ERR(is->clocks[i]))
 138                         continue;
 139                 ret = clk_prepare_enable(is->clocks[i]);
 140                 if (ret < 0) {
 141                         dev_err(&is->pdev->dev, "clock %s enable failed\n",
 142                                 fimc_is_clocks[i]);
 143                         for (--i; i >= 0; i--)
 144                                 clk_disable(is->clocks[i]);
 145                         return ret;
 146                 }
 147                 pr_debug("enabled clock: %s\n", fimc_is_clocks[i]);
 148         }
 149         return 0;
 150 }
 151
 152 static void fimc_is_disable_clocks(struct fimc_is *is)
 153 {
 154         int i;
 155
 156         for (i = 0; i < ISS_GATE_CLKS_MAX; i++) {
 157                 if (!IS_ERR(is->clocks[i])) {
 158                         clk_disable_unprepare(is->clocks[i]);
 159                         pr_debug("disabled clock: %s\n", fimc_is_clocks[i]);
 160                 }
 161         }
 162 }
 163
 164 static int fimc_is_parse_sensor_config(struct fimc_is *is, unsigned int index,
 165                                                 struct device_node *node)
 166 {
 167         struct fimc_is_sensor *sensor = &is->sensor[index];
 168         u32 tmp = 0;
 169         int ret;
 170
 171         sensor->drvdata = fimc_is_sensor_get_drvdata(node);
 172         if (!sensor->drvdata) {
 173                 dev_err(&is->pdev->dev, "no driver data found for: %s\n",
 174                                                          node->full_name);
 175                 return -EINVAL;
 176         }
 177
 178         node = of_graph_get_next_endpoint(node, NULL);
 179         if (!node)
 180                 return -ENXIO;
 181
 182         node = of_graph_get_remote_port(node);
 183         if (!node)
 184                 return -ENXIO;
 185
 186         /* Use MIPI-CSIS channel id to determine the ISP I2C bus index. */
 187         ret = of_property_read_u32(node, "reg", &tmp);
 188         if (ret < 0) {
 189                 dev_err(&is->pdev->dev, "reg property not found at: %s\n",
 190                                                          node->full_name);
 191                 return ret;
 192         }
 193
 194         sensor->i2c_bus = tmp - FIMC_INPUT_MIPI_CSI2_0;
 195         return 0;
 196 }
 197
 198 static int fimc_is_register_subdevs(struct fimc_is *is)
 199 {
 200         struct device_node *i2c_bus, *child;
 201         int ret, index = 0;
 202
 203         ret = fimc_isp_subdev_create(&is->isp);
 204         if (ret < 0)
 205                 return ret;
 206
 207         /* Initialize memory allocator context for the ISP DMA. */
 208         is->isp.alloc_ctx = is->alloc_ctx;
 209
 210         for_each_compatible_node(i2c_bus, NULL, FIMC_IS_I2C_COMPATIBLE) {
 211                 for_each_available_child_of_node(i2c_bus, child) {
 212                         ret = fimc_is_parse_sensor_config(is, index, child);
 213
 214                         if (ret < 0 || index >= FIMC_IS_SENSORS_NUM) {
 215                                 of_node_put(child);
 216                                 return ret;
 217                         }
 218                         index++;
 219                 }
 220         }
 221         return 0;
 222 }
 223
 224 static int fimc_is_unregister_subdevs(struct fimc_is *is)
 225 {
 226         fimc_isp_subdev_destroy(&is->isp);
 227         return 0;
 228 }
 229
 230 static int fimc_is_load_setfile(struct fimc_is *is, char *file_name)
 231 {
 232         const struct firmware *fw;
 233         void *buf;
 234         int ret;
 235
 236         ret = request_firmware(&fw, file_name, &is->pdev->dev);
 237         if (ret < 0) {
 238                 dev_err(&is->pdev->dev, "firmware request failed (%d)\n", ret);
 239                 return ret;
 240         }
 241         buf = is->memory.vaddr + is->setfile.base;
 242         memcpy(buf, fw->data, fw->size);
 243         fimc_is_mem_barrier();
 244         is->setfile.size = fw->size;
 245
 246         pr_debug("mem vaddr: %p, setfile buf: %p\n", is->memory.vaddr, buf);
 247
 248         memcpy(is->fw.setfile_info,
 249                 fw->data + fw->size - FIMC_IS_SETFILE_INFO_LEN,
 250                 FIMC_IS_SETFILE_INFO_LEN - 1);
 251
 252         is->fw.setfile_info[FIMC_IS_SETFILE_INFO_LEN - 1] = '\0';
 253         is->setfile.state = 1;
 254
 255         pr_debug("FIMC-IS setfile loaded: base: %#x, size: %zu B\n",
 256                  is->setfile.base, fw->size);
 257
 258         release_firmware(fw);
 259         return ret;
 260 }
 261
 262 int fimc_is_cpu_set_power(struct fimc_is *is, int on)
 263 {
 264         unsigned int timeout = FIMC_IS_POWER_ON_TIMEOUT;
 265
 266         if (on) {
 267                 /* Disable watchdog */
 268                 mcuctl_write(0, is, REG_WDT_ISP);
 269
 270                 /* Cortex-A5 start address setting */
 271                 mcuctl_write(is->memory.paddr, is, MCUCTL_REG_BBOAR);
 272
 273                 /* Enable and start Cortex-A5 */
 274                 pmuisp_write(0x18000, is, REG_PMU_ISP_ARM_OPTION);
 275                 pmuisp_write(0x1, is, REG_PMU_ISP_ARM_CONFIGURATION);
 276         } else {
 277                 /* A5 power off */
 278                 pmuisp_write(0x10000, is, REG_PMU_ISP_ARM_OPTION);
 279                 pmuisp_write(0x0, is, REG_PMU_ISP_ARM_CONFIGURATION);
 280
 281                 while (pmuisp_read(is, REG_PMU_ISP_ARM_STATUS) & 1) {
 282                         if (timeout == 0)
 283                                 return -ETIME;
 284                         timeout--;
 285                         udelay(1);
 286                 }
 287         }
 288
 289         return 0;
 290 }
 291
 292 /* Wait until @bit of @is->state is set to @state in the interrupt handler. */
 293 int fimc_is_wait_event(struct fimc_is *is, unsigned long bit,
 294                        unsigned int state, unsigned int timeout)
 295 {
 296
 297         int ret = wait_event_timeout(is->irq_queue,
 298                                      !state ^ test_bit(bit, &is->state),
 299                                      timeout);
 300         if (ret == 0) {
 301                 dev_WARN(&is->pdev->dev, "%s() timed out\n", __func__);
 302                 return -ETIME;
 303         }
 304         return 0;
 305 }
 306
 307 int fimc_is_start_firmware(struct fimc_is *is)
 308 {
 309         struct device *dev = &is->pdev->dev;
 310         int ret;
 311
 312         if (is->fw.f_w == NULL) {
 313                 dev_err(dev, "firmware is not loaded\n");
 314                 return -EINVAL;
 315         }
 316
 317         memcpy(is->memory.vaddr, is->fw.f_w->data, is->fw.f_w->size);
 318         wmb();
 319
 320         ret = fimc_is_cpu_set_power(is, 1);
 321         if (ret < 0)
 322                 return ret;
 323
 324         ret = fimc_is_wait_event(is, IS_ST_A5_PWR_ON, 1,
 325                                  msecs_to_jiffies(FIMC_IS_FW_LOAD_TIMEOUT));
 326         if (ret < 0)
 327                 dev_err(dev, "FIMC-IS CPU power on failed\n");
 328
 329         return ret;
 330 }
 331
 332 /* Allocate working memory for the FIMC-IS CPU. */
 333 static int fimc_is_alloc_cpu_memory(struct fimc_is *is)
 334 {
 335         struct device *dev = &is->pdev->dev;
 336
 337         is->memory.vaddr = dma_alloc_coherent(dev, FIMC_IS_CPU_MEM_SIZE,
 338                                               &is->memory.paddr, GFP_KERNEL);
 339         if (is->memory.vaddr == NULL)
 340                 return -ENOMEM;
 341
 342         is->memory.size = FIMC_IS_CPU_MEM_SIZE;
 343         memset(is->memory.vaddr, 0, is->memory.size);
 344
 345         dev_info(dev, "FIMC-IS CPU memory base: %#x\n", (u32)is->memory.paddr);
 346
 347         if (((u32)is->memory.paddr) & FIMC_IS_FW_ADDR_MASK) {
 348                 dev_err(dev, "invalid firmware memory alignment: %#x\n",
 349                         (u32)is->memory.paddr);
 350                 dma_free_coherent(dev, is->memory.size, is->memory.vaddr,
 351                                   is->memory.paddr);
 352                 return -EIO;
 353         }
 354
 355         is->is_p_region = (struct is_region *)(is->memory.vaddr +
 356                                 FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE);
 357
 358         is->is_dma_p_region = is->memory.paddr +
 359                                 FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE;
 360
 361         is->is_shared_region = (struct is_share_region *)(is->memory.vaddr +
 362                                 FIMC_IS_SHARED_REGION_OFFSET);
 363         return 0;
 364 }
 365
 366 static void fimc_is_free_cpu_memory(struct fimc_is *is)
 367 {
 368         struct device *dev = &is->pdev->dev;
 369
 370         if (is->memory.vaddr == NULL)
 371                 return;
 372
 373         dma_free_coherent(dev, is->memory.size, is->memory.vaddr,
 374                           is->memory.paddr);
 375 }
 376
 377 static void fimc_is_load_firmware(const struct firmware *fw, void *context)
 378 {
 379         struct fimc_is *is = context;
 380         struct device *dev = &is->pdev->dev;
 381         void *buf;
 382         int ret;
 383
 384         if (fw == NULL) {
 385                 dev_err(dev, "firmware request failed\n");
 386                 return;
 387         }
 388         mutex_lock(&is->lock);
 389
 390         if (fw->size < FIMC_IS_FW_SIZE_MIN || fw->size > FIMC_IS_FW_SIZE_MAX) {
 391                 dev_err(dev, "wrong firmware size: %d\n", fw->size);
 392                 goto done;
 393         }
 394
 395         is->fw.size = fw->size;
 396
 397         ret = fimc_is_alloc_cpu_memory(is);
 398         if (ret < 0) {
 399                 dev_err(dev, "failed to allocate FIMC-IS CPU memory\n");
 400                 goto done;
 401         }
 402
 403         memcpy(is->memory.vaddr, fw->data, fw->size);
 404         wmb();
 405
 406         /* Read firmware description. */
 407         buf = (void *)(is->memory.vaddr + fw->size - FIMC_IS_FW_DESC_LEN);
 408         memcpy(&is->fw.info, buf, FIMC_IS_FW_INFO_LEN);
 409         is->fw.info[FIMC_IS_FW_INFO_LEN] = 0;
 410
 411         buf = (void *)(is->memory.vaddr + fw->size - FIMC_IS_FW_VER_LEN);
 412         memcpy(&is->fw.version, buf, FIMC_IS_FW_VER_LEN);
 413         is->fw.version[FIMC_IS_FW_VER_LEN - 1] = 0;
 414
 415         is->fw.state = 1;
 416
 417         dev_info(dev, "loaded firmware: %s, rev. %s\n",
 418                  is->fw.info, is->fw.version);
 419         dev_dbg(dev, "FW size: %d, paddr: %#x\n", fw->size, is->memory.paddr);
 420
 421         is->is_shared_region->chip_id = 0xe4412;
 422         is->is_shared_region->chip_rev_no = 1;
 423
 424         fimc_is_mem_barrier();
 425
 426         /*
 427          * FIXME: The firmware is not being released for now, as it is
 428          * needed around for copying to the IS working memory every
 429          * time before the Cortex-A5 is restarted.
 430          */
 431         if (is->fw.f_w)
 432                 release_firmware(is->fw.f_w);
 433         is->fw.f_w = fw;
 434 done:
 435         mutex_unlock(&is->lock);
 436 }
 437
 438 static int fimc_is_request_firmware(struct fimc_is *is, const char *fw_name)
 439 {
 440         return request_firmware_nowait(THIS_MODULE,
 441                                 FW_ACTION_HOTPLUG, fw_name, &is->pdev->dev,
 442                                 GFP_KERNEL, is, fimc_is_load_firmware);
 443 }
 444
 445 /* General IS interrupt handler */
 446 static void fimc_is_general_irq_handler(struct fimc_is *is)
 447 {
 448         is->i2h_cmd.cmd = mcuctl_read(is, MCUCTL_REG_ISSR(10));
 449
 450         switch (is->i2h_cmd.cmd) {
 451         case IHC_GET_SENSOR_NUM:
 452                 fimc_is_hw_get_params(is, 1);
 453                 fimc_is_hw_wait_intmsr0_intmsd0(is);
 454                 fimc_is_hw_set_sensor_num(is);
 455                 pr_debug("ISP FW version: %#x\n", is->i2h_cmd.args[0]);
 456                 break;
 457         case IHC_SET_FACE_MARK:
 458         case IHC_FRAME_DONE:
 459                 fimc_is_hw_get_params(is, 2);
 460                 break;
 461         case IHC_SET_SHOT_MARK:
 462         case IHC_AA_DONE:
 463         case IH_REPLY_DONE:
 464                 fimc_is_hw_get_params(is, 3);
 465                 break;
 466         case IH_REPLY_NOT_DONE:
 467                 fimc_is_hw_get_params(is, 4);
 468                 break;
 469         case IHC_NOT_READY:
 470                 break;
 471         default:
 472                 pr_info("unknown command: %#x\n", is->i2h_cmd.cmd);
 473         }
 474
 475         fimc_is_fw_clear_irq1(is, FIMC_IS_INT_GENERAL);
 476
 477         switch (is->i2h_cmd.cmd) {
 478         case IHC_GET_SENSOR_NUM:
 479                 fimc_is_hw_set_intgr0_gd0(is);
 480                 set_bit(IS_ST_A5_PWR_ON, &is->state);
 481                 break;
 482
 483         case IHC_SET_SHOT_MARK:
 484                 break;
 485
 486         case IHC_SET_FACE_MARK:
 487                 is->fd_header.count = is->i2h_cmd.args[0];
 488                 is->fd_header.index = is->i2h_cmd.args[1];
 489                 is->fd_header.offset = 0;
 490                 break;
 491
 492         case IHC_FRAME_DONE:
 493                 break;
 494
 495         case IHC_AA_DONE:
 496                 pr_debug("AA_DONE - %d, %d, %d\n", is->i2h_cmd.args[0],
 497                          is->i2h_cmd.args[1], is->i2h_cmd.args[2]);
 498                 break;
 499
 500         case IH_REPLY_DONE:
 501                 pr_debug("ISR_DONE: args[0]: %#x\n", is->i2h_cmd.args[0]);
 502
 503                 switch (is->i2h_cmd.args[0]) {
 504                 case HIC_PREVIEW_STILL...HIC_CAPTURE_VIDEO:
 505                         /* Get CAC margin */
 506                         set_bit(IS_ST_CHANGE_MODE, &is->state);
 507                         is->isp.cac_margin_x = is->i2h_cmd.args[1];
 508                         is->isp.cac_margin_y = is->i2h_cmd.args[2];
 509                         pr_debug("CAC margin (x,y): (%d,%d)\n",
 510                                  is->isp.cac_margin_x, is->isp.cac_margin_y);
 511                         break;
 512
 513                 case HIC_STREAM_ON:
 514                         clear_bit(IS_ST_STREAM_OFF, &is->state);
 515                         set_bit(IS_ST_STREAM_ON, &is->state);
 516                         break;
 517
 518                 case HIC_STREAM_OFF:
 519                         clear_bit(IS_ST_STREAM_ON, &is->state);
 520                         set_bit(IS_ST_STREAM_OFF, &is->state);
 521                         break;
 522
 523                 case HIC_SET_PARAMETER:
 524                         is->config[is->config_index].p_region_index[0] = 0;
 525                         is->config[is->config_index].p_region_index[1] = 0;
 526                         set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
 527                         pr_debug("HIC_SET_PARAMETER\n");
 528                         break;
 529
 530                 case HIC_GET_PARAMETER:
 531                         break;
 532
 533                 case HIC_SET_TUNE:
 534                         break;
 535
 536                 case HIC_GET_STATUS:
 537                         break;
 538
 539                 case HIC_OPEN_SENSOR:
 540                         set_bit(IS_ST_OPEN_SENSOR, &is->state);
 541                         pr_debug("data lanes: %d, settle line: %d\n",
 542                                  is->i2h_cmd.args[2], is->i2h_cmd.args[1]);
 543                         break;
 544
 545                 case HIC_CLOSE_SENSOR:
 546                         clear_bit(IS_ST_OPEN_SENSOR, &is->state);
 547                         is->sensor_index = 0;
 548                         break;
 549
 550                 case HIC_MSG_TEST:
 551                         pr_debug("config MSG level completed\n");
 552                         break;
 553
 554                 case HIC_POWER_DOWN:
 555                         clear_bit(IS_ST_PWR_SUBIP_ON, &is->state);
 556                         break;
 557
 558                 case HIC_GET_SET_FILE_ADDR:
 559                         is->setfile.base = is->i2h_cmd.args[1];
 560                         set_bit(IS_ST_SETFILE_LOADED, &is->state);
 561                         break;
 562
 563                 case HIC_LOAD_SET_FILE:
 564                         set_bit(IS_ST_SETFILE_LOADED, &is->state);
 565                         break;
 566                 }
 567                 break;
 568
 569         case IH_REPLY_NOT_DONE:
 570                 pr_err("ISR_NDONE: %d: %#x, %s\n", is->i2h_cmd.args[0],
 571                        is->i2h_cmd.args[1],
 572                        fimc_is_strerr(is->i2h_cmd.args[1]));
 573
 574                 if (is->i2h_cmd.args[1] & IS_ERROR_TIME_OUT_FLAG)
 575                         pr_err("IS_ERROR_TIME_OUT\n");
 576
 577                 switch (is->i2h_cmd.args[1]) {
 578                 case IS_ERROR_SET_PARAMETER:
 579                         fimc_is_mem_barrier();
 580                 }
 581
 582                 switch (is->i2h_cmd.args[0]) {
 583                 case HIC_SET_PARAMETER:
 584                         is->config[is->config_index].p_region_index[0] = 0;
 585                         is->config[is->config_index].p_region_index[1] = 0;
 586                         set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
 587                         break;
 588                 }
 589                 break;
 590
 591         case IHC_NOT_READY:
 592                 pr_err("IS control sequence error: Not Ready\n");
 593                 break;
 594         }
 595
 596         wake_up(&is->irq_queue);
 597 }
 598
 599 static irqreturn_t fimc_is_irq_handler(int irq, void *priv)
 600 {
 601         struct fimc_is *is = priv;
 602         unsigned long flags;
 603         u32 status;
 604
 605         spin_lock_irqsave(&is->slock, flags);
 606         status = mcuctl_read(is, MCUCTL_REG_INTSR1);
 607
 608         if (status & (1UL << FIMC_IS_INT_GENERAL))
 609                 fimc_is_general_irq_handler(is);
 610
 611         if (status & (1UL << FIMC_IS_INT_FRAME_DONE_ISP))
 612                 fimc_isp_irq_handler(is);
 613
 614         spin_unlock_irqrestore(&is->slock, flags);
 615         return IRQ_HANDLED;
 616 }
 617
 618 static int fimc_is_hw_open_sensor(struct fimc_is *is,
 619                                   struct fimc_is_sensor *sensor)
 620 {
 621         struct sensor_open_extended *soe = (void *)&is->is_p_region->shared;
 622
 623         fimc_is_hw_wait_intmsr0_intmsd0(is);
 624
 625         soe->self_calibration_mode = 1;
 626         soe->actuator_type = 0;
 627         soe->mipi_lane_num = 0;
 628         soe->mclk = 0;
 629         soe->mipi_speed = 0;
 630         soe->fast_open_sensor = 0;
 631         soe->i2c_sclk = 88000000;
 632
 633         fimc_is_mem_barrier();
 634
 635         mcuctl_write(HIC_OPEN_SENSOR, is, MCUCTL_REG_ISSR(0));
 636         mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
 637         mcuctl_write(sensor->drvdata->id, is, MCUCTL_REG_ISSR(2));
 638         mcuctl_write(sensor->i2c_bus, is, MCUCTL_REG_ISSR(3));
 639         mcuctl_write(is->is_dma_p_region, is, MCUCTL_REG_ISSR(4));
 640
 641         fimc_is_hw_set_intgr0_gd0(is);
 642
 643         return fimc_is_wait_event(is, IS_ST_OPEN_SENSOR, 1,
 644                                   sensor->drvdata->open_timeout);
 645 }
 646
 647
 648 int fimc_is_hw_initialize(struct fimc_is *is)
 649 {
 650         const int config_ids[] = {
 651                 IS_SC_PREVIEW_STILL, IS_SC_PREVIEW_VIDEO,
 652                 IS_SC_CAPTURE_STILL, IS_SC_CAPTURE_VIDEO
 653         };
 654         struct device *dev = &is->pdev->dev;
 655         u32 prev_id;
 656         int i, ret;
 657
 658         /* Sensor initialization. Only one sensor is currently supported. */
 659         ret = fimc_is_hw_open_sensor(is, &is->sensor[0]);
 660         if (ret < 0)
 661                 return ret;
 662
 663         /* Get the setfile address. */
 664         fimc_is_hw_get_setfile_addr(is);
 665
 666         ret = fimc_is_wait_event(is, IS_ST_SETFILE_LOADED, 1,
 667                                  FIMC_IS_CONFIG_TIMEOUT);
 668         if (ret < 0) {
 669                 dev_err(dev, "get setfile address timed out\n");
 670                 return ret;
 671         }
 672         pr_debug("setfile.base: %#x\n", is->setfile.base);
 673
 674         /* Load the setfile. */
 675         fimc_is_load_setfile(is, FIMC_IS_SETFILE_6A3);
 676         clear_bit(IS_ST_SETFILE_LOADED, &is->state);
 677         fimc_is_hw_load_setfile(is);
 678         ret = fimc_is_wait_event(is, IS_ST_SETFILE_LOADED, 1,
 679                                  FIMC_IS_CONFIG_TIMEOUT);
 680         if (ret < 0) {
 681                 dev_err(dev, "loading setfile timed out\n");
 682                 return ret;
 683         }
 684
 685         pr_debug("setfile: base: %#x, size: %d\n",
 686                  is->setfile.base, is->setfile.size);
 687         pr_info("FIMC-IS Setfile info: %s\n", is->fw.setfile_info);
 688
 689         /* Check magic number. */
 690         if (is->is_p_region->shared[MAX_SHARED_COUNT - 1] !=
 691             FIMC_IS_MAGIC_NUMBER) {
 692                 dev_err(dev, "magic number error!\n");
 693                 return -EIO;
 694         }
 695
 696         pr_debug("shared region: %#x, parameter region: %#x\n",
 697                  is->memory.paddr + FIMC_IS_SHARED_REGION_OFFSET,
 698                  is->is_dma_p_region);
 699
 700         is->setfile.sub_index = 0;
 701
 702         /* Stream off. */
 703         fimc_is_hw_stream_off(is);
 704         ret = fimc_is_wait_event(is, IS_ST_STREAM_OFF, 1,
 705                                  FIMC_IS_CONFIG_TIMEOUT);
 706         if (ret < 0) {
 707                 dev_err(dev, "stream off timeout\n");
 708                 return ret;
 709         }
 710
 711         /* Preserve previous mode. */
 712         prev_id = is->config_index;
 713
 714         /* Set initial parameter values. */
 715         for (i = 0; i < ARRAY_SIZE(config_ids); i++) {
 716                 is->config_index = config_ids[i];
 717                 fimc_is_set_initial_params(is);
 718                 ret = fimc_is_itf_s_param(is, true);
 719                 if (ret < 0) {
 720                         is->config_index = prev_id;
 721                         return ret;
 722                 }
 723         }
 724         is->config_index = prev_id;
 725
 726         set_bit(IS_ST_INIT_DONE, &is->state);
 727         dev_info(dev, "initialization sequence completed (%d)\n",
 728                                                 is->config_index);
 729         return 0;
 730 }
 731
 732 static int fimc_is_log_show(struct seq_file *s, void *data)
 733 {
 734         struct fimc_is *is = s->private;
 735         const u8 *buf = is->memory.vaddr + FIMC_IS_DEBUG_REGION_OFFSET;
 736
 737         if (is->memory.vaddr == NULL) {
 738                 dev_err(&is->pdev->dev, "firmware memory is not initialized\n");
 739                 return -EIO;
 740         }
 741
 742         seq_printf(s, "%s\n", buf);
 743         return 0;
 744 }
 745
 746 static int fimc_is_debugfs_open(struct inode *inode, struct file *file)
 747 {
 748         return single_open(file, fimc_is_log_show, inode->i_private);
 749 }
 750
 751 static const struct file_operations fimc_is_debugfs_fops = {
 752         .open           = fimc_is_debugfs_open,
 753         .read           = seq_read,
 754         .llseek         = seq_lseek,
 755         .release        = single_release,
 756 };
 757
 758 static void fimc_is_debugfs_remove(struct fimc_is *is)
 759 {
 760         debugfs_remove_recursive(is->debugfs_entry);
 761         is->debugfs_entry = NULL;
 762 }
 763
 764 static int fimc_is_debugfs_create(struct fimc_is *is)
 765 {
 766         struct dentry *dentry;
 767
 768         is->debugfs_entry = debugfs_create_dir("fimc_is", NULL);
 769
 770         dentry = debugfs_create_file("fw_log", S_IRUGO, is->debugfs_entry,
 771                                      is, &fimc_is_debugfs_fops);
 772         if (!dentry)
 773                 fimc_is_debugfs_remove(is);
 774
 775         return is->debugfs_entry == NULL ? -EIO : 0;
 776 }
 777
 778 static int fimc_is_runtime_resume(struct device *dev);
 779 static int fimc_is_runtime_suspend(struct device *dev);
 780
 781 static int fimc_is_probe(struct platform_device *pdev)
 782 {
 783         struct device *dev = &pdev->dev;
 784         struct fimc_is *is;
 785         struct resource res;
 786         struct device_node *node;
 787         int ret;
 788
 789         is = devm_kzalloc(&pdev->dev, sizeof(*is), GFP_KERNEL);
 790         if (!is)
 791                 return -ENOMEM;
 792
 793         is->pdev = pdev;
 794         is->isp.pdev = pdev;
 795
 796         init_waitqueue_head(&is->irq_queue);
 797         spin_lock_init(&is->slock);
 798         mutex_init(&is->lock);
 799
 800         ret = of_address_to_resource(dev->of_node, 0, &res);
 801         if (ret < 0)
 802                 return ret;
 803
 804         is->regs = devm_ioremap_resource(dev, &res);
 805         if (IS_ERR(is->regs))
 806                 return PTR_ERR(is->regs);
 807
 808         node = of_get_child_by_name(dev->of_node, "pmu");
 809         if (!node)
 810                 return -ENODEV;
 811
 812         is->pmu_regs = of_iomap(node, 0);
 813         if (!is->pmu_regs)
 814                 return -ENOMEM;
 815
 816         is->irq = irq_of_parse_and_map(dev->of_node, 0);
 817         if (is->irq < 0) {
 818                 dev_err(dev, "no irq found\n");
 819                 return is->irq;
 820         }
 821
 822         ret = fimc_is_get_clocks(is);
 823         if (ret < 0)
 824                 return ret;
 825
 826         platform_set_drvdata(pdev, is);
 827
 828         ret = request_irq(is->irq, fimc_is_irq_handler, 0, dev_name(dev), is);
 829         if (ret < 0) {
 830                 dev_err(dev, "irq request failed\n");
 831                 goto err_clk;
 832         }
 833         pm_runtime_enable(dev);
 834
 835         if (!pm_runtime_enabled(dev)) {
 836                 ret = fimc_is_runtime_resume(dev);
 837                 if (ret < 0)
 838                         goto err_irq;
 839         }
 840
 841         ret = pm_runtime_get_sync(dev);
 842         if (ret < 0)
 843                 goto err_pm;
 844
 845         is->alloc_ctx = vb2_dma_contig_init_ctx(dev);
 846         if (IS_ERR(is->alloc_ctx)) {
 847                 ret = PTR_ERR(is->alloc_ctx);
 848                 goto err_pm;
 849         }
 850         /*
 851          * Register FIMC-IS V4L2 subdevs to this driver. The video nodes
 852          * will be created within the subdev's registered() callback.
 853          */
 854         ret = fimc_is_register_subdevs(is);
 855         if (ret < 0)
 856                 goto err_vb;
 857
 858         ret = fimc_is_debugfs_create(is);
 859         if (ret < 0)
 860                 goto err_sd;
 861
 862         ret = fimc_is_request_firmware(is, FIMC_IS_FW_FILENAME);
 863         if (ret < 0)
 864                 goto err_dfs;
 865
 866         pm_runtime_put_sync(dev);
 867
 868         dev_dbg(dev, "FIMC-IS registered successfully\n");
 869         return 0;
 870
 871 err_dfs:
 872         fimc_is_debugfs_remove(is);
 873 err_sd:
 874         fimc_is_unregister_subdevs(is);
 875 err_vb:
 876         vb2_dma_contig_cleanup_ctx(is->alloc_ctx);
 877 err_pm:
 878         if (!pm_runtime_enabled(dev))
 879                 fimc_is_runtime_suspend(dev);
 880 err_irq:
 881         free_irq(is->irq, is);
 882 err_clk:
 883         fimc_is_put_clocks(is);
 884         return ret;
 885 }
 886
 887 static int fimc_is_runtime_resume(struct device *dev)
 888 {
 889         struct fimc_is *is = dev_get_drvdata(dev);
 890         int ret;
 891
 892         ret = fimc_is_setup_clocks(is);
 893         if (ret)
 894                 return ret;
 895
 896         return fimc_is_enable_clocks(is);
 897 }
 898
 899 static int fimc_is_runtime_suspend(struct device *dev)
 900 {
 901         struct fimc_is *is = dev_get_drvdata(dev);
 902
 903         fimc_is_disable_clocks(is);
 904         return 0;
 905 }
 906
 907 #ifdef CONFIG_PM_SLEEP
 908 static int fimc_is_resume(struct device *dev)
 909 {
 910         /* TODO: */
 911         return 0;
 912 }
 913
 914 static int fimc_is_suspend(struct device *dev)
 915 {
 916         struct fimc_is *is = dev_get_drvdata(dev);
 917
 918         /* TODO: */
 919         if (test_bit(IS_ST_A5_PWR_ON, &is->state))
 920                 return -EBUSY;
 921
 922         return 0;
 923 }
 924 #endif /* CONFIG_PM_SLEEP */
 925
 926 static int fimc_is_remove(struct platform_device *pdev)
 927 {
 928         struct device *dev = &pdev->dev;
 929         struct fimc_is *is = dev_get_drvdata(dev);
 930
 931         pm_runtime_disable(dev);
 932         pm_runtime_set_suspended(dev);
 933         if (!pm_runtime_status_suspended(dev))
 934                 fimc_is_runtime_suspend(dev);
 935         free_irq(is->irq, is);
 936         fimc_is_unregister_subdevs(is);
 937         vb2_dma_contig_cleanup_ctx(is->alloc_ctx);
 938         fimc_is_put_clocks(is);
 939         fimc_is_debugfs_remove(is);
 940         if (is->fw.f_w)
 941                 release_firmware(is->fw.f_w);
 942         fimc_is_free_cpu_memory(is);
 943
 944         return 0;
 945 }
 946
 947 static const struct of_device_id fimc_is_of_match[] = {
 948         { .compatible = "samsung,exynos4212-fimc-is" },
 949         { /* sentinel */ },
 950 };
 951 MODULE_DEVICE_TABLE(of, fimc_is_of_match);
 952
 953 static const struct dev_pm_ops fimc_is_pm_ops = {
 954         SET_SYSTEM_SLEEP_PM_OPS(fimc_is_suspend, fimc_is_resume)
 955         SET_RUNTIME_PM_OPS(fimc_is_runtime_suspend, fimc_is_runtime_resume,
 956                            NULL)
 957 };
 958
 959 static struct platform_driver fimc_is_driver = {
 960         .probe          = fimc_is_probe,
 961         .remove         = fimc_is_remove,
 962         .driver = {
 963                 .of_match_table = fimc_is_of_match,
 964                 .name           = FIMC_IS_DRV_NAME,
 965                 .owner          = THIS_MODULE,
 966                 .pm             = &fimc_is_pm_ops,
 967         }
 968 };
 969
 970 static int fimc_is_module_init(void)
 971 {
 972         int ret;
 973
 974         ret = fimc_is_register_i2c_driver();
 975         if (ret < 0)
 976                 return ret;
 977
 978         ret = platform_driver_register(&fimc_is_driver);
 979
 980         if (ret < 0)
 981                 fimc_is_unregister_i2c_driver();
 982
 983         return ret;
 984 }
 985
 986 static void fimc_is_module_exit(void)
 987 {
 988         fimc_is_unregister_i2c_driver();
 989         platform_driver_unregister(&fimc_is_driver);
 990 }
 991
 992 module_init(fimc_is_module_init);
 993 module_exit(fimc_is_module_exit);
 994
 995 MODULE_ALIAS("platform:" FIMC_IS_DRV_NAME);
 996 MODULE_AUTHOR("Younghwan Joo <yhwan.joo@samsung.com>");
 997 MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
 998 MODULE_LICENSE("GPL v2");