drivers/media/i2c/adv7842.c

   1 /*
   2  * adv7842 - Analog Devices ADV7842 video decoder driver
   3  *
   4  * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
   5  *
   6  * This program is free software; you may redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  11  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  12  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  13  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  14  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  15  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  16  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  17  * SOFTWARE.
  18  *
  19  */
  20
  21 /*
  22  * References (c = chapter, p = page):
  23  * REF_01 - Analog devices, ADV7842,
  24  *              Register Settings Recommendations, Rev. 1.9, April 2011
  25  * REF_02 - Analog devices, Software User Guide, UG-206,
  26  *              ADV7842 I2C Register Maps, Rev. 0, November 2010
  27  * REF_03 - Analog devices, Hardware User Guide, UG-214,
  28  *              ADV7842 Fast Switching 2:1 HDMI 1.4 Receiver with 3D-Comb
  29  *              Decoder and Digitizer , Rev. 0, January 2011
  30  */
  31
  32
  33 #include <linux/kernel.h>
  34 #include <linux/module.h>
  35 #include <linux/slab.h>
  36 #include <linux/i2c.h>
  37 #include <linux/delay.h>
  38 #include <linux/videodev2.h>
  39 #include <linux/workqueue.h>
  40 #include <linux/v4l2-dv-timings.h>
  41 #include <media/v4l2-device.h>
  42 #include <media/v4l2-ctrls.h>
  43 #include <media/v4l2-dv-timings.h>
  44 #include <media/adv7842.h>
  45
  46 static int debug;
  47 module_param(debug, int, 0644);
  48 MODULE_PARM_DESC(debug, "debug level (0-2)");
  49
  50 MODULE_DESCRIPTION("Analog Devices ADV7842 video decoder driver");
  51 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
  52 MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
  53 MODULE_LICENSE("GPL");
  54
  55 /* ADV7842 system clock frequency */
  56 #define ADV7842_fsc (28636360)
  57
  58 /*
  59 **********************************************************************
  60 *
  61 *  Arrays with configuration parameters for the ADV7842
  62 *
  63 **********************************************************************
  64 */
  65
  66 struct adv7842_state {
  67         struct adv7842_platform_data pdata;
  68         struct v4l2_subdev sd;
  69         struct media_pad pad;
  70         struct v4l2_ctrl_handler hdl;
  71         enum adv7842_mode mode;
  72         struct v4l2_dv_timings timings;
  73         enum adv7842_vid_std_select vid_std_select;
  74         v4l2_std_id norm;
  75         struct {
  76                 u8 edid[256];
  77                 u32 present;
  78         } hdmi_edid;
  79         struct {
  80                 u8 edid[256];
  81                 u32 present;
  82         } vga_edid;
  83         struct v4l2_fract aspect_ratio;
  84         u32 rgb_quantization_range;
  85         bool is_cea_format;
  86         struct workqueue_struct *work_queues;
  87         struct delayed_work delayed_work_enable_hotplug;
  88         bool restart_stdi_once;
  89         bool hdmi_port_a;
  90
  91         /* i2c clients */
  92         struct i2c_client *i2c_sdp_io;
  93         struct i2c_client *i2c_sdp;
  94         struct i2c_client *i2c_cp;
  95         struct i2c_client *i2c_vdp;
  96         struct i2c_client *i2c_afe;
  97         struct i2c_client *i2c_hdmi;
  98         struct i2c_client *i2c_repeater;
  99         struct i2c_client *i2c_edid;
 100         struct i2c_client *i2c_infoframe;
 101         struct i2c_client *i2c_cec;
 102         struct i2c_client *i2c_avlink;
 103
 104         /* controls */
 105         struct v4l2_ctrl *detect_tx_5v_ctrl;
 106         struct v4l2_ctrl *analog_sampling_phase_ctrl;
 107         struct v4l2_ctrl *free_run_color_ctrl_manual;
 108         struct v4l2_ctrl *free_run_color_ctrl;
 109         struct v4l2_ctrl *rgb_quantization_range_ctrl;
 110 };
 111
 112 /* Unsupported timings. This device cannot support 720p30. */
 113 static const struct v4l2_dv_timings adv7842_timings_exceptions[] = {
 114         V4L2_DV_BT_CEA_1280X720P30,
 115         { }
 116 };
 117
 118 static bool adv7842_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
 119 {
 120         int i;
 121
 122         for (i = 0; adv7842_timings_exceptions[i].bt.width; i++)
 123                 if (v4l2_match_dv_timings(t, adv7842_timings_exceptions + i, 0))
 124                         return false;
 125         return true;
 126 }
 127
 128 struct adv7842_video_standards {
 129         struct v4l2_dv_timings timings;
 130         u8 vid_std;
 131         u8 v_freq;
 132 };
 133
 134 /* sorted by number of lines */
 135 static const struct adv7842_video_standards adv7842_prim_mode_comp[] = {
 136         /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
 137         { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
 138         { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
 139         { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
 140         { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
 141         { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
 142         { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
 143         { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
 144         { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
 145         /* TODO add 1920x1080P60_RB (CVT timing) */
 146         { },
 147 };
 148
 149 /* sorted by number of lines */
 150 static const struct adv7842_video_standards adv7842_prim_mode_gr[] = {
 151         { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
 152         { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
 153         { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
 154         { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
 155         { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
 156         { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
 157         { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
 158         { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
 159         { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
 160         { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
 161         { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
 162         { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
 163         { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
 164         { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
 165         { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
 166         { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
 167         { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
 168         { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
 169         { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
 170         { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
 171         /* TODO add 1600X1200P60_RB (not a DMT timing) */
 172         { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
 173         { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
 174         { },
 175 };
 176
 177 /* sorted by number of lines */
 178 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_comp[] = {
 179         { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
 180         { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
 181         { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
 182         { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
 183         { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
 184         { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
 185         { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
 186         { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
 187         { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
 188         { },
 189 };
 190
 191 /* sorted by number of lines */
 192 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_gr[] = {
 193         { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
 194         { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
 195         { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
 196         { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
 197         { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
 198         { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
 199         { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
 200         { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
 201         { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
 202         { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
 203         { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
 204         { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
 205         { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
 206         { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
 207         { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
 208         { },
 209 };
 210
 211 /* ----------------------------------------------------------------------- */
 212
 213 static inline struct adv7842_state *to_state(struct v4l2_subdev *sd)
 214 {
 215         return container_of(sd, struct adv7842_state, sd);
 216 }
 217
 218 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
 219 {
 220         return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd;
 221 }
 222
 223 static inline unsigned hblanking(const struct v4l2_bt_timings *t)
 224 {
 225         return V4L2_DV_BT_BLANKING_WIDTH(t);
 226 }
 227
 228 static inline unsigned htotal(const struct v4l2_bt_timings *t)
 229 {
 230         return V4L2_DV_BT_FRAME_WIDTH(t);
 231 }
 232
 233 static inline unsigned vblanking(const struct v4l2_bt_timings *t)
 234 {
 235         return V4L2_DV_BT_BLANKING_HEIGHT(t);
 236 }
 237
 238 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
 239 {
 240         return V4L2_DV_BT_FRAME_HEIGHT(t);
 241 }
 242
 243
 244 /* ----------------------------------------------------------------------- */
 245
 246 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
 247                                           u8 command, bool check)
 248 {
 249         union i2c_smbus_data data;
 250
 251         if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
 252                             I2C_SMBUS_READ, command,
 253                             I2C_SMBUS_BYTE_DATA, &data))
 254                 return data.byte;
 255         if (check)
 256                 v4l_err(client, "error reading %02x, %02x\n",
 257                         client->addr, command);
 258         return -EIO;
 259 }
 260
 261 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
 262 {
 263         int i;
 264
 265         for (i = 0; i < 3; i++) {
 266                 int ret = adv_smbus_read_byte_data_check(client, command, true);
 267
 268                 if (ret >= 0) {
 269                         if (i)
 270                                 v4l_err(client, "read ok after %d retries\n", i);
 271                         return ret;
 272                 }
 273         }
 274         v4l_err(client, "read failed\n");
 275         return -EIO;
 276 }
 277
 278 static s32 adv_smbus_write_byte_data(struct i2c_client *client,
 279                                      u8 command, u8 value)
 280 {
 281         union i2c_smbus_data data;
 282         int err;
 283         int i;
 284
 285         data.byte = value;
 286         for (i = 0; i < 3; i++) {
 287                 err = i2c_smbus_xfer(client->adapter, client->addr,
 288                                      client->flags,
 289                                      I2C_SMBUS_WRITE, command,
 290                                      I2C_SMBUS_BYTE_DATA, &data);
 291                 if (!err)
 292                         break;
 293         }
 294         if (err < 0)
 295                 v4l_err(client, "error writing %02x, %02x, %02x\n",
 296                         client->addr, command, value);
 297         return err;
 298 }
 299
 300 static void adv_smbus_write_byte_no_check(struct i2c_client *client,
 301                                           u8 command, u8 value)
 302 {
 303         union i2c_smbus_data data;
 304         data.byte = value;
 305
 306         i2c_smbus_xfer(client->adapter, client->addr,
 307                        client->flags,
 308                        I2C_SMBUS_WRITE, command,
 309                        I2C_SMBUS_BYTE_DATA, &data);
 310 }
 311
 312 static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
 313                                   u8 command, unsigned length, const u8 *values)
 314 {
 315         union i2c_smbus_data data;
 316
 317         if (length > I2C_SMBUS_BLOCK_MAX)
 318                 length = I2C_SMBUS_BLOCK_MAX;
 319         data.block[0] = length;
 320         memcpy(data.block + 1, values, length);
 321         return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
 322                               I2C_SMBUS_WRITE, command,
 323                               I2C_SMBUS_I2C_BLOCK_DATA, &data);
 324 }
 325
 326 /* ----------------------------------------------------------------------- */
 327
 328 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
 329 {
 330         struct i2c_client *client = v4l2_get_subdevdata(sd);
 331
 332         return adv_smbus_read_byte_data(client, reg);
 333 }
 334
 335 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 336 {
 337         struct i2c_client *client = v4l2_get_subdevdata(sd);
 338
 339         return adv_smbus_write_byte_data(client, reg, val);
 340 }
 341
 342 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 343 {
 344         return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
 345 }
 346
 347 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
 348 {
 349         struct adv7842_state *state = to_state(sd);
 350
 351         return adv_smbus_read_byte_data(state->i2c_avlink, reg);
 352 }
 353
 354 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 355 {
 356         struct adv7842_state *state = to_state(sd);
 357
 358         return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
 359 }
 360
 361 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
 362 {
 363         struct adv7842_state *state = to_state(sd);
 364
 365         return adv_smbus_read_byte_data(state->i2c_cec, reg);
 366 }
 367
 368 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 369 {
 370         struct adv7842_state *state = to_state(sd);
 371
 372         return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
 373 }
 374
 375 static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 376 {
 377         return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val);
 378 }
 379
 380 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
 381 {
 382         struct adv7842_state *state = to_state(sd);
 383
 384         return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
 385 }
 386
 387 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 388 {
 389         struct adv7842_state *state = to_state(sd);
 390
 391         return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
 392 }
 393
 394 static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg)
 395 {
 396         struct adv7842_state *state = to_state(sd);
 397
 398         return adv_smbus_read_byte_data(state->i2c_sdp_io, reg);
 399 }
 400
 401 static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 402 {
 403         struct adv7842_state *state = to_state(sd);
 404
 405         return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val);
 406 }
 407
 408 static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 409 {
 410         return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val);
 411 }
 412
 413 static inline int sdp_read(struct v4l2_subdev *sd, u8 reg)
 414 {
 415         struct adv7842_state *state = to_state(sd);
 416
 417         return adv_smbus_read_byte_data(state->i2c_sdp, reg);
 418 }
 419
 420 static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 421 {
 422         struct adv7842_state *state = to_state(sd);
 423
 424         return adv_smbus_write_byte_data(state->i2c_sdp, reg, val);
 425 }
 426
 427 static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 428 {
 429         return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val);
 430 }
 431
 432 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
 433 {
 434         struct adv7842_state *state = to_state(sd);
 435
 436         return adv_smbus_read_byte_data(state->i2c_afe, reg);
 437 }
 438
 439 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 440 {
 441         struct adv7842_state *state = to_state(sd);
 442
 443         return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
 444 }
 445
 446 static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 447 {
 448         return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val);
 449 }
 450
 451 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
 452 {
 453         struct adv7842_state *state = to_state(sd);
 454
 455         return adv_smbus_read_byte_data(state->i2c_repeater, reg);
 456 }
 457
 458 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 459 {
 460         struct adv7842_state *state = to_state(sd);
 461
 462         return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
 463 }
 464
 465 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 466 {
 467         return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
 468 }
 469
 470 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
 471 {
 472         struct adv7842_state *state = to_state(sd);
 473
 474         return adv_smbus_read_byte_data(state->i2c_edid, reg);
 475 }
 476
 477 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 478 {
 479         struct adv7842_state *state = to_state(sd);
 480
 481         return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
 482 }
 483
 484 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
 485 {
 486         struct adv7842_state *state = to_state(sd);
 487
 488         return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
 489 }
 490
 491 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 492 {
 493         struct adv7842_state *state = to_state(sd);
 494
 495         return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
 496 }
 497
 498 static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 499 {
 500         return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val);
 501 }
 502
 503 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
 504 {
 505         struct adv7842_state *state = to_state(sd);
 506
 507         return adv_smbus_read_byte_data(state->i2c_cp, reg);
 508 }
 509
 510 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 511 {
 512         struct adv7842_state *state = to_state(sd);
 513
 514         return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
 515 }
 516
 517 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 518 {
 519         return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
 520 }
 521
 522 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
 523 {
 524         struct adv7842_state *state = to_state(sd);
 525
 526         return adv_smbus_read_byte_data(state->i2c_vdp, reg);
 527 }
 528
 529 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 530 {
 531         struct adv7842_state *state = to_state(sd);
 532
 533         return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
 534 }
 535
 536 static void main_reset(struct v4l2_subdev *sd)
 537 {
 538         struct i2c_client *client = v4l2_get_subdevdata(sd);
 539
 540         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
 541
 542         adv_smbus_write_byte_no_check(client, 0xff, 0x80);
 543
 544         mdelay(5);
 545 }
 546
 547 /* ----------------------------------------------------------------------- */
 548
 549 static inline bool is_analog_input(struct v4l2_subdev *sd)
 550 {
 551         struct adv7842_state *state = to_state(sd);
 552
 553         return ((state->mode == ADV7842_MODE_RGB) ||
 554                 (state->mode == ADV7842_MODE_COMP));
 555 }
 556
 557 static inline bool is_digital_input(struct v4l2_subdev *sd)
 558 {
 559         struct adv7842_state *state = to_state(sd);
 560
 561         return state->mode == ADV7842_MODE_HDMI;
 562 }
 563
 564 static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = {
 565         .type = V4L2_DV_BT_656_1120,
 566         /* keep this initialization for compatibility with GCC < 4.4.6 */
 567         .reserved = { 0 },
 568         V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000,
 569                 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
 570                         V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
 571                 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
 572                         V4L2_DV_BT_CAP_CUSTOM)
 573 };
 574
 575 static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = {
 576         .type = V4L2_DV_BT_656_1120,
 577         /* keep this initialization for compatibility with GCC < 4.4.6 */
 578         .reserved = { 0 },
 579         V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000,
 580                 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
 581                         V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
 582                 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
 583                         V4L2_DV_BT_CAP_CUSTOM)
 584 };
 585
 586 static inline const struct v4l2_dv_timings_cap *
 587 adv7842_get_dv_timings_cap(struct v4l2_subdev *sd)
 588 {
 589         return is_digital_input(sd) ? &adv7842_timings_cap_digital :
 590                                       &adv7842_timings_cap_analog;
 591 }
 592
 593 /* ----------------------------------------------------------------------- */
 594
 595 static void adv7842_delayed_work_enable_hotplug(struct work_struct *work)
 596 {
 597         struct delayed_work *dwork = to_delayed_work(work);
 598         struct adv7842_state *state = container_of(dwork,
 599                         struct adv7842_state, delayed_work_enable_hotplug);
 600         struct v4l2_subdev *sd = &state->sd;
 601         int present = state->hdmi_edid.present;
 602         u8 mask = 0;
 603
 604         v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n",
 605                         __func__, present);
 606
 607         if (present & (0x04 << ADV7842_EDID_PORT_A))
 608                 mask |= 0x20;
 609         if (present & (0x04 << ADV7842_EDID_PORT_B))
 610                 mask |= 0x10;
 611         io_write_and_or(sd, 0x20, 0xcf, mask);
 612 }
 613
 614 static int edid_write_vga_segment(struct v4l2_subdev *sd)
 615 {
 616         struct i2c_client *client = v4l2_get_subdevdata(sd);
 617         struct adv7842_state *state = to_state(sd);
 618         const u8 *val = state->vga_edid.edid;
 619         int err = 0;
 620         int i;
 621
 622         v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__);
 623
 624         /* HPA disable on port A and B */
 625         io_write_and_or(sd, 0x20, 0xcf, 0x00);
 626
 627         /* Disable I2C access to internal EDID ram from VGA DDC port */
 628         rep_write_and_or(sd, 0x7f, 0x7f, 0x00);
 629
 630         /* edid segment pointer '1' for VGA port */
 631         rep_write_and_or(sd, 0x77, 0xef, 0x10);
 632
 633         for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
 634                 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
 635                                              I2C_SMBUS_BLOCK_MAX, val + i);
 636         if (err)
 637                 return err;
 638
 639         /* Calculates the checksums and enables I2C access
 640          * to internal EDID ram from VGA DDC port.
 641          */
 642         rep_write_and_or(sd, 0x7f, 0x7f, 0x80);
 643
 644         for (i = 0; i < 1000; i++) {
 645                 if (rep_read(sd, 0x79) & 0x20)
 646                         break;
 647                 mdelay(1);
 648         }
 649         if (i == 1000) {
 650                 v4l_err(client, "error enabling edid on VGA port\n");
 651                 return -EIO;
 652         }
 653
 654         /* enable hotplug after 200 ms */
 655         queue_delayed_work(state->work_queues,
 656                         &state->delayed_work_enable_hotplug, HZ / 5);
 657
 658         return 0;
 659 }
 660
 661 static int edid_spa_location(const u8 *edid)
 662 {
 663         u8 d;
 664
 665         /*
 666          * TODO, improve and update for other CEA extensions
 667          * currently only for 1 segment (256 bytes),
 668          * i.e. 1 extension block and CEA revision 3.
 669          */
 670         if ((edid[0x7e] != 1) ||
 671             (edid[0x80] != 0x02) ||
 672             (edid[0x81] != 0x03)) {
 673                 return -EINVAL;
 674         }
 675         /*
 676          * search Vendor Specific Data Block (tag 3)
 677          */
 678         d = edid[0x82] & 0x7f;
 679         if (d > 4) {
 680                 int i = 0x84;
 681                 int end = 0x80 + d;
 682                 do {
 683                         u8 tag = edid[i]>>5;
 684                         u8 len = edid[i] & 0x1f;
 685
 686                         if ((tag == 3) && (len >= 5))
 687                                 return i + 4;
 688                         i += len + 1;
 689                 } while (i < end);
 690         }
 691         return -EINVAL;
 692 }
 693
 694 static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port)
 695 {
 696         struct i2c_client *client = v4l2_get_subdevdata(sd);
 697         struct adv7842_state *state = to_state(sd);
 698         const u8 *val = state->hdmi_edid.edid;
 699         int spa_loc = edid_spa_location(val);
 700         int err = 0;
 701         int i;
 702
 703         v4l2_dbg(2, debug, sd, "%s: write EDID on port %c (spa at 0x%x)\n",
 704                         __func__, (port == ADV7842_EDID_PORT_A) ? 'A' : 'B', spa_loc);
 705
 706         /* HPA disable on port A and B */
 707         io_write_and_or(sd, 0x20, 0xcf, 0x00);
 708
 709         /* Disable I2C access to internal EDID ram from HDMI DDC ports */
 710         rep_write_and_or(sd, 0x77, 0xf3, 0x00);
 711
 712         if (!state->hdmi_edid.present)
 713                 return 0;
 714
 715         /* edid segment pointer '0' for HDMI ports */
 716         rep_write_and_or(sd, 0x77, 0xef, 0x00);
 717
 718         for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
 719                 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
 720                                                      I2C_SMBUS_BLOCK_MAX, val + i);
 721         if (err)
 722                 return err;
 723
 724         if (spa_loc < 0)
 725                 spa_loc = 0xc0; /* Default value [REF_02, p. 199] */
 726
 727         if (port == ADV7842_EDID_PORT_A) {
 728                 rep_write(sd, 0x72, val[spa_loc]);
 729                 rep_write(sd, 0x73, val[spa_loc + 1]);
 730         } else {
 731                 rep_write(sd, 0x74, val[spa_loc]);
 732                 rep_write(sd, 0x75, val[spa_loc + 1]);
 733         }
 734         rep_write(sd, 0x76, spa_loc & 0xff);
 735         rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40);
 736
 737         /* Calculates the checksums and enables I2C access to internal
 738          * EDID ram from HDMI DDC ports
 739          */
 740         rep_write_and_or(sd, 0x77, 0xf3, state->hdmi_edid.present);
 741
 742         for (i = 0; i < 1000; i++) {
 743                 if (rep_read(sd, 0x7d) & state->hdmi_edid.present)
 744                         break;
 745                 mdelay(1);
 746         }
 747         if (i == 1000) {
 748                 v4l_err(client, "error enabling edid on port %c\n",
 749                                 (port == ADV7842_EDID_PORT_A) ? 'A' : 'B');
 750                 return -EIO;
 751         }
 752
 753         /* enable hotplug after 200 ms */
 754         queue_delayed_work(state->work_queues,
 755                         &state->delayed_work_enable_hotplug, HZ / 5);
 756
 757         return 0;
 758 }
 759
 760 /* ----------------------------------------------------------------------- */
 761
 762 #ifdef CONFIG_VIDEO_ADV_DEBUG
 763 static void adv7842_inv_register(struct v4l2_subdev *sd)
 764 {
 765         v4l2_info(sd, "0x000-0x0ff: IO Map\n");
 766         v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
 767         v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
 768         v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
 769         v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n");
 770         v4l2_info(sd, "0x500-0x5ff: SDP Map\n");
 771         v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
 772         v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
 773         v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
 774         v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
 775         v4l2_info(sd, "0xa00-0xaff: CP Map\n");
 776         v4l2_info(sd, "0xb00-0xbff: VDP Map\n");
 777 }
 778
 779 static int adv7842_g_register(struct v4l2_subdev *sd,
 780                               struct v4l2_dbg_register *reg)
 781 {
 782         reg->size = 1;
 783         switch (reg->reg >> 8) {
 784         case 0:
 785                 reg->val = io_read(sd, reg->reg & 0xff);
 786                 break;
 787         case 1:
 788                 reg->val = avlink_read(sd, reg->reg & 0xff);
 789                 break;
 790         case 2:
 791                 reg->val = cec_read(sd, reg->reg & 0xff);
 792                 break;
 793         case 3:
 794                 reg->val = infoframe_read(sd, reg->reg & 0xff);
 795                 break;
 796         case 4:
 797                 reg->val = sdp_io_read(sd, reg->reg & 0xff);
 798                 break;
 799         case 5:
 800                 reg->val = sdp_read(sd, reg->reg & 0xff);
 801                 break;
 802         case 6:
 803                 reg->val = afe_read(sd, reg->reg & 0xff);
 804                 break;
 805         case 7:
 806                 reg->val = rep_read(sd, reg->reg & 0xff);
 807                 break;
 808         case 8:
 809                 reg->val = edid_read(sd, reg->reg & 0xff);
 810                 break;
 811         case 9:
 812                 reg->val = hdmi_read(sd, reg->reg & 0xff);
 813                 break;
 814         case 0xa:
 815                 reg->val = cp_read(sd, reg->reg & 0xff);
 816                 break;
 817         case 0xb:
 818                 reg->val = vdp_read(sd, reg->reg & 0xff);
 819                 break;
 820         default:
 821                 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
 822                 adv7842_inv_register(sd);
 823                 break;
 824         }
 825         return 0;
 826 }
 827
 828 static int adv7842_s_register(struct v4l2_subdev *sd,
 829                 const struct v4l2_dbg_register *reg)
 830 {
 831         u8 val = reg->val & 0xff;
 832
 833         switch (reg->reg >> 8) {
 834         case 0:
 835                 io_write(sd, reg->reg & 0xff, val);
 836                 break;
 837         case 1:
 838                 avlink_write(sd, reg->reg & 0xff, val);
 839                 break;
 840         case 2:
 841                 cec_write(sd, reg->reg & 0xff, val);
 842                 break;
 843         case 3:
 844                 infoframe_write(sd, reg->reg & 0xff, val);
 845                 break;
 846         case 4:
 847                 sdp_io_write(sd, reg->reg & 0xff, val);
 848                 break;
 849         case 5:
 850                 sdp_write(sd, reg->reg & 0xff, val);
 851                 break;
 852         case 6:
 853                 afe_write(sd, reg->reg & 0xff, val);
 854                 break;
 855         case 7:
 856                 rep_write(sd, reg->reg & 0xff, val);
 857                 break;
 858         case 8:
 859                 edid_write(sd, reg->reg & 0xff, val);
 860                 break;
 861         case 9:
 862                 hdmi_write(sd, reg->reg & 0xff, val);
 863                 break;
 864         case 0xa:
 865                 cp_write(sd, reg->reg & 0xff, val);
 866                 break;
 867         case 0xb:
 868                 vdp_write(sd, reg->reg & 0xff, val);
 869                 break;
 870         default:
 871                 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
 872                 adv7842_inv_register(sd);
 873                 break;
 874         }
 875         return 0;
 876 }
 877 #endif
 878
 879 static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
 880 {
 881         struct adv7842_state *state = to_state(sd);
 882         int prev = v4l2_ctrl_g_ctrl(state->detect_tx_5v_ctrl);
 883         u8 reg_io_6f = io_read(sd, 0x6f);
 884         int val = 0;
 885
 886         if (reg_io_6f & 0x02)
 887                 val |= 1; /* port A */
 888         if (reg_io_6f & 0x01)
 889                 val |= 2; /* port B */
 890
 891         v4l2_dbg(1, debug, sd, "%s: 0x%x -> 0x%x\n", __func__, prev, val);
 892
 893         if (val != prev)
 894                 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, val);
 895         return 0;
 896 }
 897
 898 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
 899                 u8 prim_mode,
 900                 const struct adv7842_video_standards *predef_vid_timings,
 901                 const struct v4l2_dv_timings *timings)
 902 {
 903         int i;
 904
 905         for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
 906                 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
 907                                           is_digital_input(sd) ? 250000 : 1000000))
 908                         continue;
 909                 /* video std */
 910                 io_write(sd, 0x00, predef_vid_timings[i].vid_std);
 911                 /* v_freq and prim mode */
 912                 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode);
 913                 return 0;
 914         }
 915
 916         return -1;
 917 }
 918
 919 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
 920                 struct v4l2_dv_timings *timings)
 921 {
 922         struct adv7842_state *state = to_state(sd);
 923         int err;
 924
 925         v4l2_dbg(1, debug, sd, "%s\n", __func__);
 926
 927         /* reset to default values */
 928         io_write(sd, 0x16, 0x43);
 929         io_write(sd, 0x17, 0x5a);
 930         /* disable embedded syncs for auto graphics mode */
 931         cp_write_and_or(sd, 0x81, 0xef, 0x00);
 932         cp_write(sd, 0x26, 0x00);
 933         cp_write(sd, 0x27, 0x00);
 934         cp_write(sd, 0x28, 0x00);
 935         cp_write(sd, 0x29, 0x00);
 936         cp_write(sd, 0x8f, 0x40);
 937         cp_write(sd, 0x90, 0x00);
 938         cp_write(sd, 0xa5, 0x00);
 939         cp_write(sd, 0xa6, 0x00);
 940         cp_write(sd, 0xa7, 0x00);
 941         cp_write(sd, 0xab, 0x00);
 942         cp_write(sd, 0xac, 0x00);
 943
 944         switch (state->mode) {
 945         case ADV7842_MODE_COMP:
 946         case ADV7842_MODE_RGB:
 947                 err = find_and_set_predefined_video_timings(sd,
 948                                 0x01, adv7842_prim_mode_comp, timings);
 949                 if (err)
 950                         err = find_and_set_predefined_video_timings(sd,
 951                                         0x02, adv7842_prim_mode_gr, timings);
 952                 break;
 953         case ADV7842_MODE_HDMI:
 954                 err = find_and_set_predefined_video_timings(sd,
 955                                 0x05, adv7842_prim_mode_hdmi_comp, timings);
 956                 if (err)
 957                         err = find_and_set_predefined_video_timings(sd,
 958                                         0x06, adv7842_prim_mode_hdmi_gr, timings);
 959                 break;
 960         default:
 961                 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
 962                                 __func__, state->mode);
 963                 err = -1;
 964                 break;
 965         }
 966
 967
 968         return err;
 969 }
 970
 971 static void configure_custom_video_timings(struct v4l2_subdev *sd,
 972                 const struct v4l2_bt_timings *bt)
 973 {
 974         struct adv7842_state *state = to_state(sd);
 975         struct i2c_client *client = v4l2_get_subdevdata(sd);
 976         u32 width = htotal(bt);
 977         u32 height = vtotal(bt);
 978         u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
 979         u16 cp_start_eav = width - bt->hfrontporch;
 980         u16 cp_start_vbi = height - bt->vfrontporch + 1;
 981         u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1;
 982         u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
 983                 ((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
 984         const u8 pll[2] = {
 985                 0xc0 | ((width >> 8) & 0x1f),
 986                 width & 0xff
 987         };
 988
 989         v4l2_dbg(2, debug, sd, "%s\n", __func__);
 990
 991         switch (state->mode) {
 992         case ADV7842_MODE_COMP:
 993         case ADV7842_MODE_RGB:
 994                 /* auto graphics */
 995                 io_write(sd, 0x00, 0x07); /* video std */
 996                 io_write(sd, 0x01, 0x02); /* prim mode */
 997                 /* enable embedded syncs for auto graphics mode */
 998                 cp_write_and_or(sd, 0x81, 0xef, 0x10);
 999
1000                 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
1001                 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
1002                 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
1003                 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) {
1004                         v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
1005                         break;
1006                 }
1007
1008                 /* active video - horizontal timing */
1009                 cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf);
1010                 cp_write(sd, 0x27, (cp_start_sav & 0xff));
1011                 cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf);
1012                 cp_write(sd, 0x29, (cp_start_eav & 0xff));
1013
1014                 /* active video - vertical timing */
1015                 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
1016                 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
1017                                         ((cp_end_vbi >> 8) & 0xf));
1018                 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
1019                 break;
1020         case ADV7842_MODE_HDMI:
1021                 /* set default prim_mode/vid_std for HDMI
1022                    according to [REF_03, c. 4.2] */
1023                 io_write(sd, 0x00, 0x02); /* video std */
1024                 io_write(sd, 0x01, 0x06); /* prim mode */
1025                 break;
1026         default:
1027                 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1028                                 __func__, state->mode);
1029                 break;
1030         }
1031
1032         cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1033         cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1034         cp_write(sd, 0xab, (height >> 4) & 0xff);
1035         cp_write(sd, 0xac, (height & 0x0f) << 4);
1036 }
1037
1038 static void adv7842_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
1039 {
1040         struct adv7842_state *state = to_state(sd);
1041         u8 offset_buf[4];
1042
1043         if (auto_offset) {
1044                 offset_a = 0x3ff;
1045                 offset_b = 0x3ff;
1046                 offset_c = 0x3ff;
1047         }
1048
1049         v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
1050                  __func__, auto_offset ? "Auto" : "Manual",
1051                  offset_a, offset_b, offset_c);
1052
1053         offset_buf[0]= (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
1054         offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1055         offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1056         offset_buf[3] = offset_c & 0x0ff;
1057
1058         /* Registers must be written in this order with no i2c access in between */
1059         if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x77, 4, offset_buf))
1060                 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1061 }
1062
1063 static void adv7842_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
1064 {
1065         struct adv7842_state *state = to_state(sd);
1066         u8 gain_buf[4];
1067         u8 gain_man = 1;
1068         u8 agc_mode_man = 1;
1069
1070         if (auto_gain) {
1071                 gain_man = 0;
1072                 agc_mode_man = 0;
1073                 gain_a = 0x100;
1074                 gain_b = 0x100;
1075                 gain_c = 0x100;
1076         }
1077
1078         v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1079                  __func__, auto_gain ? "Auto" : "Manual",
1080                  gain_a, gain_b, gain_c);
1081
1082         gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1083         gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1084         gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1085         gain_buf[3] = ((gain_c & 0x0ff));
1086
1087         /* Registers must be written in this order with no i2c access in between */
1088         if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x73, 4, gain_buf))
1089                 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1090 }
1091
1092 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1093 {
1094         struct adv7842_state *state = to_state(sd);
1095         bool rgb_output = io_read(sd, 0x02) & 0x02;
1096         bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1097
1098         v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1099                         __func__, state->rgb_quantization_range,
1100                         rgb_output, hdmi_signal);
1101
1102         adv7842_set_gain(sd, true, 0x0, 0x0, 0x0);
1103         adv7842_set_offset(sd, true, 0x0, 0x0, 0x0);
1104
1105         switch (state->rgb_quantization_range) {
1106         case V4L2_DV_RGB_RANGE_AUTO:
1107                 if (state->mode == ADV7842_MODE_RGB) {
1108                         /* Receiving analog RGB signal
1109                          * Set RGB full range (0-255) */
1110                         io_write_and_or(sd, 0x02, 0x0f, 0x10);
1111                         break;
1112                 }
1113
1114                 if (state->mode == ADV7842_MODE_COMP) {
1115                         /* Receiving analog YPbPr signal
1116                          * Set automode */
1117                         io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1118                         break;
1119                 }
1120
1121                 if (hdmi_signal) {
1122                         /* Receiving HDMI signal
1123                          * Set automode */
1124                         io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1125                         break;
1126                 }
1127
1128                 /* Receiving DVI-D signal
1129                  * ADV7842 selects RGB limited range regardless of
1130                  * input format (CE/IT) in automatic mode */
1131                 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1132                         /* RGB limited range (16-235) */
1133                         io_write_and_or(sd, 0x02, 0x0f, 0x00);
1134                 } else {
1135                         /* RGB full range (0-255) */
1136                         io_write_and_or(sd, 0x02, 0x0f, 0x10);
1137
1138                         if (is_digital_input(sd) && rgb_output) {
1139                                 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);
1140                         } else {
1141                                 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1142                                 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);
1143                         }
1144                 }
1145                 break;
1146         case V4L2_DV_RGB_RANGE_LIMITED:
1147                 if (state->mode == ADV7842_MODE_COMP) {
1148                         /* YCrCb limited range (16-235) */
1149                         io_write_and_or(sd, 0x02, 0x0f, 0x20);
1150                         break;
1151                 }
1152
1153                 /* RGB limited range (16-235) */
1154                 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1155
1156                 break;
1157         case V4L2_DV_RGB_RANGE_FULL:
1158                 if (state->mode == ADV7842_MODE_COMP) {
1159                         /* YCrCb full range (0-255) */
1160                         io_write_and_or(sd, 0x02, 0x0f, 0x60);
1161                         break;
1162                 }
1163
1164                 /* RGB full range (0-255) */
1165                 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1166
1167                 if (is_analog_input(sd) || hdmi_signal)
1168                         break;
1169
1170                 /* Adjust gain/offset for DVI-D signals only */
1171                 if (rgb_output) {
1172                         adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);
1173                 } else {
1174                         adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1175                         adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);
1176                 }
1177                 break;
1178         }
1179 }
1180
1181 static int adv7842_s_ctrl(struct v4l2_ctrl *ctrl)
1182 {
1183         struct v4l2_subdev *sd = to_sd(ctrl);
1184         struct adv7842_state *state = to_state(sd);
1185
1186         /* TODO SDP ctrls
1187            contrast/brightness/hue/free run is acting a bit strange,
1188            not sure if sdp csc is correct.
1189          */
1190         switch (ctrl->id) {
1191         /* standard ctrls */
1192         case V4L2_CID_BRIGHTNESS:
1193                 cp_write(sd, 0x3c, ctrl->val);
1194                 sdp_write(sd, 0x14, ctrl->val);
1195                 /* ignore lsb sdp 0x17[3:2] */
1196                 return 0;
1197         case V4L2_CID_CONTRAST:
1198                 cp_write(sd, 0x3a, ctrl->val);
1199                 sdp_write(sd, 0x13, ctrl->val);
1200                 /* ignore lsb sdp 0x17[1:0] */
1201                 return 0;
1202         case V4L2_CID_SATURATION:
1203                 cp_write(sd, 0x3b, ctrl->val);
1204                 sdp_write(sd, 0x15, ctrl->val);
1205                 /* ignore lsb sdp 0x17[5:4] */
1206                 return 0;
1207         case V4L2_CID_HUE:
1208                 cp_write(sd, 0x3d, ctrl->val);
1209                 sdp_write(sd, 0x16, ctrl->val);
1210                 /* ignore lsb sdp 0x17[7:6] */
1211                 return 0;
1212                 /* custom ctrls */
1213         case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1214                 afe_write(sd, 0xc8, ctrl->val);
1215                 return 0;
1216         case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1217                 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
1218                 sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2));
1219                 return 0;
1220         case V4L2_CID_ADV_RX_FREE_RUN_COLOR: {
1221                 u8 R = (ctrl->val & 0xff0000) >> 16;
1222                 u8 G = (ctrl->val & 0x00ff00) >> 8;
1223                 u8 B = (ctrl->val & 0x0000ff);
1224                 /* RGB -> YUV, numerical approximation */
1225                 int Y = 66 * R + 129 * G + 25 * B;
1226                 int U = -38 * R - 74 * G + 112 * B;
1227                 int V = 112 * R - 94 * G - 18 * B;
1228
1229                 /* Scale down to 8 bits with rounding */
1230                 Y = (Y + 128) >> 8;
1231                 U = (U + 128) >> 8;
1232                 V = (V + 128) >> 8;
1233                 /* make U,V positive */
1234                 Y += 16;
1235                 U += 128;
1236                 V += 128;
1237
1238                 v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B);
1239                 v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V);
1240
1241                 /* CP */
1242                 cp_write(sd, 0xc1, R);
1243                 cp_write(sd, 0xc0, G);
1244                 cp_write(sd, 0xc2, B);
1245                 /* SDP */
1246                 sdp_write(sd, 0xde, Y);
1247                 sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f));
1248                 return 0;
1249         }
1250         case V4L2_CID_DV_RX_RGB_RANGE:
1251                 state->rgb_quantization_range = ctrl->val;
1252                 set_rgb_quantization_range(sd);
1253                 return 0;
1254         }
1255         return -EINVAL;
1256 }
1257
1258 static inline bool no_power(struct v4l2_subdev *sd)
1259 {
1260         return io_read(sd, 0x0c) & 0x24;
1261 }
1262
1263 static inline bool no_cp_signal(struct v4l2_subdev *sd)
1264 {
1265         return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80);
1266 }
1267
1268 static inline bool is_hdmi(struct v4l2_subdev *sd)
1269 {
1270         return hdmi_read(sd, 0x05) & 0x80;
1271 }
1272
1273 static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status)
1274 {
1275         struct adv7842_state *state = to_state(sd);
1276
1277         *status = 0;
1278
1279         if (io_read(sd, 0x0c) & 0x24)
1280                 *status |= V4L2_IN_ST_NO_POWER;
1281
1282         if (state->mode == ADV7842_MODE_SDP) {
1283                 /* status from SDP block */
1284                 if (!(sdp_read(sd, 0x5A) & 0x01))
1285                         *status |= V4L2_IN_ST_NO_SIGNAL;
1286
1287                 v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n",
1288                                 __func__, *status);
1289                 return 0;
1290         }
1291         /* status from CP block */
1292         if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 ||
1293                         !(cp_read(sd, 0xb1) & 0x80))
1294                 /* TODO channel 2 */
1295                 *status |= V4L2_IN_ST_NO_SIGNAL;
1296
1297         if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03))
1298                 *status |= V4L2_IN_ST_NO_SIGNAL;
1299
1300         v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n",
1301                         __func__, *status);
1302
1303         return 0;
1304 }
1305
1306 struct stdi_readback {
1307         u16 bl, lcf, lcvs;
1308         u8 hs_pol, vs_pol;
1309         bool interlaced;
1310 };
1311
1312 static int stdi2dv_timings(struct v4l2_subdev *sd,
1313                 struct stdi_readback *stdi,
1314                 struct v4l2_dv_timings *timings)
1315 {
1316         struct adv7842_state *state = to_state(sd);
1317         u32 hfreq = (ADV7842_fsc * 8) / stdi->bl;
1318         u32 pix_clk;
1319         int i;
1320
1321         for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1322                 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
1323
1324                 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
1325                                            adv7842_get_dv_timings_cap(sd),
1326                                            adv7842_check_dv_timings, NULL))
1327                         continue;
1328                 if (vtotal(bt) != stdi->lcf + 1)
1329                         continue;
1330                 if (bt->vsync != stdi->lcvs)
1331                         continue;
1332
1333                 pix_clk = hfreq * htotal(bt);
1334
1335                 if ((pix_clk < bt->pixelclock + 1000000) &&
1336                     (pix_clk > bt->pixelclock - 1000000)) {
1337                         *timings = v4l2_dv_timings_presets[i];
1338                         return 0;
1339                 }
1340         }
1341
1342         if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1343                         (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1344                         (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1345                             timings))
1346                 return 0;
1347         if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1348                         (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1349                         (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1350                             state->aspect_ratio, timings))
1351                 return 0;
1352
1353         v4l2_dbg(2, debug, sd,
1354                 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1355                 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1356                 stdi->hs_pol, stdi->vs_pol);
1357         return -1;
1358 }
1359
1360 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1361 {
1362         u32 status;
1363
1364         adv7842_g_input_status(sd, &status);
1365         if (status & V4L2_IN_ST_NO_SIGNAL) {
1366                 v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__);
1367                 return -ENOLINK;
1368         }
1369
1370         stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1371         stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1372         stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1373
1374         if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) {
1375                 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1376                         ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1377                 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1378                         ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1379         } else {
1380                 stdi->hs_pol = 'x';
1381                 stdi->vs_pol = 'x';
1382         }
1383         stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false;
1384
1385         if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1386                 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1387                 return -ENOLINK;
1388         }
1389
1390         v4l2_dbg(2, debug, sd,
1391                 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1392                  __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1393                  stdi->hs_pol, stdi->vs_pol,
1394                  stdi->interlaced ? "interlaced" : "progressive");
1395
1396         return 0;
1397 }
1398
1399 static int adv7842_enum_dv_timings(struct v4l2_subdev *sd,
1400                                    struct v4l2_enum_dv_timings *timings)
1401 {
1402         return v4l2_enum_dv_timings_cap(timings,
1403                 adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL);
1404 }
1405
1406 static int adv7842_dv_timings_cap(struct v4l2_subdev *sd,
1407                                   struct v4l2_dv_timings_cap *cap)
1408 {
1409         *cap = *adv7842_get_dv_timings_cap(sd);
1410         return 0;
1411 }
1412
1413 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1414    if the format is listed in adv7842_timings[] */
1415 static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1416                 struct v4l2_dv_timings *timings)
1417 {
1418         v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd),
1419                         is_digital_input(sd) ? 250000 : 1000000,
1420                         adv7842_check_dv_timings, NULL);
1421 }
1422
1423 static int adv7842_query_dv_timings(struct v4l2_subdev *sd,
1424                                     struct v4l2_dv_timings *timings)
1425 {
1426         struct adv7842_state *state = to_state(sd);
1427         struct v4l2_bt_timings *bt = &timings->bt;
1428         struct stdi_readback stdi = { 0 };
1429
1430         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1431
1432         /* SDP block */
1433         if (state->mode == ADV7842_MODE_SDP)
1434                 return -ENODATA;
1435
1436         /* read STDI */
1437         if (read_stdi(sd, &stdi)) {
1438                 state->restart_stdi_once = true;
1439                 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1440                 return -ENOLINK;
1441         }
1442         bt->interlaced = stdi.interlaced ?
1443                 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1444
1445         if (is_digital_input(sd)) {
1446                 uint32_t freq;
1447
1448                 timings->type = V4L2_DV_BT_656_1120;
1449
1450                 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1451                 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
1452                 freq = (hdmi_read(sd, 0x06) * 1000000) +
1453                        ((hdmi_read(sd, 0x3b) & 0x30) >> 4) * 250000;
1454
1455                 if (is_hdmi(sd)) {
1456                         /* adjust for deep color mode */
1457                         freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 5) + 8);
1458                 }
1459                 bt->pixelclock = freq;
1460                 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
1461                         hdmi_read(sd, 0x21);
1462                 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
1463                         hdmi_read(sd, 0x23);
1464                 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
1465                         hdmi_read(sd, 0x25);
1466                 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1467                         hdmi_read(sd, 0x2b)) / 2;
1468                 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1469                         hdmi_read(sd, 0x2f)) / 2;
1470                 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1471                         hdmi_read(sd, 0x33)) / 2;
1472                 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1473                         ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1474                 if (bt->interlaced == V4L2_DV_INTERLACED) {
1475                         bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1476                                         hdmi_read(sd, 0x0c);
1477                         bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1478                                         hdmi_read(sd, 0x2d)) / 2;
1479                         bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1480                                         hdmi_read(sd, 0x31)) / 2;
1481                         bt->vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1482                                         hdmi_read(sd, 0x35)) / 2;
1483                 }
1484                 adv7842_fill_optional_dv_timings_fields(sd, timings);
1485         } else {
1486                 /* find format
1487                  * Since LCVS values are inaccurate [REF_03, p. 339-340],
1488                  * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1489                  */
1490                 if (!stdi2dv_timings(sd, &stdi, timings))
1491                         goto found;
1492                 stdi.lcvs += 1;
1493                 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1494                 if (!stdi2dv_timings(sd, &stdi, timings))
1495                         goto found;
1496                 stdi.lcvs -= 2;
1497                 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1498                 if (stdi2dv_timings(sd, &stdi, timings)) {
1499                         /*
1500                          * The STDI block may measure wrong values, especially
1501                          * for lcvs and lcf. If the driver can not find any
1502                          * valid timing, the STDI block is restarted to measure
1503                          * the video timings again. The function will return an
1504                          * error, but the restart of STDI will generate a new
1505                          * STDI interrupt and the format detection process will
1506                          * restart.
1507                          */
1508                         if (state->restart_stdi_once) {
1509                                 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1510                                 /* TODO restart STDI for Sync Channel 2 */
1511                                 /* enter one-shot mode */
1512                                 cp_write_and_or(sd, 0x86, 0xf9, 0x00);
1513                                 /* trigger STDI restart */
1514                                 cp_write_and_or(sd, 0x86, 0xf9, 0x04);
1515                                 /* reset to continuous mode */
1516                                 cp_write_and_or(sd, 0x86, 0xf9, 0x02);
1517                                 state->restart_stdi_once = false;
1518                                 return -ENOLINK;
1519                         }
1520                         v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1521                         return -ERANGE;
1522                 }
1523                 state->restart_stdi_once = true;
1524         }
1525 found:
1526
1527         if (debug > 1)
1528                 v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings:",
1529                                 timings, true);
1530         return 0;
1531 }
1532
1533 static int adv7842_s_dv_timings(struct v4l2_subdev *sd,
1534                                 struct v4l2_dv_timings *timings)
1535 {
1536         struct adv7842_state *state = to_state(sd);
1537         struct v4l2_bt_timings *bt;
1538         int err;
1539
1540         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1541
1542         if (state->mode == ADV7842_MODE_SDP)
1543                 return -ENODATA;
1544
1545         if (v4l2_match_dv_timings(&state->timings, timings, 0)) {
1546                 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1547                 return 0;
1548         }
1549
1550         bt = &timings->bt;
1551
1552         if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd),
1553                                    adv7842_check_dv_timings, NULL))
1554                 return -ERANGE;
1555
1556         adv7842_fill_optional_dv_timings_fields(sd, timings);
1557
1558         state->timings = *timings;
1559
1560         cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00);
1561
1562         /* Use prim_mode and vid_std when available */
1563         err = configure_predefined_video_timings(sd, timings);
1564         if (err) {
1565                 /* custom settings when the video format
1566                   does not have prim_mode/vid_std */
1567                 configure_custom_video_timings(sd, bt);
1568         }
1569
1570         set_rgb_quantization_range(sd);
1571
1572
1573         if (debug > 1)
1574                 v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ",
1575                                       timings, true);
1576         return 0;
1577 }
1578
1579 static int adv7842_g_dv_timings(struct v4l2_subdev *sd,
1580                                 struct v4l2_dv_timings *timings)
1581 {
1582         struct adv7842_state *state = to_state(sd);
1583
1584         if (state->mode == ADV7842_MODE_SDP)
1585                 return -ENODATA;
1586         *timings = state->timings;
1587         return 0;
1588 }
1589
1590 static void enable_input(struct v4l2_subdev *sd)
1591 {
1592         struct adv7842_state *state = to_state(sd);
1593
1594         set_rgb_quantization_range(sd);
1595         switch (state->mode) {
1596         case ADV7842_MODE_SDP:
1597         case ADV7842_MODE_COMP:
1598         case ADV7842_MODE_RGB:
1599                 io_write(sd, 0x15, 0xb0);   /* Disable Tristate of Pins (no audio) */
1600                 break;
1601         case ADV7842_MODE_HDMI:
1602                 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1603                 io_write(sd, 0x15, 0xa0);   /* Disable Tristate of Pins */
1604                 hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */
1605                 break;
1606         default:
1607                 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1608                          __func__, state->mode);
1609                 break;
1610         }
1611 }
1612
1613 static void disable_input(struct v4l2_subdev *sd)
1614 {
1615         hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio [REF_01, c. 2.2.2] */
1616         msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 8.29] */
1617         io_write(sd, 0x15, 0xbe);   /* Tristate all outputs from video core */
1618         hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1619 }
1620
1621 static void sdp_csc_coeff(struct v4l2_subdev *sd,
1622                           const struct adv7842_sdp_csc_coeff *c)
1623 {
1624         /* csc auto/manual */
1625         sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40);
1626
1627         if (!c->manual)
1628                 return;
1629
1630         /* csc scaling */
1631         sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00);
1632
1633         /* A coeff */
1634         sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8);
1635         sdp_io_write(sd, 0xe1, c->A1);
1636         sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8);
1637         sdp_io_write(sd, 0xe3, c->A2);
1638         sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8);
1639         sdp_io_write(sd, 0xe5, c->A3);
1640
1641         /* A scale */
1642         sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8);
1643         sdp_io_write(sd, 0xe7, c->A4);
1644
1645         /* B coeff */
1646         sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8);
1647         sdp_io_write(sd, 0xe9, c->B1);
1648         sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8);
1649         sdp_io_write(sd, 0xeb, c->B2);
1650         sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8);
1651         sdp_io_write(sd, 0xed, c->B3);
1652
1653         /* B scale */
1654         sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8);
1655         sdp_io_write(sd, 0xef, c->B4);
1656
1657         /* C coeff */
1658         sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8);
1659         sdp_io_write(sd, 0xf1, c->C1);
1660         sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8);
1661         sdp_io_write(sd, 0xf3, c->C2);
1662         sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8);
1663         sdp_io_write(sd, 0xf5, c->C3);
1664
1665         /* C scale */
1666         sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8);
1667         sdp_io_write(sd, 0xf7, c->C4);
1668 }
1669
1670 static void select_input(struct v4l2_subdev *sd,
1671                          enum adv7842_vid_std_select vid_std_select)
1672 {
1673         struct adv7842_state *state = to_state(sd);
1674
1675         switch (state->mode) {
1676         case ADV7842_MODE_SDP:
1677                 io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */
1678                 io_write(sd, 0x01, 0); /* prim mode */
1679                 /* enable embedded syncs for auto graphics mode */
1680                 cp_write_and_or(sd, 0x81, 0xef, 0x10);
1681
1682                 afe_write(sd, 0x00, 0x00); /* power up ADC */
1683                 afe_write(sd, 0xc8, 0x00); /* phase control */
1684
1685                 io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */
1686                 /* script says register 0xde, which don't exist in manual */
1687
1688                 /* Manual analog input muxing mode, CVBS (6.4)*/
1689                 afe_write_and_or(sd, 0x02, 0x7f, 0x80);
1690                 if (vid_std_select == ADV7842_SDP_VID_STD_CVBS_SD_4x1) {
1691                         afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1692                         afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/
1693                 } else {
1694                         afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1695                         afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/
1696                 }
1697                 afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */
1698                 afe_write(sd, 0x12, 0x63); /* ADI recommend write */
1699
1700                 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */
1701                 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */
1702
1703                 /* SDP recommended settings */
1704                 sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */
1705                 sdp_write(sd, 0x01, 0x00); /* Pedestal Off */
1706
1707                 sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */
1708                 sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */
1709                 sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */
1710                 sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */
1711                 sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */
1712                 sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */
1713                 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */
1714
1715                 /* deinterlacer enabled and 3D comb */
1716                 sdp_write_and_or(sd, 0x12, 0xf6, 0x09);
1717
1718                 break;
1719
1720         case ADV7842_MODE_COMP:
1721         case ADV7842_MODE_RGB:
1722                 /* Automatic analog input muxing mode */
1723                 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1724                 /* set mode and select free run resolution */
1725                 io_write(sd, 0x00, vid_std_select); /* video std */
1726                 io_write(sd, 0x01, 0x02); /* prim mode */
1727                 cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs
1728                                                           for auto graphics mode */
1729
1730                 afe_write(sd, 0x00, 0x00); /* power up ADC */
1731                 afe_write(sd, 0xc8, 0x00); /* phase control */
1732                 if (state->mode == ADV7842_MODE_COMP) {
1733                         /* force to YCrCb */
1734                         io_write_and_or(sd, 0x02, 0x0f, 0x60);
1735                 } else {
1736                         /* force to RGB */
1737                         io_write_and_or(sd, 0x02, 0x0f, 0x10);
1738                 }
1739
1740                 /* set ADI recommended settings for digitizer */
1741                 /* "ADV7842 Register Settings Recommendations
1742                  * (rev. 1.8, November 2010)" p. 9. */
1743                 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */
1744                 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */
1745
1746                 /* set to default gain for RGB */
1747                 cp_write(sd, 0x73, 0x10);
1748                 cp_write(sd, 0x74, 0x04);
1749                 cp_write(sd, 0x75, 0x01);
1750                 cp_write(sd, 0x76, 0x00);
1751
1752                 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1753                 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1754                 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1755                 break;
1756
1757         case ADV7842_MODE_HDMI:
1758                 /* Automatic analog input muxing mode */
1759                 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1760                 /* set mode and select free run resolution */
1761                 if (state->hdmi_port_a)
1762                         hdmi_write(sd, 0x00, 0x02); /* select port A */
1763                 else
1764                         hdmi_write(sd, 0x00, 0x03); /* select port B */
1765                 io_write(sd, 0x00, vid_std_select); /* video std */
1766                 io_write(sd, 0x01, 5); /* prim mode */
1767                 cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs
1768                                                           for auto graphics mode */
1769
1770                 /* set ADI recommended settings for HDMI: */
1771                 /* "ADV7842 Register Settings Recommendations
1772                  * (rev. 1.8, November 2010)" p. 3. */
1773                 hdmi_write(sd, 0xc0, 0x00);
1774                 hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */
1775                 hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */
1776                 hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */
1777                 hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */
1778                 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1779                 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1780                 hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */
1781                 hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */
1782                 hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit,
1783                                                Improve robustness */
1784                 hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */
1785                 hdmi_write(sd, 0x85, 0x1f); /* equaliser */
1786                 hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */
1787                 hdmi_write(sd, 0x89, 0x04); /* equaliser */
1788                 hdmi_write(sd, 0x8a, 0x1e); /* equaliser */
1789                 hdmi_write(sd, 0x93, 0x04); /* equaliser */
1790                 hdmi_write(sd, 0x94, 0x1e); /* equaliser */
1791                 hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */
1792                 hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */
1793                 hdmi_write(sd, 0x9d, 0x02); /* equaliser */
1794
1795                 afe_write(sd, 0x00, 0xff); /* power down ADC */
1796                 afe_write(sd, 0xc8, 0x40); /* phase control */
1797
1798                 /* set to default gain for HDMI */
1799                 cp_write(sd, 0x73, 0x10);
1800                 cp_write(sd, 0x74, 0x04);
1801                 cp_write(sd, 0x75, 0x01);
1802                 cp_write(sd, 0x76, 0x00);
1803
1804                 /* reset ADI recommended settings for digitizer */
1805                 /* "ADV7842 Register Settings Recommendations
1806                  * (rev. 2.5, June 2010)" p. 17. */
1807                 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1808                 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1809                 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1810
1811                 /* CP coast control */
1812                 cp_write(sd, 0xc3, 0x33); /* Component mode */
1813
1814                 /* color space conversion, autodetect color space */
1815                 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1816                 break;
1817
1818         default:
1819                 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1820                          __func__, state->mode);
1821                 break;
1822         }
1823 }
1824
1825 static int adv7842_s_routing(struct v4l2_subdev *sd,
1826                 u32 input, u32 output, u32 config)
1827 {
1828         struct adv7842_state *state = to_state(sd);
1829
1830         v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input);
1831
1832         switch (input) {
1833         case ADV7842_SELECT_HDMI_PORT_A:
1834                 state->mode = ADV7842_MODE_HDMI;
1835                 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1836                 state->hdmi_port_a = true;
1837                 break;
1838         case ADV7842_SELECT_HDMI_PORT_B:
1839                 state->mode = ADV7842_MODE_HDMI;
1840                 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1841                 state->hdmi_port_a = false;
1842                 break;
1843         case ADV7842_SELECT_VGA_COMP:
1844                 state->mode = ADV7842_MODE_COMP;
1845                 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1846                 break;
1847         case ADV7842_SELECT_VGA_RGB:
1848                 state->mode = ADV7842_MODE_RGB;
1849                 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1850                 break;
1851         case ADV7842_SELECT_SDP_CVBS:
1852                 state->mode = ADV7842_MODE_SDP;
1853                 state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1;
1854                 break;
1855         case ADV7842_SELECT_SDP_YC:
1856                 state->mode = ADV7842_MODE_SDP;
1857                 state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1;
1858                 break;
1859         default:
1860                 return -EINVAL;
1861         }
1862
1863         disable_input(sd);
1864         select_input(sd, state->vid_std_select);
1865         enable_input(sd);
1866
1867         v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL);
1868
1869         return 0;
1870 }
1871
1872 static int adv7842_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index,
1873                                  enum v4l2_mbus_pixelcode *code)
1874 {
1875         if (index)
1876                 return -EINVAL;
1877         /* Good enough for now */
1878         *code = V4L2_MBUS_FMT_FIXED;
1879         return 0;
1880 }
1881
1882 static int adv7842_g_mbus_fmt(struct v4l2_subdev *sd,
1883                               struct v4l2_mbus_framefmt *fmt)
1884 {
1885         struct adv7842_state *state = to_state(sd);
1886
1887         fmt->width = state->timings.bt.width;
1888         fmt->height = state->timings.bt.height;
1889         fmt->code = V4L2_MBUS_FMT_FIXED;
1890         fmt->field = V4L2_FIELD_NONE;
1891
1892         if (state->mode == ADV7842_MODE_SDP) {
1893                 /* SPD block */
1894                 if (!(sdp_read(sd, 0x5A) & 0x01))
1895                         return -EINVAL;
1896                 fmt->width = 720;
1897                 /* valid signal */
1898                 if (state->norm & V4L2_STD_525_60)
1899                         fmt->height = 480;
1900                 else
1901                         fmt->height = 576;
1902                 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
1903                 return 0;
1904         }
1905
1906         if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1907                 fmt->colorspace = (state->timings.bt.height <= 576) ?
1908                         V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1909         }
1910         return 0;
1911 }
1912
1913 static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable)
1914 {
1915         if (enable) {
1916                 /* Enable SSPD, STDI and CP locked/unlocked interrupts */
1917                 io_write(sd, 0x46, 0x9c);
1918                 /* ESDP_50HZ_DET interrupt */
1919                 io_write(sd, 0x5a, 0x10);
1920                 /* Enable CABLE_DET_A/B_ST (+5v) interrupt */
1921                 io_write(sd, 0x73, 0x03);
1922                 /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
1923                 io_write(sd, 0x78, 0x03);
1924                 /* Enable SDP Standard Detection Change and SDP Video Detected */
1925                 io_write(sd, 0xa0, 0x09);
1926                 /* Enable HDMI_MODE interrupt */
1927                 io_write(sd, 0x69, 0x08);
1928         } else {
1929                 io_write(sd, 0x46, 0x0);
1930                 io_write(sd, 0x5a, 0x0);
1931                 io_write(sd, 0x73, 0x0);
1932                 io_write(sd, 0x78, 0x0);
1933                 io_write(sd, 0xa0, 0x0);
1934                 io_write(sd, 0x69, 0x0);
1935         }
1936 }
1937
1938 static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1939 {
1940         struct adv7842_state *state = to_state(sd);
1941         u8 fmt_change_cp, fmt_change_digital, fmt_change_sdp;
1942         u8 irq_status[6];
1943
1944         adv7842_irq_enable(sd, false);
1945
1946         /* read status */
1947         irq_status[0] = io_read(sd, 0x43);
1948         irq_status[1] = io_read(sd, 0x57);
1949         irq_status[2] = io_read(sd, 0x70);
1950         irq_status[3] = io_read(sd, 0x75);
1951         irq_status[4] = io_read(sd, 0x9d);
1952         irq_status[5] = io_read(sd, 0x66);
1953
1954         /* and clear */
1955         if (irq_status[0])
1956                 io_write(sd, 0x44, irq_status[0]);
1957         if (irq_status[1])
1958                 io_write(sd, 0x58, irq_status[1]);
1959         if (irq_status[2])
1960                 io_write(sd, 0x71, irq_status[2]);
1961         if (irq_status[3])
1962                 io_write(sd, 0x76, irq_status[3]);
1963         if (irq_status[4])
1964                 io_write(sd, 0x9e, irq_status[4]);
1965         if (irq_status[5])
1966                 io_write(sd, 0x67, irq_status[5]);
1967
1968         adv7842_irq_enable(sd, true);
1969
1970         v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x, %x\n", __func__,
1971                  irq_status[0], irq_status[1], irq_status[2],
1972                  irq_status[3], irq_status[4], irq_status[5]);
1973
1974         /* format change CP */
1975         fmt_change_cp = irq_status[0] & 0x9c;
1976
1977         /* format change SDP */
1978         if (state->mode == ADV7842_MODE_SDP)
1979                 fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09);
1980         else
1981                 fmt_change_sdp = 0;
1982
1983         /* digital format CP */
1984         if (is_digital_input(sd))
1985                 fmt_change_digital = irq_status[3] & 0x03;
1986         else
1987                 fmt_change_digital = 0;
1988
1989         /* format change */
1990         if (fmt_change_cp || fmt_change_digital || fmt_change_sdp) {
1991                 v4l2_dbg(1, debug, sd,
1992                          "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n",
1993                          __func__, fmt_change_cp, fmt_change_digital,
1994                          fmt_change_sdp);
1995                 v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL);
1996                 if (handled)
1997                         *handled = true;
1998         }
1999
2000         /* HDMI/DVI mode */
2001         if (irq_status[5] & 0x08) {
2002                 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
2003                          (io_read(sd, 0x65) & 0x08) ? "HDMI" : "DVI");
2004                 if (handled)
2005                         *handled = true;
2006         }
2007
2008         /* tx 5v detect */
2009         if (irq_status[2] & 0x3) {
2010                 v4l2_dbg(1, debug, sd, "%s: irq tx_5v\n", __func__);
2011                 adv7842_s_detect_tx_5v_ctrl(sd);
2012                 if (handled)
2013                         *handled = true;
2014         }
2015         return 0;
2016 }
2017
2018 static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
2019 {
2020         struct adv7842_state *state = to_state(sd);
2021         u8 *data = NULL;
2022
2023         if (edid->pad > ADV7842_EDID_PORT_VGA)
2024                 return -EINVAL;
2025         if (edid->blocks == 0)
2026                 return -EINVAL;
2027         if (edid->blocks > 2)
2028                 return -EINVAL;
2029         if (edid->start_block > 1)
2030                 return -EINVAL;
2031         if (edid->start_block == 1)
2032                 edid->blocks = 1;
2033         if (!edid->edid)
2034                 return -EINVAL;
2035
2036         switch (edid->pad) {
2037         case ADV7842_EDID_PORT_A:
2038         case ADV7842_EDID_PORT_B:
2039                 if (state->hdmi_edid.present & (0x04 << edid->pad))
2040                         data = state->hdmi_edid.edid;
2041                 break;
2042         case ADV7842_EDID_PORT_VGA:
2043                 if (state->vga_edid.present)
2044                         data = state->vga_edid.edid;
2045                 break;
2046         default:
2047                 return -EINVAL;
2048         }
2049         if (!data)
2050                 return -ENODATA;
2051
2052         memcpy(edid->edid,
2053                data + edid->start_block * 128,
2054                edid->blocks * 128);
2055         return 0;
2056 }
2057
2058 static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *e)
2059 {
2060         struct adv7842_state *state = to_state(sd);
2061         int err = 0;
2062
2063         if (e->pad > ADV7842_EDID_PORT_VGA)
2064                 return -EINVAL;
2065         if (e->start_block != 0)
2066                 return -EINVAL;
2067         if (e->blocks > 2)
2068                 return -E2BIG;
2069         if (!e->edid)
2070                 return -EINVAL;
2071
2072         /* todo, per edid */
2073         state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15],
2074                         e->edid[0x16]);
2075
2076         switch (e->pad) {
2077         case ADV7842_EDID_PORT_VGA:
2078                 memset(&state->vga_edid.edid, 0, 256);
2079                 state->vga_edid.present = e->blocks ? 0x1 : 0x0;
2080                 memcpy(&state->vga_edid.edid, e->edid, 128 * e->blocks);
2081                 err = edid_write_vga_segment(sd);
2082                 break;
2083         case ADV7842_EDID_PORT_A:
2084         case ADV7842_EDID_PORT_B:
2085                 memset(&state->hdmi_edid.edid, 0, 256);
2086                 if (e->blocks)
2087                         state->hdmi_edid.present |= 0x04 << e->pad;
2088                 else
2089                         state->hdmi_edid.present &= ~(0x04 << e->pad);
2090                 memcpy(&state->hdmi_edid.edid, e->edid, 128 * e->blocks);
2091                 err = edid_write_hdmi_segment(sd, e->pad);
2092                 break;
2093         default:
2094                 return -EINVAL;
2095         }
2096         if (err < 0)
2097                 v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad);
2098         return err;
2099 }
2100
2101 /*********** avi info frame CEA-861-E **************/
2102 /* TODO move to common library */
2103
2104 struct avi_info_frame {
2105         uint8_t f17;
2106         uint8_t y10;
2107         uint8_t a0;
2108         uint8_t b10;
2109         uint8_t s10;
2110         uint8_t c10;
2111         uint8_t m10;
2112         uint8_t r3210;
2113         uint8_t itc;
2114         uint8_t ec210;
2115         uint8_t q10;
2116         uint8_t sc10;
2117         uint8_t f47;
2118         uint8_t vic;
2119         uint8_t yq10;
2120         uint8_t cn10;
2121         uint8_t pr3210;
2122         uint16_t etb;
2123         uint16_t sbb;
2124         uint16_t elb;
2125         uint16_t srb;
2126 };
2127
2128 static const char *y10_txt[4] = {
2129         "RGB",
2130         "YCbCr 4:2:2",
2131         "YCbCr 4:4:4",
2132         "Future",
2133 };
2134
2135 static const char *c10_txt[4] = {
2136         "No Data",
2137         "SMPTE 170M",
2138         "ITU-R 709",
2139         "Extended Colorimetry information valied",
2140 };
2141
2142 static const char *itc_txt[2] = {
2143         "No Data",
2144         "IT content",
2145 };
2146
2147 static const char *ec210_txt[8] = {
2148         "xvYCC601",
2149         "xvYCC709",
2150         "sYCC601",
2151         "AdobeYCC601",
2152         "AdobeRGB",
2153         "5 reserved",
2154         "6 reserved",
2155         "7 reserved",
2156 };
2157
2158 static const char *q10_txt[4] = {
2159         "Default",
2160         "Limited Range",
2161         "Full Range",
2162         "Reserved",
2163 };
2164
2165 static void parse_avi_infoframe(struct v4l2_subdev *sd, uint8_t *buf,
2166                                 struct avi_info_frame *avi)
2167 {
2168         avi->f17 = (buf[1] >> 7) & 0x1;
2169         avi->y10 = (buf[1] >> 5) & 0x3;
2170         avi->a0 = (buf[1] >> 4) & 0x1;
2171         avi->b10 = (buf[1] >> 2) & 0x3;
2172         avi->s10 = buf[1] & 0x3;
2173         avi->c10 = (buf[2] >> 6) & 0x3;
2174         avi->m10 = (buf[2] >> 4) & 0x3;
2175         avi->r3210 = buf[2] & 0xf;
2176         avi->itc = (buf[3] >> 7) & 0x1;
2177         avi->ec210 = (buf[3] >> 4) & 0x7;
2178         avi->q10 = (buf[3] >> 2) & 0x3;
2179         avi->sc10 = buf[3] & 0x3;
2180         avi->f47 = (buf[4] >> 7) & 0x1;
2181         avi->vic = buf[4] & 0x7f;
2182         avi->yq10 = (buf[5] >> 6) & 0x3;
2183         avi->cn10 = (buf[5] >> 4) & 0x3;
2184         avi->pr3210 = buf[5] & 0xf;
2185         avi->etb = buf[6] + 256*buf[7];
2186         avi->sbb = buf[8] + 256*buf[9];
2187         avi->elb = buf[10] + 256*buf[11];
2188         avi->srb = buf[12] + 256*buf[13];
2189 }
2190
2191 static void print_avi_infoframe(struct v4l2_subdev *sd)
2192 {
2193         int i;
2194         uint8_t buf[14];
2195         uint8_t avi_inf_len;
2196         struct avi_info_frame avi;
2197
2198         if (!(hdmi_read(sd, 0x05) & 0x80)) {
2199                 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
2200                 return;
2201         }
2202         if (!(io_read(sd, 0x60) & 0x01)) {
2203                 v4l2_info(sd, "AVI infoframe not received\n");
2204                 return;
2205         }
2206
2207         if (io_read(sd, 0x88) & 0x10) {
2208                 /* Note: the ADV7842 calculated incorrect checksums for InfoFrames
2209                    with a length of 14 or 15. See the ADV7842 Register Settings
2210                    Recommendations document for more details. */
2211                 v4l2_info(sd, "AVI infoframe checksum error\n");
2212                 return;
2213         }
2214
2215         avi_inf_len = infoframe_read(sd, 0xe2);
2216         v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
2217                   infoframe_read(sd, 0xe1), avi_inf_len);
2218
2219         if (infoframe_read(sd, 0xe1) != 0x02)
2220                 return;
2221
2222         for (i = 0; i < 14; i++)
2223                 buf[i] = infoframe_read(sd, i);
2224
2225         v4l2_info(sd, "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
2226                   buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
2227                   buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
2228
2229         parse_avi_infoframe(sd, buf, &avi);
2230
2231         if (avi.vic)
2232                 v4l2_info(sd, "\tVIC: %d\n", avi.vic);
2233         if (avi.itc)
2234                 v4l2_info(sd, "\t%s\n", itc_txt[avi.itc]);
2235
2236         if (avi.y10)
2237                 v4l2_info(sd, "\t%s %s\n", y10_txt[avi.y10], !avi.c10 ? "" :
2238                         (avi.c10 == 0x3 ? ec210_txt[avi.ec210] : c10_txt[avi.c10]));
2239         else
2240                 v4l2_info(sd, "\t%s %s\n", y10_txt[avi.y10], q10_txt[avi.q10]);
2241 }
2242
2243 static const char * const prim_mode_txt[] = {
2244         "SDP",
2245         "Component",
2246         "Graphics",
2247         "Reserved",
2248         "CVBS & HDMI AUDIO",
2249         "HDMI-Comp",
2250         "HDMI-GR",
2251         "Reserved",
2252         "Reserved",
2253         "Reserved",
2254         "Reserved",
2255         "Reserved",
2256         "Reserved",
2257         "Reserved",
2258         "Reserved",
2259         "Reserved",
2260 };
2261
2262 static int adv7842_sdp_log_status(struct v4l2_subdev *sd)
2263 {
2264         /* SDP (Standard definition processor) block */
2265         uint8_t sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01;
2266
2267         v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on");
2268         v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n",
2269                   io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f);
2270
2271         v4l2_info(sd, "SDP: free run: %s\n",
2272                 (sdp_read(sd, 0x56) & 0x01) ? "on" : "off");
2273         v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ?
2274                 "valid SD/PR signal detected" : "invalid/no signal");
2275         if (sdp_signal_detected) {
2276                 static const char * const sdp_std_txt[] = {
2277                         "NTSC-M/J",
2278                         "1?",
2279                         "NTSC-443",
2280                         "60HzSECAM",
2281                         "PAL-M",
2282                         "5?",
2283                         "PAL-60",
2284                         "7?", "8?", "9?", "a?", "b?",
2285                         "PAL-CombN",
2286                         "d?",
2287                         "PAL-BGHID",
2288                         "SECAM"
2289                 };
2290                 v4l2_info(sd, "SDP: standard %s\n",
2291                         sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]);
2292                 v4l2_info(sd, "SDP: %s\n",
2293                         (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz");
2294                 v4l2_info(sd, "SDP: %s\n",
2295                         (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive");
2296                 v4l2_info(sd, "SDP: deinterlacer %s\n",
2297                         (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled");
2298                 v4l2_info(sd, "SDP: csc %s mode\n",
2299                         (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual");
2300         }
2301         return 0;
2302 }
2303
2304 static int adv7842_cp_log_status(struct v4l2_subdev *sd)
2305 {
2306         /* CP block */
2307         struct adv7842_state *state = to_state(sd);
2308         struct v4l2_dv_timings timings;
2309         uint8_t reg_io_0x02 = io_read(sd, 0x02);
2310         uint8_t reg_io_0x21 = io_read(sd, 0x21);
2311         uint8_t reg_rep_0x77 = rep_read(sd, 0x77);
2312         uint8_t reg_rep_0x7d = rep_read(sd, 0x7d);
2313         bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2314         bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2315         bool audio_mute = io_read(sd, 0x65) & 0x40;
2316
2317         static const char * const csc_coeff_sel_rb[16] = {
2318                 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2319                 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2320                 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2321                 "reserved", "reserved", "reserved", "reserved", "manual"
2322         };
2323         static const char * const input_color_space_txt[16] = {
2324                 "RGB limited range (16-235)", "RGB full range (0-255)",
2325                 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2326                 "xvYCC Bt.601", "xvYCC Bt.709",
2327                 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2328                 "invalid", "invalid", "invalid", "invalid", "invalid",
2329                 "invalid", "invalid", "automatic"
2330         };
2331         static const char * const rgb_quantization_range_txt[] = {
2332                 "Automatic",
2333                 "RGB limited range (16-235)",
2334                 "RGB full range (0-255)",
2335         };
2336         static const char * const deep_color_mode_txt[4] = {
2337                 "8-bits per channel",
2338                 "10-bits per channel",
2339                 "12-bits per channel",
2340                 "16-bits per channel (not supported)"
2341         };
2342
2343         v4l2_info(sd, "-----Chip status-----\n");
2344         v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2345         v4l2_info(sd, "HDMI/DVI-D port selected: %s\n",
2346                         state->hdmi_port_a ? "A" : "B");
2347         v4l2_info(sd, "EDID A %s, B %s\n",
2348                   ((reg_rep_0x7d & 0x04) && (reg_rep_0x77 & 0x04)) ?
2349                   "enabled" : "disabled",
2350                   ((reg_rep_0x7d & 0x08) && (reg_rep_0x77 & 0x08)) ?
2351                   "enabled" : "disabled");
2352         v4l2_info(sd, "HPD A %s, B %s\n",
2353                   reg_io_0x21 & 0x02 ? "enabled" : "disabled",
2354                   reg_io_0x21 & 0x01 ? "enabled" : "disabled");
2355         v4l2_info(sd, "CEC %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
2356                         "enabled" : "disabled");
2357
2358         v4l2_info(sd, "-----Signal status-----\n");
2359         if (state->hdmi_port_a) {
2360                 v4l2_info(sd, "Cable detected (+5V power): %s\n",
2361                           io_read(sd, 0x6f) & 0x02 ? "true" : "false");
2362                 v4l2_info(sd, "TMDS signal detected: %s\n",
2363                           (io_read(sd, 0x6a) & 0x02) ? "true" : "false");
2364                 v4l2_info(sd, "TMDS signal locked: %s\n",
2365                           (io_read(sd, 0x6a) & 0x20) ? "true" : "false");
2366         } else {
2367                 v4l2_info(sd, "Cable detected (+5V power):%s\n",
2368                           io_read(sd, 0x6f) & 0x01 ? "true" : "false");
2369                 v4l2_info(sd, "TMDS signal detected: %s\n",
2370                           (io_read(sd, 0x6a) & 0x01) ? "true" : "false");
2371                 v4l2_info(sd, "TMDS signal locked: %s\n",
2372                           (io_read(sd, 0x6a) & 0x10) ? "true" : "false");
2373         }
2374         v4l2_info(sd, "CP free run: %s\n",
2375                   (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
2376         v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2377                   io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2378                   (io_read(sd, 0x01) & 0x70) >> 4);
2379
2380         v4l2_info(sd, "-----Video Timings-----\n");
2381         if (no_cp_signal(sd)) {
2382                 v4l2_info(sd, "STDI: not locked\n");
2383         } else {
2384                 uint32_t bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
2385                 uint32_t lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
2386                 uint32_t lcvs = cp_read(sd, 0xb3) >> 3;
2387                 uint32_t fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9);
2388                 char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
2389                                 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
2390                 char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
2391                                 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
2392                 v4l2_info(sd,
2393                         "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n",
2394                         lcf, bl, lcvs, fcl,
2395                         (cp_read(sd, 0xb1) & 0x40) ?
2396                                 "interlaced" : "progressive",
2397                         hs_pol, vs_pol);
2398         }
2399         if (adv7842_query_dv_timings(sd, &timings))
2400                 v4l2_info(sd, "No video detected\n");
2401         else
2402                 v4l2_print_dv_timings(sd->name, "Detected format: ",
2403                                       &timings, true);
2404         v4l2_print_dv_timings(sd->name, "Configured format: ",
2405                         &state->timings, true);
2406
2407         if (no_cp_signal(sd))
2408                 return 0;
2409
2410         v4l2_info(sd, "-----Color space-----\n");
2411         v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2412                   rgb_quantization_range_txt[state->rgb_quantization_range]);
2413         v4l2_info(sd, "Input color space: %s\n",
2414                   input_color_space_txt[reg_io_0x02 >> 4]);
2415         v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
2416                   (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2417                   (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
2418                   ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
2419                                         "enabled" : "disabled");
2420         v4l2_info(sd, "Color space conversion: %s\n",
2421                   csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]);
2422
2423         if (!is_digital_input(sd))
2424                 return 0;
2425
2426         v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2427         v4l2_info(sd, "HDCP encrypted content: %s\n",
2428                         (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2429         v4l2_info(sd, "HDCP keys read: %s%s\n",
2430                         (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2431                         (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2432         if (!is_hdmi(sd))
2433                 return 0;
2434
2435         v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2436                         audio_pll_locked ? "locked" : "not locked",
2437                         audio_sample_packet_detect ? "detected" : "not detected",
2438                         audio_mute ? "muted" : "enabled");
2439         if (audio_pll_locked && audio_sample_packet_detect) {
2440                 v4l2_info(sd, "Audio format: %s\n",
2441                         (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo");
2442         }
2443         v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2444                         (hdmi_read(sd, 0x5c) << 8) +
2445                         (hdmi_read(sd, 0x5d) & 0xf0));
2446         v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2447                         (hdmi_read(sd, 0x5e) << 8) +
2448                         hdmi_read(sd, 0x5f));
2449         v4l2_info(sd, "AV Mute: %s\n",
2450                         (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2451         v4l2_info(sd, "Deep color mode: %s\n",
2452                         deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]);
2453
2454         print_avi_infoframe(sd);
2455         return 0;
2456 }
2457
2458 static int adv7842_log_status(struct v4l2_subdev *sd)
2459 {
2460         struct adv7842_state *state = to_state(sd);
2461
2462         if (state->mode == ADV7842_MODE_SDP)
2463                 return adv7842_sdp_log_status(sd);
2464         return adv7842_cp_log_status(sd);
2465 }
2466
2467 static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
2468 {
2469         struct adv7842_state *state = to_state(sd);
2470
2471         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2472
2473         if (state->mode != ADV7842_MODE_SDP)
2474                 return -ENODATA;
2475
2476         if (!(sdp_read(sd, 0x5A) & 0x01)) {
2477                 *std = 0;
2478                 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
2479                 return 0;
2480         }
2481
2482         switch (sdp_read(sd, 0x52) & 0x0f) {
2483         case 0:
2484                 /* NTSC-M/J */
2485                 *std &= V4L2_STD_NTSC;
2486                 break;
2487         case 2:
2488                 /* NTSC-443 */
2489                 *std &= V4L2_STD_NTSC_443;
2490                 break;
2491         case 3:
2492                 /* 60HzSECAM */
2493                 *std &= V4L2_STD_SECAM;
2494                 break;
2495         case 4:
2496                 /* PAL-M */
2497                 *std &= V4L2_STD_PAL_M;
2498                 break;
2499         case 6:
2500                 /* PAL-60 */
2501                 *std &= V4L2_STD_PAL_60;
2502                 break;
2503         case 0xc:
2504                 /* PAL-CombN */
2505                 *std &= V4L2_STD_PAL_Nc;
2506                 break;
2507         case 0xe:
2508                 /* PAL-BGHID */
2509                 *std &= V4L2_STD_PAL;
2510                 break;
2511         case 0xf:
2512                 /* SECAM */
2513                 *std &= V4L2_STD_SECAM;
2514                 break;
2515         default:
2516                 *std &= V4L2_STD_ALL;
2517                 break;
2518         }
2519         return 0;
2520 }
2521
2522 static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s)
2523 {
2524         if (s && s->adjust) {
2525                 sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf);
2526                 sdp_io_write(sd, 0x95, s->hs_beg & 0xff);
2527                 sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf);
2528                 sdp_io_write(sd, 0x97, s->hs_width & 0xff);
2529                 sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf);
2530                 sdp_io_write(sd, 0x99, s->de_beg & 0xff);
2531                 sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf);
2532                 sdp_io_write(sd, 0x9b, s->de_end & 0xff);
2533                 sdp_io_write(sd, 0xa8, s->vs_beg_o);
2534                 sdp_io_write(sd, 0xa9, s->vs_beg_e);
2535                 sdp_io_write(sd, 0xaa, s->vs_end_o);
2536                 sdp_io_write(sd, 0xab, s->vs_end_e);
2537                 sdp_io_write(sd, 0xac, s->de_v_beg_o);
2538                 sdp_io_write(sd, 0xad, s->de_v_beg_e);
2539                 sdp_io_write(sd, 0xae, s->de_v_end_o);
2540                 sdp_io_write(sd, 0xaf, s->de_v_end_e);
2541         } else {
2542                 /* set to default */
2543                 sdp_io_write(sd, 0x94, 0x00);
2544                 sdp_io_write(sd, 0x95, 0x00);
2545                 sdp_io_write(sd, 0x96, 0x00);
2546                 sdp_io_write(sd, 0x97, 0x20);
2547                 sdp_io_write(sd, 0x98, 0x00);
2548                 sdp_io_write(sd, 0x99, 0x00);
2549                 sdp_io_write(sd, 0x9a, 0x00);
2550                 sdp_io_write(sd, 0x9b, 0x00);
2551                 sdp_io_write(sd, 0xa8, 0x04);
2552                 sdp_io_write(sd, 0xa9, 0x04);
2553                 sdp_io_write(sd, 0xaa, 0x04);
2554                 sdp_io_write(sd, 0xab, 0x04);
2555                 sdp_io_write(sd, 0xac, 0x04);
2556                 sdp_io_write(sd, 0xad, 0x04);
2557                 sdp_io_write(sd, 0xae, 0x04);
2558                 sdp_io_write(sd, 0xaf, 0x04);
2559         }
2560 }
2561
2562 static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
2563 {
2564         struct adv7842_state *state = to_state(sd);
2565         struct adv7842_platform_data *pdata = &state->pdata;
2566
2567         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2568
2569         if (state->mode != ADV7842_MODE_SDP)
2570                 return -ENODATA;
2571
2572         if (norm & V4L2_STD_625_50)
2573                 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625);
2574         else if (norm & V4L2_STD_525_60)
2575                 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525);
2576         else
2577                 adv7842_s_sdp_io(sd, NULL);
2578
2579         if (norm & V4L2_STD_ALL) {
2580                 state->norm = norm;
2581                 return 0;
2582         }
2583         return -EINVAL;
2584 }
2585
2586 static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
2587 {
2588         struct adv7842_state *state = to_state(sd);
2589
2590         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2591
2592         if (state->mode != ADV7842_MODE_SDP)
2593                 return -ENODATA;
2594
2595         *norm = state->norm;
2596         return 0;
2597 }
2598
2599 /* ----------------------------------------------------------------------- */
2600
2601 static int adv7842_core_init(struct v4l2_subdev *sd)
2602 {
2603         struct adv7842_state *state = to_state(sd);
2604         struct adv7842_platform_data *pdata = &state->pdata;
2605         hdmi_write(sd, 0x48,
2606                    (pdata->disable_pwrdnb ? 0x80 : 0) |
2607                    (pdata->disable_cable_det_rst ? 0x40 : 0));
2608
2609         disable_input(sd);
2610
2611         /* power */
2612         io_write(sd, 0x0c, 0x42);   /* Power up part and power down VDP */
2613         io_write(sd, 0x15, 0x80);   /* Power up pads */
2614
2615         /* video format */
2616         io_write(sd, 0x02,
2617                  0xf0 |
2618                  pdata->alt_gamma << 3 |
2619                  pdata->op_656_range << 2 |
2620                  pdata->rgb_out << 1 |
2621                  pdata->alt_data_sat << 0);
2622         io_write(sd, 0x03, pdata->op_format_sel);
2623         io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5);
2624         io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
2625                         pdata->insert_av_codes << 2 |
2626                         pdata->replicate_av_codes << 1 |
2627                         pdata->invert_cbcr << 0);
2628
2629         /* HDMI audio */
2630         hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */
2631
2632         /* Drive strength */
2633         io_write_and_or(sd, 0x14, 0xc0,
2634                         pdata->dr_str_data << 4 |
2635                         pdata->dr_str_clk << 2 |
2636                         pdata->dr_str_sync);
2637
2638         /* HDMI free run */
2639         cp_write_and_or(sd, 0xba, 0xfc, pdata->hdmi_free_run_enable |
2640                                         (pdata->hdmi_free_run_mode << 1));
2641
2642         /* SPD free run */
2643         sdp_write_and_or(sd, 0xdd, 0xf0, pdata->sdp_free_run_force |
2644                                          (pdata->sdp_free_run_cbar_en << 1) |
2645                                          (pdata->sdp_free_run_man_col_en << 2) |
2646                                          (pdata->sdp_free_run_force << 3));
2647
2648         /* TODO from platform data */
2649         cp_write(sd, 0x69, 0x14);   /* Enable CP CSC */
2650         io_write(sd, 0x06, 0xa6);   /* positive VS and HS and DE */
2651         cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2652         afe_write(sd, 0xb5, 0x01);  /* Setting MCLK to 256Fs */
2653
2654         afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2655         io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
2656
2657         sdp_csc_coeff(sd, &pdata->sdp_csc_coeff);
2658
2659         /* todo, improve settings for sdram */
2660         if (pdata->sd_ram_size >= 128) {
2661                 sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */
2662                 if (pdata->sd_ram_ddr) {
2663                         /* SDP setup for the AD eval board */
2664                         sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */
2665                         sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */
2666                         sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
2667                         sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
2668                         sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
2669                 } else {
2670                         sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/
2671                         sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */
2672                         sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3,
2673                                                          depends on memory */
2674                         sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */
2675                         sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
2676                         sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
2677                         sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
2678                 }
2679         } else {
2680                 /*
2681                  * Manual UG-214, rev 0 is bit confusing on this bit
2682                  * but a '1' disables any signal if the Ram is active.
2683                  */
2684                 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */
2685         }
2686
2687         select_input(sd, pdata->vid_std_select);
2688
2689         enable_input(sd);
2690
2691         /* disable I2C access to internal EDID ram from HDMI DDC ports */
2692         rep_write_and_or(sd, 0x77, 0xf3, 0x00);
2693
2694         hdmi_write(sd, 0x69, 0xa3); /* HPA manual */
2695         /* HPA disable on port A and B */
2696         io_write_and_or(sd, 0x20, 0xcf, 0x00);
2697
2698         /* LLC */
2699         io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase);
2700         io_write(sd, 0x33, 0x40);
2701
2702         /* interrupts */
2703         io_write(sd, 0x40, 0xf2); /* Configure INT1 */
2704
2705         adv7842_irq_enable(sd, true);
2706
2707         return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2708 }
2709
2710 /* ----------------------------------------------------------------------- */
2711
2712 static int adv7842_ddr_ram_test(struct v4l2_subdev *sd)
2713 {
2714         /*
2715          * From ADV784x external Memory test.pdf
2716          *
2717          * Reset must just been performed before running test.
2718          * Recommended to reset after test.
2719          */
2720         int i;
2721         int pass = 0;
2722         int fail = 0;
2723         int complete = 0;
2724
2725         io_write(sd, 0x00, 0x01);  /* Program SDP 4x1 */
2726         io_write(sd, 0x01, 0x00);  /* Program SDP mode */
2727         afe_write(sd, 0x80, 0x92); /* SDP Recommeneded Write */
2728         afe_write(sd, 0x9B, 0x01); /* SDP Recommeneded Write ADV7844ES1 */
2729         afe_write(sd, 0x9C, 0x60); /* SDP Recommeneded Write ADV7844ES1 */
2730         afe_write(sd, 0x9E, 0x02); /* SDP Recommeneded Write ADV7844ES1 */
2731         afe_write(sd, 0xA0, 0x0B); /* SDP Recommeneded Write ADV7844ES1 */
2732         afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */
2733         io_write(sd, 0x0C, 0x40);  /* Power up ADV7844 */
2734         io_write(sd, 0x15, 0xBA);  /* Enable outputs */
2735         sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */
2736         io_write(sd, 0xFF, 0x04);  /* Reset memory controller */
2737
2738         mdelay(5);
2739
2740         sdp_write(sd, 0x12, 0x00);    /* Disable 3D Comb, Frame TBC & 3DNR */
2741         sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */
2742         sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */
2743         sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */
2744         sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */
2745         sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */
2746         sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */
2747         sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */
2748         sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */
2749         sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */
2750         sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */
2751
2752         mdelay(5);
2753
2754         sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */
2755         sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */
2756
2757         mdelay(20);
2758
2759         for (i = 0; i < 10; i++) {
2760                 u8 result = sdp_io_read(sd, 0xdb);
2761                 if (result & 0x10) {
2762                         complete++;
2763                         if (result & 0x20)
2764                                 fail++;
2765                         else
2766                                 pass++;
2767                 }
2768                 mdelay(20);
2769         }
2770
2771         v4l2_dbg(1, debug, sd,
2772                 "Ram Test: completed %d of %d: pass %d, fail %d\n",
2773                 complete, i, pass, fail);
2774
2775         if (!complete || fail)
2776                 return -EIO;
2777         return 0;
2778 }
2779
2780 static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd,
2781                 struct adv7842_platform_data *pdata)
2782 {
2783         io_write(sd, 0xf1, pdata->i2c_sdp << 1);
2784         io_write(sd, 0xf2, pdata->i2c_sdp_io << 1);
2785         io_write(sd, 0xf3, pdata->i2c_avlink << 1);
2786         io_write(sd, 0xf4, pdata->i2c_cec << 1);
2787         io_write(sd, 0xf5, pdata->i2c_infoframe << 1);
2788
2789         io_write(sd, 0xf8, pdata->i2c_afe << 1);
2790         io_write(sd, 0xf9, pdata->i2c_repeater << 1);
2791         io_write(sd, 0xfa, pdata->i2c_edid << 1);
2792         io_write(sd, 0xfb, pdata->i2c_hdmi << 1);
2793
2794         io_write(sd, 0xfd, pdata->i2c_cp << 1);
2795         io_write(sd, 0xfe, pdata->i2c_vdp << 1);
2796 }
2797
2798 static int adv7842_command_ram_test(struct v4l2_subdev *sd)
2799 {
2800         struct i2c_client *client = v4l2_get_subdevdata(sd);
2801         struct adv7842_state *state = to_state(sd);
2802         struct adv7842_platform_data *pdata = client->dev.platform_data;
2803         struct v4l2_dv_timings timings;
2804         int ret = 0;
2805
2806         if (!pdata)
2807                 return -ENODEV;
2808
2809         if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) {
2810                 v4l2_info(sd, "no sdram or no ddr sdram\n");
2811                 return -EINVAL;
2812         }
2813
2814         main_reset(sd);
2815
2816         adv7842_rewrite_i2c_addresses(sd, pdata);
2817
2818         /* run ram test */
2819         ret = adv7842_ddr_ram_test(sd);
2820
2821         main_reset(sd);
2822
2823         adv7842_rewrite_i2c_addresses(sd, pdata);
2824
2825         /* and re-init chip and state */
2826         adv7842_core_init(sd);
2827
2828         disable_input(sd);
2829
2830         select_input(sd, state->vid_std_select);
2831
2832         enable_input(sd);
2833
2834         edid_write_vga_segment(sd);
2835         edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_A);
2836         edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_B);
2837
2838         timings = state->timings;
2839
2840         memset(&state->timings, 0, sizeof(struct v4l2_dv_timings));
2841
2842         adv7842_s_dv_timings(sd, &timings);
2843
2844         return ret;
2845 }
2846
2847 static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
2848 {
2849         switch (cmd) {
2850         case ADV7842_CMD_RAM_TEST:
2851                 return adv7842_command_ram_test(sd);
2852         }
2853         return -ENOTTY;
2854 }
2855
2856 /* ----------------------------------------------------------------------- */
2857
2858 static const struct v4l2_ctrl_ops adv7842_ctrl_ops = {
2859         .s_ctrl = adv7842_s_ctrl,
2860 };
2861
2862 static const struct v4l2_subdev_core_ops adv7842_core_ops = {
2863         .log_status = adv7842_log_status,
2864         .g_std = adv7842_g_std,
2865         .s_std = adv7842_s_std,
2866         .ioctl = adv7842_ioctl,
2867         .interrupt_service_routine = adv7842_isr,
2868 #ifdef CONFIG_VIDEO_ADV_DEBUG
2869         .g_register = adv7842_g_register,
2870         .s_register = adv7842_s_register,
2871 #endif
2872 };
2873
2874 static const struct v4l2_subdev_video_ops adv7842_video_ops = {
2875         .s_routing = adv7842_s_routing,
2876         .querystd = adv7842_querystd,
2877         .g_input_status = adv7842_g_input_status,
2878         .s_dv_timings = adv7842_s_dv_timings,
2879         .g_dv_timings = adv7842_g_dv_timings,
2880         .query_dv_timings = adv7842_query_dv_timings,
2881         .enum_dv_timings = adv7842_enum_dv_timings,
2882         .dv_timings_cap = adv7842_dv_timings_cap,
2883         .enum_mbus_fmt = adv7842_enum_mbus_fmt,
2884         .g_mbus_fmt = adv7842_g_mbus_fmt,
2885         .try_mbus_fmt = adv7842_g_mbus_fmt,
2886         .s_mbus_fmt = adv7842_g_mbus_fmt,
2887 };
2888
2889 static const struct v4l2_subdev_pad_ops adv7842_pad_ops = {
2890         .get_edid = adv7842_get_edid,
2891         .set_edid = adv7842_set_edid,
2892 };
2893
2894 static const struct v4l2_subdev_ops adv7842_ops = {
2895         .core = &adv7842_core_ops,
2896         .video = &adv7842_video_ops,
2897         .pad = &adv7842_pad_ops,
2898 };
2899
2900 /* -------------------------- custom ctrls ---------------------------------- */
2901
2902 static const struct v4l2_ctrl_config adv7842_ctrl_analog_sampling_phase = {
2903         .ops = &adv7842_ctrl_ops,
2904         .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2905         .name = "Analog Sampling Phase",
2906         .type = V4L2_CTRL_TYPE_INTEGER,
2907         .min = 0,
2908         .max = 0x1f,
2909         .step = 1,
2910         .def = 0,
2911 };
2912
2913 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color_manual = {
2914         .ops = &adv7842_ctrl_ops,
2915         .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2916         .name = "Free Running Color, Manual",
2917         .type = V4L2_CTRL_TYPE_BOOLEAN,
2918         .max = 1,
2919         .step = 1,
2920         .def = 1,
2921 };
2922
2923 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color = {
2924         .ops = &adv7842_ctrl_ops,
2925         .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2926         .name = "Free Running Color",
2927         .type = V4L2_CTRL_TYPE_INTEGER,
2928         .max = 0xffffff,
2929         .step = 0x1,
2930 };
2931
2932
2933 static void adv7842_unregister_clients(struct v4l2_subdev *sd)
2934 {
2935         struct adv7842_state *state = to_state(sd);
2936         if (state->i2c_avlink)
2937                 i2c_unregister_device(state->i2c_avlink);
2938         if (state->i2c_cec)
2939                 i2c_unregister_device(state->i2c_cec);
2940         if (state->i2c_infoframe)
2941                 i2c_unregister_device(state->i2c_infoframe);
2942         if (state->i2c_sdp_io)
2943                 i2c_unregister_device(state->i2c_sdp_io);
2944         if (state->i2c_sdp)
2945                 i2c_unregister_device(state->i2c_sdp);
2946         if (state->i2c_afe)
2947                 i2c_unregister_device(state->i2c_afe);
2948         if (state->i2c_repeater)
2949                 i2c_unregister_device(state->i2c_repeater);
2950         if (state->i2c_edid)
2951                 i2c_unregister_device(state->i2c_edid);
2952         if (state->i2c_hdmi)
2953                 i2c_unregister_device(state->i2c_hdmi);
2954         if (state->i2c_cp)
2955                 i2c_unregister_device(state->i2c_cp);
2956         if (state->i2c_vdp)
2957                 i2c_unregister_device(state->i2c_vdp);
2958
2959         state->i2c_avlink = NULL;
2960         state->i2c_cec = NULL;
2961         state->i2c_infoframe = NULL;
2962         state->i2c_sdp_io = NULL;
2963         state->i2c_sdp = NULL;
2964         state->i2c_afe = NULL;
2965         state->i2c_repeater = NULL;
2966         state->i2c_edid = NULL;
2967         state->i2c_hdmi = NULL;
2968         state->i2c_cp = NULL;
2969         state->i2c_vdp = NULL;
2970 }
2971
2972 static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd, const char *desc,
2973                                                u8 addr, u8 io_reg)
2974 {
2975         struct i2c_client *client = v4l2_get_subdevdata(sd);
2976         struct i2c_client *cp;
2977
2978         io_write(sd, io_reg, addr << 1);
2979
2980         if (addr == 0) {
2981                 v4l2_err(sd, "no %s i2c addr configured\n", desc);
2982                 return NULL;
2983         }
2984
2985         cp = i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2986         if (!cp)
2987                 v4l2_err(sd, "register %s on i2c addr 0x%x failed\n", desc, addr);
2988
2989         return cp;
2990 }
2991
2992 static int adv7842_register_clients(struct v4l2_subdev *sd)
2993 {
2994         struct adv7842_state *state = to_state(sd);
2995         struct adv7842_platform_data *pdata = &state->pdata;
2996
2997         state->i2c_avlink = adv7842_dummy_client(sd, "avlink", pdata->i2c_avlink, 0xf3);
2998         state->i2c_cec = adv7842_dummy_client(sd, "cec", pdata->i2c_cec, 0xf4);
2999         state->i2c_infoframe = adv7842_dummy_client(sd, "infoframe", pdata->i2c_infoframe, 0xf5);
3000         state->i2c_sdp_io = adv7842_dummy_client(sd, "sdp_io", pdata->i2c_sdp_io, 0xf2);
3001         state->i2c_sdp = adv7842_dummy_client(sd, "sdp", pdata->i2c_sdp, 0xf1);
3002         state->i2c_afe = adv7842_dummy_client(sd, "afe", pdata->i2c_afe, 0xf8);
3003         state->i2c_repeater = adv7842_dummy_client(sd, "repeater", pdata->i2c_repeater, 0xf9);
3004         state->i2c_edid = adv7842_dummy_client(sd, "edid", pdata->i2c_edid, 0xfa);
3005         state->i2c_hdmi = adv7842_dummy_client(sd, "hdmi", pdata->i2c_hdmi, 0xfb);
3006         state->i2c_cp = adv7842_dummy_client(sd, "cp", pdata->i2c_cp, 0xfd);
3007         state->i2c_vdp = adv7842_dummy_client(sd, "vdp", pdata->i2c_vdp, 0xfe);
3008
3009         if (!state->i2c_avlink ||
3010             !state->i2c_cec ||
3011             !state->i2c_infoframe ||
3012             !state->i2c_sdp_io ||
3013             !state->i2c_sdp ||
3014             !state->i2c_afe ||
3015             !state->i2c_repeater ||
3016             !state->i2c_edid ||
3017             !state->i2c_hdmi ||
3018             !state->i2c_cp ||
3019             !state->i2c_vdp)
3020                 return -1;
3021
3022         return 0;
3023 }
3024
3025 static int adv7842_probe(struct i2c_client *client,
3026                          const struct i2c_device_id *id)
3027 {
3028         struct adv7842_state *state;
3029         static const struct v4l2_dv_timings cea640x480 =
3030                 V4L2_DV_BT_CEA_640X480P59_94;
3031         struct adv7842_platform_data *pdata = client->dev.platform_data;
3032         struct v4l2_ctrl_handler *hdl;
3033         struct v4l2_subdev *sd;
3034         u16 rev;
3035         int err;
3036
3037         /* Check if the adapter supports the needed features */
3038         if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
3039                 return -EIO;
3040
3041         v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n",
3042                 client->addr << 1);
3043
3044         if (!pdata) {
3045                 v4l_err(client, "No platform data!\n");
3046                 return -ENODEV;
3047         }
3048
3049         state = devm_kzalloc(&client->dev, sizeof(struct adv7842_state), GFP_KERNEL);
3050         if (!state) {
3051                 v4l_err(client, "Could not allocate adv7842_state memory!\n");
3052                 return -ENOMEM;
3053         }
3054
3055         /* platform data */
3056         state->pdata = *pdata;
3057         state->timings = cea640x480;
3058
3059         sd = &state->sd;
3060         v4l2_i2c_subdev_init(sd, client, &adv7842_ops);
3061         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
3062         state->mode = pdata->mode;
3063
3064         state->hdmi_port_a = pdata->input == ADV7842_SELECT_HDMI_PORT_A;
3065         state->restart_stdi_once = true;
3066
3067         /* i2c access to adv7842? */
3068         rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
3069                 adv_smbus_read_byte_data_check(client, 0xeb, false);
3070         if (rev != 0x2012) {
3071                 v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev);
3072                 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
3073                         adv_smbus_read_byte_data_check(client, 0xeb, false);
3074         }
3075         if (rev != 0x2012) {
3076                 v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n",
3077                           client->addr << 1, rev);
3078                 return -ENODEV;
3079         }
3080
3081         if (pdata->chip_reset)
3082                 main_reset(sd);
3083
3084         /* control handlers */
3085         hdl = &state->hdl;
3086         v4l2_ctrl_handler_init(hdl, 6);
3087
3088         /* add in ascending ID order */
3089         v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3090                           V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
3091         v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3092                           V4L2_CID_CONTRAST, 0, 255, 1, 128);
3093         v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3094                           V4L2_CID_SATURATION, 0, 255, 1, 128);
3095         v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3096                           V4L2_CID_HUE, 0, 128, 1, 0);
3097
3098         /* custom controls */
3099         state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
3100                         V4L2_CID_DV_RX_POWER_PRESENT, 0, 3, 0, 0);
3101         state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl,
3102                         &adv7842_ctrl_analog_sampling_phase, NULL);
3103         state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl,
3104                         &adv7842_ctrl_free_run_color_manual, NULL);
3105         state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl,
3106                         &adv7842_ctrl_free_run_color, NULL);
3107         state->rgb_quantization_range_ctrl =
3108                 v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops,
3109                         V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
3110                         0, V4L2_DV_RGB_RANGE_AUTO);
3111         sd->ctrl_handler = hdl;
3112         if (hdl->error) {
3113                 err = hdl->error;
3114                 goto err_hdl;
3115         }
3116         state->detect_tx_5v_ctrl->is_private = true;
3117         state->rgb_quantization_range_ctrl->is_private = true;
3118         state->analog_sampling_phase_ctrl->is_private = true;
3119         state->free_run_color_ctrl_manual->is_private = true;
3120         state->free_run_color_ctrl->is_private = true;
3121
3122         if (adv7842_s_detect_tx_5v_ctrl(sd)) {
3123                 err = -ENODEV;
3124                 goto err_hdl;
3125         }
3126
3127         if (adv7842_register_clients(sd) < 0) {
3128                 err = -ENOMEM;
3129                 v4l2_err(sd, "failed to create all i2c clients\n");
3130                 goto err_i2c;
3131         }
3132
3133         /* work queues */
3134         state->work_queues = create_singlethread_workqueue(client->name);
3135         if (!state->work_queues) {
3136                 v4l2_err(sd, "Could not create work queue\n");
3137                 err = -ENOMEM;
3138                 goto err_i2c;
3139         }
3140
3141         INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
3142                         adv7842_delayed_work_enable_hotplug);
3143
3144         state->pad.flags = MEDIA_PAD_FL_SOURCE;
3145         err = media_entity_init(&sd->entity, 1, &state->pad, 0);
3146         if (err)
3147                 goto err_work_queues;
3148
3149         err = adv7842_core_init(sd);
3150         if (err)
3151                 goto err_entity;
3152
3153         v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
3154                   client->addr << 1, client->adapter->name);
3155         return 0;
3156
3157 err_entity:
3158         media_entity_cleanup(&sd->entity);
3159 err_work_queues:
3160         cancel_delayed_work(&state->delayed_work_enable_hotplug);
3161         destroy_workqueue(state->work_queues);
3162 err_i2c:
3163         adv7842_unregister_clients(sd);
3164 err_hdl:
3165         v4l2_ctrl_handler_free(hdl);
3166         return err;
3167 }
3168
3169 /* ----------------------------------------------------------------------- */
3170
3171 static int adv7842_remove(struct i2c_client *client)
3172 {
3173         struct v4l2_subdev *sd = i2c_get_clientdata(client);
3174         struct adv7842_state *state = to_state(sd);
3175
3176         adv7842_irq_enable(sd, false);
3177
3178         cancel_delayed_work(&state->delayed_work_enable_hotplug);
3179         destroy_workqueue(state->work_queues);
3180         v4l2_device_unregister_subdev(sd);
3181         media_entity_cleanup(&sd->entity);
3182         adv7842_unregister_clients(sd);
3183         v4l2_ctrl_handler_free(sd->ctrl_handler);
3184         return 0;
3185 }
3186
3187 /* ----------------------------------------------------------------------- */
3188
3189 static struct i2c_device_id adv7842_id[] = {
3190         { "adv7842", 0 },
3191         { }
3192 };
3193 MODULE_DEVICE_TABLE(i2c, adv7842_id);
3194
3195 /* ----------------------------------------------------------------------- */
3196
3197 static struct i2c_driver adv7842_driver = {
3198         .driver = {
3199                 .owner = THIS_MODULE,
3200                 .name = "adv7842",
3201         },
3202         .probe = adv7842_probe,
3203         .remove = adv7842_remove,
3204         .id_table = adv7842_id,
3205 };
3206
3207 module_i2c_driver(adv7842_driver);