drivers/media/i2c/adv7604.c

   1 /*
   2  * adv7604 - Analog Devices ADV7604 video decoder driver
   3  *
   4  * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
   5  *
   6  * This program is free software; you may redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  11  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  12  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  13  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  14  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  15  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  16  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  17  * SOFTWARE.
  18  *
  19  */
  20
  21 /*
  22  * References (c = chapter, p = page):
  23  * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
  24  *              Revision 2.5, June 2010
  25  * REF_02 - Analog devices, Register map documentation, Documentation of
  26  *              the register maps, Software manual, Rev. F, June 2010
  27  * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
  28  */
  29
  30
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/slab.h>
  34 #include <linux/i2c.h>
  35 #include <linux/delay.h>
  36 #include <linux/videodev2.h>
  37 #include <linux/workqueue.h>
  38 #include <linux/v4l2-dv-timings.h>
  39 #include <media/v4l2-device.h>
  40 #include <media/v4l2-ctrls.h>
  41 #include <media/v4l2-chip-ident.h>
  42 #include <media/adv7604.h>
  43
  44 static int debug;
  45 module_param(debug, int, 0644);
  46 MODULE_PARM_DESC(debug, "debug level (0-2)");
  47
  48 MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
  49 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
  50 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
  51 MODULE_LICENSE("GPL");
  52
  53 /* ADV7604 system clock frequency */
  54 #define ADV7604_fsc (28636360)
  55
  56 #define DIGITAL_INPUT (state->mode == ADV7604_MODE_HDMI)
  57
  58 /*
  59  **********************************************************************
  60  *
  61  *  Arrays with configuration parameters for the ADV7604
  62  *
  63  **********************************************************************
  64  */
  65 struct adv7604_state {
  66         struct adv7604_platform_data pdata;
  67         struct v4l2_subdev sd;
  68         struct media_pad pad;
  69         struct v4l2_ctrl_handler hdl;
  70         enum adv7604_mode mode;
  71         struct v4l2_dv_timings timings;
  72         u8 edid[256];
  73         unsigned edid_blocks;
  74         struct v4l2_fract aspect_ratio;
  75         u32 rgb_quantization_range;
  76         struct workqueue_struct *work_queues;
  77         struct delayed_work delayed_work_enable_hotplug;
  78         bool connector_hdmi;
  79         bool restart_stdi_once;
  80
  81         /* i2c clients */
  82         struct i2c_client *i2c_avlink;
  83         struct i2c_client *i2c_cec;
  84         struct i2c_client *i2c_infoframe;
  85         struct i2c_client *i2c_esdp;
  86         struct i2c_client *i2c_dpp;
  87         struct i2c_client *i2c_afe;
  88         struct i2c_client *i2c_repeater;
  89         struct i2c_client *i2c_edid;
  90         struct i2c_client *i2c_hdmi;
  91         struct i2c_client *i2c_test;
  92         struct i2c_client *i2c_cp;
  93         struct i2c_client *i2c_vdp;
  94
  95         /* controls */
  96         struct v4l2_ctrl *detect_tx_5v_ctrl;
  97         struct v4l2_ctrl *analog_sampling_phase_ctrl;
  98         struct v4l2_ctrl *free_run_color_manual_ctrl;
  99         struct v4l2_ctrl *free_run_color_ctrl;
 100         struct v4l2_ctrl *rgb_quantization_range_ctrl;
 101 };
 102
 103 /* Supported CEA and DMT timings */
 104 static const struct v4l2_dv_timings adv7604_timings[] = {
 105         V4L2_DV_BT_CEA_720X480P59_94,
 106         V4L2_DV_BT_CEA_720X576P50,
 107         V4L2_DV_BT_CEA_1280X720P24,
 108         V4L2_DV_BT_CEA_1280X720P25,
 109         V4L2_DV_BT_CEA_1280X720P50,
 110         V4L2_DV_BT_CEA_1280X720P60,
 111         V4L2_DV_BT_CEA_1920X1080P24,
 112         V4L2_DV_BT_CEA_1920X1080P25,
 113         V4L2_DV_BT_CEA_1920X1080P30,
 114         V4L2_DV_BT_CEA_1920X1080P50,
 115         V4L2_DV_BT_CEA_1920X1080P60,
 116
 117         /* sorted by DMT ID */
 118         V4L2_DV_BT_DMT_640X350P85,
 119         V4L2_DV_BT_DMT_640X400P85,
 120         V4L2_DV_BT_DMT_720X400P85,
 121         V4L2_DV_BT_DMT_640X480P60,
 122         V4L2_DV_BT_DMT_640X480P72,
 123         V4L2_DV_BT_DMT_640X480P75,
 124         V4L2_DV_BT_DMT_640X480P85,
 125         V4L2_DV_BT_DMT_800X600P56,
 126         V4L2_DV_BT_DMT_800X600P60,
 127         V4L2_DV_BT_DMT_800X600P72,
 128         V4L2_DV_BT_DMT_800X600P75,
 129         V4L2_DV_BT_DMT_800X600P85,
 130         V4L2_DV_BT_DMT_848X480P60,
 131         V4L2_DV_BT_DMT_1024X768P60,
 132         V4L2_DV_BT_DMT_1024X768P70,
 133         V4L2_DV_BT_DMT_1024X768P75,
 134         V4L2_DV_BT_DMT_1024X768P85,
 135         V4L2_DV_BT_DMT_1152X864P75,
 136         V4L2_DV_BT_DMT_1280X768P60_RB,
 137         V4L2_DV_BT_DMT_1280X768P60,
 138         V4L2_DV_BT_DMT_1280X768P75,
 139         V4L2_DV_BT_DMT_1280X768P85,
 140         V4L2_DV_BT_DMT_1280X800P60_RB,
 141         V4L2_DV_BT_DMT_1280X800P60,
 142         V4L2_DV_BT_DMT_1280X800P75,
 143         V4L2_DV_BT_DMT_1280X800P85,
 144         V4L2_DV_BT_DMT_1280X960P60,
 145         V4L2_DV_BT_DMT_1280X960P85,
 146         V4L2_DV_BT_DMT_1280X1024P60,
 147         V4L2_DV_BT_DMT_1280X1024P75,
 148         V4L2_DV_BT_DMT_1280X1024P85,
 149         V4L2_DV_BT_DMT_1360X768P60,
 150         V4L2_DV_BT_DMT_1400X1050P60_RB,
 151         V4L2_DV_BT_DMT_1400X1050P60,
 152         V4L2_DV_BT_DMT_1400X1050P75,
 153         V4L2_DV_BT_DMT_1400X1050P85,
 154         V4L2_DV_BT_DMT_1440X900P60_RB,
 155         V4L2_DV_BT_DMT_1440X900P60,
 156         V4L2_DV_BT_DMT_1600X1200P60,
 157         V4L2_DV_BT_DMT_1680X1050P60_RB,
 158         V4L2_DV_BT_DMT_1680X1050P60,
 159         V4L2_DV_BT_DMT_1792X1344P60,
 160         V4L2_DV_BT_DMT_1856X1392P60,
 161         V4L2_DV_BT_DMT_1920X1200P60_RB,
 162         V4L2_DV_BT_DMT_1366X768P60,
 163         V4L2_DV_BT_DMT_1920X1080P60,
 164         { },
 165 };
 166
 167 struct adv7604_video_standards {
 168         struct v4l2_dv_timings timings;
 169         u8 vid_std;
 170         u8 v_freq;
 171 };
 172
 173 /* sorted by number of lines */
 174 static const struct adv7604_video_standards adv7604_prim_mode_comp[] = {
 175         /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
 176         { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
 177         { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
 178         { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
 179         { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
 180         { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
 181         { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
 182         { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
 183         { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
 184         /* TODO add 1920x1080P60_RB (CVT timing) */
 185         { },
 186 };
 187
 188 /* sorted by number of lines */
 189 static const struct adv7604_video_standards adv7604_prim_mode_gr[] = {
 190         { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
 191         { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
 192         { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
 193         { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
 194         { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
 195         { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
 196         { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
 197         { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
 198         { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
 199         { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
 200         { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
 201         { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
 202         { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
 203         { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
 204         { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
 205         { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
 206         { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
 207         { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
 208         { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
 209         { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
 210         /* TODO add 1600X1200P60_RB (not a DMT timing) */
 211         { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
 212         { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
 213         { },
 214 };
 215
 216 /* sorted by number of lines */
 217 static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = {
 218         { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
 219         { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
 220         { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
 221         { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
 222         { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
 223         { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
 224         { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
 225         { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
 226         { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
 227         { },
 228 };
 229
 230 /* sorted by number of lines */
 231 static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = {
 232         { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
 233         { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
 234         { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
 235         { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
 236         { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
 237         { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
 238         { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
 239         { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
 240         { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
 241         { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
 242         { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
 243         { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
 244         { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
 245         { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
 246         { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
 247         { },
 248 };
 249
 250 /* ----------------------------------------------------------------------- */
 251
 252 static inline struct adv7604_state *to_state(struct v4l2_subdev *sd)
 253 {
 254         return container_of(sd, struct adv7604_state, sd);
 255 }
 256
 257 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
 258 {
 259         return &container_of(ctrl->handler, struct adv7604_state, hdl)->sd;
 260 }
 261
 262 static inline unsigned hblanking(const struct v4l2_bt_timings *t)
 263 {
 264         return t->hfrontporch + t->hsync + t->hbackporch;
 265 }
 266
 267 static inline unsigned htotal(const struct v4l2_bt_timings *t)
 268 {
 269         return t->width + t->hfrontporch + t->hsync + t->hbackporch;
 270 }
 271
 272 static inline unsigned vblanking(const struct v4l2_bt_timings *t)
 273 {
 274         return t->vfrontporch + t->vsync + t->vbackporch;
 275 }
 276
 277 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
 278 {
 279         return t->height + t->vfrontporch + t->vsync + t->vbackporch;
 280 }
 281
 282 /* ----------------------------------------------------------------------- */
 283
 284 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
 285                 u8 command, bool check)
 286 {
 287         union i2c_smbus_data data;
 288
 289         if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
 290                         I2C_SMBUS_READ, command,
 291                         I2C_SMBUS_BYTE_DATA, &data))
 292                 return data.byte;
 293         if (check)
 294                 v4l_err(client, "error reading %02x, %02x\n",
 295                                 client->addr, command);
 296         return -EIO;
 297 }
 298
 299 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
 300 {
 301         return adv_smbus_read_byte_data_check(client, command, true);
 302 }
 303
 304 static s32 adv_smbus_write_byte_data(struct i2c_client *client,
 305                                         u8 command, u8 value)
 306 {
 307         union i2c_smbus_data data;
 308         int err;
 309         int i;
 310
 311         data.byte = value;
 312         for (i = 0; i < 3; i++) {
 313                 err = i2c_smbus_xfer(client->adapter, client->addr,
 314                                 client->flags,
 315                                 I2C_SMBUS_WRITE, command,
 316                                 I2C_SMBUS_BYTE_DATA, &data);
 317                 if (!err)
 318                         break;
 319         }
 320         if (err < 0)
 321                 v4l_err(client, "error writing %02x, %02x, %02x\n",
 322                                 client->addr, command, value);
 323         return err;
 324 }
 325
 326 static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
 327                u8 command, unsigned length, const u8 *values)
 328 {
 329         union i2c_smbus_data data;
 330
 331         if (length > I2C_SMBUS_BLOCK_MAX)
 332                 length = I2C_SMBUS_BLOCK_MAX;
 333         data.block[0] = length;
 334         memcpy(data.block + 1, values, length);
 335         return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
 336                               I2C_SMBUS_WRITE, command,
 337                               I2C_SMBUS_I2C_BLOCK_DATA, &data);
 338 }
 339
 340 /* ----------------------------------------------------------------------- */
 341
 342 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
 343 {
 344         struct i2c_client *client = v4l2_get_subdevdata(sd);
 345
 346         return adv_smbus_read_byte_data(client, reg);
 347 }
 348
 349 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 350 {
 351         struct i2c_client *client = v4l2_get_subdevdata(sd);
 352
 353         return adv_smbus_write_byte_data(client, reg, val);
 354 }
 355
 356 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 357 {
 358         return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
 359 }
 360
 361 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
 362 {
 363         struct adv7604_state *state = to_state(sd);
 364
 365         return adv_smbus_read_byte_data(state->i2c_avlink, reg);
 366 }
 367
 368 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 369 {
 370         struct adv7604_state *state = to_state(sd);
 371
 372         return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
 373 }
 374
 375 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
 376 {
 377         struct adv7604_state *state = to_state(sd);
 378
 379         return adv_smbus_read_byte_data(state->i2c_cec, reg);
 380 }
 381
 382 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 383 {
 384         struct adv7604_state *state = to_state(sd);
 385
 386         return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
 387 }
 388
 389 static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 390 {
 391         return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val);
 392 }
 393
 394 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
 395 {
 396         struct adv7604_state *state = to_state(sd);
 397
 398         return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
 399 }
 400
 401 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 402 {
 403         struct adv7604_state *state = to_state(sd);
 404
 405         return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
 406 }
 407
 408 static inline int esdp_read(struct v4l2_subdev *sd, u8 reg)
 409 {
 410         struct adv7604_state *state = to_state(sd);
 411
 412         return adv_smbus_read_byte_data(state->i2c_esdp, reg);
 413 }
 414
 415 static inline int esdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 416 {
 417         struct adv7604_state *state = to_state(sd);
 418
 419         return adv_smbus_write_byte_data(state->i2c_esdp, reg, val);
 420 }
 421
 422 static inline int dpp_read(struct v4l2_subdev *sd, u8 reg)
 423 {
 424         struct adv7604_state *state = to_state(sd);
 425
 426         return adv_smbus_read_byte_data(state->i2c_dpp, reg);
 427 }
 428
 429 static inline int dpp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 430 {
 431         struct adv7604_state *state = to_state(sd);
 432
 433         return adv_smbus_write_byte_data(state->i2c_dpp, reg, val);
 434 }
 435
 436 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
 437 {
 438         struct adv7604_state *state = to_state(sd);
 439
 440         return adv_smbus_read_byte_data(state->i2c_afe, reg);
 441 }
 442
 443 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 444 {
 445         struct adv7604_state *state = to_state(sd);
 446
 447         return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
 448 }
 449
 450 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
 451 {
 452         struct adv7604_state *state = to_state(sd);
 453
 454         return adv_smbus_read_byte_data(state->i2c_repeater, reg);
 455 }
 456
 457 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 458 {
 459         struct adv7604_state *state = to_state(sd);
 460
 461         return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
 462 }
 463
 464 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 465 {
 466         return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
 467 }
 468
 469 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
 470 {
 471         struct adv7604_state *state = to_state(sd);
 472
 473         return adv_smbus_read_byte_data(state->i2c_edid, reg);
 474 }
 475
 476 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 477 {
 478         struct adv7604_state *state = to_state(sd);
 479
 480         return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
 481 }
 482
 483 static inline int edid_read_block(struct v4l2_subdev *sd, unsigned len, u8 *val)
 484 {
 485         struct adv7604_state *state = to_state(sd);
 486         struct i2c_client *client = state->i2c_edid;
 487         u8 msgbuf0[1] = { 0 };
 488         u8 msgbuf1[256];
 489         struct i2c_msg msg[2] = { { client->addr, 0, 1, msgbuf0 },
 490                                   { client->addr, 0 | I2C_M_RD, len, msgbuf1 }
 491                                 };
 492
 493         if (i2c_transfer(client->adapter, msg, 2) < 0)
 494                 return -EIO;
 495         memcpy(val, msgbuf1, len);
 496         return 0;
 497 }
 498
 499 static void adv7604_delayed_work_enable_hotplug(struct work_struct *work)
 500 {
 501         struct delayed_work *dwork = to_delayed_work(work);
 502         struct adv7604_state *state = container_of(dwork, struct adv7604_state,
 503                                                 delayed_work_enable_hotplug);
 504         struct v4l2_subdev *sd = &state->sd;
 505
 506         v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
 507
 508         v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)1);
 509 }
 510
 511 static inline int edid_write_block(struct v4l2_subdev *sd,
 512                                         unsigned len, const u8 *val)
 513 {
 514         struct i2c_client *client = v4l2_get_subdevdata(sd);
 515         struct adv7604_state *state = to_state(sd);
 516         int err = 0;
 517         int i;
 518
 519         v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len);
 520
 521         v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)0);
 522
 523         /* Disables I2C access to internal EDID ram from DDC port */
 524         rep_write_and_or(sd, 0x77, 0xf0, 0x0);
 525
 526         for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX)
 527                 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
 528                                 I2C_SMBUS_BLOCK_MAX, val + i);
 529         if (err)
 530                 return err;
 531
 532         /* adv7604 calculates the checksums and enables I2C access to internal
 533            EDID ram from DDC port. */
 534         rep_write_and_or(sd, 0x77, 0xf0, 0x1);
 535
 536         for (i = 0; i < 1000; i++) {
 537                 if (rep_read(sd, 0x7d) & 1)
 538                         break;
 539                 mdelay(1);
 540         }
 541         if (i == 1000) {
 542                 v4l_err(client, "error enabling edid\n");
 543                 return -EIO;
 544         }
 545
 546         /* enable hotplug after 100 ms */
 547         queue_delayed_work(state->work_queues,
 548                         &state->delayed_work_enable_hotplug, HZ / 10);
 549         return 0;
 550 }
 551
 552 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
 553 {
 554         struct adv7604_state *state = to_state(sd);
 555
 556         return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
 557 }
 558
 559 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 560 {
 561         struct adv7604_state *state = to_state(sd);
 562
 563         return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
 564 }
 565
 566 static inline int test_read(struct v4l2_subdev *sd, u8 reg)
 567 {
 568         struct adv7604_state *state = to_state(sd);
 569
 570         return adv_smbus_read_byte_data(state->i2c_test, reg);
 571 }
 572
 573 static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 574 {
 575         struct adv7604_state *state = to_state(sd);
 576
 577         return adv_smbus_write_byte_data(state->i2c_test, reg, val);
 578 }
 579
 580 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
 581 {
 582         struct adv7604_state *state = to_state(sd);
 583
 584         return adv_smbus_read_byte_data(state->i2c_cp, reg);
 585 }
 586
 587 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 588 {
 589         struct adv7604_state *state = to_state(sd);
 590
 591         return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
 592 }
 593
 594 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 595 {
 596         return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
 597 }
 598
 599 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
 600 {
 601         struct adv7604_state *state = to_state(sd);
 602
 603         return adv_smbus_read_byte_data(state->i2c_vdp, reg);
 604 }
 605
 606 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 607 {
 608         struct adv7604_state *state = to_state(sd);
 609
 610         return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
 611 }
 612
 613 /* ----------------------------------------------------------------------- */
 614
 615 #ifdef CONFIG_VIDEO_ADV_DEBUG
 616 static void adv7604_inv_register(struct v4l2_subdev *sd)
 617 {
 618         v4l2_info(sd, "0x000-0x0ff: IO Map\n");
 619         v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
 620         v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
 621         v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
 622         v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
 623         v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
 624         v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
 625         v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
 626         v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
 627         v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
 628         v4l2_info(sd, "0xa00-0xaff: Test Map\n");
 629         v4l2_info(sd, "0xb00-0xbff: CP Map\n");
 630         v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
 631 }
 632
 633 static int adv7604_g_register(struct v4l2_subdev *sd,
 634                                         struct v4l2_dbg_register *reg)
 635 {
 636         struct i2c_client *client = v4l2_get_subdevdata(sd);
 637
 638         if (!v4l2_chip_match_i2c_client(client, &reg->match))
 639                 return -EINVAL;
 640         if (!capable(CAP_SYS_ADMIN))
 641                 return -EPERM;
 642         reg->size = 1;
 643         switch (reg->reg >> 8) {
 644         case 0:
 645                 reg->val = io_read(sd, reg->reg & 0xff);
 646                 break;
 647         case 1:
 648                 reg->val = avlink_read(sd, reg->reg & 0xff);
 649                 break;
 650         case 2:
 651                 reg->val = cec_read(sd, reg->reg & 0xff);
 652                 break;
 653         case 3:
 654                 reg->val = infoframe_read(sd, reg->reg & 0xff);
 655                 break;
 656         case 4:
 657                 reg->val = esdp_read(sd, reg->reg & 0xff);
 658                 break;
 659         case 5:
 660                 reg->val = dpp_read(sd, reg->reg & 0xff);
 661                 break;
 662         case 6:
 663                 reg->val = afe_read(sd, reg->reg & 0xff);
 664                 break;
 665         case 7:
 666                 reg->val = rep_read(sd, reg->reg & 0xff);
 667                 break;
 668         case 8:
 669                 reg->val = edid_read(sd, reg->reg & 0xff);
 670                 break;
 671         case 9:
 672                 reg->val = hdmi_read(sd, reg->reg & 0xff);
 673                 break;
 674         case 0xa:
 675                 reg->val = test_read(sd, reg->reg & 0xff);
 676                 break;
 677         case 0xb:
 678                 reg->val = cp_read(sd, reg->reg & 0xff);
 679                 break;
 680         case 0xc:
 681                 reg->val = vdp_read(sd, reg->reg & 0xff);
 682                 break;
 683         default:
 684                 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
 685                 adv7604_inv_register(sd);
 686                 break;
 687         }
 688         return 0;
 689 }
 690
 691 static int adv7604_s_register(struct v4l2_subdev *sd,
 692                                         struct v4l2_dbg_register *reg)
 693 {
 694         struct i2c_client *client = v4l2_get_subdevdata(sd);
 695
 696         if (!v4l2_chip_match_i2c_client(client, &reg->match))
 697                 return -EINVAL;
 698         if (!capable(CAP_SYS_ADMIN))
 699                 return -EPERM;
 700         switch (reg->reg >> 8) {
 701         case 0:
 702                 io_write(sd, reg->reg & 0xff, reg->val & 0xff);
 703                 break;
 704         case 1:
 705                 avlink_write(sd, reg->reg & 0xff, reg->val & 0xff);
 706                 break;
 707         case 2:
 708                 cec_write(sd, reg->reg & 0xff, reg->val & 0xff);
 709                 break;
 710         case 3:
 711                 infoframe_write(sd, reg->reg & 0xff, reg->val & 0xff);
 712                 break;
 713         case 4:
 714                 esdp_write(sd, reg->reg & 0xff, reg->val & 0xff);
 715                 break;
 716         case 5:
 717                 dpp_write(sd, reg->reg & 0xff, reg->val & 0xff);
 718                 break;
 719         case 6:
 720                 afe_write(sd, reg->reg & 0xff, reg->val & 0xff);
 721                 break;
 722         case 7:
 723                 rep_write(sd, reg->reg & 0xff, reg->val & 0xff);
 724                 break;
 725         case 8:
 726                 edid_write(sd, reg->reg & 0xff, reg->val & 0xff);
 727                 break;
 728         case 9:
 729                 hdmi_write(sd, reg->reg & 0xff, reg->val & 0xff);
 730                 break;
 731         case 0xa:
 732                 test_write(sd, reg->reg & 0xff, reg->val & 0xff);
 733                 break;
 734         case 0xb:
 735                 cp_write(sd, reg->reg & 0xff, reg->val & 0xff);
 736                 break;
 737         case 0xc:
 738                 vdp_write(sd, reg->reg & 0xff, reg->val & 0xff);
 739                 break;
 740         default:
 741                 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
 742                 adv7604_inv_register(sd);
 743                 break;
 744         }
 745         return 0;
 746 }
 747 #endif
 748
 749 static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
 750 {
 751         struct adv7604_state *state = to_state(sd);
 752
 753         /* port A only */
 754         return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
 755                                 ((io_read(sd, 0x6f) & 0x10) >> 4));
 756 }
 757
 758 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
 759                 u8 prim_mode,
 760                 const struct adv7604_video_standards *predef_vid_timings,
 761                 const struct v4l2_dv_timings *timings)
 762 {
 763         struct adv7604_state *state = to_state(sd);
 764         int i;
 765
 766         for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
 767                 if (!v4l_match_dv_timings(timings, &predef_vid_timings[i].timings,
 768                                         DIGITAL_INPUT ? 250000 : 1000000))
 769                         continue;
 770                 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
 771                 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
 772                                 prim_mode); /* v_freq and prim mode */
 773                 return 0;
 774         }
 775
 776         return -1;
 777 }
 778
 779 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
 780                 struct v4l2_dv_timings *timings)
 781 {
 782         struct adv7604_state *state = to_state(sd);
 783         int err;
 784
 785         v4l2_dbg(1, debug, sd, "%s", __func__);
 786
 787         /* reset to default values */
 788         io_write(sd, 0x16, 0x43);
 789         io_write(sd, 0x17, 0x5a);
 790         /* disable embedded syncs for auto graphics mode */
 791         cp_write_and_or(sd, 0x81, 0xef, 0x00);
 792         cp_write(sd, 0x8f, 0x00);
 793         cp_write(sd, 0x90, 0x00);
 794         cp_write(sd, 0xa2, 0x00);
 795         cp_write(sd, 0xa3, 0x00);
 796         cp_write(sd, 0xa4, 0x00);
 797         cp_write(sd, 0xa5, 0x00);
 798         cp_write(sd, 0xa6, 0x00);
 799         cp_write(sd, 0xa7, 0x00);
 800         cp_write(sd, 0xab, 0x00);
 801         cp_write(sd, 0xac, 0x00);
 802
 803         switch (state->mode) {
 804         case ADV7604_MODE_COMP:
 805         case ADV7604_MODE_GR:
 806                 err = find_and_set_predefined_video_timings(sd,
 807                                 0x01, adv7604_prim_mode_comp, timings);
 808                 if (err)
 809                         err = find_and_set_predefined_video_timings(sd,
 810                                         0x02, adv7604_prim_mode_gr, timings);
 811                 break;
 812         case ADV7604_MODE_HDMI:
 813                 err = find_and_set_predefined_video_timings(sd,
 814                                 0x05, adv7604_prim_mode_hdmi_comp, timings);
 815                 if (err)
 816                         err = find_and_set_predefined_video_timings(sd,
 817                                         0x06, adv7604_prim_mode_hdmi_gr, timings);
 818                 break;
 819         default:
 820                 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
 821                                 __func__, state->mode);
 822                 err = -1;
 823                 break;
 824         }
 825
 826
 827         return err;
 828 }
 829
 830 static void configure_custom_video_timings(struct v4l2_subdev *sd,
 831                 const struct v4l2_bt_timings *bt)
 832 {
 833         struct adv7604_state *state = to_state(sd);
 834         struct i2c_client *client = v4l2_get_subdevdata(sd);
 835         u32 width = htotal(bt);
 836         u32 height = vtotal(bt);
 837         u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
 838         u16 cp_start_eav = width - bt->hfrontporch;
 839         u16 cp_start_vbi = height - bt->vfrontporch;
 840         u16 cp_end_vbi = bt->vsync + bt->vbackporch;
 841         u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
 842                 ((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
 843         const u8 pll[2] = {
 844                 0xc0 | ((width >> 8) & 0x1f),
 845                 width & 0xff
 846         };
 847
 848         v4l2_dbg(2, debug, sd, "%s\n", __func__);
 849
 850         switch (state->mode) {
 851         case ADV7604_MODE_COMP:
 852         case ADV7604_MODE_GR:
 853                 /* auto graphics */
 854                 io_write(sd, 0x00, 0x07); /* video std */
 855                 io_write(sd, 0x01, 0x02); /* prim mode */
 856                 /* enable embedded syncs for auto graphics mode */
 857                 cp_write_and_or(sd, 0x81, 0xef, 0x10);
 858
 859                 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
 860                 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
 861                 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
 862                 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) {
 863                         v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
 864                         break;
 865                 }
 866
 867                 /* active video - horizontal timing */
 868                 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
 869                 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
 870                                         ((cp_start_eav >> 8) & 0x0f));
 871                 cp_write(sd, 0xa4, cp_start_eav & 0xff);
 872
 873                 /* active video - vertical timing */
 874                 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
 875                 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
 876                                         ((cp_end_vbi >> 8) & 0xf));
 877                 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
 878                 break;
 879         case ADV7604_MODE_HDMI:
 880                 /* set default prim_mode/vid_std for HDMI
 881                    accoring to [REF_03, c. 4.2] */
 882                 io_write(sd, 0x00, 0x02); /* video std */
 883                 io_write(sd, 0x01, 0x06); /* prim mode */
 884                 break;
 885         default:
 886                 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
 887                                 __func__, state->mode);
 888                 break;
 889         }
 890
 891         cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
 892         cp_write(sd, 0x90, ch1_fr_ll & 0xff);
 893         cp_write(sd, 0xab, (height >> 4) & 0xff);
 894         cp_write(sd, 0xac, (height & 0x0f) << 4);
 895 }
 896
 897 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
 898 {
 899         struct adv7604_state *state = to_state(sd);
 900
 901         switch (state->rgb_quantization_range) {
 902         case V4L2_DV_RGB_RANGE_AUTO:
 903                 /* automatic */
 904                 if (DIGITAL_INPUT && !(hdmi_read(sd, 0x05) & 0x80)) {
 905                         /* receiving DVI-D signal */
 906
 907                         /* ADV7604 selects RGB limited range regardless of
 908                            input format (CE/IT) in automatic mode */
 909                         if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
 910                                 /* RGB limited range (16-235) */
 911                                 io_write_and_or(sd, 0x02, 0x0f, 0x00);
 912
 913                         } else {
 914                                 /* RGB full range (0-255) */
 915                                 io_write_and_or(sd, 0x02, 0x0f, 0x10);
 916                         }
 917                 } else {
 918                         /* receiving HDMI or analog signal, set automode */
 919                         io_write_and_or(sd, 0x02, 0x0f, 0xf0);
 920                 }
 921                 break;
 922         case V4L2_DV_RGB_RANGE_LIMITED:
 923                 /* RGB limited range (16-235) */
 924                 io_write_and_or(sd, 0x02, 0x0f, 0x00);
 925                 break;
 926         case V4L2_DV_RGB_RANGE_FULL:
 927                 /* RGB full range (0-255) */
 928                 io_write_and_or(sd, 0x02, 0x0f, 0x10);
 929                 break;
 930         }
 931 }
 932
 933
 934 static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl)
 935 {
 936         struct v4l2_subdev *sd = to_sd(ctrl);
 937         struct adv7604_state *state = to_state(sd);
 938
 939         switch (ctrl->id) {
 940         case V4L2_CID_BRIGHTNESS:
 941                 cp_write(sd, 0x3c, ctrl->val);
 942                 return 0;
 943         case V4L2_CID_CONTRAST:
 944                 cp_write(sd, 0x3a, ctrl->val);
 945                 return 0;
 946         case V4L2_CID_SATURATION:
 947                 cp_write(sd, 0x3b, ctrl->val);
 948                 return 0;
 949         case V4L2_CID_HUE:
 950                 cp_write(sd, 0x3d, ctrl->val);
 951                 return 0;
 952         case  V4L2_CID_DV_RX_RGB_RANGE:
 953                 state->rgb_quantization_range = ctrl->val;
 954                 set_rgb_quantization_range(sd);
 955                 return 0;
 956         case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
 957                 /* Set the analog sampling phase. This is needed to find the
 958                    best sampling phase for analog video: an application or
 959                    driver has to try a number of phases and analyze the picture
 960                    quality before settling on the best performing phase. */
 961                 afe_write(sd, 0xc8, ctrl->val);
 962                 return 0;
 963         case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
 964                 /* Use the default blue color for free running mode,
 965                    or supply your own. */
 966                 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
 967                 return 0;
 968         case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
 969                 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
 970                 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
 971                 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
 972                 return 0;
 973         }
 974         return -EINVAL;
 975 }
 976
 977 static int adv7604_g_chip_ident(struct v4l2_subdev *sd,
 978                                         struct v4l2_dbg_chip_ident *chip)
 979 {
 980         struct i2c_client *client = v4l2_get_subdevdata(sd);
 981
 982         return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_ADV7604, 0);
 983 }
 984
 985 /* ----------------------------------------------------------------------- */
 986
 987 static inline bool no_power(struct v4l2_subdev *sd)
 988 {
 989         /* Entire chip or CP powered off */
 990         return io_read(sd, 0x0c) & 0x24;
 991 }
 992
 993 static inline bool no_signal_tmds(struct v4l2_subdev *sd)
 994 {
 995         /* TODO port B, C and D */
 996         return !(io_read(sd, 0x6a) & 0x10);
 997 }
 998
 999 static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1000 {
1001         return (io_read(sd, 0x6a) & 0xe0) != 0xe0;
1002 }
1003
1004 static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1005 {
1006         /* TODO channel 2 */
1007         return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1008 }
1009
1010 static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1011 {
1012         /* TODO channel 2 */
1013         return !(cp_read(sd, 0xb1) & 0x80);
1014 }
1015
1016 static inline bool no_signal(struct v4l2_subdev *sd)
1017 {
1018         struct adv7604_state *state = to_state(sd);
1019         bool ret;
1020
1021         ret = no_power(sd);
1022
1023         ret |= no_lock_stdi(sd);
1024         ret |= no_lock_sspd(sd);
1025
1026         if (DIGITAL_INPUT) {
1027                 ret |= no_lock_tmds(sd);
1028                 ret |= no_signal_tmds(sd);
1029         }
1030
1031         return ret;
1032 }
1033
1034 static inline bool no_lock_cp(struct v4l2_subdev *sd)
1035 {
1036         /* CP has detected a non standard number of lines on the incoming
1037            video compared to what it is configured to receive by s_dv_timings */
1038         return io_read(sd, 0x12) & 0x01;
1039 }
1040
1041 static int adv7604_g_input_status(struct v4l2_subdev *sd, u32 *status)
1042 {
1043         struct adv7604_state *state = to_state(sd);
1044
1045         *status = 0;
1046         *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1047         *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1048         if (no_lock_cp(sd))
1049                 *status |= DIGITAL_INPUT ? V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
1050
1051         v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1052
1053         return 0;
1054 }
1055
1056 /* ----------------------------------------------------------------------- */
1057
1058 static void adv7604_print_timings(struct v4l2_subdev *sd,
1059         struct v4l2_dv_timings *timings, const char *txt, bool detailed)
1060 {
1061         struct v4l2_bt_timings *bt = &timings->bt;
1062         u32 htot, vtot;
1063
1064         if (timings->type != V4L2_DV_BT_656_1120)
1065                 return;
1066
1067         htot = htotal(bt);
1068         vtot = vtotal(bt);
1069
1070         v4l2_info(sd, "%s %dx%d%s%d (%dx%d)",
1071                         txt, bt->width, bt->height, bt->interlaced ? "i" : "p",
1072                         (htot * vtot) > 0 ? ((u32)bt->pixelclock /
1073                                 (htot * vtot)) : 0,
1074                         htot, vtot);
1075
1076         if (detailed) {
1077                 v4l2_info(sd, "    horizontal: fp = %d, %ssync = %d, bp = %d\n",
1078                                 bt->hfrontporch,
1079                                 (bt->polarities & V4L2_DV_HSYNC_POS_POL) ? "+" : "-",
1080                                 bt->hsync, bt->hbackporch);
1081                 v4l2_info(sd, "    vertical: fp = %d, %ssync = %d, bp = %d\n",
1082                                 bt->vfrontporch,
1083                                 (bt->polarities & V4L2_DV_VSYNC_POS_POL) ? "+" : "-",
1084                                 bt->vsync, bt->vbackporch);
1085                 v4l2_info(sd, "    pixelclock: %lld, flags: 0x%x, standards: 0x%x\n",
1086                                 bt->pixelclock, bt->flags, bt->standards);
1087         }
1088 }
1089
1090 struct stdi_readback {
1091         u16 bl, lcf, lcvs;
1092         u8 hs_pol, vs_pol;
1093         bool interlaced;
1094 };
1095
1096 static int stdi2dv_timings(struct v4l2_subdev *sd,
1097                 struct stdi_readback *stdi,
1098                 struct v4l2_dv_timings *timings)
1099 {
1100         struct adv7604_state *state = to_state(sd);
1101         u32 hfreq = (ADV7604_fsc * 8) / stdi->bl;
1102         u32 pix_clk;
1103         int i;
1104
1105         for (i = 0; adv7604_timings[i].bt.height; i++) {
1106                 if (vtotal(&adv7604_timings[i].bt) != stdi->lcf + 1)
1107                         continue;
1108                 if (adv7604_timings[i].bt.vsync != stdi->lcvs)
1109                         continue;
1110
1111                 pix_clk = hfreq * htotal(&adv7604_timings[i].bt);
1112
1113                 if ((pix_clk < adv7604_timings[i].bt.pixelclock + 1000000) &&
1114                     (pix_clk > adv7604_timings[i].bt.pixelclock - 1000000)) {
1115                         *timings = adv7604_timings[i];
1116                         return 0;
1117                 }
1118         }
1119
1120         if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1121                         (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1122                         (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1123                         timings))
1124                 return 0;
1125         if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1126                         (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1127                         (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1128                         state->aspect_ratio, timings))
1129                 return 0;
1130
1131         v4l2_dbg(2, debug, sd,
1132                 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1133                 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1134                 stdi->hs_pol, stdi->vs_pol);
1135         return -1;
1136 }
1137
1138 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1139 {
1140         if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1141                 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1142                 return -1;
1143         }
1144
1145         /* read STDI */
1146         stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1147         stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1148         stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1149         stdi->interlaced = io_read(sd, 0x12) & 0x10;
1150
1151         /* read SSPD */
1152         if ((cp_read(sd, 0xb5) & 0x03) == 0x01) {
1153                 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1154                                 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1155                 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1156                                 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1157         } else {
1158                 stdi->hs_pol = 'x';
1159                 stdi->vs_pol = 'x';
1160         }
1161
1162         if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1163                 v4l2_dbg(2, debug, sd,
1164                         "%s: signal lost during readout of STDI/SSPD\n", __func__);
1165                 return -1;
1166         }
1167
1168         if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1169                 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1170                 memset(stdi, 0, sizeof(struct stdi_readback));
1171                 return -1;
1172         }
1173
1174         v4l2_dbg(2, debug, sd,
1175                 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1176                 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1177                 stdi->hs_pol, stdi->vs_pol,
1178                 stdi->interlaced ? "interlaced" : "progressive");
1179
1180         return 0;
1181 }
1182
1183 static int adv7604_enum_dv_timings(struct v4l2_subdev *sd,
1184                         struct v4l2_enum_dv_timings *timings)
1185 {
1186         if (timings->index >= ARRAY_SIZE(adv7604_timings) - 1)
1187                 return -EINVAL;
1188         memset(timings->reserved, 0, sizeof(timings->reserved));
1189         timings->timings = adv7604_timings[timings->index];
1190         return 0;
1191 }
1192
1193 static int adv7604_dv_timings_cap(struct v4l2_subdev *sd,
1194                         struct v4l2_dv_timings_cap *cap)
1195 {
1196         struct adv7604_state *state = to_state(sd);
1197
1198         cap->type = V4L2_DV_BT_656_1120;
1199         cap->bt.max_width = 1920;
1200         cap->bt.max_height = 1200;
1201         cap->bt.min_pixelclock = 27000000;
1202         if (DIGITAL_INPUT)
1203                 cap->bt.max_pixelclock = 225000000;
1204         else
1205                 cap->bt.max_pixelclock = 170000000;
1206         cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1207                          V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
1208         cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
1209                 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
1210         return 0;
1211 }
1212
1213 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1214    if the format is listed in adv7604_timings[] */
1215 static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1216                 struct v4l2_dv_timings *timings)
1217 {
1218         struct adv7604_state *state = to_state(sd);
1219         int i;
1220
1221         for (i = 0; adv7604_timings[i].bt.width; i++) {
1222                 if (v4l_match_dv_timings(timings, &adv7604_timings[i],
1223                                         DIGITAL_INPUT ? 250000 : 1000000)) {
1224                         *timings = adv7604_timings[i];
1225                         break;
1226                 }
1227         }
1228 }
1229
1230 static int adv7604_query_dv_timings(struct v4l2_subdev *sd,
1231                         struct v4l2_dv_timings *timings)
1232 {
1233         struct adv7604_state *state = to_state(sd);
1234         struct v4l2_bt_timings *bt = &timings->bt;
1235         struct stdi_readback stdi;
1236
1237         if (!timings)
1238                 return -EINVAL;
1239
1240         memset(timings, 0, sizeof(struct v4l2_dv_timings));
1241
1242         if (no_signal(sd)) {
1243                 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1244                 return -ENOLINK;
1245         }
1246
1247         /* read STDI */
1248         if (read_stdi(sd, &stdi)) {
1249                 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1250                 return -ENOLINK;
1251         }
1252         bt->interlaced = stdi.interlaced ?
1253                 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1254
1255         if (DIGITAL_INPUT) {
1256                 timings->type = V4L2_DV_BT_656_1120;
1257
1258                 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1259                 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
1260                 bt->pixelclock = (hdmi_read(sd, 0x06) * 1000000) +
1261                         ((hdmi_read(sd, 0x3b) & 0x30) >> 4) * 250000;
1262                 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
1263                         hdmi_read(sd, 0x21);
1264                 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
1265                         hdmi_read(sd, 0x23);
1266                 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
1267                         hdmi_read(sd, 0x25);
1268                 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1269                         hdmi_read(sd, 0x2b)) / 2;
1270                 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1271                         hdmi_read(sd, 0x2f)) / 2;
1272                 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1273                         hdmi_read(sd, 0x33)) / 2;
1274                 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1275                         ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1276                 if (bt->interlaced == V4L2_DV_INTERLACED) {
1277                         bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1278                                         hdmi_read(sd, 0x0c);
1279                         bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1280                                         hdmi_read(sd, 0x2d)) / 2;
1281                         bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1282                                         hdmi_read(sd, 0x31)) / 2;
1283                         bt->vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1284                                         hdmi_read(sd, 0x35)) / 2;
1285                 }
1286                 adv7604_fill_optional_dv_timings_fields(sd, timings);
1287         } else {
1288                 /* find format
1289                  * Since LCVS values are inaccurate [REF_03, p. 275-276],
1290                  * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1291                  */
1292                 if (!stdi2dv_timings(sd, &stdi, timings))
1293                         goto found;
1294                 stdi.lcvs += 1;
1295                 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1296                 if (!stdi2dv_timings(sd, &stdi, timings))
1297                         goto found;
1298                 stdi.lcvs -= 2;
1299                 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1300                 if (stdi2dv_timings(sd, &stdi, timings)) {
1301                         /*
1302                          * The STDI block may measure wrong values, especially
1303                          * for lcvs and lcf. If the driver can not find any
1304                          * valid timing, the STDI block is restarted to measure
1305                          * the video timings again. The function will return an
1306                          * error, but the restart of STDI will generate a new
1307                          * STDI interrupt and the format detection process will
1308                          * restart.
1309                          */
1310                         if (state->restart_stdi_once) {
1311                                 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1312                                 /* TODO restart STDI for Sync Channel 2 */
1313                                 /* enter one-shot mode */
1314                                 cp_write_and_or(sd, 0x86, 0xf9, 0x00);
1315                                 /* trigger STDI restart */
1316                                 cp_write_and_or(sd, 0x86, 0xf9, 0x04);
1317                                 /* reset to continuous mode */
1318                                 cp_write_and_or(sd, 0x86, 0xf9, 0x02);
1319                                 state->restart_stdi_once = false;
1320                                 return -ENOLINK;
1321                         }
1322                         v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1323                         return -ERANGE;
1324                 }
1325                 state->restart_stdi_once = true;
1326         }
1327 found:
1328
1329         if (no_signal(sd)) {
1330                 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1331                 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1332                 return -ENOLINK;
1333         }
1334
1335         if ((!DIGITAL_INPUT && bt->pixelclock > 170000000) ||
1336                         (DIGITAL_INPUT && bt->pixelclock > 225000000)) {
1337                 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1338                                 __func__, (u32)bt->pixelclock);
1339                 return -ERANGE;
1340         }
1341
1342         if (debug > 1)
1343                 adv7604_print_timings(sd, timings,
1344                                 "adv7604_query_dv_timings:", true);
1345
1346         return 0;
1347 }
1348
1349 static int adv7604_s_dv_timings(struct v4l2_subdev *sd,
1350                 struct v4l2_dv_timings *timings)
1351 {
1352         struct adv7604_state *state = to_state(sd);
1353         struct v4l2_bt_timings *bt;
1354         int err;
1355
1356         if (!timings)
1357                 return -EINVAL;
1358
1359         bt = &timings->bt;
1360
1361         if ((!DIGITAL_INPUT && bt->pixelclock > 170000000) ||
1362                         (DIGITAL_INPUT && bt->pixelclock > 225000000)) {
1363                 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1364                                 __func__, (u32)bt->pixelclock);
1365                 return -ERANGE;
1366         }
1367
1368         adv7604_fill_optional_dv_timings_fields(sd, timings);
1369
1370         state->timings = *timings;
1371
1372         cp_write(sd, 0x91, bt->interlaced ? 0x50 : 0x10);
1373
1374         /* Use prim_mode and vid_std when available */
1375         err = configure_predefined_video_timings(sd, timings);
1376         if (err) {
1377                 /* custom settings when the video format
1378                  does not have prim_mode/vid_std */
1379                 configure_custom_video_timings(sd, bt);
1380         }
1381
1382         set_rgb_quantization_range(sd);
1383
1384
1385         if (debug > 1)
1386                 adv7604_print_timings(sd, timings,
1387                                 "adv7604_s_dv_timings:", true);
1388         return 0;
1389 }
1390
1391 static int adv7604_g_dv_timings(struct v4l2_subdev *sd,
1392                 struct v4l2_dv_timings *timings)
1393 {
1394         struct adv7604_state *state = to_state(sd);
1395
1396         *timings = state->timings;
1397         return 0;
1398 }
1399
1400 static void enable_input(struct v4l2_subdev *sd)
1401 {
1402         struct adv7604_state *state = to_state(sd);
1403
1404         switch (state->mode) {
1405         case ADV7604_MODE_COMP:
1406         case ADV7604_MODE_GR:
1407                 /* enable */
1408                 io_write(sd, 0x15, 0xb0);   /* Disable Tristate of Pins (no audio) */
1409                 break;
1410         case ADV7604_MODE_HDMI:
1411                 /* enable */
1412                 hdmi_write(sd, 0x1a, 0x0a); /* Unmute audio */
1413                 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1414                 io_write(sd, 0x15, 0xa0);   /* Disable Tristate of Pins */
1415                 break;
1416         default:
1417                 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1418                                 __func__, state->mode);
1419                 break;
1420         }
1421 }
1422
1423 static void disable_input(struct v4l2_subdev *sd)
1424 {
1425         /* disable */
1426         io_write(sd, 0x15, 0xbe);   /* Tristate all outputs from video core */
1427         hdmi_write(sd, 0x1a, 0x1a); /* Mute audio */
1428         hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1429 }
1430
1431 static void select_input(struct v4l2_subdev *sd)
1432 {
1433         struct adv7604_state *state = to_state(sd);
1434
1435         switch (state->mode) {
1436         case ADV7604_MODE_COMP:
1437         case ADV7604_MODE_GR:
1438                 /* reset ADI recommended settings for HDMI: */
1439                 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1440                 hdmi_write(sd, 0x0d, 0x04); /* HDMI filter optimization */
1441                 hdmi_write(sd, 0x3d, 0x00); /* DDC bus active pull-up control */
1442                 hdmi_write(sd, 0x3e, 0x74); /* TMDS PLL optimization */
1443                 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */
1444                 hdmi_write(sd, 0x57, 0x74); /* TMDS PLL optimization */
1445                 hdmi_write(sd, 0x58, 0x63); /* TMDS PLL optimization */
1446                 hdmi_write(sd, 0x8d, 0x18); /* equaliser */
1447                 hdmi_write(sd, 0x8e, 0x34); /* equaliser */
1448                 hdmi_write(sd, 0x93, 0x88); /* equaliser */
1449                 hdmi_write(sd, 0x94, 0x2e); /* equaliser */
1450                 hdmi_write(sd, 0x96, 0x00); /* enable automatic EQ changing */
1451
1452                 afe_write(sd, 0x00, 0x08); /* power up ADC */
1453                 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1454                 afe_write(sd, 0xc8, 0x00); /* phase control */
1455
1456                 /* set ADI recommended settings for digitizer */
1457                 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1458                 afe_write(sd, 0x12, 0x7b); /* ADC noise shaping filter controls */
1459                 afe_write(sd, 0x0c, 0x1f); /* CP core gain controls */
1460                 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1461                 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1462                 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1463                 break;
1464
1465         case ADV7604_MODE_HDMI:
1466                 /* set ADI recommended settings for HDMI: */
1467                 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1468                 hdmi_write(sd, 0x0d, 0x84); /* HDMI filter optimization */
1469                 hdmi_write(sd, 0x3d, 0x10); /* DDC bus active pull-up control */
1470                 hdmi_write(sd, 0x3e, 0x39); /* TMDS PLL optimization */
1471                 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */
1472                 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1473                 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1474                 hdmi_write(sd, 0x8d, 0x18); /* equaliser */
1475                 hdmi_write(sd, 0x8e, 0x34); /* equaliser */
1476                 hdmi_write(sd, 0x93, 0x8b); /* equaliser */
1477                 hdmi_write(sd, 0x94, 0x2d); /* equaliser */
1478                 hdmi_write(sd, 0x96, 0x01); /* enable automatic EQ changing */
1479
1480                 afe_write(sd, 0x00, 0xff); /* power down ADC */
1481                 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1482                 afe_write(sd, 0xc8, 0x40); /* phase control */
1483
1484                 /* reset ADI recommended settings for digitizer */
1485                 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1486                 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1487                 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1488                 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1489                 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1490                 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
1491
1492                 break;
1493         default:
1494                 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1495                                 __func__, state->mode);
1496                 break;
1497         }
1498 }
1499
1500 static int adv7604_s_routing(struct v4l2_subdev *sd,
1501                 u32 input, u32 output, u32 config)
1502 {
1503         struct adv7604_state *state = to_state(sd);
1504
1505         v4l2_dbg(2, debug, sd, "%s: input %d", __func__, input);
1506
1507         state->mode = input;
1508
1509         disable_input(sd);
1510
1511         select_input(sd);
1512
1513         enable_input(sd);
1514
1515         return 0;
1516 }
1517
1518 static int adv7604_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index,
1519                              enum v4l2_mbus_pixelcode *code)
1520 {
1521         if (index)
1522                 return -EINVAL;
1523         /* Good enough for now */
1524         *code = V4L2_MBUS_FMT_FIXED;
1525         return 0;
1526 }
1527
1528 static int adv7604_g_mbus_fmt(struct v4l2_subdev *sd,
1529                 struct v4l2_mbus_framefmt *fmt)
1530 {
1531         struct adv7604_state *state = to_state(sd);
1532
1533         fmt->width = state->timings.bt.width;
1534         fmt->height = state->timings.bt.height;
1535         fmt->code = V4L2_MBUS_FMT_FIXED;
1536         fmt->field = V4L2_FIELD_NONE;
1537         if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1538                 fmt->colorspace = (state->timings.bt.height <= 576) ?
1539                         V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1540         }
1541         return 0;
1542 }
1543
1544 static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1545 {
1546         struct adv7604_state *state = to_state(sd);
1547         u8 fmt_change, fmt_change_digital, tx_5v;
1548
1549         /* format change */
1550         fmt_change = io_read(sd, 0x43) & 0x98;
1551         if (fmt_change)
1552                 io_write(sd, 0x44, fmt_change);
1553         fmt_change_digital = DIGITAL_INPUT ? (io_read(sd, 0x6b) & 0xc0) : 0;
1554         if (fmt_change_digital)
1555                 io_write(sd, 0x6c, fmt_change_digital);
1556         if (fmt_change || fmt_change_digital) {
1557                 v4l2_dbg(1, debug, sd,
1558                         "%s: ADV7604_FMT_CHANGE, fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
1559                         __func__, fmt_change, fmt_change_digital);
1560                 v4l2_subdev_notify(sd, ADV7604_FMT_CHANGE, NULL);
1561                 if (handled)
1562                         *handled = true;
1563         }
1564         /* tx 5v detect */
1565         tx_5v = io_read(sd, 0x70) & 0x10;
1566         if (tx_5v) {
1567                 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
1568                 io_write(sd, 0x71, tx_5v);
1569                 adv7604_s_detect_tx_5v_ctrl(sd);
1570                 if (handled)
1571                         *handled = true;
1572         }
1573         return 0;
1574 }
1575
1576 static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
1577 {
1578         struct adv7604_state *state = to_state(sd);
1579
1580         if (edid->pad != 0)
1581                 return -EINVAL;
1582         if (edid->blocks == 0)
1583                 return -EINVAL;
1584         if (edid->start_block >= state->edid_blocks)
1585                 return -EINVAL;
1586         if (edid->start_block + edid->blocks > state->edid_blocks)
1587                 edid->blocks = state->edid_blocks - edid->start_block;
1588         if (!edid->edid)
1589                 return -EINVAL;
1590         memcpy(edid->edid + edid->start_block * 128,
1591                state->edid + edid->start_block * 128,
1592                edid->blocks * 128);
1593         return 0;
1594 }
1595
1596 static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
1597 {
1598         struct adv7604_state *state = to_state(sd);
1599         int err;
1600
1601         if (edid->pad != 0)
1602                 return -EINVAL;
1603         if (edid->start_block != 0)
1604                 return -EINVAL;
1605         if (edid->blocks == 0) {
1606                 /* Pull down the hotplug pin */
1607                 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)0);
1608                 /* Disables I2C access to internal EDID ram from DDC port */
1609                 rep_write_and_or(sd, 0x77, 0xf0, 0x0);
1610                 state->edid_blocks = 0;
1611                 /* Fall back to a 16:9 aspect ratio */
1612                 state->aspect_ratio.numerator = 16;
1613                 state->aspect_ratio.denominator = 9;
1614                 return 0;
1615         }
1616         if (edid->blocks > 2)
1617                 return -E2BIG;
1618         if (!edid->edid)
1619                 return -EINVAL;
1620         memcpy(state->edid, edid->edid, 128 * edid->blocks);
1621         state->edid_blocks = edid->blocks;
1622         state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
1623                         edid->edid[0x16]);
1624         err = edid_write_block(sd, 128 * edid->blocks, state->edid);
1625         if (err < 0)
1626                 v4l2_err(sd, "error %d writing edid\n", err);
1627         return err;
1628 }
1629
1630 /*********** avi info frame CEA-861-E **************/
1631
1632 static void print_avi_infoframe(struct v4l2_subdev *sd)
1633 {
1634         int i;
1635         u8 buf[14];
1636         u8 avi_len;
1637         u8 avi_ver;
1638
1639         if (!(hdmi_read(sd, 0x05) & 0x80)) {
1640                 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
1641                 return;
1642         }
1643         if (!(io_read(sd, 0x60) & 0x01)) {
1644                 v4l2_info(sd, "AVI infoframe not received\n");
1645                 return;
1646         }
1647
1648         if (io_read(sd, 0x83) & 0x01) {
1649                 v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n");
1650                 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1651                 if (io_read(sd, 0x83) & 0x01) {
1652                         v4l2_info(sd, "AVI infoframe checksum error still present\n");
1653                         io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1654                 }
1655         }
1656
1657         avi_len = infoframe_read(sd, 0xe2);
1658         avi_ver = infoframe_read(sd, 0xe1);
1659         v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
1660                         avi_ver, avi_len);
1661
1662         if (avi_ver != 0x02)
1663                 return;
1664
1665         for (i = 0; i < 14; i++)
1666                 buf[i] = infoframe_read(sd, i);
1667
1668         v4l2_info(sd,
1669                 "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
1670                 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
1671                 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
1672 }
1673
1674 static int adv7604_log_status(struct v4l2_subdev *sd)
1675 {
1676         struct adv7604_state *state = to_state(sd);
1677         struct v4l2_dv_timings timings;
1678         struct stdi_readback stdi;
1679         u8 reg_io_0x02 = io_read(sd, 0x02);
1680
1681         char *csc_coeff_sel_rb[16] = {
1682                 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
1683                 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
1684                 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
1685                 "reserved", "reserved", "reserved", "reserved", "manual"
1686         };
1687         char *input_color_space_txt[16] = {
1688                 "RGB limited range (16-235)", "RGB full range (0-255)",
1689                 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
1690                 "XvYCC Bt.601", "XvYCC Bt.709",
1691                 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
1692                 "invalid", "invalid", "invalid", "invalid", "invalid",
1693                 "invalid", "invalid", "automatic"
1694         };
1695         char *rgb_quantization_range_txt[] = {
1696                 "Automatic",
1697                 "RGB limited range (16-235)",
1698                 "RGB full range (0-255)",
1699         };
1700
1701         v4l2_info(sd, "-----Chip status-----\n");
1702         v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
1703         v4l2_info(sd, "Connector type: %s\n", state->connector_hdmi ?
1704                         "HDMI" : (DIGITAL_INPUT ? "DVI-D" : "DVI-A"));
1705         v4l2_info(sd, "EDID: %s\n", ((rep_read(sd, 0x7d) & 0x01) &&
1706                         (rep_read(sd, 0x77) & 0x01)) ? "enabled" : "disabled ");
1707         v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
1708                         "enabled" : "disabled");
1709
1710         v4l2_info(sd, "-----Signal status-----\n");
1711         v4l2_info(sd, "Cable detected (+5V power): %s\n",
1712                         (io_read(sd, 0x6f) & 0x10) ? "true" : "false");
1713         v4l2_info(sd, "TMDS signal detected: %s\n",
1714                         no_signal_tmds(sd) ? "false" : "true");
1715         v4l2_info(sd, "TMDS signal locked: %s\n",
1716                         no_lock_tmds(sd) ? "false" : "true");
1717         v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
1718         v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
1719         v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
1720         v4l2_info(sd, "CP free run: %s\n",
1721                         (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
1722         v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
1723                         io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
1724                         (io_read(sd, 0x01) & 0x70) >> 4);
1725
1726         v4l2_info(sd, "-----Video Timings-----\n");
1727         if (read_stdi(sd, &stdi))
1728                 v4l2_info(sd, "STDI: not locked\n");
1729         else
1730                 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
1731                                 stdi.lcf, stdi.bl, stdi.lcvs,
1732                                 stdi.interlaced ? "interlaced" : "progressive",
1733                                 stdi.hs_pol, stdi.vs_pol);
1734         if (adv7604_query_dv_timings(sd, &timings))
1735                 v4l2_info(sd, "No video detected\n");
1736         else
1737                 adv7604_print_timings(sd, &timings, "Detected format:", true);
1738         adv7604_print_timings(sd, &state->timings, "Configured format:", true);
1739
1740         v4l2_info(sd, "-----Color space-----\n");
1741         v4l2_info(sd, "RGB quantization range ctrl: %s\n",
1742                         rgb_quantization_range_txt[state->rgb_quantization_range]);
1743         v4l2_info(sd, "Input color space: %s\n",
1744                         input_color_space_txt[reg_io_0x02 >> 4]);
1745         v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
1746                         (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
1747                         (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
1748                         ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
1749                                         "enabled" : "disabled");
1750         v4l2_info(sd, "Color space conversion: %s\n",
1751                         csc_coeff_sel_rb[cp_read(sd, 0xfc) >> 4]);
1752
1753         /* Digital video */
1754         if (DIGITAL_INPUT) {
1755                 v4l2_info(sd, "-----HDMI status-----\n");
1756                 v4l2_info(sd, "HDCP encrypted content: %s\n",
1757                                 hdmi_read(sd, 0x05) & 0x40 ? "true" : "false");
1758
1759                 print_avi_infoframe(sd);
1760         }
1761
1762         return 0;
1763 }
1764
1765 /* ----------------------------------------------------------------------- */
1766
1767 static const struct v4l2_ctrl_ops adv7604_ctrl_ops = {
1768         .s_ctrl = adv7604_s_ctrl,
1769 };
1770
1771 static const struct v4l2_subdev_core_ops adv7604_core_ops = {
1772         .log_status = adv7604_log_status,
1773         .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
1774         .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
1775         .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
1776         .g_ctrl = v4l2_subdev_g_ctrl,
1777         .s_ctrl = v4l2_subdev_s_ctrl,
1778         .queryctrl = v4l2_subdev_queryctrl,
1779         .querymenu = v4l2_subdev_querymenu,
1780         .g_chip_ident = adv7604_g_chip_ident,
1781         .interrupt_service_routine = adv7604_isr,
1782 #ifdef CONFIG_VIDEO_ADV_DEBUG
1783         .g_register = adv7604_g_register,
1784         .s_register = adv7604_s_register,
1785 #endif
1786 };
1787
1788 static const struct v4l2_subdev_video_ops adv7604_video_ops = {
1789         .s_routing = adv7604_s_routing,
1790         .g_input_status = adv7604_g_input_status,
1791         .s_dv_timings = adv7604_s_dv_timings,
1792         .g_dv_timings = adv7604_g_dv_timings,
1793         .query_dv_timings = adv7604_query_dv_timings,
1794         .enum_dv_timings = adv7604_enum_dv_timings,
1795         .dv_timings_cap = adv7604_dv_timings_cap,
1796         .enum_mbus_fmt = adv7604_enum_mbus_fmt,
1797         .g_mbus_fmt = adv7604_g_mbus_fmt,
1798         .try_mbus_fmt = adv7604_g_mbus_fmt,
1799         .s_mbus_fmt = adv7604_g_mbus_fmt,
1800 };
1801
1802 static const struct v4l2_subdev_pad_ops adv7604_pad_ops = {
1803         .get_edid = adv7604_get_edid,
1804         .set_edid = adv7604_set_edid,
1805 };
1806
1807 static const struct v4l2_subdev_ops adv7604_ops = {
1808         .core = &adv7604_core_ops,
1809         .video = &adv7604_video_ops,
1810         .pad = &adv7604_pad_ops,
1811 };
1812
1813 /* -------------------------- custom ctrls ---------------------------------- */
1814
1815 static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
1816         .ops = &adv7604_ctrl_ops,
1817         .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
1818         .name = "Analog Sampling Phase",
1819         .type = V4L2_CTRL_TYPE_INTEGER,
1820         .min = 0,
1821         .max = 0x1f,
1822         .step = 1,
1823         .def = 0,
1824 };
1825
1826 static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = {
1827         .ops = &adv7604_ctrl_ops,
1828         .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
1829         .name = "Free Running Color, Manual",
1830         .type = V4L2_CTRL_TYPE_BOOLEAN,
1831         .min = false,
1832         .max = true,
1833         .step = 1,
1834         .def = false,
1835 };
1836
1837 static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = {
1838         .ops = &adv7604_ctrl_ops,
1839         .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
1840         .name = "Free Running Color",
1841         .type = V4L2_CTRL_TYPE_INTEGER,
1842         .min = 0x0,
1843         .max = 0xffffff,
1844         .step = 0x1,
1845         .def = 0x0,
1846 };
1847
1848 /* ----------------------------------------------------------------------- */
1849
1850 static int adv7604_core_init(struct v4l2_subdev *sd)
1851 {
1852         struct adv7604_state *state = to_state(sd);
1853         struct adv7604_platform_data *pdata = &state->pdata;
1854
1855         hdmi_write(sd, 0x48,
1856                 (pdata->disable_pwrdnb ? 0x80 : 0) |
1857                 (pdata->disable_cable_det_rst ? 0x40 : 0));
1858
1859         disable_input(sd);
1860
1861         /* power */
1862         io_write(sd, 0x0c, 0x42);   /* Power up part and power down VDP */
1863         io_write(sd, 0x0b, 0x44);   /* Power down ESDP block */
1864         cp_write(sd, 0xcf, 0x01);   /* Power down macrovision */
1865
1866         /* video format */
1867         io_write_and_or(sd, 0x02, 0xf0,
1868                         pdata->alt_gamma << 3 |
1869                         pdata->op_656_range << 2 |
1870                         pdata->rgb_out << 1 |
1871                         pdata->alt_data_sat << 0);
1872         io_write(sd, 0x03, pdata->op_format_sel);
1873         io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5);
1874         io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
1875                                         pdata->insert_av_codes << 2 |
1876                                         pdata->replicate_av_codes << 1 |
1877                                         pdata->invert_cbcr << 0);
1878
1879         /* TODO from platform data */
1880         cp_write(sd, 0x69, 0x30);   /* Enable CP CSC */
1881         io_write(sd, 0x06, 0xa6);   /* positive VS and HS */
1882         io_write(sd, 0x14, 0x7f);   /* Drive strength adjusted to max */
1883         cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
1884         cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
1885         cp_write(sd, 0xf9, 0x23); /*  STDI ch. 1 - LCVS change threshold -
1886                                       ADI recommended setting [REF_01, c. 2.3.3] */
1887         cp_write(sd, 0x45, 0x23); /*  STDI ch. 2 - LCVS change threshold -
1888                                       ADI recommended setting [REF_01, c. 2.3.3] */
1889         cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
1890                                      for digital formats */
1891
1892         /* TODO from platform data */
1893         afe_write(sd, 0xb5, 0x01);  /* Setting MCLK to 256Fs */
1894
1895         afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
1896         io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
1897
1898         /* interrupts */
1899         io_write(sd, 0x40, 0xc2); /* Configure INT1 */
1900         io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
1901         io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
1902         io_write(sd, 0x6e, 0xc0); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
1903         io_write(sd, 0x73, 0x10); /* Enable CABLE_DET_A_ST (+5v) interrupt */
1904
1905         return v4l2_ctrl_handler_setup(sd->ctrl_handler);
1906 }
1907
1908 static void adv7604_unregister_clients(struct adv7604_state *state)
1909 {
1910         if (state->i2c_avlink)
1911                 i2c_unregister_device(state->i2c_avlink);
1912         if (state->i2c_cec)
1913                 i2c_unregister_device(state->i2c_cec);
1914         if (state->i2c_infoframe)
1915                 i2c_unregister_device(state->i2c_infoframe);
1916         if (state->i2c_esdp)
1917                 i2c_unregister_device(state->i2c_esdp);
1918         if (state->i2c_dpp)
1919                 i2c_unregister_device(state->i2c_dpp);
1920         if (state->i2c_afe)
1921                 i2c_unregister_device(state->i2c_afe);
1922         if (state->i2c_repeater)
1923                 i2c_unregister_device(state->i2c_repeater);
1924         if (state->i2c_edid)
1925                 i2c_unregister_device(state->i2c_edid);
1926         if (state->i2c_hdmi)
1927                 i2c_unregister_device(state->i2c_hdmi);
1928         if (state->i2c_test)
1929                 i2c_unregister_device(state->i2c_test);
1930         if (state->i2c_cp)
1931                 i2c_unregister_device(state->i2c_cp);
1932         if (state->i2c_vdp)
1933                 i2c_unregister_device(state->i2c_vdp);
1934 }
1935
1936 static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd,
1937                                                         u8 addr, u8 io_reg)
1938 {
1939         struct i2c_client *client = v4l2_get_subdevdata(sd);
1940
1941         if (addr)
1942                 io_write(sd, io_reg, addr << 1);
1943         return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
1944 }
1945
1946 static int adv7604_probe(struct i2c_client *client,
1947                          const struct i2c_device_id *id)
1948 {
1949         struct adv7604_state *state;
1950         struct adv7604_platform_data *pdata = client->dev.platform_data;
1951         struct v4l2_ctrl_handler *hdl;
1952         struct v4l2_subdev *sd;
1953         int err;
1954
1955         /* Check if the adapter supports the needed features */
1956         if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1957                 return -EIO;
1958         v4l_dbg(1, debug, client, "detecting adv7604 client on address 0x%x\n",
1959                         client->addr << 1);
1960
1961         state = kzalloc(sizeof(struct adv7604_state), GFP_KERNEL);
1962         if (!state) {
1963                 v4l_err(client, "Could not allocate adv7604_state memory!\n");
1964                 return -ENOMEM;
1965         }
1966
1967         /* platform data */
1968         if (!pdata) {
1969                 v4l_err(client, "No platform data!\n");
1970                 err = -ENODEV;
1971                 goto err_state;
1972         }
1973         memcpy(&state->pdata, pdata, sizeof(state->pdata));
1974
1975         sd = &state->sd;
1976         v4l2_i2c_subdev_init(sd, client, &adv7604_ops);
1977         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1978         state->connector_hdmi = pdata->connector_hdmi;
1979
1980         /* i2c access to adv7604? */
1981         if (adv_smbus_read_byte_data_check(client, 0xfb, false) != 0x68) {
1982                 v4l2_info(sd, "not an adv7604 on address 0x%x\n",
1983                                 client->addr << 1);
1984                 err = -ENODEV;
1985                 goto err_state;
1986         }
1987
1988         /* control handlers */
1989         hdl = &state->hdl;
1990         v4l2_ctrl_handler_init(hdl, 9);
1991
1992         v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
1993                         V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
1994         v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
1995                         V4L2_CID_CONTRAST, 0, 255, 1, 128);
1996         v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
1997                         V4L2_CID_SATURATION, 0, 255, 1, 128);
1998         v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
1999                         V4L2_CID_HUE, 0, 128, 1, 0);
2000
2001         /* private controls */
2002         state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
2003                         V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0);
2004         state->detect_tx_5v_ctrl->is_private = true;
2005         state->rgb_quantization_range_ctrl =
2006                 v4l2_ctrl_new_std_menu(hdl, &adv7604_ctrl_ops,
2007                         V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
2008                         0, V4L2_DV_RGB_RANGE_AUTO);
2009         state->rgb_quantization_range_ctrl->is_private = true;
2010
2011         /* custom controls */
2012         state->analog_sampling_phase_ctrl =
2013                 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
2014         state->analog_sampling_phase_ctrl->is_private = true;
2015         state->free_run_color_manual_ctrl =
2016                 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color_manual, NULL);
2017         state->free_run_color_manual_ctrl->is_private = true;
2018         state->free_run_color_ctrl =
2019                 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color, NULL);
2020         state->free_run_color_ctrl->is_private = true;
2021
2022         sd->ctrl_handler = hdl;
2023         if (hdl->error) {
2024                 err = hdl->error;
2025                 goto err_hdl;
2026         }
2027         if (adv7604_s_detect_tx_5v_ctrl(sd)) {
2028                 err = -ENODEV;
2029                 goto err_hdl;
2030         }
2031
2032         state->i2c_avlink = adv7604_dummy_client(sd, pdata->i2c_avlink, 0xf3);
2033         state->i2c_cec = adv7604_dummy_client(sd, pdata->i2c_cec, 0xf4);
2034         state->i2c_infoframe = adv7604_dummy_client(sd, pdata->i2c_infoframe, 0xf5);
2035         state->i2c_esdp = adv7604_dummy_client(sd, pdata->i2c_esdp, 0xf6);
2036         state->i2c_dpp = adv7604_dummy_client(sd, pdata->i2c_dpp, 0xf7);
2037         state->i2c_afe = adv7604_dummy_client(sd, pdata->i2c_afe, 0xf8);
2038         state->i2c_repeater = adv7604_dummy_client(sd, pdata->i2c_repeater, 0xf9);
2039         state->i2c_edid = adv7604_dummy_client(sd, pdata->i2c_edid, 0xfa);
2040         state->i2c_hdmi = adv7604_dummy_client(sd, pdata->i2c_hdmi, 0xfb);
2041         state->i2c_test = adv7604_dummy_client(sd, pdata->i2c_test, 0xfc);
2042         state->i2c_cp = adv7604_dummy_client(sd, pdata->i2c_cp, 0xfd);
2043         state->i2c_vdp = adv7604_dummy_client(sd, pdata->i2c_vdp, 0xfe);
2044         if (!state->i2c_avlink || !state->i2c_cec || !state->i2c_infoframe ||
2045             !state->i2c_esdp || !state->i2c_dpp || !state->i2c_afe ||
2046             !state->i2c_repeater || !state->i2c_edid || !state->i2c_hdmi ||
2047             !state->i2c_test || !state->i2c_cp || !state->i2c_vdp) {
2048                 err = -ENOMEM;
2049                 v4l2_err(sd, "failed to create all i2c clients\n");
2050                 goto err_i2c;
2051         }
2052         state->restart_stdi_once = true;
2053
2054         /* work queues */
2055         state->work_queues = create_singlethread_workqueue(client->name);
2056         if (!state->work_queues) {
2057                 v4l2_err(sd, "Could not create work queue\n");
2058                 err = -ENOMEM;
2059                 goto err_i2c;
2060         }
2061
2062         INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2063                         adv7604_delayed_work_enable_hotplug);
2064
2065         state->pad.flags = MEDIA_PAD_FL_SOURCE;
2066         err = media_entity_init(&sd->entity, 1, &state->pad, 0);
2067         if (err)
2068                 goto err_work_queues;
2069
2070         err = adv7604_core_init(sd);
2071         if (err)
2072                 goto err_entity;
2073         v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2074                         client->addr << 1, client->adapter->name);
2075         return 0;
2076
2077 err_entity:
2078         media_entity_cleanup(&sd->entity);
2079 err_work_queues:
2080         cancel_delayed_work(&state->delayed_work_enable_hotplug);
2081         destroy_workqueue(state->work_queues);
2082 err_i2c:
2083         adv7604_unregister_clients(state);
2084 err_hdl:
2085         v4l2_ctrl_handler_free(hdl);
2086 err_state:
2087         kfree(state);
2088         return err;
2089 }
2090
2091 /* ----------------------------------------------------------------------- */
2092
2093 static int adv7604_remove(struct i2c_client *client)
2094 {
2095         struct v4l2_subdev *sd = i2c_get_clientdata(client);
2096         struct adv7604_state *state = to_state(sd);
2097
2098         cancel_delayed_work(&state->delayed_work_enable_hotplug);
2099         destroy_workqueue(state->work_queues);
2100         v4l2_device_unregister_subdev(sd);
2101         media_entity_cleanup(&sd->entity);
2102         adv7604_unregister_clients(to_state(sd));
2103         v4l2_ctrl_handler_free(sd->ctrl_handler);
2104         kfree(to_state(sd));
2105         return 0;
2106 }
2107
2108 /* ----------------------------------------------------------------------- */
2109
2110 static struct i2c_device_id adv7604_id[] = {
2111         { "adv7604", 0 },
2112         { }
2113 };
2114 MODULE_DEVICE_TABLE(i2c, adv7604_id);
2115
2116 static struct i2c_driver adv7604_driver = {
2117         .driver = {
2118                 .owner = THIS_MODULE,
2119                 .name = "adv7604",
2120         },
2121         .probe = adv7604_probe,
2122         .remove = adv7604_remove,
2123         .id_table = adv7604_id,
2124 };
2125
2126 module_i2c_driver(adv7604_driver);