2 * drxk_hard: DRX-K DVB-C/T demodulator driver
4 * Copyright (C) 2010-2011 Digital Devices GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/init.h>
28 #include <linux/delay.h>
29 #include <linux/firmware.h>
30 #include <linux/i2c.h>
31 #include <linux/hardirq.h>
32 #include <asm/div64.h>
34 #include "dvb_frontend.h"
36 #include "drxk_hard.h"
38 static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode);
39 static int PowerDownQAM(struct drxk_state *state);
40 static int SetDVBTStandard(struct drxk_state *state,
41 enum OperationMode oMode);
42 static int SetQAMStandard(struct drxk_state *state,
43 enum OperationMode oMode);
44 static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
46 static int SetDVBTStandard(struct drxk_state *state,
47 enum OperationMode oMode);
48 static int DVBTStart(struct drxk_state *state);
49 static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
51 static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus);
52 static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus);
53 static int SwitchAntennaToQAM(struct drxk_state *state);
54 static int SwitchAntennaToDVBT(struct drxk_state *state);
56 static bool IsDVBT(struct drxk_state *state)
58 return state->m_OperationMode == OM_DVBT;
61 static bool IsQAM(struct drxk_state *state)
63 return state->m_OperationMode == OM_QAM_ITU_A ||
64 state->m_OperationMode == OM_QAM_ITU_B ||
65 state->m_OperationMode == OM_QAM_ITU_C;
70 #define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0)
71 #define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0)
73 #define DEFAULT_MER_83 165
74 #define DEFAULT_MER_93 250
76 #ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
77 #define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02)
80 #ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
81 #define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03)
84 #define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700
85 #define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500
87 #ifndef DRXK_KI_RAGC_ATV
88 #define DRXK_KI_RAGC_ATV 4
90 #ifndef DRXK_KI_IAGC_ATV
91 #define DRXK_KI_IAGC_ATV 6
93 #ifndef DRXK_KI_DAGC_ATV
94 #define DRXK_KI_DAGC_ATV 7
97 #ifndef DRXK_KI_RAGC_QAM
98 #define DRXK_KI_RAGC_QAM 3
100 #ifndef DRXK_KI_IAGC_QAM
101 #define DRXK_KI_IAGC_QAM 4
103 #ifndef DRXK_KI_DAGC_QAM
104 #define DRXK_KI_DAGC_QAM 7
106 #ifndef DRXK_KI_RAGC_DVBT
107 #define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2)
109 #ifndef DRXK_KI_IAGC_DVBT
110 #define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2)
112 #ifndef DRXK_KI_DAGC_DVBT
113 #define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7)
116 #ifndef DRXK_AGC_DAC_OFFSET
117 #define DRXK_AGC_DAC_OFFSET (0x800)
120 #ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ
121 #define DRXK_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L)
124 #ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ
125 #define DRXK_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L)
128 #ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ
129 #define DRXK_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L)
132 #ifndef DRXK_QAM_SYMBOLRATE_MAX
133 #define DRXK_QAM_SYMBOLRATE_MAX (7233000)
136 #define DRXK_BL_ROM_OFFSET_TAPS_DVBT 56
137 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_A 64
138 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_C 0x5FE0
139 #define DRXK_BL_ROM_OFFSET_TAPS_BG 24
140 #define DRXK_BL_ROM_OFFSET_TAPS_DKILLP 32
141 #define DRXK_BL_ROM_OFFSET_TAPS_NTSC 40
142 #define DRXK_BL_ROM_OFFSET_TAPS_FM 48
143 #define DRXK_BL_ROM_OFFSET_UCODE 0
145 #define DRXK_BLC_TIMEOUT 100
147 #define DRXK_BLCC_NR_ELEMENTS_TAPS 2
148 #define DRXK_BLCC_NR_ELEMENTS_UCODE 6
150 #define DRXK_BLDC_NR_ELEMENTS_TAPS 28
152 #ifndef DRXK_OFDM_NE_NOTCH_WIDTH
153 #define DRXK_OFDM_NE_NOTCH_WIDTH (4)
156 #define DRXK_QAM_SL_SIG_POWER_QAM16 (40960)
157 #define DRXK_QAM_SL_SIG_POWER_QAM32 (20480)
158 #define DRXK_QAM_SL_SIG_POWER_QAM64 (43008)
159 #define DRXK_QAM_SL_SIG_POWER_QAM128 (20992)
160 #define DRXK_QAM_SL_SIG_POWER_QAM256 (43520)
162 static unsigned int debug;
163 module_param(debug, int, 0644);
164 MODULE_PARM_DESC(debug, "enable debug messages");
166 #define dprintk(level, fmt, arg...) do { \
167 if (debug >= level) \
168 printk(KERN_DEBUG "drxk: %s" fmt, __func__, ## arg); \
172 static inline u32 MulDiv32(u32 a, u32 b, u32 c)
176 tmp64 = (u64) a * (u64) b;
182 static inline u32 Frac28a(u32 a, u32 c)
188 R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */
189 Q1 = a / c; /* integer part, only the 4 least significant bits
190 will be visible in the result */
192 /* division using radix 16, 7 nibbles in the result */
193 for (i = 0; i < 7; i++) {
194 Q1 = (Q1 << 4) | (R0 / c);
204 static u32 Log10Times100(u32 x)
206 static const u8 scale = 15;
207 static const u8 indexWidth = 5;
214 log2lut[n] = (1<<scale) * 200 * log2(1.0 + ((1.0/(1<<INDEXWIDTH)) * n))
215 0 <= n < ((1<<INDEXWIDTH)+1)
218 static const u32 log2lut[] = {
220 290941, /* 290941.300628 */
221 573196, /* 573196.476418 */
222 847269, /* 847269.179851 */
223 1113620, /* 1113620.489452 */
224 1372674, /* 1372673.576986 */
225 1624818, /* 1624817.752104 */
226 1870412, /* 1870411.981536 */
227 2109788, /* 2109787.962654 */
228 2343253, /* 2343252.817465 */
229 2571091, /* 2571091.461923 */
230 2793569, /* 2793568.696416 */
231 3010931, /* 3010931.055901 */
232 3223408, /* 3223408.452106 */
233 3431216, /* 3431215.635215 */
234 3634553, /* 3634553.498355 */
235 3833610, /* 3833610.244726 */
236 4028562, /* 4028562.434393 */
237 4219576, /* 4219575.925308 */
238 4406807, /* 4406806.721144 */
239 4590402, /* 4590401.736809 */
240 4770499, /* 4770499.491025 */
241 4947231, /* 4947230.734179 */
242 5120719, /* 5120719.018555 */
243 5291081, /* 5291081.217197 */
244 5458428, /* 5458427.996830 */
245 5622864, /* 5622864.249668 */
246 5784489, /* 5784489.488298 */
247 5943398, /* 5943398.207380 */
248 6099680, /* 6099680.215452 */
249 6253421, /* 6253420.939751 */
250 6404702, /* 6404701.706649 */
251 6553600, /* 6553600.000000 */
258 /* Scale x (normalize) */
259 /* computing y in log(x/y) = log(x) - log(y) */
260 if ((x & ((0xffffffff) << (scale + 1))) == 0) {
261 for (k = scale; k > 0; k--) {
262 if (x & (((u32) 1) << scale))
267 for (k = scale; k < 31; k++) {
268 if ((x & (((u32) (-1)) << (scale + 1))) == 0)
274 Now x has binary point between bit[scale] and bit[scale-1]
275 and 1.0 <= x < 2.0 */
277 /* correction for divison: log(x) = log(x/y)+log(y) */
278 y = k * ((((u32) 1) << scale) * 200);
280 /* remove integer part */
281 x &= ((((u32) 1) << scale) - 1);
283 i = (u8) (x >> (scale - indexWidth));
284 /* compute delta (x - a) */
285 d = x & ((((u32) 1) << (scale - indexWidth)) - 1);
286 /* compute log, multiplication (d* (..)) must be within range ! */
288 ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - indexWidth));
289 /* Conver to log10() */
290 y /= 108853; /* (log2(10) << scale) */
298 /****************************************************************************/
299 /* I2C **********************************************************************/
300 /****************************************************************************/
302 static int drxk_i2c_lock(struct drxk_state *state)
304 i2c_lock_adapter(state->i2c);
305 state->drxk_i2c_exclusive_lock = true;
310 static void drxk_i2c_unlock(struct drxk_state *state)
312 if (!state->drxk_i2c_exclusive_lock)
315 i2c_unlock_adapter(state->i2c);
316 state->drxk_i2c_exclusive_lock = false;
319 static int drxk_i2c_transfer(struct drxk_state *state, struct i2c_msg *msgs,
322 if (state->drxk_i2c_exclusive_lock)
323 return __i2c_transfer(state->i2c, msgs, len);
325 return i2c_transfer(state->i2c, msgs, len);
328 static int i2c_read1(struct drxk_state *state, u8 adr, u8 *val)
330 struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD,
331 .buf = val, .len = 1}
334 return drxk_i2c_transfer(state, msgs, 1);
337 static int i2c_write(struct drxk_state *state, u8 adr, u8 *data, int len)
340 struct i2c_msg msg = {
341 .addr = adr, .flags = 0, .buf = data, .len = len };
346 for (i = 0; i < len; i++)
347 printk(KERN_CONT " %02x", data[i]);
348 printk(KERN_CONT "\n");
350 status = drxk_i2c_transfer(state, &msg, 1);
351 if (status >= 0 && status != 1)
355 printk(KERN_ERR "drxk: i2c write error at addr 0x%02x\n", adr);
360 static int i2c_read(struct drxk_state *state,
361 u8 adr, u8 *msg, int len, u8 *answ, int alen)
364 struct i2c_msg msgs[2] = {
365 {.addr = adr, .flags = 0,
366 .buf = msg, .len = len},
367 {.addr = adr, .flags = I2C_M_RD,
368 .buf = answ, .len = alen}
371 status = drxk_i2c_transfer(state, msgs, 2);
374 printk(KERN_CONT ": ERROR!\n");
378 printk(KERN_ERR "drxk: i2c read error at addr 0x%02x\n", adr);
383 dprintk(2, ": read from");
384 for (i = 0; i < len; i++)
385 printk(KERN_CONT " %02x", msg[i]);
386 printk(KERN_CONT ", value = ");
387 for (i = 0; i < alen; i++)
388 printk(KERN_CONT " %02x", answ[i]);
389 printk(KERN_CONT "\n");
394 static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
397 u8 adr = state->demod_address, mm1[4], mm2[2], len;
399 if (state->single_master)
402 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
403 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
404 mm1[1] = ((reg >> 16) & 0xFF);
405 mm1[2] = ((reg >> 24) & 0xFF) | flags;
406 mm1[3] = ((reg >> 7) & 0xFF);
409 mm1[0] = ((reg << 1) & 0xFF);
410 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
413 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
414 status = i2c_read(state, adr, mm1, len, mm2, 2);
418 *data = mm2[0] | (mm2[1] << 8);
423 static int read16(struct drxk_state *state, u32 reg, u16 *data)
425 return read16_flags(state, reg, data, 0);
428 static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
431 u8 adr = state->demod_address, mm1[4], mm2[4], len;
433 if (state->single_master)
436 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
437 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
438 mm1[1] = ((reg >> 16) & 0xFF);
439 mm1[2] = ((reg >> 24) & 0xFF) | flags;
440 mm1[3] = ((reg >> 7) & 0xFF);
443 mm1[0] = ((reg << 1) & 0xFF);
444 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
447 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
448 status = i2c_read(state, adr, mm1, len, mm2, 4);
452 *data = mm2[0] | (mm2[1] << 8) |
453 (mm2[2] << 16) | (mm2[3] << 24);
458 static int read32(struct drxk_state *state, u32 reg, u32 *data)
460 return read32_flags(state, reg, data, 0);
463 static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)
465 u8 adr = state->demod_address, mm[6], len;
467 if (state->single_master)
469 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
470 mm[0] = (((reg << 1) & 0xFF) | 0x01);
471 mm[1] = ((reg >> 16) & 0xFF);
472 mm[2] = ((reg >> 24) & 0xFF) | flags;
473 mm[3] = ((reg >> 7) & 0xFF);
476 mm[0] = ((reg << 1) & 0xFF);
477 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
480 mm[len] = data & 0xff;
481 mm[len + 1] = (data >> 8) & 0xff;
483 dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags);
484 return i2c_write(state, adr, mm, len + 2);
487 static int write16(struct drxk_state *state, u32 reg, u16 data)
489 return write16_flags(state, reg, data, 0);
492 static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)
494 u8 adr = state->demod_address, mm[8], len;
496 if (state->single_master)
498 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
499 mm[0] = (((reg << 1) & 0xFF) | 0x01);
500 mm[1] = ((reg >> 16) & 0xFF);
501 mm[2] = ((reg >> 24) & 0xFF) | flags;
502 mm[3] = ((reg >> 7) & 0xFF);
505 mm[0] = ((reg << 1) & 0xFF);
506 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
509 mm[len] = data & 0xff;
510 mm[len + 1] = (data >> 8) & 0xff;
511 mm[len + 2] = (data >> 16) & 0xff;
512 mm[len + 3] = (data >> 24) & 0xff;
513 dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags);
515 return i2c_write(state, adr, mm, len + 4);
518 static int write32(struct drxk_state *state, u32 reg, u32 data)
520 return write32_flags(state, reg, data, 0);
523 static int write_block(struct drxk_state *state, u32 Address,
524 const int BlockSize, const u8 pBlock[])
526 int status = 0, BlkSize = BlockSize;
529 if (state->single_master)
532 while (BlkSize > 0) {
533 int Chunk = BlkSize > state->m_ChunkSize ?
534 state->m_ChunkSize : BlkSize;
535 u8 *AdrBuf = &state->Chunk[0];
538 if (DRXDAP_FASI_LONG_FORMAT(Address) || (Flags != 0)) {
539 AdrBuf[0] = (((Address << 1) & 0xFF) | 0x01);
540 AdrBuf[1] = ((Address >> 16) & 0xFF);
541 AdrBuf[2] = ((Address >> 24) & 0xFF);
542 AdrBuf[3] = ((Address >> 7) & 0xFF);
545 if (Chunk == state->m_ChunkSize)
548 AdrBuf[0] = ((Address << 1) & 0xFF);
549 AdrBuf[1] = (((Address >> 16) & 0x0F) |
550 ((Address >> 18) & 0xF0));
553 memcpy(&state->Chunk[AdrLength], pBlock, Chunk);
554 dprintk(2, "(0x%08x, 0x%02x)\n", Address, Flags);
558 for (i = 0; i < Chunk; i++)
559 printk(KERN_CONT " %02x", pBlock[i]);
560 printk(KERN_CONT "\n");
562 status = i2c_write(state, state->demod_address,
563 &state->Chunk[0], Chunk + AdrLength);
565 printk(KERN_ERR "drxk: %s: i2c write error at addr 0x%02x\n",
570 Address += (Chunk >> 1);
576 #ifndef DRXK_MAX_RETRIES_POWERUP
577 #define DRXK_MAX_RETRIES_POWERUP 20
580 static int PowerUpDevice(struct drxk_state *state)
588 status = i2c_read1(state, state->demod_address, &data);
592 status = i2c_write(state, state->demod_address,
598 status = i2c_read1(state, state->demod_address,
600 } while (status < 0 &&
601 (retryCount < DRXK_MAX_RETRIES_POWERUP));
602 if (status < 0 && retryCount >= DRXK_MAX_RETRIES_POWERUP)
606 /* Make sure all clk domains are active */
607 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
610 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
613 /* Enable pll lock tests */
614 status = write16(state, SIO_CC_PLL_LOCK__A, 1);
618 state->m_currentPowerMode = DRX_POWER_UP;
622 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
628 static int init_state(struct drxk_state *state)
631 * FIXME: most (all?) of the values bellow should be moved into
632 * struct drxk_config, as they are probably board-specific
634 u32 ulVSBIfAgcMode = DRXK_AGC_CTRL_AUTO;
635 u32 ulVSBIfAgcOutputLevel = 0;
636 u32 ulVSBIfAgcMinLevel = 0;
637 u32 ulVSBIfAgcMaxLevel = 0x7FFF;
638 u32 ulVSBIfAgcSpeed = 3;
640 u32 ulVSBRfAgcMode = DRXK_AGC_CTRL_AUTO;
641 u32 ulVSBRfAgcOutputLevel = 0;
642 u32 ulVSBRfAgcMinLevel = 0;
643 u32 ulVSBRfAgcMaxLevel = 0x7FFF;
644 u32 ulVSBRfAgcSpeed = 3;
645 u32 ulVSBRfAgcTop = 9500;
646 u32 ulVSBRfAgcCutOffCurrent = 4000;
648 u32 ulATVIfAgcMode = DRXK_AGC_CTRL_AUTO;
649 u32 ulATVIfAgcOutputLevel = 0;
650 u32 ulATVIfAgcMinLevel = 0;
651 u32 ulATVIfAgcMaxLevel = 0;
652 u32 ulATVIfAgcSpeed = 3;
654 u32 ulATVRfAgcMode = DRXK_AGC_CTRL_OFF;
655 u32 ulATVRfAgcOutputLevel = 0;
656 u32 ulATVRfAgcMinLevel = 0;
657 u32 ulATVRfAgcMaxLevel = 0;
658 u32 ulATVRfAgcTop = 9500;
659 u32 ulATVRfAgcCutOffCurrent = 4000;
660 u32 ulATVRfAgcSpeed = 3;
662 u32 ulQual83 = DEFAULT_MER_83;
663 u32 ulQual93 = DEFAULT_MER_93;
665 u32 ulMpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
666 u32 ulDemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
668 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
669 /* io_pad_cfg_mode output mode is drive always */
670 /* io_pad_cfg_drive is set to power 2 (23 mA) */
671 u32 ulGPIOCfg = 0x0113;
672 u32 ulInvertTSClock = 0;
673 u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH;
674 u32 ulDVBTBitrate = 50000000;
675 u32 ulDVBCBitrate = DRXK_QAM_SYMBOLRATE_MAX * 8;
677 u32 ulInsertRSByte = 0;
684 state->m_hasLNA = false;
685 state->m_hasDVBT = false;
686 state->m_hasDVBC = false;
687 state->m_hasATV = false;
688 state->m_hasOOB = false;
689 state->m_hasAudio = false;
691 if (!state->m_ChunkSize)
692 state->m_ChunkSize = 124;
694 state->m_oscClockFreq = 0;
695 state->m_smartAntInverted = false;
696 state->m_bPDownOpenBridge = false;
698 /* real system clock frequency in kHz */
699 state->m_sysClockFreq = 151875;
700 /* Timing div, 250ns/Psys */
701 /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */
702 state->m_HICfgTimingDiv = ((state->m_sysClockFreq / 1000) *
703 HI_I2C_DELAY) / 1000;
705 if (state->m_HICfgTimingDiv > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
706 state->m_HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
707 state->m_HICfgWakeUpKey = (state->demod_address << 1);
708 /* port/bridge/power down ctrl */
709 state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
711 state->m_bPowerDown = (ulPowerDown != 0);
713 state->m_DRXK_A3_PATCH_CODE = false;
715 /* Init AGC and PGA parameters */
717 state->m_vsbIfAgcCfg.ctrlMode = (ulVSBIfAgcMode);
718 state->m_vsbIfAgcCfg.outputLevel = (ulVSBIfAgcOutputLevel);
719 state->m_vsbIfAgcCfg.minOutputLevel = (ulVSBIfAgcMinLevel);
720 state->m_vsbIfAgcCfg.maxOutputLevel = (ulVSBIfAgcMaxLevel);
721 state->m_vsbIfAgcCfg.speed = (ulVSBIfAgcSpeed);
722 state->m_vsbPgaCfg = 140;
725 state->m_vsbRfAgcCfg.ctrlMode = (ulVSBRfAgcMode);
726 state->m_vsbRfAgcCfg.outputLevel = (ulVSBRfAgcOutputLevel);
727 state->m_vsbRfAgcCfg.minOutputLevel = (ulVSBRfAgcMinLevel);
728 state->m_vsbRfAgcCfg.maxOutputLevel = (ulVSBRfAgcMaxLevel);
729 state->m_vsbRfAgcCfg.speed = (ulVSBRfAgcSpeed);
730 state->m_vsbRfAgcCfg.top = (ulVSBRfAgcTop);
731 state->m_vsbRfAgcCfg.cutOffCurrent = (ulVSBRfAgcCutOffCurrent);
732 state->m_vsbPreSawCfg.reference = 0x07;
733 state->m_vsbPreSawCfg.usePreSaw = true;
735 state->m_Quality83percent = DEFAULT_MER_83;
736 state->m_Quality93percent = DEFAULT_MER_93;
737 if (ulQual93 <= 500 && ulQual83 < ulQual93) {
738 state->m_Quality83percent = ulQual83;
739 state->m_Quality93percent = ulQual93;
743 state->m_atvIfAgcCfg.ctrlMode = (ulATVIfAgcMode);
744 state->m_atvIfAgcCfg.outputLevel = (ulATVIfAgcOutputLevel);
745 state->m_atvIfAgcCfg.minOutputLevel = (ulATVIfAgcMinLevel);
746 state->m_atvIfAgcCfg.maxOutputLevel = (ulATVIfAgcMaxLevel);
747 state->m_atvIfAgcCfg.speed = (ulATVIfAgcSpeed);
750 state->m_atvRfAgcCfg.ctrlMode = (ulATVRfAgcMode);
751 state->m_atvRfAgcCfg.outputLevel = (ulATVRfAgcOutputLevel);
752 state->m_atvRfAgcCfg.minOutputLevel = (ulATVRfAgcMinLevel);
753 state->m_atvRfAgcCfg.maxOutputLevel = (ulATVRfAgcMaxLevel);
754 state->m_atvRfAgcCfg.speed = (ulATVRfAgcSpeed);
755 state->m_atvRfAgcCfg.top = (ulATVRfAgcTop);
756 state->m_atvRfAgcCfg.cutOffCurrent = (ulATVRfAgcCutOffCurrent);
757 state->m_atvPreSawCfg.reference = 0x04;
758 state->m_atvPreSawCfg.usePreSaw = true;
762 state->m_dvbtRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
763 state->m_dvbtRfAgcCfg.outputLevel = 0;
764 state->m_dvbtRfAgcCfg.minOutputLevel = 0;
765 state->m_dvbtRfAgcCfg.maxOutputLevel = 0xFFFF;
766 state->m_dvbtRfAgcCfg.top = 0x2100;
767 state->m_dvbtRfAgcCfg.cutOffCurrent = 4000;
768 state->m_dvbtRfAgcCfg.speed = 1;
772 state->m_dvbtIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
773 state->m_dvbtIfAgcCfg.outputLevel = 0;
774 state->m_dvbtIfAgcCfg.minOutputLevel = 0;
775 state->m_dvbtIfAgcCfg.maxOutputLevel = 9000;
776 state->m_dvbtIfAgcCfg.top = 13424;
777 state->m_dvbtIfAgcCfg.cutOffCurrent = 0;
778 state->m_dvbtIfAgcCfg.speed = 3;
779 state->m_dvbtIfAgcCfg.FastClipCtrlDelay = 30;
780 state->m_dvbtIfAgcCfg.IngainTgtMax = 30000;
781 /* state->m_dvbtPgaCfg = 140; */
783 state->m_dvbtPreSawCfg.reference = 4;
784 state->m_dvbtPreSawCfg.usePreSaw = false;
787 state->m_qamRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
788 state->m_qamRfAgcCfg.outputLevel = 0;
789 state->m_qamRfAgcCfg.minOutputLevel = 6023;
790 state->m_qamRfAgcCfg.maxOutputLevel = 27000;
791 state->m_qamRfAgcCfg.top = 0x2380;
792 state->m_qamRfAgcCfg.cutOffCurrent = 4000;
793 state->m_qamRfAgcCfg.speed = 3;
796 state->m_qamIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
797 state->m_qamIfAgcCfg.outputLevel = 0;
798 state->m_qamIfAgcCfg.minOutputLevel = 0;
799 state->m_qamIfAgcCfg.maxOutputLevel = 9000;
800 state->m_qamIfAgcCfg.top = 0x0511;
801 state->m_qamIfAgcCfg.cutOffCurrent = 0;
802 state->m_qamIfAgcCfg.speed = 3;
803 state->m_qamIfAgcCfg.IngainTgtMax = 5119;
804 state->m_qamIfAgcCfg.FastClipCtrlDelay = 50;
806 state->m_qamPgaCfg = 140;
807 state->m_qamPreSawCfg.reference = 4;
808 state->m_qamPreSawCfg.usePreSaw = false;
810 state->m_OperationMode = OM_NONE;
811 state->m_DrxkState = DRXK_UNINITIALIZED;
813 /* MPEG output configuration */
814 state->m_enableMPEGOutput = true; /* If TRUE; enable MPEG ouput */
815 state->m_insertRSByte = false; /* If TRUE; insert RS byte */
816 state->m_invertDATA = false; /* If TRUE; invert DATA signals */
817 state->m_invertERR = false; /* If TRUE; invert ERR signal */
818 state->m_invertSTR = false; /* If TRUE; invert STR signals */
819 state->m_invertVAL = false; /* If TRUE; invert VAL signals */
820 state->m_invertCLK = (ulInvertTSClock != 0); /* If TRUE; invert CLK signals */
822 /* If TRUE; static MPEG clockrate will be used;
823 otherwise clockrate will adapt to the bitrate of the TS */
825 state->m_DVBTBitrate = ulDVBTBitrate;
826 state->m_DVBCBitrate = ulDVBCBitrate;
828 state->m_TSDataStrength = (ulTSDataStrength & 0x07);
830 /* Maximum bitrate in b/s in case static clockrate is selected */
831 state->m_mpegTsStaticBitrate = 19392658;
832 state->m_disableTEIhandling = false;
835 state->m_insertRSByte = true;
837 state->m_MpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
838 if (ulMpegLockTimeOut < 10000)
839 state->m_MpegLockTimeOut = ulMpegLockTimeOut;
840 state->m_DemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
841 if (ulDemodLockTimeOut < 10000)
842 state->m_DemodLockTimeOut = ulDemodLockTimeOut;
845 state->m_Constellation = DRX_CONSTELLATION_AUTO;
846 state->m_qamInterleaveMode = DRXK_QAM_I12_J17;
847 state->m_fecRsPlen = 204 * 8; /* fecRsPlen annex A */
848 state->m_fecRsPrescale = 1;
850 state->m_sqiSpeed = DRXK_DVBT_SQI_SPEED_MEDIUM;
851 state->m_agcFastClipCtrlDelay = 0;
853 state->m_GPIOCfg = (ulGPIOCfg);
855 state->m_bPowerDown = false;
856 state->m_currentPowerMode = DRX_POWER_DOWN;
858 state->m_rfmirror = (ulRfMirror == 0);
859 state->m_IfAgcPol = false;
863 static int DRXX_Open(struct drxk_state *state)
871 /* stop lock indicator process */
872 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
875 /* Check device id */
876 status = read16(state, SIO_TOP_COMM_KEY__A, &key);
879 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
882 status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
885 status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);
888 status = write16(state, SIO_TOP_COMM_KEY__A, key);
891 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
895 static int GetDeviceCapabilities(struct drxk_state *state)
897 u16 sioPdrOhwCfg = 0;
898 u32 sioTopJtagidLo = 0;
900 const char *spin = "";
905 /* stop lock indicator process */
906 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
909 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
912 status = read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg);
915 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
919 switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
921 /* ignore (bypass ?) */
925 state->m_oscClockFreq = 27000;
929 state->m_oscClockFreq = 20250;
933 state->m_oscClockFreq = 20250;
936 printk(KERN_ERR "drxk: Clock Frequency is unknown\n");
940 Determine device capabilities
943 status = read32(state, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo);
947 printk(KERN_INFO "drxk: status = 0x%08x\n", sioTopJtagidLo);
950 switch ((sioTopJtagidLo >> 29) & 0xF) {
952 state->m_deviceSpin = DRXK_SPIN_A1;
956 state->m_deviceSpin = DRXK_SPIN_A2;
960 state->m_deviceSpin = DRXK_SPIN_A3;
964 state->m_deviceSpin = DRXK_SPIN_UNKNOWN;
966 printk(KERN_ERR "drxk: Spin %d unknown\n",
967 (sioTopJtagidLo >> 29) & 0xF);
970 switch ((sioTopJtagidLo >> 12) & 0xFF) {
972 /* typeId = DRX3913K_TYPE_ID */
973 state->m_hasLNA = false;
974 state->m_hasOOB = false;
975 state->m_hasATV = false;
976 state->m_hasAudio = false;
977 state->m_hasDVBT = true;
978 state->m_hasDVBC = true;
979 state->m_hasSAWSW = true;
980 state->m_hasGPIO2 = false;
981 state->m_hasGPIO1 = false;
982 state->m_hasIRQN = false;
985 /* typeId = DRX3915K_TYPE_ID */
986 state->m_hasLNA = false;
987 state->m_hasOOB = false;
988 state->m_hasATV = true;
989 state->m_hasAudio = false;
990 state->m_hasDVBT = true;
991 state->m_hasDVBC = false;
992 state->m_hasSAWSW = true;
993 state->m_hasGPIO2 = true;
994 state->m_hasGPIO1 = true;
995 state->m_hasIRQN = false;
998 /* typeId = DRX3916K_TYPE_ID */
999 state->m_hasLNA = false;
1000 state->m_hasOOB = false;
1001 state->m_hasATV = true;
1002 state->m_hasAudio = false;
1003 state->m_hasDVBT = true;
1004 state->m_hasDVBC = false;
1005 state->m_hasSAWSW = true;
1006 state->m_hasGPIO2 = true;
1007 state->m_hasGPIO1 = true;
1008 state->m_hasIRQN = false;
1011 /* typeId = DRX3918K_TYPE_ID */
1012 state->m_hasLNA = false;
1013 state->m_hasOOB = false;
1014 state->m_hasATV = true;
1015 state->m_hasAudio = true;
1016 state->m_hasDVBT = true;
1017 state->m_hasDVBC = false;
1018 state->m_hasSAWSW = true;
1019 state->m_hasGPIO2 = true;
1020 state->m_hasGPIO1 = true;
1021 state->m_hasIRQN = false;
1024 /* typeId = DRX3921K_TYPE_ID */
1025 state->m_hasLNA = false;
1026 state->m_hasOOB = false;
1027 state->m_hasATV = true;
1028 state->m_hasAudio = true;
1029 state->m_hasDVBT = true;
1030 state->m_hasDVBC = true;
1031 state->m_hasSAWSW = true;
1032 state->m_hasGPIO2 = true;
1033 state->m_hasGPIO1 = true;
1034 state->m_hasIRQN = false;
1037 /* typeId = DRX3923K_TYPE_ID */
1038 state->m_hasLNA = false;
1039 state->m_hasOOB = false;
1040 state->m_hasATV = true;
1041 state->m_hasAudio = true;
1042 state->m_hasDVBT = true;
1043 state->m_hasDVBC = true;
1044 state->m_hasSAWSW = true;
1045 state->m_hasGPIO2 = true;
1046 state->m_hasGPIO1 = true;
1047 state->m_hasIRQN = false;
1050 /* typeId = DRX3925K_TYPE_ID */
1051 state->m_hasLNA = false;
1052 state->m_hasOOB = false;
1053 state->m_hasATV = true;
1054 state->m_hasAudio = true;
1055 state->m_hasDVBT = true;
1056 state->m_hasDVBC = true;
1057 state->m_hasSAWSW = true;
1058 state->m_hasGPIO2 = true;
1059 state->m_hasGPIO1 = true;
1060 state->m_hasIRQN = false;
1063 /* typeId = DRX3926K_TYPE_ID */
1064 state->m_hasLNA = false;
1065 state->m_hasOOB = false;
1066 state->m_hasATV = true;
1067 state->m_hasAudio = false;
1068 state->m_hasDVBT = true;
1069 state->m_hasDVBC = true;
1070 state->m_hasSAWSW = true;
1071 state->m_hasGPIO2 = true;
1072 state->m_hasGPIO1 = true;
1073 state->m_hasIRQN = false;
1076 printk(KERN_ERR "drxk: DeviceID 0x%02x not supported\n",
1077 ((sioTopJtagidLo >> 12) & 0xFF));
1083 "drxk: detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n",
1084 ((sioTopJtagidLo >> 12) & 0xFF), spin,
1085 state->m_oscClockFreq / 1000,
1086 state->m_oscClockFreq % 1000);
1090 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1096 static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult)
1104 status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);
1107 if (cmd == SIO_HI_RA_RAM_CMD_RESET)
1111 (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
1112 ((state->m_HICfgCtrl) &
1113 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) ==
1114 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ);
1115 if (powerdown_cmd == false) {
1116 /* Wait until command rdy */
1123 status = read16(state, SIO_HI_RA_RAM_CMD__A,
1125 } while ((status < 0) && (retryCount < DRXK_MAX_RETRIES)
1129 status = read16(state, SIO_HI_RA_RAM_RES__A, pResult);
1133 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1138 static int HI_CfgCommand(struct drxk_state *state)
1144 mutex_lock(&state->mutex);
1146 status = write16(state, SIO_HI_RA_RAM_PAR_6__A, state->m_HICfgTimeout);
1149 status = write16(state, SIO_HI_RA_RAM_PAR_5__A, state->m_HICfgCtrl);
1152 status = write16(state, SIO_HI_RA_RAM_PAR_4__A, state->m_HICfgWakeUpKey);
1155 status = write16(state, SIO_HI_RA_RAM_PAR_3__A, state->m_HICfgBridgeDelay);
1158 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, state->m_HICfgTimingDiv);
1161 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
1164 status = HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0);
1168 state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1170 mutex_unlock(&state->mutex);
1172 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1176 static int InitHI(struct drxk_state *state)
1180 state->m_HICfgWakeUpKey = (state->demod_address << 1);
1181 state->m_HICfgTimeout = 0x96FF;
1182 /* port/bridge/power down ctrl */
1183 state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
1185 return HI_CfgCommand(state);
1188 static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)
1191 u16 sioPdrMclkCfg = 0;
1192 u16 sioPdrMdxCfg = 0;
1195 dprintk(1, ": mpeg %s, %s mode\n",
1196 mpegEnable ? "enable" : "disable",
1197 state->m_enableParallel ? "parallel" : "serial");
1199 /* stop lock indicator process */
1200 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1204 /* MPEG TS pad configuration */
1205 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
1209 if (mpegEnable == false) {
1210 /* Set MPEG TS pads to inputmode */
1211 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
1214 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);
1217 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);
1220 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);
1223 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);
1226 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1229 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1232 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1235 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1238 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1241 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1244 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1248 /* Enable MPEG output */
1250 ((state->m_TSDataStrength <<
1251 SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003);
1252 sioPdrMclkCfg = ((state->m_TSClockkStrength <<
1253 SIO_PDR_MCLK_CFG_DRIVE__B) |
1256 status = write16(state, SIO_PDR_MSTRT_CFG__A, sioPdrMdxCfg);
1260 if (state->enable_merr_cfg)
1261 err_cfg = sioPdrMdxCfg;
1263 status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg);
1266 status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg);
1270 if (state->m_enableParallel == true) {
1271 /* paralel -> enable MD1 to MD7 */
1272 status = write16(state, SIO_PDR_MD1_CFG__A, sioPdrMdxCfg);
1275 status = write16(state, SIO_PDR_MD2_CFG__A, sioPdrMdxCfg);
1278 status = write16(state, SIO_PDR_MD3_CFG__A, sioPdrMdxCfg);
1281 status = write16(state, SIO_PDR_MD4_CFG__A, sioPdrMdxCfg);
1284 status = write16(state, SIO_PDR_MD5_CFG__A, sioPdrMdxCfg);
1287 status = write16(state, SIO_PDR_MD6_CFG__A, sioPdrMdxCfg);
1290 status = write16(state, SIO_PDR_MD7_CFG__A, sioPdrMdxCfg);
1294 sioPdrMdxCfg = ((state->m_TSDataStrength <<
1295 SIO_PDR_MD0_CFG_DRIVE__B)
1297 /* serial -> disable MD1 to MD7 */
1298 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1301 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1304 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1307 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1310 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1313 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1316 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1320 status = write16(state, SIO_PDR_MCLK_CFG__A, sioPdrMclkCfg);
1323 status = write16(state, SIO_PDR_MD0_CFG__A, sioPdrMdxCfg);
1327 /* Enable MB output over MPEG pads and ctl input */
1328 status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
1331 /* Write nomagic word to enable pdr reg write */
1332 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
1335 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1339 static int MPEGTSDisable(struct drxk_state *state)
1343 return MPEGTSConfigurePins(state, false);
1346 static int BLChainCmd(struct drxk_state *state,
1347 u16 romOffset, u16 nrOfElements, u32 timeOut)
1354 mutex_lock(&state->mutex);
1355 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1358 status = write16(state, SIO_BL_CHAIN_ADDR__A, romOffset);
1361 status = write16(state, SIO_BL_CHAIN_LEN__A, nrOfElements);
1364 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1368 end = jiffies + msecs_to_jiffies(timeOut);
1371 status = read16(state, SIO_BL_STATUS__A, &blStatus);
1374 } while ((blStatus == 0x1) &&
1375 ((time_is_after_jiffies(end))));
1377 if (blStatus == 0x1) {
1378 printk(KERN_ERR "drxk: SIO not ready\n");
1384 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1386 mutex_unlock(&state->mutex);
1391 static int DownloadMicrocode(struct drxk_state *state,
1392 const u8 pMCImage[], u32 Length)
1394 const u8 *pSrc = pMCImage;
1404 /* down the drain (we don't care about MAGIC_WORD) */
1406 /* For future reference */
1407 Drain = (pSrc[0] << 8) | pSrc[1];
1409 pSrc += sizeof(u16);
1410 offset += sizeof(u16);
1411 nBlocks = (pSrc[0] << 8) | pSrc[1];
1412 pSrc += sizeof(u16);
1413 offset += sizeof(u16);
1415 for (i = 0; i < nBlocks; i += 1) {
1416 Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
1417 (pSrc[2] << 8) | pSrc[3];
1418 pSrc += sizeof(u32);
1419 offset += sizeof(u32);
1421 BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
1422 pSrc += sizeof(u16);
1423 offset += sizeof(u16);
1426 /* For future reference */
1427 Flags = (pSrc[0] << 8) | pSrc[1];
1429 pSrc += sizeof(u16);
1430 offset += sizeof(u16);
1433 /* For future reference */
1434 BlockCRC = (pSrc[0] << 8) | pSrc[1];
1436 pSrc += sizeof(u16);
1437 offset += sizeof(u16);
1439 if (offset + BlockSize > Length) {
1440 printk(KERN_ERR "drxk: Firmware is corrupted.\n");
1444 status = write_block(state, Address, BlockSize, pSrc);
1446 printk(KERN_ERR "drxk: Error %d while loading firmware\n", status);
1450 offset += BlockSize;
1455 static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable)
1459 u16 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON;
1460 u16 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED;
1465 if (enable == false) {
1466 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF;
1467 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN;
1470 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1471 if (status >= 0 && data == desiredStatus) {
1472 /* tokenring already has correct status */
1475 /* Disable/enable dvbt tokenring bridge */
1476 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl);
1478 end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
1480 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1481 if ((status >= 0 && data == desiredStatus) || time_is_after_jiffies(end))
1485 if (data != desiredStatus) {
1486 printk(KERN_ERR "drxk: SIO not ready\n");
1492 static int MPEGTSStop(struct drxk_state *state)
1495 u16 fecOcSncMode = 0;
1496 u16 fecOcIprMode = 0;
1500 /* Gracefull shutdown (byte boundaries) */
1501 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1504 fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M;
1505 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1509 /* Suppress MCLK during absence of data */
1510 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcIprMode);
1513 fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M;
1514 status = write16(state, FEC_OC_IPR_MODE__A, fecOcIprMode);
1518 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1523 static int scu_command(struct drxk_state *state,
1524 u16 cmd, u8 parameterLen,
1525 u16 *parameter, u8 resultLen, u16 *result)
1527 #if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15
1528 #error DRXK register mapping no longer compatible with this routine!
1531 int status = -EINVAL;
1540 if ((cmd == 0) || ((parameterLen > 0) && (parameter == NULL)) ||
1541 ((resultLen > 0) && (result == NULL))) {
1542 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1546 mutex_lock(&state->mutex);
1548 /* assume that the command register is ready
1549 since it is checked afterwards */
1550 for (ii = parameterLen - 1; ii >= 0; ii -= 1) {
1551 buffer[cnt++] = (parameter[ii] & 0xFF);
1552 buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF);
1554 buffer[cnt++] = (cmd & 0xFF);
1555 buffer[cnt++] = ((cmd >> 8) & 0xFF);
1557 write_block(state, SCU_RAM_PARAM_0__A -
1558 (parameterLen - 1), cnt, buffer);
1559 /* Wait until SCU has processed command */
1560 end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
1563 status = read16(state, SCU_RAM_COMMAND__A, &curCmd);
1566 } while (!(curCmd == DRX_SCU_READY) && (time_is_after_jiffies(end)));
1567 if (curCmd != DRX_SCU_READY) {
1568 printk(KERN_ERR "drxk: SCU not ready\n");
1573 if ((resultLen > 0) && (result != NULL)) {
1577 for (ii = resultLen - 1; ii >= 0; ii -= 1) {
1578 status = read16(state, SCU_RAM_PARAM_0__A - ii, &result[ii]);
1583 /* Check if an error was reported by SCU */
1584 err = (s16)result[0];
1588 /* check for the known error codes */
1590 case SCU_RESULT_UNKCMD:
1591 p = "SCU_RESULT_UNKCMD";
1593 case SCU_RESULT_UNKSTD:
1594 p = "SCU_RESULT_UNKSTD";
1596 case SCU_RESULT_SIZE:
1597 p = "SCU_RESULT_SIZE";
1599 case SCU_RESULT_INVPAR:
1600 p = "SCU_RESULT_INVPAR";
1602 default: /* Other negative values are errors */
1603 sprintf(errname, "ERROR: %d\n", err);
1606 printk(KERN_ERR "drxk: %s while sending cmd 0x%04x with params:", p, cmd);
1607 print_hex_dump_bytes("drxk: ", DUMP_PREFIX_NONE, buffer, cnt);
1614 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1616 mutex_unlock(&state->mutex);
1620 static int SetIqmAf(struct drxk_state *state, bool active)
1628 status = read16(state, IQM_AF_STDBY__A, &data);
1633 data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY
1634 | IQM_AF_STDBY_STDBY_AMP_STANDBY
1635 | IQM_AF_STDBY_STDBY_PD_STANDBY
1636 | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
1637 | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY);
1639 data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY)
1640 & (~IQM_AF_STDBY_STDBY_AMP_STANDBY)
1641 & (~IQM_AF_STDBY_STDBY_PD_STANDBY)
1642 & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY)
1643 & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY)
1646 status = write16(state, IQM_AF_STDBY__A, data);
1650 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1654 static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode)
1657 u16 sioCcPwdMode = 0;
1661 /* Check arguments */
1667 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_NONE;
1669 case DRXK_POWER_DOWN_OFDM:
1670 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OFDM;
1672 case DRXK_POWER_DOWN_CORE:
1673 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
1675 case DRXK_POWER_DOWN_PLL:
1676 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_PLL;
1678 case DRX_POWER_DOWN:
1679 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OSC;
1682 /* Unknow sleep mode */
1686 /* If already in requested power mode, do nothing */
1687 if (state->m_currentPowerMode == *mode)
1690 /* For next steps make sure to start from DRX_POWER_UP mode */
1691 if (state->m_currentPowerMode != DRX_POWER_UP) {
1692 status = PowerUpDevice(state);
1695 status = DVBTEnableOFDMTokenRing(state, true);
1700 if (*mode == DRX_POWER_UP) {
1701 /* Restore analog & pin configuartion */
1703 /* Power down to requested mode */
1704 /* Backup some register settings */
1705 /* Set pins with possible pull-ups connected
1706 to them in input mode */
1707 /* Analog power down */
1708 /* ADC power down */
1709 /* Power down device */
1710 /* stop all comm_exec */
1711 /* Stop and power down previous standard */
1712 switch (state->m_OperationMode) {
1714 status = MPEGTSStop(state);
1717 status = PowerDownDVBT(state, false);
1723 status = MPEGTSStop(state);
1726 status = PowerDownQAM(state);
1733 status = DVBTEnableOFDMTokenRing(state, false);
1736 status = write16(state, SIO_CC_PWD_MODE__A, sioCcPwdMode);
1739 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
1743 if (*mode != DRXK_POWER_DOWN_OFDM) {
1744 state->m_HICfgCtrl |=
1745 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1746 status = HI_CfgCommand(state);
1751 state->m_currentPowerMode = *mode;
1755 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1760 static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode)
1762 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
1769 status = read16(state, SCU_COMM_EXEC__A, &data);
1772 if (data == SCU_COMM_EXEC_ACTIVE) {
1773 /* Send OFDM stop command */
1774 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
1777 /* Send OFDM reset command */
1778 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
1783 /* Reset datapath for OFDM, processors first */
1784 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1787 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1790 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
1795 status = SetIqmAf(state, false);
1799 /* powerdown to OFDM mode */
1801 status = CtrlPowerMode(state, &powerMode);
1807 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1811 static int SetOperationMode(struct drxk_state *state,
1812 enum OperationMode oMode)
1818 Stop and power down previous standard
1819 TODO investigate total power down instead of partial
1820 power down depending on "previous" standard.
1823 /* disable HW lock indicator */
1824 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1828 /* Device is already at the required mode */
1829 if (state->m_OperationMode == oMode)
1832 switch (state->m_OperationMode) {
1833 /* OM_NONE was added for start up */
1837 status = MPEGTSStop(state);
1840 status = PowerDownDVBT(state, true);
1843 state->m_OperationMode = OM_NONE;
1845 case OM_QAM_ITU_A: /* fallthrough */
1847 status = MPEGTSStop(state);
1850 status = PowerDownQAM(state);
1853 state->m_OperationMode = OM_NONE;
1862 Power up new standard
1866 dprintk(1, ": DVB-T\n");
1867 state->m_OperationMode = oMode;
1868 status = SetDVBTStandard(state, oMode);
1872 case OM_QAM_ITU_A: /* fallthrough */
1874 dprintk(1, ": DVB-C Annex %c\n",
1875 (state->m_OperationMode == OM_QAM_ITU_A) ? 'A' : 'C');
1876 state->m_OperationMode = oMode;
1877 status = SetQAMStandard(state, oMode);
1887 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1891 static int Start(struct drxk_state *state, s32 offsetFreq,
1892 s32 IntermediateFrequency)
1894 int status = -EINVAL;
1897 s32 OffsetkHz = offsetFreq / 1000;
1900 if (state->m_DrxkState != DRXK_STOPPED &&
1901 state->m_DrxkState != DRXK_DTV_STARTED)
1904 state->m_bMirrorFreqSpect = (state->props.inversion == INVERSION_ON);
1906 if (IntermediateFrequency < 0) {
1907 state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect;
1908 IntermediateFrequency = -IntermediateFrequency;
1911 switch (state->m_OperationMode) {
1914 IFreqkHz = (IntermediateFrequency / 1000);
1915 status = SetQAM(state, IFreqkHz, OffsetkHz);
1918 state->m_DrxkState = DRXK_DTV_STARTED;
1921 IFreqkHz = (IntermediateFrequency / 1000);
1922 status = MPEGTSStop(state);
1925 status = SetDVBT(state, IFreqkHz, OffsetkHz);
1928 status = DVBTStart(state);
1931 state->m_DrxkState = DRXK_DTV_STARTED;
1938 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1942 static int ShutDown(struct drxk_state *state)
1950 static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus,
1953 int status = -EINVAL;
1957 if (pLockStatus == NULL)
1960 *pLockStatus = NOT_LOCKED;
1962 /* define the SCU command code */
1963 switch (state->m_OperationMode) {
1967 status = GetQAMLockStatus(state, pLockStatus);
1970 status = GetDVBTLockStatus(state, pLockStatus);
1977 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1981 static int MPEGTSStart(struct drxk_state *state)
1985 u16 fecOcSncMode = 0;
1987 /* Allow OC to sync again */
1988 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1991 fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M;
1992 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1995 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
1998 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2002 static int MPEGTSDtoInit(struct drxk_state *state)
2008 /* Rate integration settings */
2009 status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
2012 status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
2015 status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);
2018 status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);
2021 status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);
2024 status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
2027 status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
2030 status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);
2034 /* Additional configuration */
2035 status = write16(state, FEC_OC_OCR_INVERT__A, 0);
2038 status = write16(state, FEC_OC_SNC_LWM__A, 2);
2041 status = write16(state, FEC_OC_SNC_HWM__A, 12);
2044 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2049 static int MPEGTSDtoSetup(struct drxk_state *state,
2050 enum OperationMode oMode)
2054 u16 fecOcRegMode = 0; /* FEC_OC_MODE register value */
2055 u16 fecOcRegIprMode = 0; /* FEC_OC_IPR_MODE register value */
2056 u16 fecOcDtoMode = 0; /* FEC_OC_IPR_INVERT register value */
2057 u16 fecOcFctMode = 0; /* FEC_OC_IPR_INVERT register value */
2058 u16 fecOcDtoPeriod = 2; /* FEC_OC_IPR_INVERT register value */
2059 u16 fecOcDtoBurstLen = 188; /* FEC_OC_IPR_INVERT register value */
2060 u32 fecOcRcnCtlRate = 0; /* FEC_OC_IPR_INVERT register value */
2061 u16 fecOcTmdMode = 0;
2062 u16 fecOcTmdIntUpdRate = 0;
2064 bool staticCLK = false;
2068 /* Check insertion of the Reed-Solomon parity bytes */
2069 status = read16(state, FEC_OC_MODE__A, &fecOcRegMode);
2072 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcRegIprMode);
2075 fecOcRegMode &= (~FEC_OC_MODE_PARITY__M);
2076 fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
2077 if (state->m_insertRSByte == true) {
2078 /* enable parity symbol forward */
2079 fecOcRegMode |= FEC_OC_MODE_PARITY__M;
2080 /* MVAL disable during parity bytes */
2081 fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
2082 /* TS burst length to 204 */
2083 fecOcDtoBurstLen = 204;
2086 /* Check serial or parrallel output */
2087 fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
2088 if (state->m_enableParallel == false) {
2089 /* MPEG data output is serial -> set ipr_mode[0] */
2090 fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M;
2095 maxBitRate = state->m_DVBTBitrate;
2097 fecOcRcnCtlRate = 0xC00000;
2098 staticCLK = state->m_DVBTStaticCLK;
2100 case OM_QAM_ITU_A: /* fallthrough */
2102 fecOcTmdMode = 0x0004;
2103 fecOcRcnCtlRate = 0xD2B4EE; /* good for >63 Mb/s */
2104 maxBitRate = state->m_DVBCBitrate;
2105 staticCLK = state->m_DVBCStaticCLK;
2109 } /* switch (standard) */
2113 /* Configure DTO's */
2117 /* Rational DTO for MCLK source (static MCLK rate),
2118 Dynamic DTO for optimal grouping
2119 (avoid intra-packet gaps),
2120 DTO offset enable to sync TS burst with MSTRT */
2121 fecOcDtoMode = (FEC_OC_DTO_MODE_DYNAMIC__M |
2122 FEC_OC_DTO_MODE_OFFSET_ENABLE__M);
2123 fecOcFctMode = (FEC_OC_FCT_MODE_RAT_ENA__M |
2124 FEC_OC_FCT_MODE_VIRT_ENA__M);
2126 /* Check user defined bitrate */
2127 bitRate = maxBitRate;
2128 if (bitRate > 75900000UL) { /* max is 75.9 Mb/s */
2129 bitRate = 75900000UL;
2131 /* Rational DTO period:
2132 dto_period = (Fsys / bitrate) - 2
2134 Result should be floored,
2135 to make sure >= requested bitrate
2137 fecOcDtoPeriod = (u16) (((state->m_sysClockFreq)
2139 if (fecOcDtoPeriod <= 2)
2142 fecOcDtoPeriod -= 2;
2143 fecOcTmdIntUpdRate = 8;
2145 /* (commonAttr->staticCLK == false) => dynamic mode */
2146 fecOcDtoMode = FEC_OC_DTO_MODE_DYNAMIC__M;
2147 fecOcFctMode = FEC_OC_FCT_MODE__PRE;
2148 fecOcTmdIntUpdRate = 5;
2151 /* Write appropriate registers with requested configuration */
2152 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fecOcDtoBurstLen);
2155 status = write16(state, FEC_OC_DTO_PERIOD__A, fecOcDtoPeriod);
2158 status = write16(state, FEC_OC_DTO_MODE__A, fecOcDtoMode);
2161 status = write16(state, FEC_OC_FCT_MODE__A, fecOcFctMode);
2164 status = write16(state, FEC_OC_MODE__A, fecOcRegMode);
2167 status = write16(state, FEC_OC_IPR_MODE__A, fecOcRegIprMode);
2171 /* Rate integration settings */
2172 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fecOcRcnCtlRate);
2175 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, fecOcTmdIntUpdRate);
2178 status = write16(state, FEC_OC_TMD_MODE__A, fecOcTmdMode);
2181 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2185 static int MPEGTSConfigurePolarity(struct drxk_state *state)
2187 u16 fecOcRegIprInvert = 0;
2189 /* Data mask for the output data byte */
2190 u16 InvertDataMask =
2191 FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
2192 FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
2193 FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
2194 FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
2198 /* Control selective inversion of output bits */
2199 fecOcRegIprInvert &= (~(InvertDataMask));
2200 if (state->m_invertDATA == true)
2201 fecOcRegIprInvert |= InvertDataMask;
2202 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M));
2203 if (state->m_invertERR == true)
2204 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M;
2205 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
2206 if (state->m_invertSTR == true)
2207 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M;
2208 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
2209 if (state->m_invertVAL == true)
2210 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M;
2211 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
2212 if (state->m_invertCLK == true)
2213 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M;
2215 return write16(state, FEC_OC_IPR_INVERT__A, fecOcRegIprInvert);
2218 #define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000
2220 static int SetAgcRf(struct drxk_state *state,
2221 struct SCfgAgc *pAgcCfg, bool isDTV)
2223 int status = -EINVAL;
2225 struct SCfgAgc *pIfAgcSettings;
2229 if (pAgcCfg == NULL)
2232 switch (pAgcCfg->ctrlMode) {
2233 case DRXK_AGC_CTRL_AUTO:
2234 /* Enable RF AGC DAC */
2235 status = read16(state, IQM_AF_STDBY__A, &data);
2238 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2239 status = write16(state, IQM_AF_STDBY__A, data);
2242 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2246 /* Enable SCU RF AGC loop */
2247 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2250 if (state->m_RfAgcPol)
2251 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2253 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2254 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2258 /* Set speed (using complementary reduction value) */
2259 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2263 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
2264 data |= (~(pAgcCfg->speed <<
2265 SCU_RAM_AGC_KI_RED_RAGC_RED__B)
2266 & SCU_RAM_AGC_KI_RED_RAGC_RED__M);
2268 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2273 pIfAgcSettings = &state->m_dvbtIfAgcCfg;
2274 else if (IsQAM(state))
2275 pIfAgcSettings = &state->m_qamIfAgcCfg;
2277 pIfAgcSettings = &state->m_atvIfAgcCfg;
2278 if (pIfAgcSettings == NULL) {
2283 /* Set TOP, only if IF-AGC is in AUTO mode */
2284 if (pIfAgcSettings->ctrlMode == DRXK_AGC_CTRL_AUTO)
2285 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->top);
2289 /* Cut-Off current */
2290 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, pAgcCfg->cutOffCurrent);
2294 /* Max. output level */
2295 status = write16(state, SCU_RAM_AGC_RF_MAX__A, pAgcCfg->maxOutputLevel);
2301 case DRXK_AGC_CTRL_USER:
2302 /* Enable RF AGC DAC */
2303 status = read16(state, IQM_AF_STDBY__A, &data);
2306 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2307 status = write16(state, IQM_AF_STDBY__A, data);
2311 /* Disable SCU RF AGC loop */
2312 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2315 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2316 if (state->m_RfAgcPol)
2317 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2319 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2320 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2324 /* SCU c.o.c. to 0, enabling full control range */
2325 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
2329 /* Write value to output pin */
2330 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, pAgcCfg->outputLevel);
2335 case DRXK_AGC_CTRL_OFF:
2336 /* Disable RF AGC DAC */
2337 status = read16(state, IQM_AF_STDBY__A, &data);
2340 data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2341 status = write16(state, IQM_AF_STDBY__A, data);
2345 /* Disable SCU RF AGC loop */
2346 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2349 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2350 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2361 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2365 #define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000
2367 static int SetAgcIf(struct drxk_state *state,
2368 struct SCfgAgc *pAgcCfg, bool isDTV)
2372 struct SCfgAgc *pRfAgcSettings;
2376 switch (pAgcCfg->ctrlMode) {
2377 case DRXK_AGC_CTRL_AUTO:
2379 /* Enable IF AGC DAC */
2380 status = read16(state, IQM_AF_STDBY__A, &data);
2383 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2384 status = write16(state, IQM_AF_STDBY__A, data);
2388 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2392 /* Enable SCU IF AGC loop */
2393 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2396 if (state->m_IfAgcPol)
2397 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2399 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2400 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2404 /* Set speed (using complementary reduction value) */
2405 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2408 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
2409 data |= (~(pAgcCfg->speed <<
2410 SCU_RAM_AGC_KI_RED_IAGC_RED__B)
2411 & SCU_RAM_AGC_KI_RED_IAGC_RED__M);
2413 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2418 pRfAgcSettings = &state->m_qamRfAgcCfg;
2420 pRfAgcSettings = &state->m_atvRfAgcCfg;
2421 if (pRfAgcSettings == NULL)
2424 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pRfAgcSettings->top);
2429 case DRXK_AGC_CTRL_USER:
2431 /* Enable IF AGC DAC */
2432 status = read16(state, IQM_AF_STDBY__A, &data);
2435 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2436 status = write16(state, IQM_AF_STDBY__A, data);
2440 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2444 /* Disable SCU IF AGC loop */
2445 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2448 if (state->m_IfAgcPol)
2449 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2451 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2452 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2456 /* Write value to output pin */
2457 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->outputLevel);
2462 case DRXK_AGC_CTRL_OFF:
2464 /* Disable If AGC DAC */
2465 status = read16(state, IQM_AF_STDBY__A, &data);
2468 data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2469 status = write16(state, IQM_AF_STDBY__A, data);
2473 /* Disable SCU IF AGC loop */
2474 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2477 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2478 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2482 } /* switch (agcSettingsIf->ctrlMode) */
2484 /* always set the top to support
2485 configurations without if-loop */
2486 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, pAgcCfg->top);
2489 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2493 static int ReadIFAgc(struct drxk_state *state, u32 *pValue)
2501 status = read16(state, IQM_AF_AGC_IF__A, &agcDacLvl);
2503 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2509 if (agcDacLvl > DRXK_AGC_DAC_OFFSET)
2510 Level = agcDacLvl - DRXK_AGC_DAC_OFFSET;
2512 *pValue = (14000 - Level) / 4;
2519 static int GetQAMSignalToNoise(struct drxk_state *state,
2520 s32 *pSignalToNoise)
2523 u16 qamSlErrPower = 0; /* accum. error between
2524 raw and sliced symbols */
2525 u32 qamSlSigPower = 0; /* used for MER, depends of
2527 u32 qamSlMer = 0; /* QAM MER */
2531 /* MER calculation */
2533 /* get the register value needed for MER */
2534 status = read16(state, QAM_SL_ERR_POWER__A, &qamSlErrPower);
2536 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2540 switch (state->props.modulation) {
2542 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2;
2545 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM32 << 2;
2548 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM64 << 2;
2551 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM128 << 2;
2555 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM256 << 2;
2559 if (qamSlErrPower > 0) {
2560 qamSlMer = Log10Times100(qamSlSigPower) -
2561 Log10Times100((u32) qamSlErrPower);
2563 *pSignalToNoise = qamSlMer;
2568 static int GetDVBTSignalToNoise(struct drxk_state *state,
2569 s32 *pSignalToNoise)
2573 u32 EqRegTdSqrErrI = 0;
2574 u32 EqRegTdSqrErrQ = 0;
2575 u16 EqRegTdSqrErrExp = 0;
2576 u16 EqRegTdTpsPwrOfs = 0;
2577 u16 EqRegTdReqSmbCnt = 0;
2584 u16 transmissionParams = 0;
2588 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &EqRegTdTpsPwrOfs);
2591 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, &EqRegTdReqSmbCnt);
2594 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, &EqRegTdSqrErrExp);
2597 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, ®Data);
2600 /* Extend SQR_ERR_I operational range */
2601 EqRegTdSqrErrI = (u32) regData;
2602 if ((EqRegTdSqrErrExp > 11) &&
2603 (EqRegTdSqrErrI < 0x00000FFFUL)) {
2604 EqRegTdSqrErrI += 0x00010000UL;
2606 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, ®Data);
2609 /* Extend SQR_ERR_Q operational range */
2610 EqRegTdSqrErrQ = (u32) regData;
2611 if ((EqRegTdSqrErrExp > 11) &&
2612 (EqRegTdSqrErrQ < 0x00000FFFUL))
2613 EqRegTdSqrErrQ += 0x00010000UL;
2615 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, &transmissionParams);
2619 /* Check input data for MER */
2621 /* MER calculation (in 0.1 dB) without math.h */
2622 if ((EqRegTdTpsPwrOfs == 0) || (EqRegTdReqSmbCnt == 0))
2624 else if ((EqRegTdSqrErrI + EqRegTdSqrErrQ) == 0) {
2625 /* No error at all, this must be the HW reset value
2626 * Apparently no first measurement yet
2630 SqrErrIQ = (EqRegTdSqrErrI + EqRegTdSqrErrQ) <<
2632 if ((transmissionParams &
2633 OFDM_SC_RA_RAM_OP_PARAM_MODE__M)
2634 == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K)
2639 /* IMER = 100 * log10 (x)
2640 where x = (EqRegTdTpsPwrOfs^2 *
2641 EqRegTdReqSmbCnt * tpsCnt)/SqrErrIQ
2644 where a = 100 * log10 (EqRegTdTpsPwrOfs^2)
2645 b = 100 * log10 (EqRegTdReqSmbCnt * tpsCnt)
2646 c = 100 * log10 (SqrErrIQ)
2649 /* log(x) x = 9bits * 9bits->18 bits */
2650 a = Log10Times100(EqRegTdTpsPwrOfs *
2652 /* log(x) x = 16bits * 7bits->23 bits */
2653 b = Log10Times100(EqRegTdReqSmbCnt * tpsCnt);
2654 /* log(x) x = (16bits + 16bits) << 15 ->32 bits */
2655 c = Log10Times100(SqrErrIQ);
2658 /* No negative MER, clip to zero */
2664 *pSignalToNoise = iMER;
2668 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2672 static int GetSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise)
2676 *pSignalToNoise = 0;
2677 switch (state->m_OperationMode) {
2679 return GetDVBTSignalToNoise(state, pSignalToNoise);
2682 return GetQAMSignalToNoise(state, pSignalToNoise);
2690 static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality)
2692 /* SNR Values for quasi errorfree reception rom Nordig 2.2 */
2697 static s32 QE_SN[] = {
2703 108, /* 16-QAM 1/2 */
2704 131, /* 16-QAM 2/3 */
2705 146, /* 16-QAM 3/4 */
2706 156, /* 16-QAM 5/6 */
2707 160, /* 16-QAM 7/8 */
2708 165, /* 64-QAM 1/2 */
2709 187, /* 64-QAM 2/3 */
2710 202, /* 64-QAM 3/4 */
2711 216, /* 64-QAM 5/6 */
2712 225, /* 64-QAM 7/8 */
2718 s32 SignalToNoise = 0;
2719 u16 Constellation = 0;
2721 u32 SignalToNoiseRel;
2724 status = GetDVBTSignalToNoise(state, &SignalToNoise);
2727 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A, &Constellation);
2730 Constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M;
2732 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, &CodeRate);
2735 CodeRate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M;
2737 if (Constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM ||
2738 CodeRate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8)
2740 SignalToNoiseRel = SignalToNoise -
2741 QE_SN[Constellation * 5 + CodeRate];
2744 if (SignalToNoiseRel < -70)
2746 else if (SignalToNoiseRel < 30)
2747 *pQuality = ((SignalToNoiseRel + 70) *
2750 *pQuality = BERQuality;
2755 static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality)
2763 u32 SignalToNoise = 0;
2764 u32 BERQuality = 100;
2765 u32 SignalToNoiseRel = 0;
2767 status = GetQAMSignalToNoise(state, &SignalToNoise);
2771 switch (state->props.modulation) {
2773 SignalToNoiseRel = SignalToNoise - 200;
2776 SignalToNoiseRel = SignalToNoise - 230;
2777 break; /* Not in NorDig */
2779 SignalToNoiseRel = SignalToNoise - 260;
2782 SignalToNoiseRel = SignalToNoise - 290;
2786 SignalToNoiseRel = SignalToNoise - 320;
2790 if (SignalToNoiseRel < -70)
2792 else if (SignalToNoiseRel < 30)
2793 *pQuality = ((SignalToNoiseRel + 70) *
2796 *pQuality = BERQuality;
2802 static int GetQuality(struct drxk_state *state, s32 *pQuality)
2806 switch (state->m_OperationMode) {
2808 return GetDVBTQuality(state, pQuality);
2810 return GetDVBCQuality(state, pQuality);
2819 /* Free data ram in SIO HI */
2820 #define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
2821 #define SIO_HI_RA_RAM_USR_END__A 0x420060
2823 #define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
2824 #define DRXK_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
2825 #define DRXK_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
2826 #define DRXK_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
2828 #define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr) >> 22) & 0x3F)
2829 #define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F)
2830 #define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF)
2832 static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge)
2834 int status = -EINVAL;
2838 if (state->m_DrxkState == DRXK_UNINITIALIZED)
2840 if (state->m_DrxkState == DRXK_POWERED_DOWN)
2843 if (state->no_i2c_bridge)
2846 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
2849 if (bEnableBridge) {
2850 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
2854 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
2859 status = HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, 0);
2863 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2867 static int SetPreSaw(struct drxk_state *state,
2868 struct SCfgPreSaw *pPreSawCfg)
2870 int status = -EINVAL;
2874 if ((pPreSawCfg == NULL)
2875 || (pPreSawCfg->reference > IQM_AF_PDREF__M))
2878 status = write16(state, IQM_AF_PDREF__A, pPreSawCfg->reference);
2881 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2885 static int BLDirectCmd(struct drxk_state *state, u32 targetAddr,
2886 u16 romOffset, u16 nrOfElements, u32 timeOut)
2889 u16 offset = (u16) ((targetAddr >> 0) & 0x00FFFF);
2890 u16 blockbank = (u16) ((targetAddr >> 16) & 0x000FFF);
2896 mutex_lock(&state->mutex);
2897 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
2900 status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
2903 status = write16(state, SIO_BL_TGT_ADDR__A, offset);
2906 status = write16(state, SIO_BL_SRC_ADDR__A, romOffset);
2909 status = write16(state, SIO_BL_SRC_LEN__A, nrOfElements);
2912 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2916 end = jiffies + msecs_to_jiffies(timeOut);
2918 status = read16(state, SIO_BL_STATUS__A, &blStatus);
2921 } while ((blStatus == 0x1) && time_is_after_jiffies(end));
2922 if (blStatus == 0x1) {
2923 printk(KERN_ERR "drxk: SIO not ready\n");
2929 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2931 mutex_unlock(&state->mutex);
2936 static int ADCSyncMeasurement(struct drxk_state *state, u16 *count)
2943 /* Start measurement */
2944 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2947 status = write16(state, IQM_AF_START_LOCK__A, 1);
2952 status = read16(state, IQM_AF_PHASE0__A, &data);
2956 *count = *count + 1;
2957 status = read16(state, IQM_AF_PHASE1__A, &data);
2961 *count = *count + 1;
2962 status = read16(state, IQM_AF_PHASE2__A, &data);
2966 *count = *count + 1;
2970 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2974 static int ADCSynchronization(struct drxk_state *state)
2981 status = ADCSyncMeasurement(state, &count);
2986 /* Try sampling on a diffrent edge */
2989 status = read16(state, IQM_AF_CLKNEG__A, &clkNeg);
2992 if ((clkNeg & IQM_AF_CLKNEG_CLKNEGDATA__M) ==
2993 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) {
2994 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2996 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG;
2998 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
3000 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS;
3002 status = write16(state, IQM_AF_CLKNEG__A, clkNeg);
3005 status = ADCSyncMeasurement(state, &count);
3014 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3018 static int SetFrequencyShifter(struct drxk_state *state,
3019 u16 intermediateFreqkHz,
3020 s32 tunerFreqOffset, bool isDTV)
3022 bool selectPosImage = false;
3023 u32 rfFreqResidual = tunerFreqOffset;
3024 u32 fmFrequencyShift = 0;
3025 bool tunerMirror = !state->m_bMirrorFreqSpect;
3030 u32 samplingFrequency = (u32) (state->m_sysClockFreq / 3);
3037 Program frequency shifter
3038 No need to account for mirroring on RF
3041 if ((state->m_OperationMode == OM_QAM_ITU_A) ||
3042 (state->m_OperationMode == OM_QAM_ITU_C) ||
3043 (state->m_OperationMode == OM_DVBT))
3044 selectPosImage = true;
3046 selectPosImage = false;
3049 /* tuner doesn't mirror */
3050 ifFreqActual = intermediateFreqkHz +
3051 rfFreqResidual + fmFrequencyShift;
3054 ifFreqActual = intermediateFreqkHz -
3055 rfFreqResidual - fmFrequencyShift;
3056 if (ifFreqActual > samplingFrequency / 2) {
3058 adcFreq = samplingFrequency - ifFreqActual;
3061 /* adc doesn't mirror */
3062 adcFreq = ifFreqActual;
3066 frequencyShift = adcFreq;
3067 imageToSelect = state->m_rfmirror ^ tunerMirror ^
3068 adcFlip ^ selectPosImage;
3069 state->m_IqmFsRateOfs =
3070 Frac28a((frequencyShift), samplingFrequency);
3073 state->m_IqmFsRateOfs = ~state->m_IqmFsRateOfs + 1;
3075 /* Program frequency shifter with tuner offset compensation */
3076 /* frequencyShift += tunerFreqOffset; TODO */
3077 status = write32(state, IQM_FS_RATE_OFS_LO__A,
3078 state->m_IqmFsRateOfs);
3080 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3084 static int InitAGC(struct drxk_state *state, bool isDTV)
3087 u16 ingainTgtMin = 0;
3088 u16 ingainTgtMax = 0;
3096 u16 kiInnergainMin = 0;
3097 u16 ifIaccuHiTgt = 0;
3098 u16 ifIaccuHiTgtMin = 0;
3099 u16 ifIaccuHiTgtMax = 0;
3101 u16 fastClpCtrlDelay = 0;
3102 u16 clpCtrlMode = 0;
3107 /* Common settings */
3109 ifIaccuHiTgtMin = 2047;
3113 /* AGCInit() not available for DVBT; init done in microcode */
3114 if (!IsQAM(state)) {
3115 printk(KERN_ERR "drxk: %s: mode %d is not DVB-C\n", __func__, state->m_OperationMode);
3119 /* FIXME: Analog TV AGC require different settings */
3121 /* Standard specific settings */
3123 clpDirTo = (u16) -9;
3126 snsDirTo = (u16) -9;
3127 kiInnergainMin = (u16) -1030;
3128 ifIaccuHiTgtMax = 0x2380;
3129 ifIaccuHiTgt = 0x2380;
3130 ingainTgtMin = 0x0511;
3132 ingainTgtMax = 5119;
3133 fastClpCtrlDelay = state->m_qamIfAgcCfg.FastClipCtrlDelay;
3135 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, fastClpCtrlDelay);
3139 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clpCtrlMode);
3142 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingainTgt);
3145 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingainTgtMin);
3148 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingainTgtMax);
3151 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, ifIaccuHiTgtMin);
3154 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, ifIaccuHiTgtMax);
3157 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
3160 status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);
3163 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);
3166 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
3169 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clpSumMax);
3172 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, snsSumMax);
3176 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, kiInnergainMin);
3179 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, ifIaccuHiTgt);
3182 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clpCyclen);
3186 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);
3189 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);
3192 status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);
3196 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
3199 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clpSumMin);
3202 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, snsSumMin);
3205 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clpDirTo);
3208 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, snsDirTo);
3211 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
3214 status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);
3217 status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);
3220 status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);
3223 status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);
3226 status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);
3229 status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);
3232 status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);
3235 status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);
3238 status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);
3241 status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);
3244 status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);
3247 status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);
3250 status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);
3254 /* Initialize inner-loop KI gain factors */
3255 status = read16(state, SCU_RAM_AGC_KI__A, &data);
3260 data &= ~SCU_RAM_AGC_KI_RF__M;
3261 data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B);
3262 data &= ~SCU_RAM_AGC_KI_IF__M;
3263 data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B);
3265 status = write16(state, SCU_RAM_AGC_KI__A, data);
3268 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3272 static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 *packetErr)
3277 if (packetErr == NULL)
3278 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
3280 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, packetErr);
3282 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3286 static int DVBTScCommand(struct drxk_state *state,
3287 u16 cmd, u16 subcmd,
3288 u16 param0, u16 param1, u16 param2,
3289 u16 param3, u16 param4)
3298 status = read16(state, OFDM_SC_COMM_EXEC__A, &scExec);
3300 /* SC is not running */
3306 /* Wait until sc is ready to receive command */
3310 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
3312 } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
3313 if (retryCnt >= DRXK_MAX_RETRIES && (status < 0))
3316 /* Write sub-command */
3318 /* All commands using sub-cmd */
3319 case OFDM_SC_RA_RAM_CMD_PROC_START:
3320 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3321 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3322 status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
3331 /* Write needed parameters and the command */
3333 /* All commands using 5 parameters */
3334 /* All commands using 4 parameters */
3335 /* All commands using 3 parameters */
3336 /* All commands using 2 parameters */
3337 case OFDM_SC_RA_RAM_CMD_PROC_START:
3338 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3339 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3340 status = write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
3341 /* All commands using 1 parameters */
3342 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3343 case OFDM_SC_RA_RAM_CMD_USER_IO:
3344 status = write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
3345 /* All commands using 0 parameters */
3346 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3347 case OFDM_SC_RA_RAM_CMD_NULL:
3349 status = write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);
3352 /* Unknown command */
3358 /* Wait until sc is ready processing command */
3362 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
3364 } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
3365 if (retryCnt >= DRXK_MAX_RETRIES && (status < 0))
3368 /* Check for illegal cmd */
3369 status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &errCode);
3370 if (errCode == 0xFFFF) {
3371 /* illegal command */
3377 /* Retreive results parameters from SC */
3379 /* All commands yielding 5 results */
3380 /* All commands yielding 4 results */
3381 /* All commands yielding 3 results */
3382 /* All commands yielding 2 results */
3383 /* All commands yielding 1 result */
3384 case OFDM_SC_RA_RAM_CMD_USER_IO:
3385 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3386 status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
3387 /* All commands yielding 0 results */
3388 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3389 case OFDM_SC_RA_RAM_CMD_SET_TIMER:
3390 case OFDM_SC_RA_RAM_CMD_PROC_START:
3391 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3392 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3393 case OFDM_SC_RA_RAM_CMD_NULL:
3396 /* Unknown command */
3399 } /* switch (cmd->cmd) */
3402 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3406 static int PowerUpDVBT(struct drxk_state *state)
3408 enum DRXPowerMode powerMode = DRX_POWER_UP;
3412 status = CtrlPowerMode(state, &powerMode);
3414 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3418 static int DVBTCtrlSetIncEnable(struct drxk_state *state, bool *enabled)
3423 if (*enabled == true)
3424 status = write16(state, IQM_CF_BYPASSDET__A, 0);
3426 status = write16(state, IQM_CF_BYPASSDET__A, 1);
3428 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3432 #define DEFAULT_FR_THRES_8K 4000
3433 static int DVBTCtrlSetFrEnable(struct drxk_state *state, bool *enabled)
3439 if (*enabled == true) {
3440 /* write mask to 1 */
3441 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
3442 DEFAULT_FR_THRES_8K);
3444 /* write mask to 0 */
3445 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
3448 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3453 static int DVBTCtrlSetEchoThreshold(struct drxk_state *state,
3454 struct DRXKCfgDvbtEchoThres_t *echoThres)
3460 status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);
3464 switch (echoThres->fftMode) {
3465 case DRX_FFTMODE_2K:
3466 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M;
3467 data |= ((echoThres->threshold <<
3468 OFDM_SC_RA_RAM_ECHO_THRES_2K__B)
3469 & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M));
3471 case DRX_FFTMODE_8K:
3472 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M;
3473 data |= ((echoThres->threshold <<
3474 OFDM_SC_RA_RAM_ECHO_THRES_8K__B)
3475 & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M));
3481 status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
3484 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3488 static int DVBTCtrlSetSqiSpeed(struct drxk_state *state,
3489 enum DRXKCfgDvbtSqiSpeed *speed)
3491 int status = -EINVAL;
3496 case DRXK_DVBT_SQI_SPEED_FAST:
3497 case DRXK_DVBT_SQI_SPEED_MEDIUM:
3498 case DRXK_DVBT_SQI_SPEED_SLOW:
3503 status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
3507 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3511 /*============================================================================*/
3514 * \brief Activate DVBT specific presets
3515 * \param demod instance of demodulator.
3516 * \return DRXStatus_t.
3518 * Called in DVBTSetStandard
3521 static int DVBTActivatePresets(struct drxk_state *state)
3524 bool setincenable = false;
3525 bool setfrenable = true;
3527 struct DRXKCfgDvbtEchoThres_t echoThres2k = { 0, DRX_FFTMODE_2K };
3528 struct DRXKCfgDvbtEchoThres_t echoThres8k = { 0, DRX_FFTMODE_8K };
3531 status = DVBTCtrlSetIncEnable(state, &setincenable);
3534 status = DVBTCtrlSetFrEnable(state, &setfrenable);
3537 status = DVBTCtrlSetEchoThreshold(state, &echoThres2k);
3540 status = DVBTCtrlSetEchoThreshold(state, &echoThres8k);
3543 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, state->m_dvbtIfAgcCfg.IngainTgtMax);
3546 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3550 /*============================================================================*/
3553 * \brief Initialize channelswitch-independent settings for DVBT.
3554 * \param demod instance of demodulator.
3555 * \return DRXStatus_t.
3557 * For ROM code channel filter taps are loaded from the bootloader. For microcode
3558 * the DVB-T taps from the drxk_filters.h are used.
3560 static int SetDVBTStandard(struct drxk_state *state,
3561 enum OperationMode oMode)
3570 /* added antenna switch */
3571 SwitchAntennaToDVBT(state);
3572 /* send OFDM reset command */
3573 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
3577 /* send OFDM setenv command */
3578 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 0, NULL, 1, &cmdResult);
3582 /* reset datapath for OFDM, processors first */
3583 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3586 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3589 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
3594 /* synchronize on ofdstate->m_festart */
3595 status = write16(state, IQM_AF_UPD_SEL__A, 1);
3598 /* window size for clipping ADC detection */
3599 status = write16(state, IQM_AF_CLP_LEN__A, 0);
3602 /* window size for for sense pre-SAW detection */
3603 status = write16(state, IQM_AF_SNS_LEN__A, 0);
3606 /* sense threshold for sense pre-SAW detection */
3607 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
3610 status = SetIqmAf(state, true);
3614 status = write16(state, IQM_AF_AGC_RF__A, 0);
3618 /* Impulse noise cruncher setup */
3619 status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */
3622 status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */
3625 status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */
3629 status = write16(state, IQM_RC_STRETCH__A, 16);
3632 status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */
3635 status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */
3638 status = write16(state, IQM_CF_SCALE__A, 1600);
3641 status = write16(state, IQM_CF_SCALE_SH__A, 0);
3645 /* virtual clipping threshold for clipping ADC detection */
3646 status = write16(state, IQM_AF_CLP_TH__A, 448);
3649 status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */
3653 status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
3657 status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */
3660 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);
3663 /* enable power measurement interrupt */
3664 status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);
3667 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
3671 /* IQM will not be reset from here, sync ADC and update/init AGC */
3672 status = ADCSynchronization(state);
3675 status = SetPreSaw(state, &state->m_dvbtPreSawCfg);
3679 /* Halt SCU to enable safe non-atomic accesses */
3680 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3684 status = SetAgcRf(state, &state->m_dvbtRfAgcCfg, true);
3687 status = SetAgcIf(state, &state->m_dvbtIfAgcCfg, true);
3691 /* Set Noise Estimation notch width and enable DC fix */
3692 status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);
3695 data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M;
3696 status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);
3700 /* Activate SCU to enable SCU commands */
3701 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3705 if (!state->m_DRXK_A3_ROM_CODE) {
3706 /* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay */
3707 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, state->m_dvbtIfAgcCfg.FastClipCtrlDelay);
3713 #ifdef COMPILE_FOR_NONRT
3714 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
3717 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
3723 status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */
3728 #ifdef COMPILE_FOR_NONRT
3729 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
3733 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);
3737 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);
3741 /* Setup MPEG bus */
3742 status = MPEGTSDtoSetup(state, OM_DVBT);
3745 /* Set DVBT Presets */
3746 status = DVBTActivatePresets(state);
3752 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3756 /*============================================================================*/
3758 * \brief Start dvbt demodulating for channel.
3759 * \param demod instance of demodulator.
3760 * \return DRXStatus_t.
3762 static int DVBTStart(struct drxk_state *state)
3766 /* DRXKOfdmScCmd_t scCmd; */
3769 /* Start correct processes to get in lock */
3770 /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */
3771 param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;
3772 status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1, 0, 0, 0);
3776 status = MPEGTSStart(state);
3779 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
3784 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3789 /*============================================================================*/
3792 * \brief Set up dvbt demodulator for channel.
3793 * \param demod instance of demodulator.
3794 * \return DRXStatus_t.
3795 * // original DVBTSetChannel()
3797 static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3798 s32 tunerFreqOffset)
3801 u16 transmissionParams = 0;
3802 u16 operationMode = 0;
3803 u32 iqmRcRateOfs = 0;
3808 dprintk(1, "IF =%d, TFO = %d\n", IntermediateFreqkHz, tunerFreqOffset);
3810 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
3814 /* Halt SCU to enable safe non-atomic accesses */
3815 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3819 /* Stop processors */
3820 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3823 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3827 /* Mandatory fix, always stop CP, required to set spl offset back to
3828 hardware default (is set to 0 by ucode during pilot detection */
3829 status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
3833 /*== Write channel settings to device =====================================*/
3836 switch (state->props.transmission_mode) {
3837 case TRANSMISSION_MODE_AUTO:
3839 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M;
3840 /* fall through , try first guess DRX_FFTMODE_8K */
3841 case TRANSMISSION_MODE_8K:
3842 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K;
3844 case TRANSMISSION_MODE_2K:
3845 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K;
3850 switch (state->props.guard_interval) {
3852 case GUARD_INTERVAL_AUTO:
3853 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M;
3854 /* fall through , try first guess DRX_GUARD_1DIV4 */
3855 case GUARD_INTERVAL_1_4:
3856 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4;
3858 case GUARD_INTERVAL_1_32:
3859 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32;
3861 case GUARD_INTERVAL_1_16:
3862 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16;
3864 case GUARD_INTERVAL_1_8:
3865 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8;
3870 switch (state->props.hierarchy) {
3871 case HIERARCHY_AUTO:
3872 case HIERARCHY_NONE:
3874 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M;
3875 /* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */
3876 /* transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */
3879 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1;
3882 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2;
3885 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4;
3891 switch (state->props.modulation) {
3894 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M;
3895 /* fall through , try first guess DRX_CONSTELLATION_QAM64 */
3897 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64;
3900 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK;
3903 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16;
3907 /* No hierachical channels support in BDA */
3908 /* Priority (only for hierarchical channels) */
3909 switch (channel->priority) {
3910 case DRX_PRIORITY_LOW:
3911 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO;
3912 WR16(devAddr, OFDM_EC_SB_PRIOR__A,
3913 OFDM_EC_SB_PRIOR_LO);
3915 case DRX_PRIORITY_HIGH:
3916 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3917 WR16(devAddr, OFDM_EC_SB_PRIOR__A,
3918 OFDM_EC_SB_PRIOR_HI));
3920 case DRX_PRIORITY_UNKNOWN: /* fall through */
3926 /* Set Priorty high */
3927 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3928 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
3934 switch (state->props.code_rate_HP) {
3937 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M;
3938 /* fall through , try first guess DRX_CODERATE_2DIV3 */
3940 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3;
3943 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2;
3946 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4;
3949 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6;
3952 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8;
3956 /* SAW filter selection: normaly not necesarry, but if wanted
3957 the application can select a SAW filter via the driver by using UIOs */
3958 /* First determine real bandwidth (Hz) */
3959 /* Also set delay for impulse noise cruncher */
3960 /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed
3961 by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC
3963 switch (state->props.bandwidth_hz) {
3965 state->props.bandwidth_hz = 8000000;
3968 bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ;
3969 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052);
3972 /* cochannel protection for PAL 8 MHz */
3973 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7);
3976 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7);
3979 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7);
3982 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3987 bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ;
3988 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491);
3991 /* cochannel protection for PAL 7 MHz */
3992 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8);
3995 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8);
3998 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4);
4001 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
4006 bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ;
4007 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073);
4010 /* cochannel protection for NTSC 6 MHz */
4011 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19);
4014 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19);
4017 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14);
4020 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
4029 if (iqmRcRateOfs == 0) {
4030 /* Now compute IQM_RC_RATE_OFS
4031 (((SysFreq/BandWidth)/2)/2) -1) * 2^23)
4033 ((SysFreq / BandWidth) * (2^21)) - (2^23)
4035 /* (SysFreq / BandWidth) * (2^28) */
4036 /* assert (MAX(sysClk)/MIN(bandwidth) < 16)
4037 => assert(MAX(sysClk) < 16*MIN(bandwidth))
4038 => assert(109714272 > 48000000) = true so Frac 28 can be used */
4039 iqmRcRateOfs = Frac28a((u32)
4040 ((state->m_sysClockFreq *
4041 1000) / 3), bandwidth);
4042 /* (SysFreq / BandWidth) * (2^21), rounding before truncating */
4043 if ((iqmRcRateOfs & 0x7fL) >= 0x40)
4044 iqmRcRateOfs += 0x80L;
4045 iqmRcRateOfs = iqmRcRateOfs >> 7;
4046 /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */
4047 iqmRcRateOfs = iqmRcRateOfs - (1 << 23);
4051 ((((u32) IQM_RC_RATE_OFS_HI__M) <<
4052 IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M);
4053 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRateOfs);
4057 /* Bandwidth setting done */
4060 status = DVBTSetFrequencyShift(demod, channel, tunerOffset);
4064 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
4068 /*== Start SC, write channel settings to SC ===============================*/
4070 /* Activate SCU to enable SCU commands */
4071 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
4075 /* Enable SC after setting all other parameters */
4076 status = write16(state, OFDM_SC_COMM_STATE__A, 0);
4079 status = write16(state, OFDM_SC_COMM_EXEC__A, 1);
4084 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult);
4088 /* Write SC parameter registers, set all AUTO flags in operation mode */
4089 param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M |
4090 OFDM_SC_RA_RAM_OP_AUTO_GUARD__M |
4091 OFDM_SC_RA_RAM_OP_AUTO_CONST__M |
4092 OFDM_SC_RA_RAM_OP_AUTO_HIER__M |
4093 OFDM_SC_RA_RAM_OP_AUTO_RATE__M);
4094 status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
4095 0, transmissionParams, param1, 0, 0, 0);
4099 if (!state->m_DRXK_A3_ROM_CODE)
4100 status = DVBTCtrlSetSqiSpeed(state, &state->m_sqiSpeed);
4103 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4109 /*============================================================================*/
4112 * \brief Retreive lock status .
4113 * \param demod Pointer to demodulator instance.
4114 * \param lockStat Pointer to lock status structure.
4115 * \return DRXStatus_t.
4118 static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus)
4121 const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M |
4122 OFDM_SC_RA_RAM_LOCK_FEC__M);
4123 const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M);
4124 const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M;
4126 u16 ScRaRamLock = 0;
4131 *pLockStatus = NOT_LOCKED;
4133 /* Check if SC is running */
4134 status = read16(state, OFDM_SC_COMM_EXEC__A, &ScCommExec);
4137 if (ScCommExec == OFDM_SC_COMM_EXEC_STOP)
4140 status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock);
4144 if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask)
4145 *pLockStatus = MPEG_LOCK;
4146 else if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
4147 *pLockStatus = FEC_LOCK;
4148 else if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
4149 *pLockStatus = DEMOD_LOCK;
4150 else if (ScRaRamLock & OFDM_SC_RA_RAM_LOCK_NODVBT__M)
4151 *pLockStatus = NEVER_LOCK;
4154 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4159 static int PowerUpQAM(struct drxk_state *state)
4161 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
4165 status = CtrlPowerMode(state, &powerMode);
4167 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4173 /** Power Down QAM */
4174 static int PowerDownQAM(struct drxk_state *state)
4181 status = read16(state, SCU_COMM_EXEC__A, &data);
4184 if (data == SCU_COMM_EXEC_ACTIVE) {
4189 /* stop all comstate->m_exec */
4190 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
4193 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
4198 status = SetIqmAf(state, false);
4202 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4207 /*============================================================================*/
4210 * \brief Setup of the QAM Measurement intervals for signal quality
4211 * \param demod instance of demod.
4212 * \param modulation current modulation.
4213 * \return DRXStatus_t.
4216 * Take into account that for certain settings the errorcounters can overflow.
4217 * The implementation does not check this.
4220 static int SetQAMMeasurement(struct drxk_state *state,
4221 enum EDrxkConstellation modulation,
4224 u32 fecBitsDesired = 0; /* BER accounting period */
4225 u32 fecRsPeriodTotal = 0; /* Total period */
4226 u16 fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */
4227 u16 fecRsPeriod = 0; /* Value for corresponding I2C register */
4233 /* fecBitsDesired = symbolRate [kHz] *
4239 switch (modulation) {
4240 case DRX_CONSTELLATION_QAM16:
4241 fecBitsDesired = 4 * symbolRate;
4243 case DRX_CONSTELLATION_QAM32:
4244 fecBitsDesired = 5 * symbolRate;
4246 case DRX_CONSTELLATION_QAM64:
4247 fecBitsDesired = 6 * symbolRate;
4249 case DRX_CONSTELLATION_QAM128:
4250 fecBitsDesired = 7 * symbolRate;
4252 case DRX_CONSTELLATION_QAM256:
4253 fecBitsDesired = 8 * symbolRate;
4261 fecBitsDesired /= 1000; /* symbolRate [Hz] -> symbolRate [kHz] */
4262 fecBitsDesired *= 500; /* meas. period [ms] */
4264 /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */
4265 /* fecRsPeriodTotal = fecBitsDesired / 1632 */
4266 fecRsPeriodTotal = (fecBitsDesired / 1632UL) + 1; /* roughly ceil */
4268 /* fecRsPeriodTotal = fecRsPrescale * fecRsPeriod */
4269 fecRsPrescale = 1 + (u16) (fecRsPeriodTotal >> 16);
4270 if (fecRsPrescale == 0) {
4271 /* Divide by zero (though impossible) */
4277 ((u16) fecRsPeriodTotal +
4278 (fecRsPrescale >> 1)) / fecRsPrescale;
4280 /* write corresponding registers */
4281 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod);
4284 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale);
4287 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod);
4290 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4294 static int SetQAM16(struct drxk_state *state)
4299 /* QAM Equalizer Setup */
4301 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);
4304 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);
4307 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);
4310 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);
4313 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);
4316 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);
4319 /* Decision Feedback Equalizer */
4320 status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);
4323 status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);
4326 status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);
4329 status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);
4332 status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);
4335 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4339 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4342 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4345 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4349 /* QAM Slicer Settings */
4350 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16);
4354 /* QAM Loop Controller Coeficients */
4355 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4358 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4361 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4364 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4367 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4370 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4373 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4376 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4380 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4383 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4386 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4389 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4392 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4395 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4398 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4401 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4404 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);
4407 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4410 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4413 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4418 /* QAM State Machine (FSM) Thresholds */
4420 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);
4423 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4426 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);
4429 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);
4432 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);
4435 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);
4439 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4442 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4445 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);
4450 /* QAM FSM Tracking Parameters */
4452 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);
4455 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);
4458 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);
4461 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);
4464 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);
4467 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);
4470 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);
4476 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4480 /*============================================================================*/
4483 * \brief QAM32 specific setup
4484 * \param demod instance of demod.
4485 * \return DRXStatus_t.
4487 static int SetQAM32(struct drxk_state *state)
4493 /* QAM Equalizer Setup */
4495 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
4498 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
4501 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
4504 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
4507 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
4510 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
4514 /* Decision Feedback Equalizer */
4515 status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);
4518 status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);
4521 status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);
4524 status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);
4527 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4530 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4534 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4537 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4540 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4544 /* QAM Slicer Settings */
4546 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32);
4551 /* QAM Loop Controller Coeficients */
4553 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4556 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4559 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4562 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4565 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4568 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4571 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4574 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4578 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4581 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4584 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4587 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4590 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4593 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4596 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4599 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4602 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
4605 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4608 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4611 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4616 /* QAM State Machine (FSM) Thresholds */
4618 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);
4621 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4624 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4627 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4630 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);
4633 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4637 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4640 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4643 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);
4648 /* QAM FSM Tracking Parameters */
4650 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4653 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
4656 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
4659 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
4662 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
4665 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
4668 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
4671 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4675 /*============================================================================*/
4678 * \brief QAM64 specific setup
4679 * \param demod instance of demod.
4680 * \return DRXStatus_t.
4682 static int SetQAM64(struct drxk_state *state)
4687 /* QAM Equalizer Setup */
4689 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);
4692 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);
4695 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);
4698 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);
4701 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);
4704 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);
4708 /* Decision Feedback Equalizer */
4709 status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);
4712 status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);
4715 status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);
4718 status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);
4721 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4724 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4728 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4731 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4734 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4738 /* QAM Slicer Settings */
4739 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64);
4744 /* QAM Loop Controller Coeficients */
4746 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4749 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4752 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4755 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4758 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4761 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4764 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4767 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4771 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4774 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);
4777 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);
4780 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4783 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);
4786 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4789 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4792 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4795 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
4798 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4801 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4804 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4809 /* QAM State Machine (FSM) Thresholds */
4811 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);
4814 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4817 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4820 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);
4823 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);
4826 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);
4830 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4833 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4836 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);
4841 /* QAM FSM Tracking Parameters */
4843 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4846 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);
4849 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);
4852 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);
4855 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);
4858 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);
4861 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);
4864 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4869 /*============================================================================*/
4872 * \brief QAM128 specific setup
4873 * \param demod: instance of demod.
4874 * \return DRXStatus_t.
4876 static int SetQAM128(struct drxk_state *state)
4881 /* QAM Equalizer Setup */
4883 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);
4886 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);
4889 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);
4892 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);
4895 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);
4898 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);
4902 /* Decision Feedback Equalizer */
4903 status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);
4906 status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);
4909 status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);
4912 status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);
4915 status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);
4918 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4922 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4925 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4928 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4933 /* QAM Slicer Settings */
4935 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM128);
4940 /* QAM Loop Controller Coeficients */
4942 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4945 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4948 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4951 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4954 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4957 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4960 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4963 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4967 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4970 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);
4973 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);
4976 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4979 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);
4982 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);
4985 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4988 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4991 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);
4994 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4997 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
5000 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
5005 /* QAM State Machine (FSM) Thresholds */
5007 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
5010 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5013 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5016 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5019 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);
5022 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
5026 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5029 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);
5033 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5037 /* QAM FSM Tracking Parameters */
5039 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5042 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);
5045 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);
5048 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);
5051 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);
5054 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);
5057 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);
5060 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5065 /*============================================================================*/
5068 * \brief QAM256 specific setup
5069 * \param demod: instance of demod.
5070 * \return DRXStatus_t.
5072 static int SetQAM256(struct drxk_state *state)
5077 /* QAM Equalizer Setup */
5079 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);
5082 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);
5085 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);
5088 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);
5091 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);
5094 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);
5098 /* Decision Feedback Equalizer */
5099 status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);
5102 status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);
5105 status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);
5108 status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);
5111 status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);
5114 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
5118 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
5121 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
5124 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
5128 /* QAM Slicer Settings */
5130 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM256);
5135 /* QAM Loop Controller Coeficients */
5137 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
5140 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
5143 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
5146 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
5149 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
5152 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
5155 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
5158 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
5162 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
5165 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);
5168 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);
5171 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
5174 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);
5177 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);
5180 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
5183 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
5186 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
5189 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
5192 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
5195 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
5200 /* QAM State Machine (FSM) Thresholds */
5202 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
5205 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5208 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5211 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5214 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);
5217 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);
5221 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5224 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
5227 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5232 /* QAM FSM Tracking Parameters */
5234 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5237 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
5240 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
5243 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
5246 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
5249 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
5252 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
5255 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5260 /*============================================================================*/
5262 * \brief Reset QAM block.
5263 * \param demod: instance of demod.
5264 * \param channel: pointer to channel data.
5265 * \return DRXStatus_t.
5267 static int QAMResetQAM(struct drxk_state *state)
5273 /* Stop QAM comstate->m_exec */
5274 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
5278 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
5281 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5285 /*============================================================================*/
5288 * \brief Set QAM symbolrate.
5289 * \param demod: instance of demod.
5290 * \param channel: pointer to channel data.
5291 * \return DRXStatus_t.
5293 static int QAMSetSymbolrate(struct drxk_state *state)
5295 u32 adcFrequency = 0;
5303 /* Select & calculate correct IQM rate */
5304 adcFrequency = (state->m_sysClockFreq * 1000) / 3;
5306 /* printk(KERN_DEBUG "drxk: SR %d\n", state->props.symbol_rate); */
5307 if (state->props.symbol_rate <= 1188750)
5309 else if (state->props.symbol_rate <= 2377500)
5311 else if (state->props.symbol_rate <= 4755000)
5313 status = write16(state, IQM_FD_RATESEL__A, ratesel);
5318 IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23)
5320 symbFreq = state->props.symbol_rate * (1 << ratesel);
5321 if (symbFreq == 0) {
5322 /* Divide by zero */
5326 iqmRcRate = (adcFrequency / symbFreq) * (1 << 21) +
5327 (Frac28a((adcFrequency % symbFreq), symbFreq) >> 7) -
5329 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate);
5332 state->m_iqmRcRate = iqmRcRate;
5334 LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15))
5336 symbFreq = state->props.symbol_rate;
5337 if (adcFrequency == 0) {
5338 /* Divide by zero */
5342 lcSymbRate = (symbFreq / adcFrequency) * (1 << 12) +
5343 (Frac28a((symbFreq % adcFrequency), adcFrequency) >>
5345 if (lcSymbRate > 511)
5347 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate);
5351 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5355 /*============================================================================*/
5358 * \brief Get QAM lock status.
5359 * \param demod: instance of demod.
5360 * \param channel: pointer to channel data.
5361 * \return DRXStatus_t.
5364 static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus)
5367 u16 Result[2] = { 0, 0 };
5370 *pLockStatus = NOT_LOCKED;
5371 status = scu_command(state,
5372 SCU_RAM_COMMAND_STANDARD_QAM |
5373 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2,
5376 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5378 if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) {
5379 /* 0x0000 NOT LOCKED */
5380 } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) {
5381 /* 0x4000 DEMOD LOCKED */
5382 *pLockStatus = DEMOD_LOCK;
5383 } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) {
5384 /* 0x8000 DEMOD + FEC LOCKED (system lock) */
5385 *pLockStatus = MPEG_LOCK;
5387 /* 0xC000 NEVER LOCKED */
5388 /* (system will never be able to lock to the signal) */
5389 /* TODO: check this, intermediate & standard specific lock states are not
5390 taken into account here */
5391 *pLockStatus = NEVER_LOCK;
5396 #define QAM_MIRROR__M 0x03
5397 #define QAM_MIRROR_NORMAL 0x00
5398 #define QAM_MIRRORED 0x01
5399 #define QAM_MIRROR_AUTO_ON 0x02
5400 #define QAM_LOCKRANGE__M 0x10
5401 #define QAM_LOCKRANGE_NORMAL 0x10
5403 static int QAMDemodulatorCommand(struct drxk_state *state,
5404 int numberOfParameters)
5408 u16 setParamParameters[4] = { 0, 0, 0, 0 };
5410 setParamParameters[0] = state->m_Constellation; /* modulation */
5411 setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */
5413 if (numberOfParameters == 2) {
5414 u16 setEnvParameters[1] = { 0 };
5416 if (state->m_OperationMode == OM_QAM_ITU_C)
5417 setEnvParameters[0] = QAM_TOP_ANNEX_C;
5419 setEnvParameters[0] = QAM_TOP_ANNEX_A;
5421 status = scu_command(state,
5422 SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,
5423 1, setEnvParameters, 1, &cmdResult);
5427 status = scu_command(state,
5428 SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
5429 numberOfParameters, setParamParameters,
5431 } else if (numberOfParameters == 4) {
5432 if (state->m_OperationMode == OM_QAM_ITU_C)
5433 setParamParameters[2] = QAM_TOP_ANNEX_C;
5435 setParamParameters[2] = QAM_TOP_ANNEX_A;
5437 setParamParameters[3] |= (QAM_MIRROR_AUTO_ON);
5438 /* Env parameters */
5439 /* check for LOCKRANGE Extented */
5440 /* setParamParameters[3] |= QAM_LOCKRANGE_NORMAL; */
5442 status = scu_command(state,
5443 SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
5444 numberOfParameters, setParamParameters,
5447 printk(KERN_WARNING "drxk: Unknown QAM demodulator parameter "
5448 "count %d\n", numberOfParameters);
5454 printk(KERN_WARNING "drxk: Warning %d on %s\n",
5459 static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5460 s32 tunerFreqOffset)
5464 int qamDemodParamCount = state->qam_demod_parameter_count;
5468 * STEP 1: reset demodulator
5469 * resets FEC DI and FEC RS
5471 * resets SCU variables
5473 status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
5476 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
5479 status = QAMResetQAM(state);
5484 * STEP 2: configure demodulator
5485 * -set params; resets IQM,QAM,FEC HW; initializes some
5488 status = QAMSetSymbolrate(state);
5493 switch (state->props.modulation) {
5495 state->m_Constellation = DRX_CONSTELLATION_QAM256;
5499 state->m_Constellation = DRX_CONSTELLATION_QAM64;
5502 state->m_Constellation = DRX_CONSTELLATION_QAM16;
5505 state->m_Constellation = DRX_CONSTELLATION_QAM32;
5508 state->m_Constellation = DRX_CONSTELLATION_QAM128;
5517 /* Use the 4-parameter if it's requested or we're probing for
5518 * the correct command. */
5519 if (state->qam_demod_parameter_count == 4
5520 || !state->qam_demod_parameter_count) {
5521 qamDemodParamCount = 4;
5522 status = QAMDemodulatorCommand(state, qamDemodParamCount);
5525 /* Use the 2-parameter command if it was requested or if we're
5526 * probing for the correct command and the 4-parameter command
5528 if (state->qam_demod_parameter_count == 2
5529 || (!state->qam_demod_parameter_count && status < 0)) {
5530 qamDemodParamCount = 2;
5531 status = QAMDemodulatorCommand(state, qamDemodParamCount);
5535 dprintk(1, "Could not set demodulator parameters. Make "
5536 "sure qam_demod_parameter_count (%d) is correct for "
5537 "your firmware (%s).\n",
5538 state->qam_demod_parameter_count,
5539 state->microcode_name);
5541 } else if (!state->qam_demod_parameter_count) {
5542 dprintk(1, "Auto-probing the correct QAM demodulator command "
5543 "parameters was successful - using %d parameters.\n",
5544 qamDemodParamCount);
5547 * One of our commands was successful. We don't need to
5548 * auto-probe anymore, now that we got the correct command.
5550 state->qam_demod_parameter_count = qamDemodParamCount;
5554 * STEP 3: enable the system in a mode where the ADC provides valid
5555 * signal setup modulation independent registers
5558 status = SetFrequency(channel, tunerFreqOffset));
5562 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
5566 /* Setup BER measurement */
5567 status = SetQAMMeasurement(state, state->m_Constellation, state->props.symbol_rate);
5571 /* Reset default values */
5572 status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
5575 status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
5579 /* Reset default LC values */
5580 status = write16(state, QAM_LC_RATE_LIMIT__A, 3);
5583 status = write16(state, QAM_LC_LPF_FACTORP__A, 4);
5586 status = write16(state, QAM_LC_LPF_FACTORI__A, 4);
5589 status = write16(state, QAM_LC_MODE__A, 7);
5593 status = write16(state, QAM_LC_QUAL_TAB0__A, 1);
5596 status = write16(state, QAM_LC_QUAL_TAB1__A, 1);
5599 status = write16(state, QAM_LC_QUAL_TAB2__A, 1);
5602 status = write16(state, QAM_LC_QUAL_TAB3__A, 1);
5605 status = write16(state, QAM_LC_QUAL_TAB4__A, 2);
5608 status = write16(state, QAM_LC_QUAL_TAB5__A, 2);
5611 status = write16(state, QAM_LC_QUAL_TAB6__A, 2);
5614 status = write16(state, QAM_LC_QUAL_TAB8__A, 2);
5617 status = write16(state, QAM_LC_QUAL_TAB9__A, 2);
5620 status = write16(state, QAM_LC_QUAL_TAB10__A, 2);
5623 status = write16(state, QAM_LC_QUAL_TAB12__A, 2);
5626 status = write16(state, QAM_LC_QUAL_TAB15__A, 3);
5629 status = write16(state, QAM_LC_QUAL_TAB16__A, 3);
5632 status = write16(state, QAM_LC_QUAL_TAB20__A, 4);
5635 status = write16(state, QAM_LC_QUAL_TAB25__A, 4);
5639 /* Mirroring, QAM-block starting point not inverted */
5640 status = write16(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS);
5644 /* Halt SCU to enable safe non-atomic accesses */
5645 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5649 /* STEP 4: modulation specific setup */
5650 switch (state->props.modulation) {
5652 status = SetQAM16(state);
5655 status = SetQAM32(state);
5659 status = SetQAM64(state);
5662 status = SetQAM128(state);
5665 status = SetQAM256(state);
5674 /* Activate SCU to enable SCU commands */
5675 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5679 /* Re-configure MPEG output, requires knowledge of channel bitrate */
5680 /* extAttr->currentChannel.modulation = channel->modulation; */
5681 /* extAttr->currentChannel.symbolrate = channel->symbolrate; */
5682 status = MPEGTSDtoSetup(state, state->m_OperationMode);
5686 /* Start processes */
5687 status = MPEGTSStart(state);
5690 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
5693 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
5696 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
5700 /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
5701 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult);
5705 /* update global DRXK data container */
5706 /*? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */
5710 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5714 static int SetQAMStandard(struct drxk_state *state,
5715 enum OperationMode oMode)
5718 #ifdef DRXK_QAM_TAPS
5719 #define DRXK_QAMA_TAPS_SELECT
5720 #include "drxk_filters.h"
5721 #undef DRXK_QAMA_TAPS_SELECT
5726 /* added antenna switch */
5727 SwitchAntennaToQAM(state);
5729 /* Ensure correct power-up mode */
5730 status = PowerUpQAM(state);
5733 /* Reset QAM block */
5734 status = QAMResetQAM(state);
5740 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
5743 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
5747 /* Upload IQM Channel Filter settings by
5748 boot loader from ROM table */
5751 status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5754 status = BLDirectCmd(state, IQM_CF_TAP_RE0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5757 status = BLDirectCmd(state, IQM_CF_TAP_IM0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5765 status = write16(state, IQM_CF_OUT_ENA__A, (1 << IQM_CF_OUT_ENA_QAM__B));
5768 status = write16(state, IQM_CF_SYMMETRIC__A, 0);
5771 status = write16(state, IQM_CF_MIDTAP__A, ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B)));
5775 status = write16(state, IQM_RC_STRETCH__A, 21);
5778 status = write16(state, IQM_AF_CLP_LEN__A, 0);
5781 status = write16(state, IQM_AF_CLP_TH__A, 448);
5784 status = write16(state, IQM_AF_SNS_LEN__A, 0);
5787 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);
5791 status = write16(state, IQM_FS_ADJ_SEL__A, 1);
5794 status = write16(state, IQM_RC_ADJ_SEL__A, 1);
5797 status = write16(state, IQM_CF_ADJ_SEL__A, 1);
5800 status = write16(state, IQM_AF_UPD_SEL__A, 0);
5804 /* IQM Impulse Noise Processing Unit */
5805 status = write16(state, IQM_CF_CLP_VAL__A, 500);
5808 status = write16(state, IQM_CF_DATATH__A, 1000);
5811 status = write16(state, IQM_CF_BYPASSDET__A, 1);
5814 status = write16(state, IQM_CF_DET_LCT__A, 0);
5817 status = write16(state, IQM_CF_WND_LEN__A, 1);
5820 status = write16(state, IQM_CF_PKDTH__A, 1);
5823 status = write16(state, IQM_AF_INC_BYPASS__A, 1);
5827 /* turn on IQMAF. Must be done before setAgc**() */
5828 status = SetIqmAf(state, true);
5831 status = write16(state, IQM_AF_START_LOCK__A, 0x01);
5835 /* IQM will not be reset from here, sync ADC and update/init AGC */
5836 status = ADCSynchronization(state);
5840 /* Set the FSM step period */
5841 status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);
5845 /* Halt SCU to enable safe non-atomic accesses */
5846 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5850 /* No more resets of the IQM, current standard correctly set =>
5851 now AGCs can be configured. */
5853 status = InitAGC(state, true);
5856 status = SetPreSaw(state, &(state->m_qamPreSawCfg));
5860 /* Configure AGC's */
5861 status = SetAgcRf(state, &(state->m_qamRfAgcCfg), true);
5864 status = SetAgcIf(state, &(state->m_qamIfAgcCfg), true);
5868 /* Activate SCU to enable SCU commands */
5869 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5872 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5876 static int WriteGPIO(struct drxk_state *state)
5882 /* stop lock indicator process */
5883 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
5887 /* Write magic word to enable pdr reg write */
5888 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
5892 if (state->m_hasSAWSW) {
5893 if (state->UIO_mask & 0x0001) { /* UIO-1 */
5894 /* write to io pad configuration register - output mode */
5895 status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg);
5899 /* use corresponding bit in io data output registar */
5900 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5903 if ((state->m_GPIO & 0x0001) == 0)
5904 value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */
5906 value |= 0x8000; /* write one to 15th bit - 1st UIO */
5907 /* write back to io data output register */
5908 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5912 if (state->UIO_mask & 0x0002) { /* UIO-2 */
5913 /* write to io pad configuration register - output mode */
5914 status = write16(state, SIO_PDR_SMA_RX_CFG__A, state->m_GPIOCfg);
5918 /* use corresponding bit in io data output registar */
5919 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5922 if ((state->m_GPIO & 0x0002) == 0)
5923 value &= 0xBFFF; /* write zero to 14th bit - 2st UIO */
5925 value |= 0x4000; /* write one to 14th bit - 2st UIO */
5926 /* write back to io data output register */
5927 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5931 if (state->UIO_mask & 0x0004) { /* UIO-3 */
5932 /* write to io pad configuration register - output mode */
5933 status = write16(state, SIO_PDR_GPIO_CFG__A, state->m_GPIOCfg);
5937 /* use corresponding bit in io data output registar */
5938 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5941 if ((state->m_GPIO & 0x0004) == 0)
5942 value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */
5944 value |= 0x0004; /* write one to 2nd bit - 3rd UIO */
5945 /* write back to io data output register */
5946 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5951 /* Write magic word to disable pdr reg write */
5952 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
5955 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5959 static int SwitchAntennaToQAM(struct drxk_state *state)
5966 if (!state->antenna_gpio)
5969 gpio_state = state->m_GPIO & state->antenna_gpio;
5971 if (state->antenna_dvbt ^ gpio_state) {
5972 /* Antenna is on DVB-T mode. Switch */
5973 if (state->antenna_dvbt)
5974 state->m_GPIO &= ~state->antenna_gpio;
5976 state->m_GPIO |= state->antenna_gpio;
5977 status = WriteGPIO(state);
5980 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5984 static int SwitchAntennaToDVBT(struct drxk_state *state)
5991 if (!state->antenna_gpio)
5994 gpio_state = state->m_GPIO & state->antenna_gpio;
5996 if (!(state->antenna_dvbt ^ gpio_state)) {
5997 /* Antenna is on DVB-C mode. Switch */
5998 if (state->antenna_dvbt)
5999 state->m_GPIO |= state->antenna_gpio;
6001 state->m_GPIO &= ~state->antenna_gpio;
6002 status = WriteGPIO(state);
6005 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
6010 static int PowerDownDevice(struct drxk_state *state)
6012 /* Power down to requested mode */
6013 /* Backup some register settings */
6014 /* Set pins with possible pull-ups connected to them in input mode */
6015 /* Analog power down */
6016 /* ADC power down */
6017 /* Power down device */
6021 if (state->m_bPDownOpenBridge) {
6022 /* Open I2C bridge before power down of DRXK */
6023 status = ConfigureI2CBridge(state, true);
6028 status = DVBTEnableOFDMTokenRing(state, false);
6032 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK);
6035 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6038 state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
6039 status = HI_CfgCommand(state);
6042 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
6047 static int init_drxk(struct drxk_state *state)
6049 int status = 0, n = 0;
6050 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
6054 if ((state->m_DrxkState == DRXK_UNINITIALIZED)) {
6055 drxk_i2c_lock(state);
6056 status = PowerUpDevice(state);
6059 status = DRXX_Open(state);
6062 /* Soft reset of OFDM-, sys- and osc-clockdomain */
6063 status = write16(state, SIO_CC_SOFT_RST__A, SIO_CC_SOFT_RST_OFDM__M | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M);
6066 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6069 /* TODO is this needed, if yes how much delay in worst case scenario */
6071 state->m_DRXK_A3_PATCH_CODE = true;
6072 status = GetDeviceCapabilities(state);
6076 /* Bridge delay, uses oscilator clock */
6077 /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */
6078 /* SDA brdige delay */
6079 state->m_HICfgBridgeDelay =
6080 (u16) ((state->m_oscClockFreq / 1000) *
6081 HI_I2C_BRIDGE_DELAY) / 1000;
6083 if (state->m_HICfgBridgeDelay >
6084 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) {
6085 state->m_HICfgBridgeDelay =
6086 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
6088 /* SCL bridge delay, same as SDA for now */
6089 state->m_HICfgBridgeDelay +=
6090 state->m_HICfgBridgeDelay <<
6091 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B;
6093 status = InitHI(state);
6096 /* disable various processes */
6098 if (!(state->m_DRXK_A1_ROM_CODE)
6099 && !(state->m_DRXK_A2_ROM_CODE))
6102 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
6107 /* disable MPEG port */
6108 status = MPEGTSDisable(state);
6112 /* Stop AUD and SCU */
6113 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
6116 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
6120 /* enable token-ring bus through OFDM block for possible ucode upload */
6121 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON);
6125 /* include boot loader section */
6126 status = write16(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE);
6129 status = BLChainCmd(state, 0, 6, 100);
6134 status = DownloadMicrocode(state, state->fw->data,
6140 /* disable token-ring bus through OFDM block for possible ucode upload */
6141 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF);
6145 /* Run SCU for a little while to initialize microcode version numbers */
6146 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
6149 status = DRXX_Open(state);
6152 /* added for test */
6155 powerMode = DRXK_POWER_DOWN_OFDM;
6156 status = CtrlPowerMode(state, &powerMode);
6160 /* Stamp driver version number in SCU data RAM in BCD code
6161 Done to enable field application engineers to retreive drxdriver version
6162 via I2C from SCU RAM.
6163 Not using SCU command interface for SCU register access since no
6164 microcode may be present.
6167 (((DRXK_VERSION_MAJOR / 100) % 10) << 12) +
6168 (((DRXK_VERSION_MAJOR / 10) % 10) << 8) +
6169 ((DRXK_VERSION_MAJOR % 10) << 4) +
6170 (DRXK_VERSION_MINOR % 10);
6171 status = write16(state, SCU_RAM_DRIVER_VER_HI__A, driverVersion);
6175 (((DRXK_VERSION_PATCH / 1000) % 10) << 12) +
6176 (((DRXK_VERSION_PATCH / 100) % 10) << 8) +
6177 (((DRXK_VERSION_PATCH / 10) % 10) << 4) +
6178 (DRXK_VERSION_PATCH % 10);
6179 status = write16(state, SCU_RAM_DRIVER_VER_LO__A, driverVersion);
6183 printk(KERN_INFO "DRXK driver version %d.%d.%d\n",
6184 DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR,
6185 DRXK_VERSION_PATCH);
6187 /* Dirty fix of default values for ROM/PATCH microcode
6188 Dirty because this fix makes it impossible to setup suitable values
6189 before calling DRX_Open. This solution requires changes to RF AGC speed
6190 to be done via the CTRL function after calling DRX_Open */
6192 /* m_dvbtRfAgcCfg.speed = 3; */
6194 /* Reset driver debug flags to 0 */
6195 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);
6200 NOTE: No more full FEC resets allowed afterwards!! */
6201 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
6204 /* MPEGTS functions are still the same */
6205 status = MPEGTSDtoInit(state);
6208 status = MPEGTSStop(state);
6211 status = MPEGTSConfigurePolarity(state);
6214 status = MPEGTSConfigurePins(state, state->m_enableMPEGOutput);
6217 /* added: configure GPIO */
6218 status = WriteGPIO(state);
6222 state->m_DrxkState = DRXK_STOPPED;
6224 if (state->m_bPowerDown) {
6225 status = PowerDownDevice(state);
6228 state->m_DrxkState = DRXK_POWERED_DOWN;
6230 state->m_DrxkState = DRXK_STOPPED;
6232 /* Initialize the supported delivery systems */
6234 if (state->m_hasDVBC) {
6235 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A;
6236 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C;
6237 strlcat(state->frontend.ops.info.name, " DVB-C",
6238 sizeof(state->frontend.ops.info.name));
6240 if (state->m_hasDVBT) {
6241 state->frontend.ops.delsys[n++] = SYS_DVBT;
6242 strlcat(state->frontend.ops.info.name, " DVB-T",
6243 sizeof(state->frontend.ops.info.name));
6245 drxk_i2c_unlock(state);
6249 state->m_DrxkState = DRXK_NO_DEV;
6250 drxk_i2c_unlock(state);
6251 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
6257 static void load_firmware_cb(const struct firmware *fw,
6260 struct drxk_state *state = context;
6262 dprintk(1, ": %s\n", fw ? "firmware loaded" : "firmware not loaded");
6265 "drxk: Could not load firmware file %s.\n",
6266 state->microcode_name);
6268 "drxk: Copy %s to your hotplug directory!\n",
6269 state->microcode_name);
6270 state->microcode_name = NULL;
6273 * As firmware is now load asynchronous, it is not possible
6274 * anymore to fail at frontend attach. We might silently
6275 * return here, and hope that the driver won't crash.
6276 * We might also change all DVB callbacks to return -ENODEV
6277 * if the device is not initialized.
6278 * As the DRX-K devices have their own internal firmware,
6279 * let's just hope that it will match a firmware revision
6280 * compatible with this driver and proceed.
6288 static void drxk_release(struct dvb_frontend *fe)
6290 struct drxk_state *state = fe->demodulator_priv;
6294 release_firmware(state->fw);
6299 static int drxk_sleep(struct dvb_frontend *fe)
6301 struct drxk_state *state = fe->demodulator_priv;
6305 if (state->m_DrxkState == DRXK_NO_DEV)
6307 if (state->m_DrxkState == DRXK_UNINITIALIZED)
6314 static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
6316 struct drxk_state *state = fe->demodulator_priv;
6318 dprintk(1, ": %s\n", enable ? "enable" : "disable");
6320 if (state->m_DrxkState == DRXK_NO_DEV)
6323 return ConfigureI2CBridge(state, enable ? true : false);
6326 static int drxk_set_parameters(struct dvb_frontend *fe)
6328 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6329 u32 delsys = p->delivery_system, old_delsys;
6330 struct drxk_state *state = fe->demodulator_priv;
6335 if (state->m_DrxkState == DRXK_NO_DEV)
6338 if (state->m_DrxkState == DRXK_UNINITIALIZED)
6341 if (!fe->ops.tuner_ops.get_if_frequency) {
6343 "drxk: Error: get_if_frequency() not defined at tuner. Can't work without it!\n");
6347 if (fe->ops.i2c_gate_ctrl)
6348 fe->ops.i2c_gate_ctrl(fe, 1);
6349 if (fe->ops.tuner_ops.set_params)
6350 fe->ops.tuner_ops.set_params(fe);
6351 if (fe->ops.i2c_gate_ctrl)
6352 fe->ops.i2c_gate_ctrl(fe, 0);
6354 old_delsys = state->props.delivery_system;
6357 if (old_delsys != delsys) {
6360 case SYS_DVBC_ANNEX_A:
6361 case SYS_DVBC_ANNEX_C:
6362 if (!state->m_hasDVBC)
6364 state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ? true : false;
6365 if (state->m_itut_annex_c)
6366 SetOperationMode(state, OM_QAM_ITU_C);
6368 SetOperationMode(state, OM_QAM_ITU_A);
6371 if (!state->m_hasDVBT)
6373 SetOperationMode(state, OM_DVBT);
6380 fe->ops.tuner_ops.get_if_frequency(fe, &IF);
6381 Start(state, 0, IF);
6383 /* printk(KERN_DEBUG "drxk: %s IF=%d done\n", __func__, IF); */
6388 static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status)
6390 struct drxk_state *state = fe->demodulator_priv;
6395 if (state->m_DrxkState == DRXK_NO_DEV)
6397 if (state->m_DrxkState == DRXK_UNINITIALIZED)
6401 GetLockStatus(state, &stat, 0);
6402 if (stat == MPEG_LOCK)
6404 if (stat == FEC_LOCK)
6406 if (stat == DEMOD_LOCK)
6411 static int drxk_read_ber(struct dvb_frontend *fe, u32 *ber)
6413 struct drxk_state *state = fe->demodulator_priv;
6417 if (state->m_DrxkState == DRXK_NO_DEV)
6419 if (state->m_DrxkState == DRXK_UNINITIALIZED)
6426 static int drxk_read_signal_strength(struct dvb_frontend *fe,
6429 struct drxk_state *state = fe->demodulator_priv;
6434 if (state->m_DrxkState == DRXK_NO_DEV)
6436 if (state->m_DrxkState == DRXK_UNINITIALIZED)
6439 ReadIFAgc(state, &val);
6440 *strength = val & 0xffff;
6444 static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr)
6446 struct drxk_state *state = fe->demodulator_priv;
6451 if (state->m_DrxkState == DRXK_NO_DEV)
6453 if (state->m_DrxkState == DRXK_UNINITIALIZED)
6456 GetSignalToNoise(state, &snr2);
6457 *snr = snr2 & 0xffff;
6461 static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
6463 struct drxk_state *state = fe->demodulator_priv;
6468 if (state->m_DrxkState == DRXK_NO_DEV)
6470 if (state->m_DrxkState == DRXK_UNINITIALIZED)
6473 DVBTQAMGetAccPktErr(state, &err);
6474 *ucblocks = (u32) err;
6478 static int drxk_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings
6481 struct drxk_state *state = fe->demodulator_priv;
6482 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6486 if (state->m_DrxkState == DRXK_NO_DEV)
6488 if (state->m_DrxkState == DRXK_UNINITIALIZED)
6491 switch (p->delivery_system) {
6492 case SYS_DVBC_ANNEX_A:
6493 case SYS_DVBC_ANNEX_C:
6495 sets->min_delay_ms = 3000;
6496 sets->max_drift = 0;
6497 sets->step_size = 0;
6504 static struct dvb_frontend_ops drxk_ops = {
6505 /* .delsys will be filled dynamically */
6508 .frequency_min = 47000000,
6509 .frequency_max = 865000000,
6511 .symbol_rate_min = 870000,
6512 .symbol_rate_max = 11700000,
6514 .frequency_stepsize = 166667,
6516 .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
6517 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO |
6518 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
6519 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_MUTE_TS |
6520 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
6521 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO
6524 .release = drxk_release,
6525 .sleep = drxk_sleep,
6526 .i2c_gate_ctrl = drxk_gate_ctrl,
6528 .set_frontend = drxk_set_parameters,
6529 .get_tune_settings = drxk_get_tune_settings,
6531 .read_status = drxk_read_status,
6532 .read_ber = drxk_read_ber,
6533 .read_signal_strength = drxk_read_signal_strength,
6534 .read_snr = drxk_read_snr,
6535 .read_ucblocks = drxk_read_ucblocks,
6538 struct dvb_frontend *drxk_attach(const struct drxk_config *config,
6539 struct i2c_adapter *i2c)
6541 struct drxk_state *state = NULL;
6542 u8 adr = config->adr;
6546 state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL);
6551 state->demod_address = adr;
6552 state->single_master = config->single_master;
6553 state->microcode_name = config->microcode_name;
6554 state->qam_demod_parameter_count = config->qam_demod_parameter_count;
6555 state->no_i2c_bridge = config->no_i2c_bridge;
6556 state->antenna_gpio = config->antenna_gpio;
6557 state->antenna_dvbt = config->antenna_dvbt;
6558 state->m_ChunkSize = config->chunk_size;
6559 state->enable_merr_cfg = config->enable_merr_cfg;
6561 if (config->dynamic_clk) {
6562 state->m_DVBTStaticCLK = 0;
6563 state->m_DVBCStaticCLK = 0;
6565 state->m_DVBTStaticCLK = 1;
6566 state->m_DVBCStaticCLK = 1;
6570 if (config->mpeg_out_clk_strength)
6571 state->m_TSClockkStrength = config->mpeg_out_clk_strength & 0x07;
6573 state->m_TSClockkStrength = 0x06;
6575 if (config->parallel_ts)
6576 state->m_enableParallel = true;
6578 state->m_enableParallel = false;
6580 /* NOTE: as more UIO bits will be used, add them to the mask */
6581 state->UIO_mask = config->antenna_gpio;
6583 /* Default gpio to DVB-C */
6584 if (!state->antenna_dvbt && state->antenna_gpio)
6585 state->m_GPIO |= state->antenna_gpio;
6587 state->m_GPIO &= ~state->antenna_gpio;
6589 mutex_init(&state->mutex);
6591 memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops));
6592 state->frontend.demodulator_priv = state;
6596 /* Load firmware and initialize DRX-K */
6597 if (state->microcode_name) {
6598 if (config->load_firmware_sync) {
6599 const struct firmware *fw = NULL;
6601 status = request_firmware(&fw, state->microcode_name,
6602 state->i2c->dev.parent);
6605 load_firmware_cb(fw, state);
6607 status = request_firmware_nowait(THIS_MODULE, 1,
6608 state->microcode_name,
6609 state->i2c->dev.parent,
6611 state, load_firmware_cb);
6614 "drxk: failed to request a firmware\n");
6618 } else if (init_drxk(state) < 0)
6621 printk(KERN_INFO "drxk: frontend initialized.\n");
6622 return &state->frontend;
6625 printk(KERN_ERR "drxk: not found\n");
6629 EXPORT_SYMBOL(drxk_attach);
6631 MODULE_DESCRIPTION("DRX-K driver");
6632 MODULE_AUTHOR("Ralph Metzler");
6633 MODULE_LICENSE("GPL");