2 * Linux-DVB Driver for DiBcom's DiB8000 chip (ISDB-T).
4 * Copyright (C) 2009 DiBcom (http://www.dibcom.fr/)
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation, version 2.
10 #include <linux/kernel.h>
11 #include <linux/slab.h>
12 #include <linux/i2c.h>
13 #include <linux/mutex.h>
17 #include "dvb_frontend.h"
26 #define FE_CALLBACK_TIME_NEVER 0xffffffff
27 #define MAX_NUMBER_OF_FRONTENDS 6
30 module_param(debug, int, 0644);
31 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
33 #define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB8000: "); printk(args); printk("\n"); } } while (0)
35 #define FE_STATUS_TUNE_FAILED 0
38 struct i2c_adapter *adap;
42 struct mutex *i2c_buffer_lock;
45 struct dib8000_state {
46 struct dib8000_config cfg;
48 struct i2c_device i2c;
50 struct dibx000_i2c_master i2c_master;
55 u32 current_bandwidth;
56 struct dibx000_agc_config *current_agc;
65 u8 differential_constellation;
68 s16 ber_monitored_layer;
74 enum frontend_tune_state tune_state;
77 struct dvb_frontend *fe[MAX_NUMBER_OF_FRONTENDS];
79 /* for the I2C transfer */
80 struct i2c_msg msg[2];
81 u8 i2c_write_buffer[4];
82 u8 i2c_read_buffer[2];
83 struct mutex i2c_buffer_lock;
87 struct i2c_adapter dib8096p_tuner_adap;
90 enum dib8000_power_mode {
91 DIB8000_POWER_ALL = 0,
92 DIB8000_POWER_INTERFACE_ONLY,
95 static u16 dib8000_i2c_read16(struct i2c_device *i2c, u16 reg)
98 struct i2c_msg msg[2] = {
99 {.addr = i2c->addr >> 1, .flags = 0, .len = 2},
100 {.addr = i2c->addr >> 1, .flags = I2C_M_RD, .len = 2},
103 if (mutex_lock_interruptible(i2c->i2c_buffer_lock) < 0) {
104 dprintk("could not acquire lock");
108 msg[0].buf = i2c->i2c_write_buffer;
109 msg[0].buf[0] = reg >> 8;
110 msg[0].buf[1] = reg & 0xff;
111 msg[1].buf = i2c->i2c_read_buffer;
113 if (i2c_transfer(i2c->adap, msg, 2) != 2)
114 dprintk("i2c read error on %d", reg);
116 ret = (msg[1].buf[0] << 8) | msg[1].buf[1];
117 mutex_unlock(i2c->i2c_buffer_lock);
121 static u16 dib8000_read_word(struct dib8000_state *state, u16 reg)
125 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
126 dprintk("could not acquire lock");
130 state->i2c_write_buffer[0] = reg >> 8;
131 state->i2c_write_buffer[1] = reg & 0xff;
133 memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
134 state->msg[0].addr = state->i2c.addr >> 1;
135 state->msg[0].flags = 0;
136 state->msg[0].buf = state->i2c_write_buffer;
137 state->msg[0].len = 2;
138 state->msg[1].addr = state->i2c.addr >> 1;
139 state->msg[1].flags = I2C_M_RD;
140 state->msg[1].buf = state->i2c_read_buffer;
141 state->msg[1].len = 2;
143 if (i2c_transfer(state->i2c.adap, state->msg, 2) != 2)
144 dprintk("i2c read error on %d", reg);
146 ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
147 mutex_unlock(&state->i2c_buffer_lock);
152 static u32 dib8000_read32(struct dib8000_state *state, u16 reg)
156 rw[0] = dib8000_read_word(state, reg + 0);
157 rw[1] = dib8000_read_word(state, reg + 1);
159 return ((rw[0] << 16) | (rw[1]));
162 static int dib8000_i2c_write16(struct i2c_device *i2c, u16 reg, u16 val)
164 struct i2c_msg msg = {.addr = i2c->addr >> 1, .flags = 0, .len = 4};
167 if (mutex_lock_interruptible(i2c->i2c_buffer_lock) < 0) {
168 dprintk("could not acquire lock");
172 msg.buf = i2c->i2c_write_buffer;
173 msg.buf[0] = (reg >> 8) & 0xff;
174 msg.buf[1] = reg & 0xff;
175 msg.buf[2] = (val >> 8) & 0xff;
176 msg.buf[3] = val & 0xff;
178 ret = i2c_transfer(i2c->adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
179 mutex_unlock(i2c->i2c_buffer_lock);
184 static int dib8000_write_word(struct dib8000_state *state, u16 reg, u16 val)
188 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
189 dprintk("could not acquire lock");
193 state->i2c_write_buffer[0] = (reg >> 8) & 0xff;
194 state->i2c_write_buffer[1] = reg & 0xff;
195 state->i2c_write_buffer[2] = (val >> 8) & 0xff;
196 state->i2c_write_buffer[3] = val & 0xff;
198 memset(&state->msg[0], 0, sizeof(struct i2c_msg));
199 state->msg[0].addr = state->i2c.addr >> 1;
200 state->msg[0].flags = 0;
201 state->msg[0].buf = state->i2c_write_buffer;
202 state->msg[0].len = 4;
204 ret = (i2c_transfer(state->i2c.adap, state->msg, 1) != 1 ?
206 mutex_unlock(&state->i2c_buffer_lock);
211 static const s16 coeff_2k_sb_1seg_dqpsk[8] = {
212 (769 << 5) | 0x0a, (745 << 5) | 0x03, (595 << 5) | 0x0d, (769 << 5) | 0x0a, (920 << 5) | 0x09, (784 << 5) | 0x02, (519 << 5) | 0x0c,
216 static const s16 coeff_2k_sb_1seg[8] = {
217 (692 << 5) | 0x0b, (683 << 5) | 0x01, (519 << 5) | 0x09, (692 << 5) | 0x0b, 0 | 0x1f, 0 | 0x1f, 0 | 0x1f, 0 | 0x1f
220 static const s16 coeff_2k_sb_3seg_0dqpsk_1dqpsk[8] = {
221 (832 << 5) | 0x10, (912 << 5) | 0x05, (900 << 5) | 0x12, (832 << 5) | 0x10, (-931 << 5) | 0x0f, (912 << 5) | 0x04, (807 << 5) | 0x11,
225 static const s16 coeff_2k_sb_3seg_0dqpsk[8] = {
226 (622 << 5) | 0x0c, (941 << 5) | 0x04, (796 << 5) | 0x10, (622 << 5) | 0x0c, (982 << 5) | 0x0c, (519 << 5) | 0x02, (572 << 5) | 0x0e,
230 static const s16 coeff_2k_sb_3seg_1dqpsk[8] = {
231 (699 << 5) | 0x14, (607 << 5) | 0x04, (944 << 5) | 0x13, (699 << 5) | 0x14, (-720 << 5) | 0x0d, (640 << 5) | 0x03, (866 << 5) | 0x12,
235 static const s16 coeff_2k_sb_3seg[8] = {
236 (664 << 5) | 0x0c, (925 << 5) | 0x03, (937 << 5) | 0x10, (664 << 5) | 0x0c, (-610 << 5) | 0x0a, (697 << 5) | 0x01, (836 << 5) | 0x0e,
240 static const s16 coeff_4k_sb_1seg_dqpsk[8] = {
241 (-955 << 5) | 0x0e, (687 << 5) | 0x04, (818 << 5) | 0x10, (-955 << 5) | 0x0e, (-922 << 5) | 0x0d, (750 << 5) | 0x03, (665 << 5) | 0x0f,
245 static const s16 coeff_4k_sb_1seg[8] = {
246 (638 << 5) | 0x0d, (683 << 5) | 0x02, (638 << 5) | 0x0d, (638 << 5) | 0x0d, (-655 << 5) | 0x0a, (517 << 5) | 0x00, (698 << 5) | 0x0d,
250 static const s16 coeff_4k_sb_3seg_0dqpsk_1dqpsk[8] = {
251 (-707 << 5) | 0x14, (910 << 5) | 0x06, (889 << 5) | 0x16, (-707 << 5) | 0x14, (-958 << 5) | 0x13, (993 << 5) | 0x05, (523 << 5) | 0x14,
255 static const s16 coeff_4k_sb_3seg_0dqpsk[8] = {
256 (-723 << 5) | 0x13, (910 << 5) | 0x05, (777 << 5) | 0x14, (-723 << 5) | 0x13, (-568 << 5) | 0x0f, (547 << 5) | 0x03, (696 << 5) | 0x12,
260 static const s16 coeff_4k_sb_3seg_1dqpsk[8] = {
261 (-940 << 5) | 0x15, (607 << 5) | 0x05, (915 << 5) | 0x16, (-940 << 5) | 0x15, (-848 << 5) | 0x13, (683 << 5) | 0x04, (543 << 5) | 0x14,
265 static const s16 coeff_4k_sb_3seg[8] = {
266 (612 << 5) | 0x12, (910 << 5) | 0x04, (864 << 5) | 0x14, (612 << 5) | 0x12, (-869 << 5) | 0x13, (683 << 5) | 0x02, (869 << 5) | 0x12,
270 static const s16 coeff_8k_sb_1seg_dqpsk[8] = {
271 (-835 << 5) | 0x12, (684 << 5) | 0x05, (735 << 5) | 0x14, (-835 << 5) | 0x12, (-598 << 5) | 0x10, (781 << 5) | 0x04, (739 << 5) | 0x13,
275 static const s16 coeff_8k_sb_1seg[8] = {
276 (673 << 5) | 0x0f, (683 << 5) | 0x03, (808 << 5) | 0x12, (673 << 5) | 0x0f, (585 << 5) | 0x0f, (512 << 5) | 0x01, (780 << 5) | 0x0f,
280 static const s16 coeff_8k_sb_3seg_0dqpsk_1dqpsk[8] = {
281 (863 << 5) | 0x17, (930 << 5) | 0x07, (878 << 5) | 0x19, (863 << 5) | 0x17, (0 << 5) | 0x14, (521 << 5) | 0x05, (980 << 5) | 0x18,
285 static const s16 coeff_8k_sb_3seg_0dqpsk[8] = {
286 (-924 << 5) | 0x17, (910 << 5) | 0x06, (774 << 5) | 0x17, (-924 << 5) | 0x17, (-877 << 5) | 0x15, (565 << 5) | 0x04, (553 << 5) | 0x15,
290 static const s16 coeff_8k_sb_3seg_1dqpsk[8] = {
291 (-921 << 5) | 0x19, (607 << 5) | 0x06, (881 << 5) | 0x19, (-921 << 5) | 0x19, (-921 << 5) | 0x14, (713 << 5) | 0x05, (1018 << 5) | 0x18,
295 static const s16 coeff_8k_sb_3seg[8] = {
296 (514 << 5) | 0x14, (910 << 5) | 0x05, (861 << 5) | 0x17, (514 << 5) | 0x14, (690 << 5) | 0x14, (683 << 5) | 0x03, (662 << 5) | 0x15,
300 static const s16 ana_fe_coeff_3seg[24] = {
301 81, 80, 78, 74, 68, 61, 54, 45, 37, 28, 19, 11, 4, 1022, 1017, 1013, 1010, 1008, 1008, 1008, 1008, 1010, 1014, 1017
304 static const s16 ana_fe_coeff_1seg[24] = {
305 249, 226, 164, 82, 5, 981, 970, 988, 1018, 20, 31, 26, 8, 1012, 1000, 1018, 1012, 8, 15, 14, 9, 3, 1017, 1003
308 static const s16 ana_fe_coeff_13seg[24] = {
309 396, 305, 105, -51, -77, -12, 41, 31, -11, -30, -11, 14, 15, -2, -13, -7, 5, 8, 1, -6, -7, -3, 0, 1
312 static u16 fft_to_mode(struct dib8000_state *state)
315 switch (state->fe[0]->dtv_property_cache.transmission_mode) {
316 case TRANSMISSION_MODE_2K:
319 case TRANSMISSION_MODE_4K:
323 case TRANSMISSION_MODE_AUTO:
324 case TRANSMISSION_MODE_8K:
331 static void dib8000_set_acquisition_mode(struct dib8000_state *state)
333 u16 nud = dib8000_read_word(state, 298);
334 nud |= (1 << 3) | (1 << 0);
335 dprintk("acquisition mode activated");
336 dib8000_write_word(state, 298, nud);
338 static int dib8000_set_output_mode(struct dvb_frontend *fe, int mode)
340 struct dib8000_state *state = fe->demodulator_priv;
342 u16 outreg, fifo_threshold, smo_mode, sram = 0x0205; /* by default SDRAM deintlv is enabled */
345 fifo_threshold = 1792;
346 smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1);
348 dprintk("-I- Setting output mode for demod %p to %d",
349 &state->fe[0], mode);
352 case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock
353 outreg = (1 << 10); /* 0x0400 */
355 case OUTMODE_MPEG2_PAR_CONT_CLK: // STBs with parallel continues clock
356 outreg = (1 << 10) | (1 << 6); /* 0x0440 */
358 case OUTMODE_MPEG2_SERIAL: // STBs with serial input
359 outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0482 */
361 case OUTMODE_DIVERSITY:
362 if (state->cfg.hostbus_diversity) {
363 outreg = (1 << 10) | (4 << 6); /* 0x0500 */
368 case OUTMODE_MPEG2_FIFO: // e.g. USB feeding
369 smo_mode |= (3 << 1);
370 fifo_threshold = 512;
371 outreg = (1 << 10) | (5 << 6);
373 case OUTMODE_HIGH_Z: // disable
377 case OUTMODE_ANALOG_ADC:
378 outreg = (1 << 10) | (3 << 6);
379 dib8000_set_acquisition_mode(state);
383 dprintk("Unhandled output_mode passed to be set for demod %p",
388 if (state->cfg.output_mpeg2_in_188_bytes)
389 smo_mode |= (1 << 5);
391 dib8000_write_word(state, 299, smo_mode);
392 dib8000_write_word(state, 300, fifo_threshold); /* synchronous fread */
393 dib8000_write_word(state, 1286, outreg);
394 dib8000_write_word(state, 1291, sram);
399 static int dib8000_set_diversity_in(struct dvb_frontend *fe, int onoff)
401 struct dib8000_state *state = fe->demodulator_priv;
402 u16 sync_wait = dib8000_read_word(state, 273) & 0xfff0;
404 if (!state->differential_constellation) {
405 dib8000_write_word(state, 272, 1 << 9); //dvsy_off_lmod4 = 1
406 dib8000_write_word(state, 273, sync_wait | (1 << 2) | 2); // sync_enable = 1; comb_mode = 2
408 dib8000_write_word(state, 272, 0); //dvsy_off_lmod4 = 0
409 dib8000_write_word(state, 273, sync_wait); // sync_enable = 0; comb_mode = 0
411 state->diversity_onoff = onoff;
414 case 0: /* only use the internal way - not the diversity input */
415 dib8000_write_word(state, 270, 1);
416 dib8000_write_word(state, 271, 0);
418 case 1: /* both ways */
419 dib8000_write_word(state, 270, 6);
420 dib8000_write_word(state, 271, 6);
422 case 2: /* only the diversity input */
423 dib8000_write_word(state, 270, 0);
424 dib8000_write_word(state, 271, 1);
430 static void dib8000_set_power_mode(struct dib8000_state *state, enum dib8000_power_mode mode)
432 /* by default everything is going to be powered off */
433 u16 reg_774 = 0x3fff, reg_775 = 0xffff, reg_776 = 0xffff,
434 reg_900 = (dib8000_read_word(state, 900) & 0xfffc) | 0x3,
437 if (state->revision != 0x8090)
438 reg_1280 = (dib8000_read_word(state, 1280) & 0x00ff) | 0xff00;
440 reg_1280 = (dib8000_read_word(state, 1280) & 0x707f) | 0x8f80;
442 /* now, depending on the requested mode, we power on */
444 /* power up everything in the demod */
445 case DIB8000_POWER_ALL:
450 if (state->revision != 0x8090)
455 case DIB8000_POWER_INTERFACE_ONLY:
456 if (state->revision != 0x8090)
463 dprintk("powermode : 774 : %x ; 775 : %x; 776 : %x ; 900 : %x; 1280 : %x", reg_774, reg_775, reg_776, reg_900, reg_1280);
464 dib8000_write_word(state, 774, reg_774);
465 dib8000_write_word(state, 775, reg_775);
466 dib8000_write_word(state, 776, reg_776);
467 dib8000_write_word(state, 900, reg_900);
468 dib8000_write_word(state, 1280, reg_1280);
471 static int dib8000_init_sdram(struct dib8000_state *state)
474 dprintk("Init sdram");
476 reg = dib8000_read_word(state, 274)&0xfff0;
477 /* P_dintlv_delay_ram = 7 because of MobileSdram */
478 dib8000_write_word(state, 274, reg | 0x7);
480 dib8000_write_word(state, 1803, (7<<2));
482 reg = dib8000_read_word(state, 1280);
483 /* force restart P_restart_sdram */
484 dib8000_write_word(state, 1280, reg | (1<<2));
486 /* release restart P_restart_sdram */
487 dib8000_write_word(state, 1280, reg);
492 static int dib8000_set_adc_state(struct dib8000_state *state, enum dibx000_adc_states no)
495 u16 reg, reg_907 = dib8000_read_word(state, 907);
496 u16 reg_908 = dib8000_read_word(state, 908);
499 case DIBX000_SLOW_ADC_ON:
500 if (state->revision != 0x8090) {
501 reg_908 |= (1 << 1) | (1 << 0);
502 ret |= dib8000_write_word(state, 908, reg_908);
503 reg_908 &= ~(1 << 1);
505 reg = dib8000_read_word(state, 1925);
506 /* en_slowAdc = 1 & reset_sladc = 1 */
507 dib8000_write_word(state, 1925, reg |
510 /* read acces to make it works... strange ... */
511 reg = dib8000_read_word(state, 1925);
513 /* en_slowAdc = 1 & reset_sladc = 0 */
514 dib8000_write_word(state, 1925, reg & ~(1<<4));
516 reg = dib8000_read_word(state, 921) & ~((0x3 << 14)
518 /* ref = Vin1 => Vbg ; sel = Vin0 or Vin3 ;
520 dib8000_write_word(state, 921, reg | (1 << 14)
525 case DIBX000_SLOW_ADC_OFF:
526 if (state->revision == 0x8090) {
527 reg = dib8000_read_word(state, 1925);
528 /* reset_sladc = 1 en_slowAdc = 0 */
529 dib8000_write_word(state, 1925,
530 (reg & ~(1<<2)) | (1<<4));
532 reg_908 |= (1 << 1) | (1 << 0);
540 case DIBX000_ADC_OFF: // leave the VBG voltage on
541 reg_907 |= (1 << 14) | (1 << 13) | (1 << 12);
542 reg_908 |= (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2);
545 case DIBX000_VBG_ENABLE:
546 reg_907 &= ~(1 << 15);
549 case DIBX000_VBG_DISABLE:
550 reg_907 |= (1 << 15);
557 ret |= dib8000_write_word(state, 907, reg_907);
558 ret |= dib8000_write_word(state, 908, reg_908);
563 static int dib8000_set_bandwidth(struct dvb_frontend *fe, u32 bw)
565 struct dib8000_state *state = fe->demodulator_priv;
571 if (state->timf == 0) {
572 dprintk("using default timf");
573 timf = state->timf_default;
575 dprintk("using updated timf");
579 dib8000_write_word(state, 29, (u16) ((timf >> 16) & 0xffff));
580 dib8000_write_word(state, 30, (u16) ((timf) & 0xffff));
585 static int dib8000_sad_calib(struct dib8000_state *state)
587 if (state->revision == 0x8090) {
588 dprintk("%s: the sad calibration is not needed for the dib8096P",
593 dib8000_write_word(state, 923, (0 << 1) | (0 << 0));
594 dib8000_write_word(state, 924, 776); // 0.625*3.3 / 4096
596 /* do the calibration */
597 dib8000_write_word(state, 923, (1 << 0));
598 dib8000_write_word(state, 923, (0 << 0));
604 int dib8000_set_wbd_ref(struct dvb_frontend *fe, u16 value)
606 struct dib8000_state *state = fe->demodulator_priv;
609 state->wbd_ref = value;
610 return dib8000_write_word(state, 106, value);
613 EXPORT_SYMBOL(dib8000_set_wbd_ref);
614 static void dib8000_reset_pll_common(struct dib8000_state *state, const struct dibx000_bandwidth_config *bw)
616 dprintk("ifreq: %d %x, inversion: %d", bw->ifreq, bw->ifreq, bw->ifreq >> 25);
617 if (state->revision != 0x8090) {
618 dib8000_write_word(state, 23,
619 (u16) (((bw->internal * 1000) >> 16) & 0xffff));
620 dib8000_write_word(state, 24,
621 (u16) ((bw->internal * 1000) & 0xffff));
623 dib8000_write_word(state, 23, (u16) (((bw->internal / 2 * 1000) >> 16) & 0xffff));
624 dib8000_write_word(state, 24,
625 (u16) ((bw->internal / 2 * 1000) & 0xffff));
627 dib8000_write_word(state, 27, (u16) ((bw->ifreq >> 16) & 0x01ff));
628 dib8000_write_word(state, 28, (u16) (bw->ifreq & 0xffff));
629 dib8000_write_word(state, 26, (u16) ((bw->ifreq >> 25) & 0x0003));
631 if (state->revision != 0x8090)
632 dib8000_write_word(state, 922, bw->sad_cfg);
635 static void dib8000_reset_pll(struct dib8000_state *state)
637 const struct dibx000_bandwidth_config *pll = state->cfg.pll;
640 if (state->revision != 0x8090) {
641 dib8000_write_word(state, 901,
642 (pll->pll_prediv << 8) | (pll->pll_ratio << 0));
644 clk_cfg1 = (1 << 10) | (0 << 9) | (pll->IO_CLK_en_core << 8) |
645 (pll->bypclk_div << 5) | (pll->enable_refdiv << 4) |
646 (1 << 3) | (pll->pll_range << 1) |
647 (pll->pll_reset << 0);
649 dib8000_write_word(state, 902, clk_cfg1);
650 clk_cfg1 = (clk_cfg1 & 0xfff7) | (pll->pll_bypass << 3);
651 dib8000_write_word(state, 902, clk_cfg1);
653 dprintk("clk_cfg1: 0x%04x", clk_cfg1);
655 /* smpl_cfg: P_refclksel=2, P_ensmplsel=1 nodivsmpl=1 */
656 if (state->cfg.pll->ADClkSrc == 0)
657 dib8000_write_word(state, 904,
658 (0 << 15) | (0 << 12) | (0 << 10) |
660 (pll->ADClkSrc << 7) | (0 << 1));
661 else if (state->cfg.refclksel != 0)
662 dib8000_write_word(state, 904, (0 << 15) | (1 << 12) |
663 ((state->cfg.refclksel & 0x3) << 10) |
665 (pll->ADClkSrc << 7) | (0 << 1));
667 dib8000_write_word(state, 904, (0 << 15) | (1 << 12) |
668 (3 << 10) | (pll->modulo << 8) |
669 (pll->ADClkSrc << 7) | (0 << 1));
671 dib8000_write_word(state, 1856, (!pll->pll_reset<<13) |
672 (pll->pll_range<<12) | (pll->pll_ratio<<6) |
675 reg = dib8000_read_word(state, 1857);
676 dib8000_write_word(state, 1857, reg|(!pll->pll_bypass<<15));
678 reg = dib8000_read_word(state, 1858); /* Force clk out pll /2 */
679 dib8000_write_word(state, 1858, reg | 1);
681 dib8000_write_word(state, 904, (pll->modulo << 8));
684 dib8000_reset_pll_common(state, pll);
687 int dib8000_update_pll(struct dvb_frontend *fe,
688 struct dibx000_bandwidth_config *pll)
690 struct dib8000_state *state = fe->demodulator_priv;
691 u16 reg_1857, reg_1856 = dib8000_read_word(state, 1856);
695 /* get back old values */
696 prediv = reg_1856 & 0x3f;
697 loopdiv = (reg_1856 >> 6) & 0x3f;
699 if ((pll != NULL) && (pll->pll_prediv != prediv ||
700 pll->pll_ratio != loopdiv)) {
701 dprintk("Updating pll (prediv: old = %d new = %d ; loopdiv : old = %d new = %d)", prediv, pll->pll_prediv, loopdiv, pll->pll_ratio);
703 reg_1857 = dib8000_read_word(state, 1857);
705 dib8000_write_word(state, 1857, reg_1857 & ~(1 << 15));
707 dib8000_write_word(state, 1856, reg_1856 |
708 ((pll->pll_ratio & 0x3f) << 6) |
709 (pll->pll_prediv & 0x3f));
711 /* write new system clk into P_sec_len */
712 internal = dib8000_read32(state, 23) / 1000;
713 dprintk("Old Internal = %d", internal);
714 xtal = 2 * (internal / loopdiv) * prediv;
715 internal = 1000 * (xtal/pll->pll_prediv) * pll->pll_ratio;
716 dprintk("Xtal = %d , New Fmem = %d New Fdemod = %d, New Fsampling = %d", xtal, internal/1000, internal/2000, internal/8000);
717 dprintk("New Internal = %d", internal);
719 dib8000_write_word(state, 23,
720 (u16) (((internal / 2) >> 16) & 0xffff));
721 dib8000_write_word(state, 24, (u16) ((internal / 2) & 0xffff));
723 dib8000_write_word(state, 1857, reg_1857 | (1 << 15));
725 while (((dib8000_read_word(state, 1856)>>15)&0x1) != 1)
726 dprintk("Waiting for PLL to lock");
729 reg_1856 = dib8000_read_word(state, 1856);
730 dprintk("PLL Updated with prediv = %d and loopdiv = %d",
731 reg_1856&0x3f, (reg_1856>>6)&0x3f);
737 EXPORT_SYMBOL(dib8000_update_pll);
740 static int dib8000_reset_gpio(struct dib8000_state *st)
742 /* reset the GPIOs */
743 dib8000_write_word(st, 1029, st->cfg.gpio_dir);
744 dib8000_write_word(st, 1030, st->cfg.gpio_val);
746 /* TODO 782 is P_gpio_od */
748 dib8000_write_word(st, 1032, st->cfg.gpio_pwm_pos);
750 dib8000_write_word(st, 1037, st->cfg.pwm_freq_div);
754 static int dib8000_cfg_gpio(struct dib8000_state *st, u8 num, u8 dir, u8 val)
756 st->cfg.gpio_dir = dib8000_read_word(st, 1029);
757 st->cfg.gpio_dir &= ~(1 << num); /* reset the direction bit */
758 st->cfg.gpio_dir |= (dir & 0x1) << num; /* set the new direction */
759 dib8000_write_word(st, 1029, st->cfg.gpio_dir);
761 st->cfg.gpio_val = dib8000_read_word(st, 1030);
762 st->cfg.gpio_val &= ~(1 << num); /* reset the direction bit */
763 st->cfg.gpio_val |= (val & 0x01) << num; /* set the new value */
764 dib8000_write_word(st, 1030, st->cfg.gpio_val);
766 dprintk("gpio dir: %x: gpio val: %x", st->cfg.gpio_dir, st->cfg.gpio_val);
771 int dib8000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val)
773 struct dib8000_state *state = fe->demodulator_priv;
774 return dib8000_cfg_gpio(state, num, dir, val);
777 EXPORT_SYMBOL(dib8000_set_gpio);
778 static const u16 dib8000_defaults[] = {
779 /* auto search configuration - lock0 by default waiting
780 * for cpil_lock; lock1 cpil_lock; lock2 tmcc_sync_lock */
801 0x6680 // P_corm_thres Lock algorithms configuration */
803 11, 80, /* set ADC level to -16 */
804 (1 << 13) - 825 - 117,
805 (1 << 13) - 837 - 117,
806 (1 << 13) - 811 - 117,
807 (1 << 13) - 766 - 117,
808 (1 << 13) - 737 - 117,
809 (1 << 13) - 693 - 117,
810 (1 << 13) - 648 - 117,
811 (1 << 13) - 619 - 117,
812 (1 << 13) - 575 - 117,
813 (1 << 13) - 531 - 117,
814 (1 << 13) - 501 - 117,
825 8192, // P_fft_nb_to_cut
828 0x2800, // P_coff_corthres_ ( 2k 4k 8k ) 0x2800
831 0x2800, // P_coff_cpilthres_ ( 2k 4k 8k ) 0x2800
836 0x0666, // P_pha3_thres
837 0x0000, // P_cti_use_cpe, P_cti_use_prog
840 0x200f, // P_cspu_regul, P_cspu_win_cut
841 0x000f, // P_des_shift_work
844 0x023d, // P_adp_regul_cnt
845 0x00a4, // P_adp_noise_cnt
846 0x00a4, // P_adp_regul_ext
847 0x7ff0, // P_adp_noise_ext
851 0x0000, // P_2d_byp_ti_num
854 0x800, //P_equal_thres_wgn
857 (2 << 9) | 39, // P_equal_ctrl_synchro, P_equal_speedmode
860 0x0001, // P_div_lock0_wait
864 0x0062, /* P_smo_mode, P_smo_rs_discard, P_smo_fifo_flush, P_smo_pid_parse, P_smo_error_discard */
867 (1 << 12) | // P_ctrl_corm_thres4pre_freq_inh=1
869 (0 << 9) | /* P_ctrl_pre_freq_inh=0 */
870 (3 << 5) | /* P_ctrl_pre_freq_step=3 */
871 (1 << 0), /* P_pre_freq_win_len=1 */
876 static u16 dib8000_identify(struct i2c_device *client)
880 //because of glitches sometimes
881 value = dib8000_i2c_read16(client, 896);
883 if ((value = dib8000_i2c_read16(client, 896)) != 0x01b3) {
884 dprintk("wrong Vendor ID (read=0x%x)", value);
888 value = dib8000_i2c_read16(client, 897);
889 if (value != 0x8000 && value != 0x8001 &&
890 value != 0x8002 && value != 0x8090) {
891 dprintk("wrong Device ID (%x)", value);
897 dprintk("found DiB8000A");
900 dprintk("found DiB8000B");
903 dprintk("found DiB8000C");
906 dprintk("found DiB8096P");
912 static int dib8000_reset(struct dvb_frontend *fe)
914 struct dib8000_state *state = fe->demodulator_priv;
916 if ((state->revision = dib8000_identify(&state->i2c)) == 0)
919 /* sram lead in, rdy */
920 if (state->revision != 0x8090)
921 dib8000_write_word(state, 1287, 0x0003);
923 if (state->revision == 0x8000)
924 dprintk("error : dib8000 MA not supported");
926 dibx000_reset_i2c_master(&state->i2c_master);
928 dib8000_set_power_mode(state, DIB8000_POWER_ALL);
930 /* always leave the VBG voltage on - it consumes almost nothing but takes a long time to start */
931 dib8000_set_adc_state(state, DIBX000_VBG_ENABLE);
933 /* restart all parts */
934 dib8000_write_word(state, 770, 0xffff);
935 dib8000_write_word(state, 771, 0xffff);
936 dib8000_write_word(state, 772, 0xfffc);
937 if (state->revision == 0x8090)
938 dib8000_write_word(state, 1280, 0x0045);
940 dib8000_write_word(state, 1280, 0x004d);
941 dib8000_write_word(state, 1281, 0x000c);
943 dib8000_write_word(state, 770, 0x0000);
944 dib8000_write_word(state, 771, 0x0000);
945 dib8000_write_word(state, 772, 0x0000);
946 dib8000_write_word(state, 898, 0x0004); // sad
947 dib8000_write_word(state, 1280, 0x0000);
948 dib8000_write_word(state, 1281, 0x0000);
951 if (state->revision != 0x8090) {
952 if (state->cfg.drives)
953 dib8000_write_word(state, 906, state->cfg.drives);
955 dprintk("using standard PAD-drive-settings, please adjust settings in config-struct to be optimal.");
956 /* min drive SDRAM - not optimal - adjust */
957 dib8000_write_word(state, 906, 0x2d98);
961 dib8000_reset_pll(state);
962 if (state->revision != 0x8090)
963 dib8000_write_word(state, 898, 0x0004);
965 if (dib8000_reset_gpio(state) != 0)
966 dprintk("GPIO reset was not successful.");
968 if ((state->revision != 0x8090) &&
969 (dib8000_set_output_mode(fe, OUTMODE_HIGH_Z) != 0))
970 dprintk("OUTPUT_MODE could not be resetted.");
972 state->current_agc = NULL;
974 // P_iqc_alpha_pha, P_iqc_alpha_amp, P_iqc_dcc_alpha, ...
975 /* P_iqc_ca2 = 0; P_iqc_impnc_on = 0; P_iqc_mode = 0; */
976 if (state->cfg.pll->ifreq == 0)
977 dib8000_write_word(state, 40, 0x0755); /* P_iqc_corr_inh = 0 enable IQcorr block */
979 dib8000_write_word(state, 40, 0x1f55); /* P_iqc_corr_inh = 1 disable IQcorr block */
984 n = dib8000_defaults;
989 dib8000_write_word(state, r, *n++);
995 if (state->revision != 0x8090)
996 dib8000_write_word(state, 903, (0 << 4) | 2);
997 state->isdbt_cfg_loaded = 0;
999 //div_cfg override for special configs
1000 if (state->cfg.div_cfg != 0)
1001 dib8000_write_word(state, 903, state->cfg.div_cfg);
1003 /* unforce divstr regardless whether i2c enumeration was done or not */
1004 dib8000_write_word(state, 1285, dib8000_read_word(state, 1285) & ~(1 << 1));
1006 dib8000_set_bandwidth(fe, 6000);
1008 dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON);
1009 if (state->revision != 0x8090) {
1010 dib8000_sad_calib(state);
1011 dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF);
1014 dib8000_set_power_mode(state, DIB8000_POWER_INTERFACE_ONLY);
1019 static void dib8000_restart_agc(struct dib8000_state *state)
1021 // P_restart_iqc & P_restart_agc
1022 dib8000_write_word(state, 770, 0x0a00);
1023 dib8000_write_word(state, 770, 0x0000);
1026 static int dib8000_update_lna(struct dib8000_state *state)
1030 if (state->cfg.update_lna) {
1031 // read dyn_gain here (because it is demod-dependent and not tuner)
1032 dyn_gain = dib8000_read_word(state, 390);
1034 if (state->cfg.update_lna(state->fe[0], dyn_gain)) {
1035 dib8000_restart_agc(state);
1042 static int dib8000_set_agc_config(struct dib8000_state *state, u8 band)
1044 struct dibx000_agc_config *agc = NULL;
1048 if (state->current_band == band && state->current_agc != NULL)
1050 state->current_band = band;
1052 for (i = 0; i < state->cfg.agc_config_count; i++)
1053 if (state->cfg.agc[i].band_caps & band) {
1054 agc = &state->cfg.agc[i];
1059 dprintk("no valid AGC configuration found for band 0x%02x", band);
1063 state->current_agc = agc;
1066 dib8000_write_word(state, 76, agc->setup);
1067 dib8000_write_word(state, 77, agc->inv_gain);
1068 dib8000_write_word(state, 78, agc->time_stabiliz);
1069 dib8000_write_word(state, 101, (agc->alpha_level << 12) | agc->thlock);
1071 // Demod AGC loop configuration
1072 dib8000_write_word(state, 102, (agc->alpha_mant << 5) | agc->alpha_exp);
1073 dib8000_write_word(state, 103, (agc->beta_mant << 6) | agc->beta_exp);
1075 dprintk("WBD: ref: %d, sel: %d, active: %d, alpha: %d",
1076 state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel);
1079 if (state->wbd_ref != 0)
1080 dib8000_write_word(state, 106, state->wbd_ref);
1082 dib8000_write_word(state, 106, agc->wbd_ref);
1084 if (state->revision == 0x8090) {
1085 reg = dib8000_read_word(state, 922) & (0x3 << 2);
1086 dib8000_write_word(state, 922, reg | (agc->wbd_sel << 2));
1089 dib8000_write_word(state, 107, (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8));
1090 dib8000_write_word(state, 108, agc->agc1_max);
1091 dib8000_write_word(state, 109, agc->agc1_min);
1092 dib8000_write_word(state, 110, agc->agc2_max);
1093 dib8000_write_word(state, 111, agc->agc2_min);
1094 dib8000_write_word(state, 112, (agc->agc1_pt1 << 8) | agc->agc1_pt2);
1095 dib8000_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
1096 dib8000_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
1097 dib8000_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
1099 dib8000_write_word(state, 75, agc->agc1_pt3);
1100 if (state->revision != 0x8090)
1101 dib8000_write_word(state, 923,
1102 (dib8000_read_word(state, 923) & 0xffe3) |
1103 (agc->wbd_inv << 4) | (agc->wbd_sel << 2));
1108 void dib8000_pwm_agc_reset(struct dvb_frontend *fe)
1110 struct dib8000_state *state = fe->demodulator_priv;
1111 dib8000_set_adc_state(state, DIBX000_ADC_ON);
1112 dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000)));
1114 EXPORT_SYMBOL(dib8000_pwm_agc_reset);
1116 static int dib8000_agc_soft_split(struct dib8000_state *state)
1118 u16 agc, split_offset;
1120 if (!state->current_agc || !state->current_agc->perform_agc_softsplit || state->current_agc->split.max == 0)
1121 return FE_CALLBACK_TIME_NEVER;
1124 agc = dib8000_read_word(state, 390);
1126 if (agc > state->current_agc->split.min_thres)
1127 split_offset = state->current_agc->split.min;
1128 else if (agc < state->current_agc->split.max_thres)
1129 split_offset = state->current_agc->split.max;
1131 split_offset = state->current_agc->split.max *
1132 (agc - state->current_agc->split.min_thres) /
1133 (state->current_agc->split.max_thres - state->current_agc->split.min_thres);
1135 dprintk("AGC split_offset: %d", split_offset);
1137 // P_agc_force_split and P_agc_split_offset
1138 dib8000_write_word(state, 107, (dib8000_read_word(state, 107) & 0xff00) | split_offset);
1142 static int dib8000_agc_startup(struct dvb_frontend *fe)
1144 struct dib8000_state *state = fe->demodulator_priv;
1145 enum frontend_tune_state *tune_state = &state->tune_state;
1147 u16 reg, upd_demod_gain_period = 0x8000;
1149 switch (*tune_state) {
1151 // set power-up level: interf+analog+AGC
1153 if (state->revision != 0x8090)
1154 dib8000_set_adc_state(state, DIBX000_ADC_ON);
1156 dib8000_set_power_mode(state, DIB8000_POWER_ALL);
1158 reg = dib8000_read_word(state, 1947)&0xff00;
1159 dib8000_write_word(state, 1946,
1160 upd_demod_gain_period & 0xFFFF);
1161 /* bit 14 = enDemodGain */
1162 dib8000_write_word(state, 1947, reg | (1<<14) |
1163 ((upd_demod_gain_period >> 16) & 0xFF));
1165 /* enable adc i & q */
1166 reg = dib8000_read_word(state, 1920);
1167 dib8000_write_word(state, 1920, (reg | 0x3) &
1171 if (dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000))) != 0) {
1172 *tune_state = CT_AGC_STOP;
1173 state->status = FE_STATUS_TUNE_FAILED;
1178 *tune_state = CT_AGC_STEP_0;
1182 //AGC initialization
1183 if (state->cfg.agc_control)
1184 state->cfg.agc_control(fe, 1);
1186 dib8000_restart_agc(state);
1188 // wait AGC rough lock time
1190 *tune_state = CT_AGC_STEP_1;
1194 // wait AGC accurate lock time
1197 if (dib8000_update_lna(state))
1198 // wait only AGC rough lock time
1201 *tune_state = CT_AGC_STEP_2;
1205 dib8000_agc_soft_split(state);
1207 if (state->cfg.agc_control)
1208 state->cfg.agc_control(fe, 0);
1210 *tune_state = CT_AGC_STOP;
1213 ret = dib8000_agc_soft_split(state);
1220 static void dib8096p_host_bus_drive(struct dib8000_state *state, u8 drive)
1226 /* drive host bus 2, 3, 4 */
1227 reg = dib8000_read_word(state, 1798) &
1228 ~(0x7 | (0x7 << 6) | (0x7 << 12));
1229 reg |= (drive<<12) | (drive<<6) | drive;
1230 dib8000_write_word(state, 1798, reg);
1232 /* drive host bus 5,6 */
1233 reg = dib8000_read_word(state, 1799) & ~((0x7 << 2) | (0x7 << 8));
1234 reg |= (drive<<8) | (drive<<2);
1235 dib8000_write_word(state, 1799, reg);
1237 /* drive host bus 7, 8, 9 */
1238 reg = dib8000_read_word(state, 1800) &
1239 ~(0x7 | (0x7 << 6) | (0x7 << 12));
1240 reg |= (drive<<12) | (drive<<6) | drive;
1241 dib8000_write_word(state, 1800, reg);
1243 /* drive host bus 10, 11 */
1244 reg = dib8000_read_word(state, 1801) & ~((0x7 << 2) | (0x7 << 8));
1245 reg |= (drive<<8) | (drive<<2);
1246 dib8000_write_word(state, 1801, reg);
1248 /* drive host bus 12, 13, 14 */
1249 reg = dib8000_read_word(state, 1802) &
1250 ~(0x7 | (0x7 << 6) | (0x7 << 12));
1251 reg |= (drive<<12) | (drive<<6) | drive;
1252 dib8000_write_word(state, 1802, reg);
1255 static u32 dib8096p_calcSyncFreq(u32 P_Kin, u32 P_Kout,
1256 u32 insertExtSynchro, u32 syncSize)
1259 u32 nom = (insertExtSynchro * P_Kin+syncSize);
1261 u32 syncFreq = ((nom << quantif) / denom);
1263 if ((syncFreq & ((1 << quantif) - 1)) != 0)
1264 syncFreq = (syncFreq >> quantif) + 1;
1266 syncFreq = (syncFreq >> quantif);
1269 syncFreq = syncFreq - 1;
1274 static void dib8096p_cfg_DibTx(struct dib8000_state *state, u32 P_Kin,
1275 u32 P_Kout, u32 insertExtSynchro, u32 synchroMode,
1276 u32 syncWord, u32 syncSize)
1278 dprintk("Configure DibStream Tx");
1280 dib8000_write_word(state, 1615, 1);
1281 dib8000_write_word(state, 1603, P_Kin);
1282 dib8000_write_word(state, 1605, P_Kout);
1283 dib8000_write_word(state, 1606, insertExtSynchro);
1284 dib8000_write_word(state, 1608, synchroMode);
1285 dib8000_write_word(state, 1609, (syncWord >> 16) & 0xffff);
1286 dib8000_write_word(state, 1610, syncWord & 0xffff);
1287 dib8000_write_word(state, 1612, syncSize);
1288 dib8000_write_word(state, 1615, 0);
1291 static void dib8096p_cfg_DibRx(struct dib8000_state *state, u32 P_Kin,
1292 u32 P_Kout, u32 synchroMode, u32 insertExtSynchro,
1293 u32 syncWord, u32 syncSize, u32 dataOutRate)
1297 dprintk("Configure DibStream Rx synchroMode = %d", synchroMode);
1299 if ((P_Kin != 0) && (P_Kout != 0)) {
1300 syncFreq = dib8096p_calcSyncFreq(P_Kin, P_Kout,
1301 insertExtSynchro, syncSize);
1302 dib8000_write_word(state, 1542, syncFreq);
1305 dib8000_write_word(state, 1554, 1);
1306 dib8000_write_word(state, 1536, P_Kin);
1307 dib8000_write_word(state, 1537, P_Kout);
1308 dib8000_write_word(state, 1539, synchroMode);
1309 dib8000_write_word(state, 1540, (syncWord >> 16) & 0xffff);
1310 dib8000_write_word(state, 1541, syncWord & 0xffff);
1311 dib8000_write_word(state, 1543, syncSize);
1312 dib8000_write_word(state, 1544, dataOutRate);
1313 dib8000_write_word(state, 1554, 0);
1316 static void dib8096p_enMpegMux(struct dib8000_state *state, int onoff)
1320 reg_1287 = dib8000_read_word(state, 1287);
1324 reg_1287 &= ~(1 << 8);
1327 reg_1287 |= (1 << 8);
1331 dib8000_write_word(state, 1287, reg_1287);
1334 static void dib8096p_configMpegMux(struct dib8000_state *state,
1335 u16 pulseWidth, u16 enSerialMode, u16 enSerialClkDiv2)
1339 dprintk("Enable Mpeg mux");
1341 dib8096p_enMpegMux(state, 0);
1343 /* If the input mode is MPEG do not divide the serial clock */
1344 if ((enSerialMode == 1) && (state->input_mode_mpeg == 1))
1345 enSerialClkDiv2 = 0;
1347 reg_1287 = ((pulseWidth & 0x1f) << 3) |
1348 ((enSerialMode & 0x1) << 2) | (enSerialClkDiv2 & 0x1);
1349 dib8000_write_word(state, 1287, reg_1287);
1351 dib8096p_enMpegMux(state, 1);
1354 static void dib8096p_setDibTxMux(struct dib8000_state *state, int mode)
1356 u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 7);
1360 dprintk("SET MPEG ON DIBSTREAM TX");
1361 dib8096p_cfg_DibTx(state, 8, 5, 0, 0, 0, 0);
1362 reg_1288 |= (1 << 9); break;
1364 dprintk("SET DIV_OUT ON DIBSTREAM TX");
1365 dib8096p_cfg_DibTx(state, 5, 5, 0, 0, 0, 0);
1366 reg_1288 |= (1 << 8); break;
1368 dprintk("SET ADC_OUT ON DIBSTREAM TX");
1369 dib8096p_cfg_DibTx(state, 20, 5, 10, 0, 0, 0);
1370 reg_1288 |= (1 << 7); break;
1374 dib8000_write_word(state, 1288, reg_1288);
1377 static void dib8096p_setHostBusMux(struct dib8000_state *state, int mode)
1379 u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 4);
1382 case DEMOUT_ON_HOSTBUS:
1383 dprintk("SET DEM OUT OLD INTERF ON HOST BUS");
1384 dib8096p_enMpegMux(state, 0);
1385 reg_1288 |= (1 << 6);
1387 case DIBTX_ON_HOSTBUS:
1388 dprintk("SET DIBSTREAM TX ON HOST BUS");
1389 dib8096p_enMpegMux(state, 0);
1390 reg_1288 |= (1 << 5);
1392 case MPEG_ON_HOSTBUS:
1393 dprintk("SET MPEG MUX ON HOST BUS");
1394 reg_1288 |= (1 << 4);
1399 dib8000_write_word(state, 1288, reg_1288);
1402 static int dib8096p_set_diversity_in(struct dvb_frontend *fe, int onoff)
1404 struct dib8000_state *state = fe->demodulator_priv;
1408 case 0: /* only use the internal way - not the diversity input */
1409 dprintk("%s mode OFF : by default Enable Mpeg INPUT",
1411 /* outputRate = 8 */
1412 dib8096p_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0);
1414 /* Do not divide the serial clock of MPEG MUX in
1415 SERIAL MODE in case input mode MPEG is used */
1416 reg_1287 = dib8000_read_word(state, 1287);
1417 /* enSerialClkDiv2 == 1 ? */
1418 if ((reg_1287 & 0x1) == 1) {
1419 /* force enSerialClkDiv2 = 0 */
1421 dib8000_write_word(state, 1287, reg_1287);
1423 state->input_mode_mpeg = 1;
1425 case 1: /* both ways */
1426 case 2: /* only the diversity input */
1427 dprintk("%s ON : Enable diversity INPUT", __func__);
1428 dib8096p_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0);
1429 state->input_mode_mpeg = 0;
1433 dib8000_set_diversity_in(state->fe[0], onoff);
1437 static int dib8096p_set_output_mode(struct dvb_frontend *fe, int mode)
1439 struct dib8000_state *state = fe->demodulator_priv;
1440 u16 outreg, smo_mode, fifo_threshold;
1441 u8 prefer_mpeg_mux_use = 1;
1444 dib8096p_host_bus_drive(state, 1);
1446 fifo_threshold = 1792;
1447 smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1);
1448 outreg = dib8000_read_word(state, 1286) &
1449 ~((1 << 10) | (0x7 << 6) | (1 << 1));
1452 case OUTMODE_HIGH_Z:
1456 case OUTMODE_MPEG2_SERIAL:
1457 if (prefer_mpeg_mux_use) {
1458 dprintk("dib8096P setting output mode TS_SERIAL using Mpeg Mux");
1459 dib8096p_configMpegMux(state, 3, 1, 1);
1460 dib8096p_setHostBusMux(state, MPEG_ON_HOSTBUS);
1461 } else {/* Use Smooth block */
1462 dprintk("dib8096P setting output mode TS_SERIAL using Smooth bloc");
1463 dib8096p_setHostBusMux(state,
1465 outreg |= (2 << 6) | (0 << 1);
1469 case OUTMODE_MPEG2_PAR_GATED_CLK:
1470 if (prefer_mpeg_mux_use) {
1471 dprintk("dib8096P setting output mode TS_PARALLEL_GATED using Mpeg Mux");
1472 dib8096p_configMpegMux(state, 2, 0, 0);
1473 dib8096p_setHostBusMux(state, MPEG_ON_HOSTBUS);
1474 } else { /* Use Smooth block */
1475 dprintk("dib8096P setting output mode TS_PARALLEL_GATED using Smooth block");
1476 dib8096p_setHostBusMux(state,
1482 case OUTMODE_MPEG2_PAR_CONT_CLK: /* Using Smooth block only */
1483 dprintk("dib8096P setting output mode TS_PARALLEL_CONT using Smooth block");
1484 dib8096p_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
1488 case OUTMODE_MPEG2_FIFO:
1489 /* Using Smooth block because not supported
1490 by new Mpeg Mux bloc */
1491 dprintk("dib8096P setting output mode TS_FIFO using Smooth block");
1492 dib8096p_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
1494 smo_mode |= (3 << 1);
1495 fifo_threshold = 512;
1498 case OUTMODE_DIVERSITY:
1499 dprintk("dib8096P setting output mode MODE_DIVERSITY");
1500 dib8096p_setDibTxMux(state, DIV_ON_DIBTX);
1501 dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS);
1504 case OUTMODE_ANALOG_ADC:
1505 dprintk("dib8096P setting output mode MODE_ANALOG_ADC");
1506 dib8096p_setDibTxMux(state, ADC_ON_DIBTX);
1507 dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS);
1511 if (mode != OUTMODE_HIGH_Z)
1514 dprintk("output_mpeg2_in_188_bytes = %d",
1515 state->cfg.output_mpeg2_in_188_bytes);
1516 if (state->cfg.output_mpeg2_in_188_bytes)
1517 smo_mode |= (1 << 5);
1519 ret |= dib8000_write_word(state, 299, smo_mode);
1520 /* synchronous fread */
1521 ret |= dib8000_write_word(state, 299 + 1, fifo_threshold);
1522 ret |= dib8000_write_word(state, 1286, outreg);
1527 static int map_addr_to_serpar_number(struct i2c_msg *msg)
1529 if (msg->buf[0] <= 15)
1531 else if (msg->buf[0] == 17)
1533 else if (msg->buf[0] == 16)
1535 else if (msg->buf[0] == 19)
1537 else if (msg->buf[0] >= 21 && msg->buf[0] <= 25)
1539 else if (msg->buf[0] == 28)
1541 else if (msg->buf[0] == 99)
1548 static int dib8096p_tuner_write_serpar(struct i2c_adapter *i2c_adap,
1549 struct i2c_msg msg[], int num)
1551 struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
1554 u16 serpar_num = msg[0].buf[0];
1556 while (n_overflow == 1 && i) {
1557 n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1;
1560 dprintk("Tuner ITF: write busy (overflow)");
1562 dib8000_write_word(state, 1985, (1 << 6) | (serpar_num & 0x3f));
1563 dib8000_write_word(state, 1986, (msg[0].buf[1] << 8) | msg[0].buf[2]);
1568 static int dib8096p_tuner_read_serpar(struct i2c_adapter *i2c_adap,
1569 struct i2c_msg msg[], int num)
1571 struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
1572 u8 n_overflow = 1, n_empty = 1;
1574 u16 serpar_num = msg[0].buf[0];
1577 while (n_overflow == 1 && i) {
1578 n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1;
1581 dprintk("TunerITF: read busy (overflow)");
1583 dib8000_write_word(state, 1985, (0<<6) | (serpar_num&0x3f));
1586 while (n_empty == 1 && i) {
1587 n_empty = dib8000_read_word(state, 1984)&0x1;
1590 dprintk("TunerITF: read busy (empty)");
1593 read_word = dib8000_read_word(state, 1987);
1594 msg[1].buf[0] = (read_word >> 8) & 0xff;
1595 msg[1].buf[1] = (read_word) & 0xff;
1600 static int dib8096p_tuner_rw_serpar(struct i2c_adapter *i2c_adap,
1601 struct i2c_msg msg[], int num)
1603 if (map_addr_to_serpar_number(&msg[0]) == 0) {
1604 if (num == 1) /* write */
1605 return dib8096p_tuner_write_serpar(i2c_adap, msg, 1);
1607 return dib8096p_tuner_read_serpar(i2c_adap, msg, 2);
1612 static int dib8096p_rw_on_apb(struct i2c_adapter *i2c_adap,
1613 struct i2c_msg msg[], int num, u16 apb_address)
1615 struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
1618 if (num == 1) { /* write */
1619 dib8000_write_word(state, apb_address,
1620 ((msg[0].buf[1] << 8) | (msg[0].buf[2])));
1622 word = dib8000_read_word(state, apb_address);
1623 msg[1].buf[0] = (word >> 8) & 0xff;
1624 msg[1].buf[1] = (word) & 0xff;
1629 static int dib8096p_tuner_xfer(struct i2c_adapter *i2c_adap,
1630 struct i2c_msg msg[], int num)
1632 struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
1633 u16 apb_address = 0, word;
1636 switch (msg[0].buf[0]) {
1722 /* get sad sel request */
1723 i = ((dib8000_read_word(state, 921) >> 12)&0x3);
1724 word = dib8000_read_word(state, 924+i);
1725 msg[1].buf[0] = (word >> 8) & 0xff;
1726 msg[1].buf[1] = (word) & 0xff;
1729 if (num == 1) { /* write */
1730 word = (u16) ((msg[0].buf[1] << 8) |
1732 /* in the VGAMODE Sel are located on bit 0/1 */
1734 word = (dib8000_read_word(state, 921) &
1735 ~(3<<12)) | (word<<12);
1736 /* Set the proper input */
1737 dib8000_write_word(state, 921, word);
1742 if (apb_address != 0) /* R/W acces via APB */
1743 return dib8096p_rw_on_apb(i2c_adap, msg, num, apb_address);
1744 else /* R/W access via SERPAR */
1745 return dib8096p_tuner_rw_serpar(i2c_adap, msg, num);
1750 static u32 dib8096p_i2c_func(struct i2c_adapter *adapter)
1752 return I2C_FUNC_I2C;
1755 static struct i2c_algorithm dib8096p_tuner_xfer_algo = {
1756 .master_xfer = dib8096p_tuner_xfer,
1757 .functionality = dib8096p_i2c_func,
1760 struct i2c_adapter *dib8096p_get_i2c_tuner(struct dvb_frontend *fe)
1762 struct dib8000_state *st = fe->demodulator_priv;
1763 return &st->dib8096p_tuner_adap;
1765 EXPORT_SYMBOL(dib8096p_get_i2c_tuner);
1767 int dib8096p_tuner_sleep(struct dvb_frontend *fe, int onoff)
1769 struct dib8000_state *state = fe->demodulator_priv;
1772 dprintk("sleep dib8096p: %d", onoff);
1774 en_cur_state = dib8000_read_word(state, 1922);
1776 /* LNAs and MIX are ON and therefore it is a valid configuration */
1777 if (en_cur_state > 0xff)
1778 state->tuner_enable = en_cur_state ;
1781 en_cur_state &= 0x00ff;
1783 if (state->tuner_enable != 0)
1784 en_cur_state = state->tuner_enable;
1787 dib8000_write_word(state, 1922, en_cur_state);
1791 EXPORT_SYMBOL(dib8096p_tuner_sleep);
1793 static const s32 lut_1000ln_mant[] =
1795 908, 7003, 7090, 7170, 7244, 7313, 7377, 7438, 7495, 7549, 7600
1798 s32 dib8000_get_adc_power(struct dvb_frontend *fe, u8 mode)
1800 struct dib8000_state *state = fe->demodulator_priv;
1801 u32 ix = 0, tmp_val = 0, exp = 0, mant = 0;
1804 val = dib8000_read32(state, 384);
1807 while (tmp_val >>= 1)
1809 mant = (val * 1000 / (1<<exp));
1810 ix = (u8)((mant-1000)/100); /* index of the LUT */
1811 val = (lut_1000ln_mant[ix] + 693*(exp-20) - 6908);
1812 val = (val*256)/1000;
1816 EXPORT_SYMBOL(dib8000_get_adc_power);
1818 int dib8090p_get_dc_power(struct dvb_frontend *fe, u8 IQ)
1820 struct dib8000_state *state = fe->demodulator_priv;
1825 val = dib8000_read_word(state, 403);
1828 val = dib8000_read_word(state, 404);
1836 EXPORT_SYMBOL(dib8090p_get_dc_power);
1838 static void dib8000_update_timf(struct dib8000_state *state)
1840 u32 timf = state->timf = dib8000_read32(state, 435);
1842 dib8000_write_word(state, 29, (u16) (timf >> 16));
1843 dib8000_write_word(state, 30, (u16) (timf & 0xffff));
1844 dprintk("Updated timing frequency: %d (default: %d)", state->timf, state->timf_default);
1847 u32 dib8000_ctrl_timf(struct dvb_frontend *fe, uint8_t op, uint32_t timf)
1849 struct dib8000_state *state = fe->demodulator_priv;
1852 case DEMOD_TIMF_SET:
1855 case DEMOD_TIMF_UPDATE:
1856 dib8000_update_timf(state);
1858 case DEMOD_TIMF_GET:
1861 dib8000_set_bandwidth(state->fe[0], 6000);
1865 EXPORT_SYMBOL(dib8000_ctrl_timf);
1867 static const u16 adc_target_16dB[11] = {
1868 (1 << 13) - 825 - 117,
1869 (1 << 13) - 837 - 117,
1870 (1 << 13) - 811 - 117,
1871 (1 << 13) - 766 - 117,
1872 (1 << 13) - 737 - 117,
1873 (1 << 13) - 693 - 117,
1874 (1 << 13) - 648 - 117,
1875 (1 << 13) - 619 - 117,
1876 (1 << 13) - 575 - 117,
1877 (1 << 13) - 531 - 117,
1878 (1 << 13) - 501 - 117
1880 static const u8 permu_seg[] = { 6, 5, 7, 4, 8, 3, 9, 2, 10, 1, 11, 0, 12 };
1882 static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosearching)
1884 u16 mode, max_constellation, seg_diff_mask = 0, nbseg_diff = 0;
1885 u8 guard, crate, constellation, timeI;
1886 u16 i, coeff[4], P_cfr_left_edge = 0, P_cfr_right_edge = 0, seg_mask13 = 0x1fff; // All 13 segments enabled
1887 const s16 *ncoeff = NULL, *ana_fe;
1889 u16 coff_pow = 0x2800;
1890 u16 init_prbs = 0xfff;
1893 if (state->revision == 0x8090)
1894 dib8000_init_sdram(state);
1896 if (state->ber_monitored_layer != LAYER_ALL)
1897 dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & 0x60) | state->ber_monitored_layer);
1899 dib8000_write_word(state, 285, dib8000_read_word(state, 285) & 0x60);
1901 i = dib8000_read_word(state, 26) & 1; // P_dds_invspec
1902 dib8000_write_word(state, 26, state->fe[0]->dtv_property_cache.inversion^i);
1904 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode) {
1905 //compute new dds_freq for the seg and adjust prbs
1907 state->fe[0]->dtv_property_cache.isdbt_sb_segment_idx -
1908 (state->fe[0]->dtv_property_cache.isdbt_sb_segment_count / 2) -
1909 (state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2);
1910 int clk = state->cfg.pll->internal;
1911 u32 segtodds = ((u32) (430 << 23) / clk) << 3; // segtodds = SegBW / Fclk * pow(2,26)
1912 int dds_offset = seg_offset * segtodds;
1913 int new_dds, sub_channel;
1914 if ((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
1915 dds_offset -= (int)(segtodds / 2);
1917 if (state->cfg.pll->ifreq == 0) {
1918 if ((state->fe[0]->dtv_property_cache.inversion ^ i) == 0) {
1919 dib8000_write_word(state, 26, dib8000_read_word(state, 26) | 1);
1920 new_dds = dds_offset;
1922 new_dds = dds_offset;
1924 // We shift tuning frequency if the wanted segment is :
1925 // - the segment of center frequency with an odd total number of segments
1926 // - the segment to the left of center frequency with an even total number of segments
1927 // - the segment to the right of center frequency with an even total number of segments
1928 if ((state->fe[0]->dtv_property_cache.delivery_system == SYS_ISDBT)
1929 && (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1)
1930 && (((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2)
1931 && (state->fe[0]->dtv_property_cache.isdbt_sb_segment_idx ==
1932 ((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count / 2) + 1)))
1933 || (((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
1934 && (state->fe[0]->dtv_property_cache.isdbt_sb_segment_idx == (state->fe[0]->dtv_property_cache.isdbt_sb_segment_count / 2)))
1935 || (((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
1936 && (state->fe[0]->dtv_property_cache.isdbt_sb_segment_idx ==
1937 ((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count / 2) + 1)))
1939 new_dds -= ((u32) (850 << 22) / clk) << 4; // new_dds = 850 (freq shift in KHz) / Fclk * pow(2,26)
1942 if ((state->fe[0]->dtv_property_cache.inversion ^ i) == 0)
1943 new_dds = state->cfg.pll->ifreq - dds_offset;
1945 new_dds = state->cfg.pll->ifreq + dds_offset;
1947 dib8000_write_word(state, 27, (u16) ((new_dds >> 16) & 0x01ff));
1948 dib8000_write_word(state, 28, (u16) (new_dds & 0xffff));
1949 if (state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2)
1950 sub_channel = ((state->fe[0]->dtv_property_cache.isdbt_sb_subchannel + (3 * seg_offset) + 1) % 41) / 3;
1952 sub_channel = ((state->fe[0]->dtv_property_cache.isdbt_sb_subchannel + (3 * seg_offset)) % 41) / 3;
1955 if (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_2K
1956 || state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_4K) {
1957 dib8000_write_word(state, 219, dib8000_read_word(state, 219) | 0x1); //adp_pass =1
1958 dib8000_write_word(state, 190, dib8000_read_word(state, 190) | (0x1 << 14)); //pha3_force_pha_shift = 1
1960 dib8000_write_word(state, 219, dib8000_read_word(state, 219) & 0xfffe); //adp_pass =0
1961 dib8000_write_word(state, 190, dib8000_read_word(state, 190) & 0xbfff); //pha3_force_pha_shift = 0
1964 switch (state->fe[0]->dtv_property_cache.transmission_mode) {
1965 case TRANSMISSION_MODE_2K:
1966 switch (sub_channel) {
2013 case TRANSMISSION_MODE_4K:
2014 switch (sub_channel) {
2062 case TRANSMISSION_MODE_8K:
2063 switch (sub_channel) {
2111 dib8000_write_word(state, 27, (u16) ((state->cfg.pll->ifreq >> 16) & 0x01ff));
2112 dib8000_write_word(state, 28, (u16) (state->cfg.pll->ifreq & 0xffff));
2113 dib8000_write_word(state, 26, (u16) ((state->cfg.pll->ifreq >> 25) & 0x0003));
2116 dib8000_write_word(state, 10, (seq << 4));
2117 // dib8000_write_word(state, 287, (dib8000_read_word(state, 287) & 0xe000) | 0x1000);
2119 switch (state->fe[0]->dtv_property_cache.guard_interval) {
2120 case GUARD_INTERVAL_1_32:
2123 case GUARD_INTERVAL_1_16:
2126 case GUARD_INTERVAL_1_8:
2129 case GUARD_INTERVAL_1_4:
2135 dib8000_write_word(state, 1, (init_prbs << 2) | (guard & 0x3)); // ADDR 1
2137 max_constellation = DQPSK;
2138 for (i = 0; i < 3; i++) {
2139 switch (state->fe[0]->dtv_property_cache.layer[i].modulation) {
2155 switch (state->fe[0]->dtv_property_cache.layer[i].fec) {
2174 if ((state->fe[0]->dtv_property_cache.layer[i].interleaving > 0) &&
2175 ((state->fe[0]->dtv_property_cache.layer[i].interleaving <= 3) ||
2176 (state->fe[0]->dtv_property_cache.layer[i].interleaving == 4 && state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1))
2178 timeI = state->fe[0]->dtv_property_cache.layer[i].interleaving;
2181 dib8000_write_word(state, 2 + i, (constellation << 10) | ((state->fe[0]->dtv_property_cache.layer[i].segment_count & 0xf) << 6) |
2182 (crate << 3) | timeI);
2183 if (state->fe[0]->dtv_property_cache.layer[i].segment_count > 0) {
2184 switch (max_constellation) {
2187 if (state->fe[0]->dtv_property_cache.layer[i].modulation == QAM_16 ||
2188 state->fe[0]->dtv_property_cache.layer[i].modulation == QAM_64)
2189 max_constellation = state->fe[0]->dtv_property_cache.layer[i].modulation;
2192 if (state->fe[0]->dtv_property_cache.layer[i].modulation == QAM_64)
2193 max_constellation = state->fe[0]->dtv_property_cache.layer[i].modulation;
2199 mode = fft_to_mode(state);
2201 //dib8000_write_word(state, 5, 13); /*p_last_seg = 13*/
2203 dib8000_write_word(state, 274, (dib8000_read_word(state, 274) & 0xffcf) |
2204 ((state->fe[0]->dtv_property_cache.isdbt_partial_reception & 1) << 5) | ((state->fe[0]->dtv_property_cache.
2205 isdbt_sb_mode & 1) << 4));
2207 dprintk("mode = %d ; guard = %d", mode, state->fe[0]->dtv_property_cache.guard_interval);
2209 /* signal optimization parameter */
2211 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception) {
2212 seg_diff_mask = (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) << permu_seg[0];
2213 for (i = 1; i < 3; i++)
2215 (state->fe[0]->dtv_property_cache.layer[i].modulation == DQPSK) * state->fe[0]->dtv_property_cache.layer[i].segment_count;
2216 for (i = 0; i < nbseg_diff; i++)
2217 seg_diff_mask |= 1 << permu_seg[i + 1];
2219 for (i = 0; i < 3; i++)
2221 (state->fe[0]->dtv_property_cache.layer[i].modulation == DQPSK) * state->fe[0]->dtv_property_cache.layer[i].segment_count;
2222 for (i = 0; i < nbseg_diff; i++)
2223 seg_diff_mask |= 1 << permu_seg[i];
2225 dprintk("nbseg_diff = %X (%d)", seg_diff_mask, seg_diff_mask);
2227 state->differential_constellation = (seg_diff_mask != 0);
2228 if (state->revision != 0x8090)
2229 dib8000_set_diversity_in(state->fe[0], state->diversity_onoff);
2231 dib8096p_set_diversity_in(state->fe[0], state->diversity_onoff);
2233 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
2234 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 1)
2235 seg_mask13 = 0x00E0;
2237 seg_mask13 = 0x0040;
2239 seg_mask13 = 0x1fff;
2241 // WRITE: Mode & Diff mask
2242 dib8000_write_word(state, 0, (mode << 13) | seg_diff_mask);
2244 if ((seg_diff_mask) || (state->fe[0]->dtv_property_cache.isdbt_sb_mode))
2245 dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200);
2247 dib8000_write_word(state, 268, (2 << 9) | 39); //init value
2251 dib8000_write_word(state, 352, seg_diff_mask); // ADDR 352
2253 dib8000_write_word(state, 353, seg_mask13); // ADDR 353
2255 /* // P_small_narrow_band=0, P_small_last_seg=13, P_small_offset_num_car=5 */
2258 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
2259 switch (state->fe[0]->dtv_property_cache.transmission_mode) {
2260 case TRANSMISSION_MODE_2K:
2261 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {
2262 if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK)
2263 ncoeff = coeff_2k_sb_1seg_dqpsk;
2265 ncoeff = coeff_2k_sb_1seg;
2266 } else { // 3-segments
2267 if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) {
2268 if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK)
2269 ncoeff = coeff_2k_sb_3seg_0dqpsk_1dqpsk;
2270 else // QPSK or QAM on external segments
2271 ncoeff = coeff_2k_sb_3seg_0dqpsk;
2272 } else { // QPSK or QAM on central segment
2273 if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK)
2274 ncoeff = coeff_2k_sb_3seg_1dqpsk;
2275 else // QPSK or QAM on external segments
2276 ncoeff = coeff_2k_sb_3seg;
2281 case TRANSMISSION_MODE_4K:
2282 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {
2283 if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK)
2284 ncoeff = coeff_4k_sb_1seg_dqpsk;
2286 ncoeff = coeff_4k_sb_1seg;
2287 } else { // 3-segments
2288 if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) {
2289 if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) {
2290 ncoeff = coeff_4k_sb_3seg_0dqpsk_1dqpsk;
2291 } else { // QPSK or QAM on external segments
2292 ncoeff = coeff_4k_sb_3seg_0dqpsk;
2294 } else { // QPSK or QAM on central segment
2295 if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) {
2296 ncoeff = coeff_4k_sb_3seg_1dqpsk;
2297 } else // QPSK or QAM on external segments
2298 ncoeff = coeff_4k_sb_3seg;
2303 case TRANSMISSION_MODE_AUTO:
2304 case TRANSMISSION_MODE_8K:
2306 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {
2307 if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK)
2308 ncoeff = coeff_8k_sb_1seg_dqpsk;
2310 ncoeff = coeff_8k_sb_1seg;
2311 } else { // 3-segments
2312 if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) {
2313 if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) {
2314 ncoeff = coeff_8k_sb_3seg_0dqpsk_1dqpsk;
2315 } else { // QPSK or QAM on external segments
2316 ncoeff = coeff_8k_sb_3seg_0dqpsk;
2318 } else { // QPSK or QAM on central segment
2319 if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) {
2320 ncoeff = coeff_8k_sb_3seg_1dqpsk;
2321 } else // QPSK or QAM on external segments
2322 ncoeff = coeff_8k_sb_3seg;
2327 for (i = 0; i < 8; i++)
2328 dib8000_write_word(state, 343 + i, ncoeff[i]);
2331 // P_small_coef_ext_enable=ISDB-Tsb, P_small_narrow_band=ISDB-Tsb, P_small_last_seg=13, P_small_offset_num_car=5
2332 dib8000_write_word(state, 351,
2333 (state->fe[0]->dtv_property_cache.isdbt_sb_mode << 9) | (state->fe[0]->dtv_property_cache.isdbt_sb_mode << 8) | (13 << 4) | 5);
2336 // Carloff, the most robust
2337 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
2339 // P_coff_cpil_alpha=4, P_coff_inh=0, P_coff_cpil_winlen=64
2340 // P_coff_narrow_band=1, P_coff_square_val=1, P_coff_one_seg=~partial_rcpt, P_coff_use_tmcc=1, P_coff_use_ac=1
2341 dib8000_write_word(state, 187,
2342 (4 << 12) | (0 << 11) | (63 << 5) | (0x3 << 3) | ((~state->fe[0]->dtv_property_cache.isdbt_partial_reception & 1) << 2)
2345 /* // P_small_coef_ext_enable = 1 */
2346 /* dib8000_write_word(state, 351, dib8000_read_word(state, 351) | 0x200); */
2348 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {
2350 // P_coff_winlen=63, P_coff_thres_lock=15, P_coff_one_seg_width= (P_mode == 3) , P_coff_one_seg_sym= (P_mode-1)
2352 dib8000_write_word(state, 180, 0x1fcf | ((mode - 1) << 14));
2354 dib8000_write_word(state, 180, 0x0fcf | ((mode - 1) << 14));
2355 // P_ctrl_corm_thres4pre_freq_inh=1,P_ctrl_pre_freq_mode_sat=1,
2356 // P_ctrl_pre_freq_inh=0, P_ctrl_pre_freq_step = 5, P_pre_freq_win_len=4
2357 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (5 << 5) | 4);
2358 // P_ctrl_pre_freq_win_len=16, P_ctrl_pre_freq_thres_lockin=8
2359 dib8000_write_word(state, 340, (16 << 6) | (8 << 0));
2360 // P_ctrl_pre_freq_thres_lockout=6, P_small_use_tmcc/ac/cp=1
2361 dib8000_write_word(state, 341, (6 << 3) | (1 << 2) | (1 << 1) | (1 << 0));
2363 // P_coff_corthres_8k, 4k, 2k and P_coff_cpilthres_8k, 4k, 2k
2364 dib8000_write_word(state, 181, 300);
2365 dib8000_write_word(state, 182, 150);
2366 dib8000_write_word(state, 183, 80);
2367 dib8000_write_word(state, 184, 300);
2368 dib8000_write_word(state, 185, 150);
2369 dib8000_write_word(state, 186, 80);
2370 } else { // Sound Broadcasting mode 3 seg
2371 // P_coff_one_seg_sym= 1, P_coff_one_seg_width= 1, P_coff_winlen=63, P_coff_thres_lock=15
2372 /* if (mode == 3) */
2373 /* dib8000_write_word(state, 180, 0x2fca | ((0) << 14)); */
2375 /* dib8000_write_word(state, 180, 0x2fca | ((1) << 14)); */
2376 dib8000_write_word(state, 180, 0x1fcf | (1 << 14));
2378 // P_ctrl_corm_thres4pre_freq_inh = 1, P_ctrl_pre_freq_mode_sat=1,
2379 // P_ctrl_pre_freq_inh=0, P_ctrl_pre_freq_step = 4, P_pre_freq_win_len=4
2380 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (4 << 5) | 4);
2381 // P_ctrl_pre_freq_win_len=16, P_ctrl_pre_freq_thres_lockin=8
2382 dib8000_write_word(state, 340, (16 << 6) | (8 << 0));
2383 //P_ctrl_pre_freq_thres_lockout=6, P_small_use_tmcc/ac/cp=1
2384 dib8000_write_word(state, 341, (6 << 3) | (1 << 2) | (1 << 1) | (1 << 0));
2386 // P_coff_corthres_8k, 4k, 2k and P_coff_cpilthres_8k, 4k, 2k
2387 dib8000_write_word(state, 181, 350);
2388 dib8000_write_word(state, 182, 300);
2389 dib8000_write_word(state, 183, 250);
2390 dib8000_write_word(state, 184, 350);
2391 dib8000_write_word(state, 185, 300);
2392 dib8000_write_word(state, 186, 250);
2395 } else if (state->isdbt_cfg_loaded == 0) { // if not Sound Broadcasting mode : put default values for 13 segments
2396 dib8000_write_word(state, 180, (16 << 6) | 9);
2397 dib8000_write_word(state, 187, (4 << 12) | (8 << 5) | 0x2);
2399 for (i = 0; i < 6; i++)
2400 dib8000_write_word(state, 181 + i, coff_pow);
2402 // P_ctrl_corm_thres4pre_freq_inh=1, P_ctrl_pre_freq_mode_sat=1,
2403 // P_ctrl_pre_freq_mode_sat=1, P_ctrl_pre_freq_inh=0, P_ctrl_pre_freq_step = 3, P_pre_freq_win_len=1
2404 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (3 << 5) | 1);
2406 // P_ctrl_pre_freq_win_len=8, P_ctrl_pre_freq_thres_lockin=6
2407 dib8000_write_word(state, 340, (8 << 6) | (6 << 0));
2408 // P_ctrl_pre_freq_thres_lockout=4, P_small_use_tmcc/ac/cp=1
2409 dib8000_write_word(state, 341, (4 << 3) | (1 << 2) | (1 << 1) | (1 << 0));
2412 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1 && state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0)
2413 dib8000_write_word(state, 178, 64); // P_fft_powrange=64
2415 dib8000_write_word(state, 178, 32); // P_fft_powrange=32
2417 /* make the cpil_coff_lock more robust but slower p_coff_winlen
2418 * 6bits; p_coff_thres_lock 6bits (for coff lock if needed)
2420 /* if ( ( nbseg_diff>0)&&(nbseg_diff<13))
2421 dib8000_write_word(state, 187, (dib8000_read_word(state, 187) & 0xfffb) | (1 << 3)); */
2423 dib8000_write_word(state, 189, ~seg_mask13 | seg_diff_mask); /* P_lmod4_seg_inh */
2424 dib8000_write_word(state, 192, ~seg_mask13 | seg_diff_mask); /* P_pha3_seg_inh */
2425 dib8000_write_word(state, 225, ~seg_mask13 | seg_diff_mask); /* P_tac_seg_inh */
2426 if ((!state->fe[0]->dtv_property_cache.isdbt_sb_mode) && (state->cfg.pll->ifreq == 0))
2427 dib8000_write_word(state, 266, ~seg_mask13 | seg_diff_mask | 0x40); /* P_equal_noise_seg_inh */
2429 dib8000_write_word(state, 266, ~seg_mask13 | seg_diff_mask); /* P_equal_noise_seg_inh */
2430 dib8000_write_word(state, 287, ~seg_mask13 | 0x1000); /* P_tmcc_seg_inh */
2431 //dib8000_write_word(state, 288, ~seg_mask13 | seg_diff_mask); /* P_tmcc_seg_eq_inh */
2433 dib8000_write_word(state, 288, (~seg_mask13 | seg_diff_mask) & 0x1fff); /* P_tmcc_seg_eq_inh */
2435 dib8000_write_word(state, 288, 0x1fff); //disable equalisation of the tmcc when autosearch to be able to find the DQPSK channels.
2436 dprintk("287 = %X (%d)", ~seg_mask13 | 0x1000, ~seg_mask13 | 0x1000);
2438 dib8000_write_word(state, 211, seg_mask13 & (~seg_diff_mask)); /* P_des_seg_enabled */
2440 /* offset loop parameters */
2441 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
2442 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0)
2443 /* P_timf_alpha = (11-P_mode), P_corm_alpha=6, P_corm_thres=0x80 */
2444 dib8000_write_word(state, 32, ((11 - mode) << 12) | (6 << 8) | 0x40);
2446 else // Sound Broadcasting mode 3 seg
2447 /* P_timf_alpha = (10-P_mode), P_corm_alpha=6, P_corm_thres=0x80 */
2448 dib8000_write_word(state, 32, ((10 - mode) << 12) | (6 << 8) | 0x60);
2450 // TODO in 13 seg, timf_alpha can always be the same or not ?
2451 /* P_timf_alpha = (9-P_mode, P_corm_alpha=6, P_corm_thres=0x80 */
2452 dib8000_write_word(state, 32, ((9 - mode) << 12) | (6 << 8) | 0x80);
2454 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
2455 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0)
2456 /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = (11-P_mode) */
2457 dib8000_write_word(state, 37, (3 << 5) | (0 << 4) | (10 - mode));
2459 else // Sound Broadcasting mode 3 seg
2460 /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = (10-P_mode) */
2461 dib8000_write_word(state, 37, (3 << 5) | (0 << 4) | (9 - mode));
2463 /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = 9 */
2464 dib8000_write_word(state, 37, (3 << 5) | (0 << 4) | (8 - mode));
2466 /* P_dvsy_sync_wait - reuse mode */
2467 switch (state->fe[0]->dtv_property_cache.transmission_mode) {
2468 case TRANSMISSION_MODE_8K:
2471 case TRANSMISSION_MODE_4K:
2475 case TRANSMISSION_MODE_2K:
2479 if (state->cfg.diversity_delay == 0)
2480 mode = (mode * (1 << (guard)) * 3) / 2 + 48; // add 50% SFN margin + compensate for one DVSY-fifo
2482 mode = (mode * (1 << (guard)) * 3) / 2 + state->cfg.diversity_delay; // add 50% SFN margin + compensate for DVSY-fifo
2484 dib8000_write_word(state, 273, (dib8000_read_word(state, 273) & 0x000f) | mode);
2486 /* channel estimation fine configuration */
2487 switch (max_constellation) {
2489 ana_gain = 0x7; // -1 : avoid def_est saturation when ADC target is -16dB
2490 coeff[0] = 0x0148; /* P_adp_regul_cnt 0.04 */
2491 coeff[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */
2492 coeff[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
2493 coeff[3] = 0xfff8; /* P_adp_noise_ext -0.001 */
2494 //if (!state->cfg.hostbus_diversity) //if diversity, we should prehaps use the configuration of the max_constallation -1
2497 ana_gain = 0x7; // -1 : avoid def_est saturation when ADC target is -16dB
2498 coeff[0] = 0x023d; /* P_adp_regul_cnt 0.07 */
2499 coeff[1] = 0xffdf; /* P_adp_noise_cnt -0.004 */
2500 coeff[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
2501 coeff[3] = 0xfff0; /* P_adp_noise_ext -0.002 */
2502 //if (!((state->cfg.hostbus_diversity) && (max_constellation == QAM_16)))
2505 ana_gain = 0; // 0 : goes along with ADC target at -22dB to keep good mobile performance and lock at sensitivity level
2506 coeff[0] = 0x099a; /* P_adp_regul_cnt 0.3 */
2507 coeff[1] = 0xffae; /* P_adp_noise_cnt -0.01 */
2508 coeff[2] = 0x0333; /* P_adp_regul_ext 0.1 */
2509 coeff[3] = 0xfff8; /* P_adp_noise_ext -0.002 */
2512 for (mode = 0; mode < 4; mode++)
2513 dib8000_write_word(state, 215 + mode, coeff[mode]);
2515 // update ana_gain depending on max constellation
2516 dib8000_write_word(state, 116, ana_gain);
2517 // update ADC target depending on ana_gain
2518 if (ana_gain) { // set -16dB ADC target for ana_gain=-1
2519 for (i = 0; i < 10; i++)
2520 dib8000_write_word(state, 80 + i, adc_target_16dB[i]);
2521 } else { // set -22dB ADC target for ana_gain=0
2522 for (i = 0; i < 10; i++)
2523 dib8000_write_word(state, 80 + i, adc_target_16dB[i] - 355);
2527 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode) {
2528 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 1)
2529 ana_fe = ana_fe_coeff_3seg;
2531 ana_fe = ana_fe_coeff_1seg;
2533 ana_fe = ana_fe_coeff_13seg;
2535 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1 || state->isdbt_cfg_loaded == 0)
2536 for (mode = 0; mode < 24; mode++)
2537 dib8000_write_word(state, 117 + mode, ana_fe[mode]);
2539 // ---- CHAN_BLK ----
2540 for (i = 0; i < 13; i++) {
2541 if ((((~seg_diff_mask) >> i) & 1) == 1) {
2542 P_cfr_left_edge += (1 << i) * ((i == 0) || ((((seg_mask13 & (~seg_diff_mask)) >> (i - 1)) & 1) == 0));
2543 P_cfr_right_edge += (1 << i) * ((i == 12) || ((((seg_mask13 & (~seg_diff_mask)) >> (i + 1)) & 1) == 0));
2546 dib8000_write_word(state, 222, P_cfr_left_edge); // P_cfr_left_edge
2547 dib8000_write_word(state, 223, P_cfr_right_edge); // P_cfr_right_edge
2548 // "P_cspu_left_edge" not used => do not care
2549 // "P_cspu_right_edge" not used => do not care
2551 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
2552 dib8000_write_word(state, 228, 1); // P_2d_mode_byp=1
2553 dib8000_write_word(state, 205, dib8000_read_word(state, 205) & 0xfff0); // P_cspu_win_cut = 0
2554 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0
2555 && state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_2K) {
2556 //dib8000_write_word(state, 219, dib8000_read_word(state, 219) & 0xfffe); // P_adp_pass = 0
2557 dib8000_write_word(state, 265, 15); // P_equal_noise_sel = 15
2559 } else if (state->isdbt_cfg_loaded == 0) {
2560 dib8000_write_word(state, 228, 0); // default value
2561 dib8000_write_word(state, 265, 31); // default value
2562 dib8000_write_word(state, 205, 0x200f); // init value
2565 for (i = 0; i < 3; i++)
2567 (((state->fe[0]->dtv_property_cache.layer[i].modulation == DQPSK) * 4 + 1) * state->fe[0]->dtv_property_cache.layer[i].segment_count);
2568 // Quantif of "P_tmcc_dec_thres_?k" is (0, 5+mode, 9);
2569 // Threshold is set at 1/4 of max power.
2570 tmcc_pow *= (1 << (9 - 2));
2572 dib8000_write_word(state, 290, tmcc_pow); // P_tmcc_dec_thres_2k
2573 dib8000_write_word(state, 291, tmcc_pow); // P_tmcc_dec_thres_4k
2574 dib8000_write_word(state, 292, tmcc_pow); // P_tmcc_dec_thres_8k
2575 //dib8000_write_word(state, 287, (1 << 13) | 0x1000 );
2578 if (state->isdbt_cfg_loaded == 0)
2579 dib8000_write_word(state, 250, 3285); /*p_2d_hspeed_thr0 */
2581 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1)
2582 state->isdbt_cfg_loaded = 0;
2584 state->isdbt_cfg_loaded = 1;
2588 static int dib8000_autosearch_start(struct dvb_frontend *fe)
2592 struct dib8000_state *state = fe->demodulator_priv;
2596 state->fe[0]->dtv_property_cache.inversion = 0;
2597 if (!state->fe[0]->dtv_property_cache.isdbt_sb_mode)
2598 state->fe[0]->dtv_property_cache.layer[0].segment_count = 13;
2599 state->fe[0]->dtv_property_cache.layer[0].modulation = QAM_64;
2600 state->fe[0]->dtv_property_cache.layer[0].fec = FEC_2_3;
2601 state->fe[0]->dtv_property_cache.layer[0].interleaving = 0;
2603 //choose the right list, in sb, always do everything
2604 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode) {
2605 state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K;
2606 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8;
2608 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13));
2610 if (state->fe[0]->dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO) {
2611 if (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO) {
2613 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); // P_mode = 1 to have autosearch start ok with mode2
2617 if (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO) {
2619 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); // P_mode = 1
2624 if (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO)
2625 state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K;
2626 if (state->fe[0]->dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO)
2627 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8;
2629 dprintk("using list for autosearch : %d", slist);
2630 dib8000_set_channel(state, (unsigned char)slist, 1);
2631 //dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); // P_mode = 1
2635 //set lock_mask values
2636 dib8000_write_word(state, 6, 0x4);
2637 dib8000_write_word(state, 7, 0x8);
2638 dib8000_write_word(state, 8, 0x1000);
2640 //set lock_mask wait time values
2641 value = 50 * state->cfg.pll->internal * factor;
2642 dib8000_write_word(state, 11, (u16) ((value >> 16) & 0xffff)); // lock0 wait time
2643 dib8000_write_word(state, 12, (u16) (value & 0xffff)); // lock0 wait time
2644 value = 100 * state->cfg.pll->internal * factor;
2645 dib8000_write_word(state, 13, (u16) ((value >> 16) & 0xffff)); // lock1 wait time
2646 dib8000_write_word(state, 14, (u16) (value & 0xffff)); // lock1 wait time
2647 value = 1000 * state->cfg.pll->internal * factor;
2648 dib8000_write_word(state, 15, (u16) ((value >> 16) & 0xffff)); // lock2 wait time
2649 dib8000_write_word(state, 16, (u16) (value & 0xffff)); // lock2 wait time
2651 value = dib8000_read_word(state, 0);
2652 dib8000_write_word(state, 0, (u16) ((1 << 15) | value));
2653 dib8000_read_word(state, 1284); // reset the INT. n_irq_pending
2654 dib8000_write_word(state, 0, (u16) value);
2661 static int dib8000_autosearch_irq(struct dvb_frontend *fe)
2663 struct dib8000_state *state = fe->demodulator_priv;
2664 u16 irq_pending = dib8000_read_word(state, 1284);
2666 if (irq_pending & 0x1) { // failed
2667 dprintk("dib8000_autosearch_irq failed");
2671 if (irq_pending & 0x2) { // succeeded
2672 dprintk("dib8000_autosearch_irq succeeded");
2676 return 0; // still pending
2679 static int dib8000_tune(struct dvb_frontend *fe)
2681 struct dib8000_state *state = fe->demodulator_priv;
2683 u16 lock, value, mode;
2685 // we are already tuned - just resuming from suspend
2689 mode = fft_to_mode(state);
2691 dib8000_set_bandwidth(fe, state->fe[0]->dtv_property_cache.bandwidth_hz / 1000);
2692 dib8000_set_channel(state, 0, 0);
2695 ret |= dib8000_write_word(state, 770, 0x4000);
2696 ret |= dib8000_write_word(state, 770, 0x0000);
2699 /* P_ctrl_inh_cor=0, P_ctrl_alpha_cor=4, P_ctrl_inh_isi=0, P_ctrl_alpha_isi=3 */
2700 /* ret |= dib8000_write_word(state, 29, (0 << 9) | (4 << 5) | (0 << 4) | (3 << 0) ); workaround inh_isi stays at 1 */
2702 // never achieved a lock before - wait for timfreq to update
2703 if (state->timf == 0) {
2704 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
2705 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0)
2707 else // Sound Broadcasting mode 3 seg
2712 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
2713 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {
2715 /* P_timf_alpha = (13-P_mode) , P_corm_alpha=6, P_corm_thres=0x40 alpha to check on board */
2716 dib8000_write_word(state, 32, ((13 - mode) << 12) | (6 << 8) | 0x40);
2717 //dib8000_write_word(state, 32, (8 << 12) | (6 << 8) | 0x80);
2719 /* P_ctrl_sfreq_step= (12-P_mode) P_ctrl_sfreq_inh =0 P_ctrl_pha_off_max */
2720 ret |= dib8000_write_word(state, 37, (12 - mode) | ((5 + mode) << 5));
2722 } else { // Sound Broadcasting mode 3 seg
2724 /* P_timf_alpha = (12-P_mode) , P_corm_alpha=6, P_corm_thres=0x60 alpha to check on board */
2725 dib8000_write_word(state, 32, ((12 - mode) << 12) | (6 << 8) | 0x60);
2727 ret |= dib8000_write_word(state, 37, (11 - mode) | ((5 + mode) << 5));
2731 /* P_timf_alpha = 8 , P_corm_alpha=6, P_corm_thres=0x80 alpha to check on board */
2732 dib8000_write_word(state, 32, ((11 - mode) << 12) | (6 << 8) | 0x80);
2734 ret |= dib8000_write_word(state, 37, (10 - mode) | ((5 + mode) << 5));
2738 // we achieved a coff_cpil_lock - it's time to update the timf
2739 if (state->revision != 0x8090)
2740 lock = dib8000_read_word(state, 568);
2742 lock = dib8000_read_word(state, 570);
2743 if ((lock >> 11) & 0x1)
2744 dib8000_update_timf(state);
2746 //now that tune is finished, lock0 should lock on fec_mpeg to output this lock on MP_LOCK. It's changed in autosearch start
2747 dib8000_write_word(state, 6, 0x200);
2749 if (state->revision == 0x8002) {
2750 value = dib8000_read_word(state, 903);
2751 dib8000_write_word(state, 903, value & ~(1 << 3));
2753 dib8000_write_word(state, 903, value | (1 << 3));
2759 static int dib8000_wakeup(struct dvb_frontend *fe)
2761 struct dib8000_state *state = fe->demodulator_priv;
2765 dib8000_set_power_mode(state, DIB8000_POWER_ALL);
2766 dib8000_set_adc_state(state, DIBX000_ADC_ON);
2767 if (dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0)
2768 dprintk("could not start Slow ADC");
2770 if (state->revision != 0x8090)
2771 dib8000_sad_calib(state);
2773 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
2774 ret = state->fe[index_frontend]->ops.init(state->fe[index_frontend]);
2782 static int dib8000_sleep(struct dvb_frontend *fe)
2784 struct dib8000_state *state = fe->demodulator_priv;
2788 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
2789 ret = state->fe[index_frontend]->ops.sleep(state->fe[index_frontend]);
2794 if (state->revision != 0x8090)
2795 dib8000_set_output_mode(fe, OUTMODE_HIGH_Z);
2796 dib8000_set_power_mode(state, DIB8000_POWER_INTERFACE_ONLY);
2797 return dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF) | dib8000_set_adc_state(state, DIBX000_ADC_OFF);
2800 enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend *fe)
2802 struct dib8000_state *state = fe->demodulator_priv;
2803 return state->tune_state;
2805 EXPORT_SYMBOL(dib8000_get_tune_state);
2807 int dib8000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
2809 struct dib8000_state *state = fe->demodulator_priv;
2810 state->tune_state = tune_state;
2813 EXPORT_SYMBOL(dib8000_set_tune_state);
2815 static int dib8000_get_frontend(struct dvb_frontend *fe)
2817 struct dib8000_state *state = fe->demodulator_priv;
2820 u8 index_frontend, sub_index_frontend;
2822 fe->dtv_property_cache.bandwidth_hz = 6000000;
2824 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
2825 state->fe[index_frontend]->ops.read_status(state->fe[index_frontend], &stat);
2826 if (stat&FE_HAS_SYNC) {
2827 dprintk("TMCC lock on the slave%i", index_frontend);
2828 /* synchronize the cache with the other frontends */
2829 state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend]);
2830 for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_index_frontend] != NULL); sub_index_frontend++) {
2831 if (sub_index_frontend != index_frontend) {
2832 state->fe[sub_index_frontend]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode;
2833 state->fe[sub_index_frontend]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_property_cache.inversion;
2834 state->fe[sub_index_frontend]->dtv_property_cache.transmission_mode = state->fe[index_frontend]->dtv_property_cache.transmission_mode;
2835 state->fe[sub_index_frontend]->dtv_property_cache.guard_interval = state->fe[index_frontend]->dtv_property_cache.guard_interval;
2836 state->fe[sub_index_frontend]->dtv_property_cache.isdbt_partial_reception = state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception;
2837 for (i = 0; i < 3; i++) {
2838 state->fe[sub_index_frontend]->dtv_property_cache.layer[i].segment_count = state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count;
2839 state->fe[sub_index_frontend]->dtv_property_cache.layer[i].interleaving = state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving;
2840 state->fe[sub_index_frontend]->dtv_property_cache.layer[i].fec = state->fe[index_frontend]->dtv_property_cache.layer[i].fec;
2841 state->fe[sub_index_frontend]->dtv_property_cache.layer[i].modulation = state->fe[index_frontend]->dtv_property_cache.layer[i].modulation;
2849 fe->dtv_property_cache.isdbt_sb_mode = dib8000_read_word(state, 508) & 0x1;
2851 if (state->revision == 0x8090)
2852 val = dib8000_read_word(state, 572);
2854 val = dib8000_read_word(state, 570);
2855 fe->dtv_property_cache.inversion = (val & 0x40) >> 6;
2856 switch ((val & 0x30) >> 4) {
2858 fe->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_2K;
2862 fe->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K;
2866 switch (val & 0x3) {
2868 fe->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_32;
2869 dprintk("dib8000_get_frontend GI = 1/32 ");
2872 fe->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_16;
2873 dprintk("dib8000_get_frontend GI = 1/16 ");
2876 dprintk("dib8000_get_frontend GI = 1/8 ");
2877 fe->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8;
2880 dprintk("dib8000_get_frontend GI = 1/4 ");
2881 fe->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_4;
2885 val = dib8000_read_word(state, 505);
2886 fe->dtv_property_cache.isdbt_partial_reception = val & 1;
2887 dprintk("dib8000_get_frontend : partial_reception = %d ", fe->dtv_property_cache.isdbt_partial_reception);
2889 for (i = 0; i < 3; i++) {
2890 val = dib8000_read_word(state, 493 + i);
2891 fe->dtv_property_cache.layer[i].segment_count = val & 0x0F;
2892 dprintk("dib8000_get_frontend : Layer %d segments = %d ", i, fe->dtv_property_cache.layer[i].segment_count);
2894 val = dib8000_read_word(state, 499 + i);
2895 fe->dtv_property_cache.layer[i].interleaving = val & 0x3;
2896 dprintk("dib8000_get_frontend : Layer %d time_intlv = %d ", i, fe->dtv_property_cache.layer[i].interleaving);
2898 val = dib8000_read_word(state, 481 + i);
2899 switch (val & 0x7) {
2901 fe->dtv_property_cache.layer[i].fec = FEC_1_2;
2902 dprintk("dib8000_get_frontend : Layer %d Code Rate = 1/2 ", i);
2905 fe->dtv_property_cache.layer[i].fec = FEC_2_3;
2906 dprintk("dib8000_get_frontend : Layer %d Code Rate = 2/3 ", i);
2909 fe->dtv_property_cache.layer[i].fec = FEC_3_4;
2910 dprintk("dib8000_get_frontend : Layer %d Code Rate = 3/4 ", i);
2913 fe->dtv_property_cache.layer[i].fec = FEC_5_6;
2914 dprintk("dib8000_get_frontend : Layer %d Code Rate = 5/6 ", i);
2917 fe->dtv_property_cache.layer[i].fec = FEC_7_8;
2918 dprintk("dib8000_get_frontend : Layer %d Code Rate = 7/8 ", i);
2922 val = dib8000_read_word(state, 487 + i);
2923 switch (val & 0x3) {
2925 dprintk("dib8000_get_frontend : Layer %d DQPSK ", i);
2926 fe->dtv_property_cache.layer[i].modulation = DQPSK;
2929 fe->dtv_property_cache.layer[i].modulation = QPSK;
2930 dprintk("dib8000_get_frontend : Layer %d QPSK ", i);
2933 fe->dtv_property_cache.layer[i].modulation = QAM_16;
2934 dprintk("dib8000_get_frontend : Layer %d QAM16 ", i);
2938 dprintk("dib8000_get_frontend : Layer %d QAM64 ", i);
2939 fe->dtv_property_cache.layer[i].modulation = QAM_64;
2944 /* synchronize the cache with the other frontends */
2945 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
2946 state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode = fe->dtv_property_cache.isdbt_sb_mode;
2947 state->fe[index_frontend]->dtv_property_cache.inversion = fe->dtv_property_cache.inversion;
2948 state->fe[index_frontend]->dtv_property_cache.transmission_mode = fe->dtv_property_cache.transmission_mode;
2949 state->fe[index_frontend]->dtv_property_cache.guard_interval = fe->dtv_property_cache.guard_interval;
2950 state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception = fe->dtv_property_cache.isdbt_partial_reception;
2951 for (i = 0; i < 3; i++) {
2952 state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count = fe->dtv_property_cache.layer[i].segment_count;
2953 state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving = fe->dtv_property_cache.layer[i].interleaving;
2954 state->fe[index_frontend]->dtv_property_cache.layer[i].fec = fe->dtv_property_cache.layer[i].fec;
2955 state->fe[index_frontend]->dtv_property_cache.layer[i].modulation = fe->dtv_property_cache.layer[i].modulation;
2961 static int dib8000_set_frontend(struct dvb_frontend *fe)
2963 struct dib8000_state *state = fe->demodulator_priv;
2964 u8 nbr_pending, exit_condition, index_frontend;
2965 s8 index_frontend_success = -1;
2967 int time_slave = FE_CALLBACK_TIME_NEVER;
2969 if (state->fe[0]->dtv_property_cache.frequency == 0) {
2970 dprintk("dib8000: must at least specify frequency ");
2974 if (state->fe[0]->dtv_property_cache.bandwidth_hz == 0) {
2975 dprintk("dib8000: no bandwidth specified, set to default ");
2976 state->fe[0]->dtv_property_cache.bandwidth_hz = 6000000;
2979 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
2980 /* synchronization of the cache */
2981 state->fe[index_frontend]->dtv_property_cache.delivery_system = SYS_ISDBT;
2982 memcpy(&state->fe[index_frontend]->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_frontend_properties));
2984 if (state->revision != 0x8090)
2985 dib8000_set_output_mode(state->fe[index_frontend],
2988 dib8096p_set_output_mode(state->fe[index_frontend],
2990 if (state->fe[index_frontend]->ops.tuner_ops.set_params)
2991 state->fe[index_frontend]->ops.tuner_ops.set_params(state->fe[index_frontend]);
2993 dib8000_set_tune_state(state->fe[index_frontend], CT_AGC_START);
2996 /* start up the AGC */
2998 time = dib8000_agc_startup(state->fe[0]);
2999 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3000 time_slave = dib8000_agc_startup(state->fe[index_frontend]);
3001 if (time == FE_CALLBACK_TIME_NEVER)
3003 else if ((time_slave != FE_CALLBACK_TIME_NEVER) && (time_slave > time))
3006 if (time != FE_CALLBACK_TIME_NEVER)
3011 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3012 if (dib8000_get_tune_state(state->fe[index_frontend]) != CT_AGC_STOP) {
3017 } while (exit_condition == 0);
3019 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
3020 dib8000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START);
3022 if ((state->fe[0]->dtv_property_cache.delivery_system != SYS_ISDBT) ||
3023 (state->fe[0]->dtv_property_cache.inversion == INVERSION_AUTO) ||
3024 (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO) ||
3025 (state->fe[0]->dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO) ||
3026 (((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (1 << 0)) != 0) &&
3027 (state->fe[0]->dtv_property_cache.layer[0].segment_count != 0xff) &&
3028 (state->fe[0]->dtv_property_cache.layer[0].segment_count != 0) &&
3029 ((state->fe[0]->dtv_property_cache.layer[0].modulation == QAM_AUTO) ||
3030 (state->fe[0]->dtv_property_cache.layer[0].fec == FEC_AUTO))) ||
3031 (((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (1 << 1)) != 0) &&
3032 (state->fe[0]->dtv_property_cache.layer[1].segment_count != 0xff) &&
3033 (state->fe[0]->dtv_property_cache.layer[1].segment_count != 0) &&
3034 ((state->fe[0]->dtv_property_cache.layer[1].modulation == QAM_AUTO) ||
3035 (state->fe[0]->dtv_property_cache.layer[1].fec == FEC_AUTO))) ||
3036 (((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (1 << 2)) != 0) &&
3037 (state->fe[0]->dtv_property_cache.layer[2].segment_count != 0xff) &&
3038 (state->fe[0]->dtv_property_cache.layer[2].segment_count != 0) &&
3039 ((state->fe[0]->dtv_property_cache.layer[2].modulation == QAM_AUTO) ||
3040 (state->fe[0]->dtv_property_cache.layer[2].fec == FEC_AUTO))) ||
3041 (((state->fe[0]->dtv_property_cache.layer[0].segment_count == 0) ||
3042 ((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (1 << 0)) == 0)) &&
3043 ((state->fe[0]->dtv_property_cache.layer[1].segment_count == 0) ||
3044 ((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (2 << 0)) == 0)) &&
3045 ((state->fe[0]->dtv_property_cache.layer[2].segment_count == 0) || ((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (3 << 0)) == 0)))) {
3050 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3051 dib8000_set_bandwidth(state->fe[index_frontend], fe->dtv_property_cache.bandwidth_hz / 1000);
3052 dib8000_autosearch_start(state->fe[index_frontend]);
3058 exit_condition = 0; /* 0: tune pending; 1: tune failed; 2:tune success */
3059 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3060 if (((tune_failed >> index_frontend) & 0x1) == 0) {
3061 found = dib8000_autosearch_irq(state->fe[index_frontend]);
3063 case 0: /* tune pending */
3067 dprintk("autosearch succeed on the frontend%i", index_frontend);
3069 index_frontend_success = index_frontend;
3072 dprintk("unhandled autosearch result");
3074 tune_failed |= (1 << index_frontend);
3075 dprintk("autosearch failed for the frontend%i", index_frontend);
3081 /* if all tune are done and no success, exit: tune failed */
3082 if ((nbr_pending == 0) && (exit_condition == 0))
3084 } while ((exit_condition == 0) && i--);
3086 if (exit_condition == 1) { /* tune failed */
3087 dprintk("tune failed");
3091 dprintk("tune success on frontend%i", index_frontend_success);
3093 dib8000_get_frontend(fe);
3096 for (index_frontend = 0, ret = 0; (ret >= 0) && (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
3097 ret = dib8000_tune(state->fe[index_frontend]);
3099 /* set output mode and diversity input */
3100 if (state->revision != 0x8090) {
3101 dib8000_set_output_mode(state->fe[0], state->cfg.output_mode);
3102 for (index_frontend = 1;
3103 (index_frontend < MAX_NUMBER_OF_FRONTENDS) &&
3104 (state->fe[index_frontend] != NULL);
3106 dib8000_set_output_mode(state->fe[index_frontend],
3108 dib8000_set_diversity_in(state->fe[index_frontend-1], 1);
3111 /* turn off the diversity of the last chip */
3112 dib8000_set_diversity_in(state->fe[index_frontend-1], 0);
3114 dib8096p_set_output_mode(state->fe[0], state->cfg.output_mode);
3115 if (state->cfg.enMpegOutput == 0) {
3116 dib8096p_setDibTxMux(state, MPEG_ON_DIBTX);
3117 dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS);
3119 for (index_frontend = 1;
3120 (index_frontend < MAX_NUMBER_OF_FRONTENDS) &&
3121 (state->fe[index_frontend] != NULL);
3123 dib8096p_set_output_mode(state->fe[index_frontend],
3125 dib8096p_set_diversity_in(state->fe[index_frontend-1], 1);
3128 /* turn off the diversity of the last chip */
3129 dib8096p_set_diversity_in(state->fe[index_frontend-1], 0);
3135 static u16 dib8000_read_lock(struct dvb_frontend *fe)
3137 struct dib8000_state *state = fe->demodulator_priv;
3139 if (state->revision == 0x8090)
3140 return dib8000_read_word(state, 570);
3141 return dib8000_read_word(state, 568);
3144 static int dib8000_read_status(struct dvb_frontend *fe, fe_status_t * stat)
3146 struct dib8000_state *state = fe->demodulator_priv;
3147 u16 lock_slave = 0, lock;
3150 if (state->revision == 0x8090)
3151 lock = dib8000_read_word(state, 570);
3153 lock = dib8000_read_word(state, 568);
3155 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
3156 lock_slave |= dib8000_read_lock(state->fe[index_frontend]);
3160 if (((lock >> 13) & 1) || ((lock_slave >> 13) & 1))
3161 *stat |= FE_HAS_SIGNAL;
3163 if (((lock >> 8) & 1) || ((lock_slave >> 8) & 1)) /* Equal */
3164 *stat |= FE_HAS_CARRIER;
3166 if ((((lock >> 1) & 0xf) == 0xf) || (((lock_slave >> 1) & 0xf) == 0xf)) /* TMCC_SYNC */
3167 *stat |= FE_HAS_SYNC;
3169 if ((((lock >> 12) & 1) || ((lock_slave >> 12) & 1)) && ((lock >> 5) & 7)) /* FEC MPEG */
3170 *stat |= FE_HAS_LOCK;
3172 if (((lock >> 12) & 1) || ((lock_slave >> 12) & 1)) {
3173 lock = dib8000_read_word(state, 554); /* Viterbi Layer A */
3175 *stat |= FE_HAS_VITERBI;
3177 lock = dib8000_read_word(state, 555); /* Viterbi Layer B */
3179 *stat |= FE_HAS_VITERBI;
3181 lock = dib8000_read_word(state, 556); /* Viterbi Layer C */
3183 *stat |= FE_HAS_VITERBI;
3189 static int dib8000_read_ber(struct dvb_frontend *fe, u32 * ber)
3191 struct dib8000_state *state = fe->demodulator_priv;
3194 if (state->revision == 0x8090)
3195 *ber = (dib8000_read_word(state, 562) << 16) |
3196 dib8000_read_word(state, 563);
3198 *ber = (dib8000_read_word(state, 560) << 16) |
3199 dib8000_read_word(state, 561);
3203 static int dib8000_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
3205 struct dib8000_state *state = fe->demodulator_priv;
3207 /* packet error on 13 seg */
3208 if (state->revision == 0x8090)
3209 *unc = dib8000_read_word(state, 567);
3211 *unc = dib8000_read_word(state, 565);
3215 static int dib8000_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
3217 struct dib8000_state *state = fe->demodulator_priv;
3222 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3223 state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val);
3224 if (val > 65535 - *strength)
3230 val = 65535 - dib8000_read_word(state, 390);
3231 if (val > 65535 - *strength)
3238 static u32 dib8000_get_snr(struct dvb_frontend *fe)
3240 struct dib8000_state *state = fe->demodulator_priv;
3244 if (state->revision != 0x8090)
3245 val = dib8000_read_word(state, 542);
3247 val = dib8000_read_word(state, 544);
3248 n = (val >> 6) & 0xff;
3250 if ((exp & 0x20) != 0)
3254 if (state->revision != 0x8090)
3255 val = dib8000_read_word(state, 543);
3257 val = dib8000_read_word(state, 545);
3258 s = (val >> 6) & 0xff;
3260 if ((exp & 0x20) != 0)
3265 u32 t = (s/n) << 16;
3266 return t + ((s << 16) - n*t) / n;
3271 static int dib8000_read_snr(struct dvb_frontend *fe, u16 * snr)
3273 struct dib8000_state *state = fe->demodulator_priv;
3277 snr_master = dib8000_get_snr(fe);
3278 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
3279 snr_master += dib8000_get_snr(state->fe[index_frontend]);
3281 if ((snr_master >> 16) != 0) {
3282 snr_master = 10*intlog10(snr_master>>16);
3283 *snr = snr_master / ((1 << 24) / 10);
3291 int dib8000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave)
3293 struct dib8000_state *state = fe->demodulator_priv;
3294 u8 index_frontend = 1;
3296 while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))
3298 if (index_frontend < MAX_NUMBER_OF_FRONTENDS) {
3299 dprintk("set slave fe %p to index %i", fe_slave, index_frontend);
3300 state->fe[index_frontend] = fe_slave;
3304 dprintk("too many slave frontend");
3307 EXPORT_SYMBOL(dib8000_set_slave_frontend);
3309 int dib8000_remove_slave_frontend(struct dvb_frontend *fe)
3311 struct dib8000_state *state = fe->demodulator_priv;
3312 u8 index_frontend = 1;
3314 while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))
3316 if (index_frontend != 1) {
3317 dprintk("remove slave fe %p (index %i)", state->fe[index_frontend-1], index_frontend-1);
3318 state->fe[index_frontend] = NULL;
3322 dprintk("no frontend to be removed");
3325 EXPORT_SYMBOL(dib8000_remove_slave_frontend);
3327 struct dvb_frontend *dib8000_get_slave_frontend(struct dvb_frontend *fe, int slave_index)
3329 struct dib8000_state *state = fe->demodulator_priv;
3331 if (slave_index >= MAX_NUMBER_OF_FRONTENDS)
3333 return state->fe[slave_index];
3335 EXPORT_SYMBOL(dib8000_get_slave_frontend);
3338 int dib8000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods,
3339 u8 default_addr, u8 first_addr, u8 is_dib8096p)
3343 struct i2c_device client = {.adap = host };
3345 client.i2c_write_buffer = kzalloc(4 * sizeof(u8), GFP_KERNEL);
3346 if (!client.i2c_write_buffer) {
3347 dprintk("%s: not enough memory", __func__);
3350 client.i2c_read_buffer = kzalloc(4 * sizeof(u8), GFP_KERNEL);
3351 if (!client.i2c_read_buffer) {
3352 dprintk("%s: not enough memory", __func__);
3354 goto error_memory_read;
3356 client.i2c_buffer_lock = kzalloc(sizeof(struct mutex), GFP_KERNEL);
3357 if (!client.i2c_buffer_lock) {
3358 dprintk("%s: not enough memory", __func__);
3360 goto error_memory_lock;
3362 mutex_init(client.i2c_buffer_lock);
3364 for (k = no_of_demods - 1; k >= 0; k--) {
3365 /* designated i2c address */
3366 new_addr = first_addr + (k << 1);
3368 client.addr = new_addr;
3370 dib8000_i2c_write16(&client, 1287, 0x0003); /* sram lead in, rdy */
3371 if (dib8000_identify(&client) == 0) {
3372 /* sram lead in, rdy */
3374 dib8000_i2c_write16(&client, 1287, 0x0003);
3375 client.addr = default_addr;
3376 if (dib8000_identify(&client) == 0) {
3377 dprintk("#%d: not identified", k);
3383 /* start diversity to pull_down div_str - just for i2c-enumeration */
3384 dib8000_i2c_write16(&client, 1286, (1 << 10) | (4 << 6));
3386 /* set new i2c address and force divstart */
3387 dib8000_i2c_write16(&client, 1285, (new_addr << 2) | 0x2);
3388 client.addr = new_addr;
3389 dib8000_identify(&client);
3391 dprintk("IC %d initialized (to i2c_address 0x%x)", k, new_addr);
3394 for (k = 0; k < no_of_demods; k++) {
3395 new_addr = first_addr | (k << 1);
3396 client.addr = new_addr;
3399 dib8000_i2c_write16(&client, 1285, new_addr << 2);
3401 /* deactivate div - it was just for i2c-enumeration */
3402 dib8000_i2c_write16(&client, 1286, 0);
3406 kfree(client.i2c_buffer_lock);
3408 kfree(client.i2c_read_buffer);
3410 kfree(client.i2c_write_buffer);
3415 EXPORT_SYMBOL(dib8000_i2c_enumeration);
3416 static int dib8000_fe_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *tune)
3418 tune->min_delay_ms = 1000;
3419 tune->step_size = 0;
3420 tune->max_drift = 0;
3424 static void dib8000_release(struct dvb_frontend *fe)
3426 struct dib8000_state *st = fe->demodulator_priv;
3429 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (st->fe[index_frontend] != NULL); index_frontend++)
3430 dvb_frontend_detach(st->fe[index_frontend]);
3432 dibx000_exit_i2c_master(&st->i2c_master);
3433 i2c_del_adapter(&st->dib8096p_tuner_adap);
3438 struct i2c_adapter *dib8000_get_i2c_master(struct dvb_frontend *fe, enum dibx000_i2c_interface intf, int gating)
3440 struct dib8000_state *st = fe->demodulator_priv;
3441 return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating);
3444 EXPORT_SYMBOL(dib8000_get_i2c_master);
3446 int dib8000_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
3448 struct dib8000_state *st = fe->demodulator_priv;
3449 u16 val = dib8000_read_word(st, 299) & 0xffef;
3450 val |= (onoff & 0x1) << 4;
3452 dprintk("pid filter enabled %d", onoff);
3453 return dib8000_write_word(st, 299, val);
3455 EXPORT_SYMBOL(dib8000_pid_filter_ctrl);
3457 int dib8000_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
3459 struct dib8000_state *st = fe->demodulator_priv;
3460 dprintk("Index %x, PID %d, OnOff %d", id, pid, onoff);
3461 return dib8000_write_word(st, 305 + id, onoff ? (1 << 13) | pid : 0);
3463 EXPORT_SYMBOL(dib8000_pid_filter);
3465 static const struct dvb_frontend_ops dib8000_ops = {
3466 .delsys = { SYS_ISDBT },
3468 .name = "DiBcom 8000 ISDB-T",
3469 .frequency_min = 44250000,
3470 .frequency_max = 867250000,
3471 .frequency_stepsize = 62500,
3472 .caps = FE_CAN_INVERSION_AUTO |
3473 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
3474 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
3475 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
3476 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER | FE_CAN_HIERARCHY_AUTO,
3479 .release = dib8000_release,
3481 .init = dib8000_wakeup,
3482 .sleep = dib8000_sleep,
3484 .set_frontend = dib8000_set_frontend,
3485 .get_tune_settings = dib8000_fe_get_tune_settings,
3486 .get_frontend = dib8000_get_frontend,
3488 .read_status = dib8000_read_status,
3489 .read_ber = dib8000_read_ber,
3490 .read_signal_strength = dib8000_read_signal_strength,
3491 .read_snr = dib8000_read_snr,
3492 .read_ucblocks = dib8000_read_unc_blocks,
3495 struct dvb_frontend *dib8000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib8000_config *cfg)
3497 struct dvb_frontend *fe;
3498 struct dib8000_state *state;
3500 dprintk("dib8000_attach");
3502 state = kzalloc(sizeof(struct dib8000_state), GFP_KERNEL);
3505 fe = kzalloc(sizeof(struct dvb_frontend), GFP_KERNEL);
3509 memcpy(&state->cfg, cfg, sizeof(struct dib8000_config));
3510 state->i2c.adap = i2c_adap;
3511 state->i2c.addr = i2c_addr;
3512 state->i2c.i2c_write_buffer = state->i2c_write_buffer;
3513 state->i2c.i2c_read_buffer = state->i2c_read_buffer;
3514 mutex_init(&state->i2c_buffer_lock);
3515 state->i2c.i2c_buffer_lock = &state->i2c_buffer_lock;
3516 state->gpio_val = cfg->gpio_val;
3517 state->gpio_dir = cfg->gpio_dir;
3519 /* Ensure the output mode remains at the previous default if it's
3520 * not specifically set by the caller.
3522 if ((state->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (state->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
3523 state->cfg.output_mode = OUTMODE_MPEG2_FIFO;
3526 fe->demodulator_priv = state;
3527 memcpy(&state->fe[0]->ops, &dib8000_ops, sizeof(struct dvb_frontend_ops));
3529 state->timf_default = cfg->pll->timf;
3531 if (dib8000_identify(&state->i2c) == 0)
3534 dibx000_init_i2c_master(&state->i2c_master, DIB8000, state->i2c.adap, state->i2c.addr);
3536 /* init 8096p tuner adapter */
3537 strncpy(state->dib8096p_tuner_adap.name, "DiB8096P tuner interface",
3538 sizeof(state->dib8096p_tuner_adap.name));
3539 state->dib8096p_tuner_adap.algo = &dib8096p_tuner_xfer_algo;
3540 state->dib8096p_tuner_adap.algo_data = NULL;
3541 state->dib8096p_tuner_adap.dev.parent = state->i2c.adap->dev.parent;
3542 i2c_set_adapdata(&state->dib8096p_tuner_adap, state);
3543 i2c_add_adapter(&state->dib8096p_tuner_adap);
3547 dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5)); /* ber_rs_len = 3 */
3556 EXPORT_SYMBOL(dib8000_attach);
3558 MODULE_AUTHOR("Olivier Grenie <Olivier.Grenie@dibcom.fr, " "Patrick Boettcher <pboettcher@dibcom.fr>");
3559 MODULE_DESCRIPTION("Driver for the DiBcom 8000 ISDB-T demodulator");
3560 MODULE_LICENSE("GPL");