2 * Afatech AF9033 demodulator driver
4 * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
5 * Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 #include "af9033_priv.h"
25 struct i2c_adapter *i2c;
26 struct dvb_frontend fe;
27 struct af9033_config cfg;
30 bool ts_mode_parallel;
35 unsigned long last_stat_check;
38 /* write multiple registers */
39 static int af9033_wr_regs(struct af9033_state *state, u32 reg, const u8 *val,
44 struct i2c_msg msg[1] = {
46 .addr = state->cfg.i2c_addr,
53 buf[0] = (reg >> 16) & 0xff;
54 buf[1] = (reg >> 8) & 0xff;
55 buf[2] = (reg >> 0) & 0xff;
56 memcpy(&buf[3], val, len);
58 ret = i2c_transfer(state->i2c, msg, 1);
62 dev_warn(&state->i2c->dev, "%s: i2c wr failed=%d reg=%06x " \
63 "len=%d\n", KBUILD_MODNAME, ret, reg, len);
70 /* read multiple registers */
71 static int af9033_rd_regs(struct af9033_state *state, u32 reg, u8 *val, int len)
74 u8 buf[3] = { (reg >> 16) & 0xff, (reg >> 8) & 0xff,
76 struct i2c_msg msg[2] = {
78 .addr = state->cfg.i2c_addr,
83 .addr = state->cfg.i2c_addr,
90 ret = i2c_transfer(state->i2c, msg, 2);
94 dev_warn(&state->i2c->dev, "%s: i2c rd failed=%d reg=%06x " \
95 "len=%d\n", KBUILD_MODNAME, ret, reg, len);
103 /* write single register */
104 static int af9033_wr_reg(struct af9033_state *state, u32 reg, u8 val)
106 return af9033_wr_regs(state, reg, &val, 1);
109 /* read single register */
110 static int af9033_rd_reg(struct af9033_state *state, u32 reg, u8 *val)
112 return af9033_rd_regs(state, reg, val, 1);
115 /* write single register with mask */
116 static int af9033_wr_reg_mask(struct af9033_state *state, u32 reg, u8 val,
122 /* no need for read if whole reg is written */
124 ret = af9033_rd_regs(state, reg, &tmp, 1);
133 return af9033_wr_regs(state, reg, &val, 1);
136 /* read single register with mask */
137 static int af9033_rd_reg_mask(struct af9033_state *state, u32 reg, u8 *val,
143 ret = af9033_rd_regs(state, reg, &tmp, 1);
149 /* find position of the first bit */
150 for (i = 0; i < 8; i++) {
151 if ((mask >> i) & 0x01)
159 static u32 af9033_div(struct af9033_state *state, u32 a, u32 b, u32 x)
163 dev_dbg(&state->i2c->dev, "%s: a=%d b=%d x=%d\n", __func__, a, b, x);
170 for (i = 0; i < x; i++) {
178 r = (c << (u32)x) + r;
180 dev_dbg(&state->i2c->dev, "%s: a=%d b=%d x=%d r=%d r=%x\n",
181 __func__, a, b, x, r, r);
186 static void af9033_release(struct dvb_frontend *fe)
188 struct af9033_state *state = fe->demodulator_priv;
193 static int af9033_init(struct dvb_frontend *fe)
195 struct af9033_state *state = fe->demodulator_priv;
197 const struct reg_val *init;
199 u32 adc_cw, clock_cw;
200 struct reg_val_mask tab[] = {
201 { 0x80fb24, 0x00, 0x08 },
202 { 0x80004c, 0x00, 0xff },
203 { 0x00f641, state->cfg.tuner, 0xff },
204 { 0x80f5ca, 0x01, 0x01 },
205 { 0x80f715, 0x01, 0x01 },
206 { 0x00f41f, 0x04, 0x04 },
207 { 0x00f41a, 0x01, 0x01 },
208 { 0x80f731, 0x00, 0x01 },
209 { 0x00d91e, 0x00, 0x01 },
210 { 0x00d919, 0x00, 0x01 },
211 { 0x80f732, 0x00, 0x01 },
212 { 0x00d91f, 0x00, 0x01 },
213 { 0x00d91a, 0x00, 0x01 },
214 { 0x80f730, 0x00, 0x01 },
215 { 0x80f778, 0x00, 0xff },
216 { 0x80f73c, 0x01, 0x01 },
217 { 0x80f776, 0x00, 0x01 },
218 { 0x00d8fd, 0x01, 0xff },
219 { 0x00d830, 0x01, 0xff },
220 { 0x00d831, 0x00, 0xff },
221 { 0x00d832, 0x00, 0xff },
222 { 0x80f985, state->ts_mode_serial, 0x01 },
223 { 0x80f986, state->ts_mode_parallel, 0x01 },
224 { 0x00d827, 0x00, 0xff },
225 { 0x00d829, 0x00, 0xff },
228 /* program clock control */
229 clock_cw = af9033_div(state, state->cfg.clock, 1000000ul, 19ul);
230 buf[0] = (clock_cw >> 0) & 0xff;
231 buf[1] = (clock_cw >> 8) & 0xff;
232 buf[2] = (clock_cw >> 16) & 0xff;
233 buf[3] = (clock_cw >> 24) & 0xff;
235 dev_dbg(&state->i2c->dev, "%s: clock=%d clock_cw=%08x\n",
236 __func__, state->cfg.clock, clock_cw);
238 ret = af9033_wr_regs(state, 0x800025, buf, 4);
242 /* program ADC control */
243 for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) {
244 if (clock_adc_lut[i].clock == state->cfg.clock)
248 adc_cw = af9033_div(state, clock_adc_lut[i].adc, 1000000ul, 19ul);
249 buf[0] = (adc_cw >> 0) & 0xff;
250 buf[1] = (adc_cw >> 8) & 0xff;
251 buf[2] = (adc_cw >> 16) & 0xff;
253 dev_dbg(&state->i2c->dev, "%s: adc=%d adc_cw=%06x\n",
254 __func__, clock_adc_lut[i].adc, adc_cw);
256 ret = af9033_wr_regs(state, 0x80f1cd, buf, 3);
260 /* program register table */
261 for (i = 0; i < ARRAY_SIZE(tab); i++) {
262 ret = af9033_wr_reg_mask(state, tab[i].reg, tab[i].val,
268 /* settings for TS interface */
269 if (state->cfg.ts_mode == AF9033_TS_MODE_USB) {
270 ret = af9033_wr_reg_mask(state, 0x80f9a5, 0x00, 0x01);
274 ret = af9033_wr_reg_mask(state, 0x80f9b5, 0x01, 0x01);
278 ret = af9033_wr_reg_mask(state, 0x80f990, 0x00, 0x01);
282 ret = af9033_wr_reg_mask(state, 0x80f9b5, 0x00, 0x01);
287 /* load OFSM settings */
288 dev_dbg(&state->i2c->dev, "%s: load ofsm settings\n", __func__);
289 len = ARRAY_SIZE(ofsm_init);
291 for (i = 0; i < len; i++) {
292 ret = af9033_wr_reg(state, init[i].reg, init[i].val);
297 /* load tuner specific settings */
298 dev_dbg(&state->i2c->dev, "%s: load tuner specific settings\n",
300 switch (state->cfg.tuner) {
301 case AF9033_TUNER_TUA9001:
302 len = ARRAY_SIZE(tuner_init_tua9001);
303 init = tuner_init_tua9001;
305 case AF9033_TUNER_FC0011:
306 len = ARRAY_SIZE(tuner_init_fc0011);
307 init = tuner_init_fc0011;
309 case AF9033_TUNER_MXL5007T:
310 len = ARRAY_SIZE(tuner_init_mxl5007t);
311 init = tuner_init_mxl5007t;
313 case AF9033_TUNER_TDA18218:
314 len = ARRAY_SIZE(tuner_init_tda18218);
315 init = tuner_init_tda18218;
317 case AF9033_TUNER_FC2580:
318 len = ARRAY_SIZE(tuner_init_fc2580);
319 init = tuner_init_fc2580;
322 dev_dbg(&state->i2c->dev, "%s: unsupported tuner ID=%d\n",
323 __func__, state->cfg.tuner);
328 for (i = 0; i < len; i++) {
329 ret = af9033_wr_reg(state, init[i].reg, init[i].val);
334 state->bandwidth_hz = 0; /* force to program all parameters */
339 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
344 static int af9033_sleep(struct dvb_frontend *fe)
346 struct af9033_state *state = fe->demodulator_priv;
350 ret = af9033_wr_reg(state, 0x80004c, 1);
354 ret = af9033_wr_reg(state, 0x800000, 0);
358 for (i = 100, tmp = 1; i && tmp; i--) {
359 ret = af9033_rd_reg(state, 0x80004c, &tmp);
363 usleep_range(200, 10000);
366 dev_dbg(&state->i2c->dev, "%s: loop=%d\n", __func__, i);
373 ret = af9033_wr_reg_mask(state, 0x80fb24, 0x08, 0x08);
377 /* prevent current leak (?) */
378 if (state->cfg.ts_mode == AF9033_TS_MODE_SERIAL) {
379 /* enable parallel TS */
380 ret = af9033_wr_reg_mask(state, 0x00d917, 0x00, 0x01);
384 ret = af9033_wr_reg_mask(state, 0x00d916, 0x01, 0x01);
392 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
397 static int af9033_get_tune_settings(struct dvb_frontend *fe,
398 struct dvb_frontend_tune_settings *fesettings)
400 fesettings->min_delay_ms = 800;
401 fesettings->step_size = 0;
402 fesettings->max_drift = 0;
407 static int af9033_set_frontend(struct dvb_frontend *fe)
409 struct af9033_state *state = fe->demodulator_priv;
410 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
411 int ret, i, spec_inv, sampling_freq;
412 u8 tmp, buf[3], bandwidth_reg_val;
413 u32 if_frequency, freq_cw, adc_freq;
415 dev_dbg(&state->i2c->dev, "%s: frequency=%d bandwidth_hz=%d\n",
416 __func__, c->frequency, c->bandwidth_hz);
418 /* check bandwidth */
419 switch (c->bandwidth_hz) {
421 bandwidth_reg_val = 0x00;
424 bandwidth_reg_val = 0x01;
427 bandwidth_reg_val = 0x02;
430 dev_dbg(&state->i2c->dev, "%s: invalid bandwidth_hz\n",
437 if (fe->ops.tuner_ops.set_params)
438 fe->ops.tuner_ops.set_params(fe);
440 /* program CFOE coefficients */
441 if (c->bandwidth_hz != state->bandwidth_hz) {
442 for (i = 0; i < ARRAY_SIZE(coeff_lut); i++) {
443 if (coeff_lut[i].clock == state->cfg.clock &&
444 coeff_lut[i].bandwidth_hz == c->bandwidth_hz) {
448 ret = af9033_wr_regs(state, 0x800001,
449 coeff_lut[i].val, sizeof(coeff_lut[i].val));
452 /* program frequency control */
453 if (c->bandwidth_hz != state->bandwidth_hz) {
454 spec_inv = state->cfg.spec_inv ? -1 : 1;
456 for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) {
457 if (clock_adc_lut[i].clock == state->cfg.clock)
460 adc_freq = clock_adc_lut[i].adc;
462 /* get used IF frequency */
463 if (fe->ops.tuner_ops.get_if_frequency)
464 fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
468 sampling_freq = if_frequency;
470 while (sampling_freq > (adc_freq / 2))
471 sampling_freq -= adc_freq;
473 if (sampling_freq >= 0)
478 freq_cw = af9033_div(state, sampling_freq, adc_freq, 23ul);
481 freq_cw = 0x800000 - freq_cw;
483 /* get adc multiplies */
484 ret = af9033_rd_reg(state, 0x800045, &tmp);
491 buf[0] = (freq_cw >> 0) & 0xff;
492 buf[1] = (freq_cw >> 8) & 0xff;
493 buf[2] = (freq_cw >> 16) & 0x7f;
494 ret = af9033_wr_regs(state, 0x800029, buf, 3);
498 state->bandwidth_hz = c->bandwidth_hz;
501 ret = af9033_wr_reg_mask(state, 0x80f904, bandwidth_reg_val, 0x03);
505 ret = af9033_wr_reg(state, 0x800040, 0x00);
509 ret = af9033_wr_reg(state, 0x800047, 0x00);
513 ret = af9033_wr_reg_mask(state, 0x80f999, 0x00, 0x01);
517 if (c->frequency <= 230000000)
518 tmp = 0x00; /* VHF */
520 tmp = 0x01; /* UHF */
522 ret = af9033_wr_reg(state, 0x80004b, tmp);
526 ret = af9033_wr_reg(state, 0x800000, 0x00);
533 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
538 static int af9033_get_frontend(struct dvb_frontend *fe)
540 struct af9033_state *state = fe->demodulator_priv;
541 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
545 dev_dbg(&state->i2c->dev, "%s:\n", __func__);
547 /* read all needed registers */
548 ret = af9033_rd_regs(state, 0x80f900, buf, sizeof(buf));
552 switch ((buf[0] >> 0) & 3) {
554 c->transmission_mode = TRANSMISSION_MODE_2K;
557 c->transmission_mode = TRANSMISSION_MODE_8K;
561 switch ((buf[1] >> 0) & 3) {
563 c->guard_interval = GUARD_INTERVAL_1_32;
566 c->guard_interval = GUARD_INTERVAL_1_16;
569 c->guard_interval = GUARD_INTERVAL_1_8;
572 c->guard_interval = GUARD_INTERVAL_1_4;
576 switch ((buf[2] >> 0) & 7) {
578 c->hierarchy = HIERARCHY_NONE;
581 c->hierarchy = HIERARCHY_1;
584 c->hierarchy = HIERARCHY_2;
587 c->hierarchy = HIERARCHY_4;
591 switch ((buf[3] >> 0) & 3) {
593 c->modulation = QPSK;
596 c->modulation = QAM_16;
599 c->modulation = QAM_64;
603 switch ((buf[4] >> 0) & 3) {
605 c->bandwidth_hz = 6000000;
608 c->bandwidth_hz = 7000000;
611 c->bandwidth_hz = 8000000;
615 switch ((buf[6] >> 0) & 7) {
617 c->code_rate_HP = FEC_1_2;
620 c->code_rate_HP = FEC_2_3;
623 c->code_rate_HP = FEC_3_4;
626 c->code_rate_HP = FEC_5_6;
629 c->code_rate_HP = FEC_7_8;
632 c->code_rate_HP = FEC_NONE;
636 switch ((buf[7] >> 0) & 7) {
638 c->code_rate_LP = FEC_1_2;
641 c->code_rate_LP = FEC_2_3;
644 c->code_rate_LP = FEC_3_4;
647 c->code_rate_LP = FEC_5_6;
650 c->code_rate_LP = FEC_7_8;
653 c->code_rate_LP = FEC_NONE;
660 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
665 static int af9033_read_status(struct dvb_frontend *fe, fe_status_t *status)
667 struct af9033_state *state = fe->demodulator_priv;
673 /* radio channel status, 0=no result, 1=has signal, 2=no signal */
674 ret = af9033_rd_reg(state, 0x800047, &tmp);
680 *status |= FE_HAS_SIGNAL;
684 ret = af9033_rd_reg_mask(state, 0x80f5a9, &tmp, 0x01);
689 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
693 ret = af9033_rd_reg_mask(state, 0x80f999, &tmp, 0x01);
698 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
699 FE_HAS_VITERBI | FE_HAS_SYNC |
706 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
711 static int af9033_read_snr(struct dvb_frontend *fe, u16 *snr)
713 struct af9033_state *state = fe->demodulator_priv;
717 const struct val_snr *uninitialized_var(snr_lut);
720 ret = af9033_rd_regs(state, 0x80002c, buf, 3);
724 snr_val = (buf[2] << 16) | (buf[1] << 8) | buf[0];
726 /* read current modulation */
727 ret = af9033_rd_reg(state, 0x80f903, &tmp);
731 switch ((tmp >> 0) & 3) {
733 len = ARRAY_SIZE(qpsk_snr_lut);
734 snr_lut = qpsk_snr_lut;
737 len = ARRAY_SIZE(qam16_snr_lut);
738 snr_lut = qam16_snr_lut;
741 len = ARRAY_SIZE(qam64_snr_lut);
742 snr_lut = qam64_snr_lut;
748 for (i = 0; i < len; i++) {
749 tmp = snr_lut[i].snr;
751 if (snr_val < snr_lut[i].val)
755 *snr = tmp * 10; /* dB/10 */
760 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
765 static int af9033_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
767 struct af9033_state *state = fe->demodulator_priv;
771 /* read signal strength of 0-100 scale */
772 ret = af9033_rd_reg(state, 0x800048, &strength2);
776 /* scale value to 0x0000-0xffff */
777 *strength = strength2 * 0xffff / 100;
782 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
787 static int af9033_update_ch_stat(struct af9033_state *state)
790 u32 err_cnt, bit_cnt;
794 /* only update data every half second */
795 if (time_after(jiffies, state->last_stat_check + msecs_to_jiffies(500))) {
796 ret = af9033_rd_regs(state, 0x800032, buf, sizeof(buf));
799 /* in 8 byte packets? */
800 abort_cnt = (buf[1] << 8) + buf[0];
802 err_cnt = (buf[4] << 16) + (buf[3] << 8) + buf[2];
803 /* in 8 byte packets? always(?) 0x2710 = 10000 */
804 bit_cnt = (buf[6] << 8) + buf[5];
806 if (bit_cnt < abort_cnt) {
808 state->ber = 0xffffffff;
810 /* 8 byte packets, that have not been rejected already */
811 bit_cnt -= (u32)abort_cnt;
813 state->ber = 0xffffffff;
815 err_cnt -= (u32)abort_cnt * 8 * 8;
817 state->ber = err_cnt * (0xffffffff / bit_cnt);
820 state->ucb += abort_cnt;
821 state->last_stat_check = jiffies;
826 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
831 static int af9033_read_ber(struct dvb_frontend *fe, u32 *ber)
833 struct af9033_state *state = fe->demodulator_priv;
836 ret = af9033_update_ch_stat(state);
845 static int af9033_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
847 struct af9033_state *state = fe->demodulator_priv;
850 ret = af9033_update_ch_stat(state);
854 *ucblocks = state->ucb;
859 static int af9033_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
861 struct af9033_state *state = fe->demodulator_priv;
864 dev_dbg(&state->i2c->dev, "%s: enable=%d\n", __func__, enable);
866 ret = af9033_wr_reg_mask(state, 0x00fa04, enable, 0x01);
873 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
878 static struct dvb_frontend_ops af9033_ops;
880 struct dvb_frontend *af9033_attach(const struct af9033_config *config,
881 struct i2c_adapter *i2c)
884 struct af9033_state *state;
887 dev_dbg(&i2c->dev, "%s:\n", __func__);
889 /* allocate memory for the internal state */
890 state = kzalloc(sizeof(struct af9033_state), GFP_KERNEL);
894 /* setup the state */
896 memcpy(&state->cfg, config, sizeof(struct af9033_config));
898 if (state->cfg.clock != 12000000) {
899 dev_err(&state->i2c->dev, "%s: af9033: unsupported clock=%d, " \
900 "only 12000000 Hz is supported currently\n",
901 KBUILD_MODNAME, state->cfg.clock);
905 /* firmware version */
906 ret = af9033_rd_regs(state, 0x0083e9, &buf[0], 4);
910 ret = af9033_rd_regs(state, 0x804191, &buf[4], 4);
914 dev_info(&state->i2c->dev, "%s: firmware version: LINK=%d.%d.%d.%d " \
915 "OFDM=%d.%d.%d.%d\n", KBUILD_MODNAME, buf[0], buf[1],
916 buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]);
919 ret = af9033_wr_reg(state, 0x80004c, 1);
923 ret = af9033_wr_reg(state, 0x800000, 0);
927 /* configure internal TS mode */
928 switch (state->cfg.ts_mode) {
929 case AF9033_TS_MODE_PARALLEL:
930 state->ts_mode_parallel = true;
932 case AF9033_TS_MODE_SERIAL:
933 state->ts_mode_serial = true;
935 case AF9033_TS_MODE_USB:
936 /* usb mode for AF9035 */
941 /* create dvb_frontend */
942 memcpy(&state->fe.ops, &af9033_ops, sizeof(struct dvb_frontend_ops));
943 state->fe.demodulator_priv = state;
951 EXPORT_SYMBOL(af9033_attach);
953 static struct dvb_frontend_ops af9033_ops = {
954 .delsys = { SYS_DVBT },
956 .name = "Afatech AF9033 (DVB-T)",
957 .frequency_min = 174000000,
958 .frequency_max = 862000000,
959 .frequency_stepsize = 250000,
960 .frequency_tolerance = 0,
961 .caps = FE_CAN_FEC_1_2 |
971 FE_CAN_TRANSMISSION_MODE_AUTO |
972 FE_CAN_GUARD_INTERVAL_AUTO |
973 FE_CAN_HIERARCHY_AUTO |
978 .release = af9033_release,
981 .sleep = af9033_sleep,
983 .get_tune_settings = af9033_get_tune_settings,
984 .set_frontend = af9033_set_frontend,
985 .get_frontend = af9033_get_frontend,
987 .read_status = af9033_read_status,
988 .read_snr = af9033_read_snr,
989 .read_signal_strength = af9033_read_signal_strength,
990 .read_ber = af9033_read_ber,
991 .read_ucblocks = af9033_read_ucblocks,
993 .i2c_gate_ctrl = af9033_i2c_gate_ctrl,
996 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
997 MODULE_DESCRIPTION("Afatech AF9033 DVB-T demodulator driver");
998 MODULE_LICENSE("GPL");