2 * Afatech AF9033 demodulator driver
4 * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
5 * Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 #include "af9033_priv.h"
25 struct i2c_adapter *i2c;
26 struct dvb_frontend fe;
27 struct af9033_config cfg;
30 bool ts_mode_parallel;
35 unsigned long last_stat_check;
38 /* write multiple registers */
39 static int af9033_wr_regs(struct af9033_state *state, u32 reg, const u8 *val,
44 struct i2c_msg msg[1] = {
46 .addr = state->cfg.i2c_addr,
53 buf[0] = (reg >> 16) & 0xff;
54 buf[1] = (reg >> 8) & 0xff;
55 buf[2] = (reg >> 0) & 0xff;
56 memcpy(&buf[3], val, len);
58 ret = i2c_transfer(state->i2c, msg, 1);
62 dev_warn(&state->i2c->dev, "%s: i2c wr failed=%d reg=%06x " \
63 "len=%d\n", KBUILD_MODNAME, ret, reg, len);
70 /* read multiple registers */
71 static int af9033_rd_regs(struct af9033_state *state, u32 reg, u8 *val, int len)
74 u8 buf[3] = { (reg >> 16) & 0xff, (reg >> 8) & 0xff,
76 struct i2c_msg msg[2] = {
78 .addr = state->cfg.i2c_addr,
83 .addr = state->cfg.i2c_addr,
90 ret = i2c_transfer(state->i2c, msg, 2);
94 dev_warn(&state->i2c->dev, "%s: i2c rd failed=%d reg=%06x " \
95 "len=%d\n", KBUILD_MODNAME, ret, reg, len);
103 /* write single register */
104 static int af9033_wr_reg(struct af9033_state *state, u32 reg, u8 val)
106 return af9033_wr_regs(state, reg, &val, 1);
109 /* read single register */
110 static int af9033_rd_reg(struct af9033_state *state, u32 reg, u8 *val)
112 return af9033_rd_regs(state, reg, val, 1);
115 /* write single register with mask */
116 static int af9033_wr_reg_mask(struct af9033_state *state, u32 reg, u8 val,
122 /* no need for read if whole reg is written */
124 ret = af9033_rd_regs(state, reg, &tmp, 1);
133 return af9033_wr_regs(state, reg, &val, 1);
136 /* read single register with mask */
137 static int af9033_rd_reg_mask(struct af9033_state *state, u32 reg, u8 *val,
143 ret = af9033_rd_regs(state, reg, &tmp, 1);
149 /* find position of the first bit */
150 for (i = 0; i < 8; i++) {
151 if ((mask >> i) & 0x01)
159 static u32 af9033_div(struct af9033_state *state, u32 a, u32 b, u32 x)
163 dev_dbg(&state->i2c->dev, "%s: a=%d b=%d x=%d\n", __func__, a, b, x);
170 for (i = 0; i < x; i++) {
178 r = (c << (u32)x) + r;
180 dev_dbg(&state->i2c->dev, "%s: a=%d b=%d x=%d r=%d r=%x\n",
181 __func__, a, b, x, r, r);
186 static void af9033_release(struct dvb_frontend *fe)
188 struct af9033_state *state = fe->demodulator_priv;
193 static int af9033_init(struct dvb_frontend *fe)
195 struct af9033_state *state = fe->demodulator_priv;
197 const struct reg_val *init;
199 u32 adc_cw, clock_cw;
200 struct reg_val_mask tab[] = {
201 { 0x80fb24, 0x00, 0x08 },
202 { 0x80004c, 0x00, 0xff },
203 { 0x00f641, state->cfg.tuner, 0xff },
204 { 0x80f5ca, 0x01, 0x01 },
205 { 0x80f715, 0x01, 0x01 },
206 { 0x00f41f, 0x04, 0x04 },
207 { 0x00f41a, 0x01, 0x01 },
208 { 0x80f731, 0x00, 0x01 },
209 { 0x00d91e, 0x00, 0x01 },
210 { 0x00d919, 0x00, 0x01 },
211 { 0x80f732, 0x00, 0x01 },
212 { 0x00d91f, 0x00, 0x01 },
213 { 0x00d91a, 0x00, 0x01 },
214 { 0x80f730, 0x00, 0x01 },
215 { 0x80f778, 0x00, 0xff },
216 { 0x80f73c, 0x01, 0x01 },
217 { 0x80f776, 0x00, 0x01 },
218 { 0x00d8fd, 0x01, 0xff },
219 { 0x00d830, 0x01, 0xff },
220 { 0x00d831, 0x00, 0xff },
221 { 0x00d832, 0x00, 0xff },
222 { 0x80f985, state->ts_mode_serial, 0x01 },
223 { 0x80f986, state->ts_mode_parallel, 0x01 },
224 { 0x00d827, 0x00, 0xff },
225 { 0x00d829, 0x00, 0xff },
226 { 0x800045, state->cfg.adc_multiplier, 0xff },
229 /* program clock control */
230 clock_cw = af9033_div(state, state->cfg.clock, 1000000ul, 19ul);
231 buf[0] = (clock_cw >> 0) & 0xff;
232 buf[1] = (clock_cw >> 8) & 0xff;
233 buf[2] = (clock_cw >> 16) & 0xff;
234 buf[3] = (clock_cw >> 24) & 0xff;
236 dev_dbg(&state->i2c->dev, "%s: clock=%d clock_cw=%08x\n",
237 __func__, state->cfg.clock, clock_cw);
239 ret = af9033_wr_regs(state, 0x800025, buf, 4);
243 /* program ADC control */
244 for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) {
245 if (clock_adc_lut[i].clock == state->cfg.clock)
249 adc_cw = af9033_div(state, clock_adc_lut[i].adc, 1000000ul, 19ul);
250 buf[0] = (adc_cw >> 0) & 0xff;
251 buf[1] = (adc_cw >> 8) & 0xff;
252 buf[2] = (adc_cw >> 16) & 0xff;
254 dev_dbg(&state->i2c->dev, "%s: adc=%d adc_cw=%06x\n",
255 __func__, clock_adc_lut[i].adc, adc_cw);
257 ret = af9033_wr_regs(state, 0x80f1cd, buf, 3);
261 /* program register table */
262 for (i = 0; i < ARRAY_SIZE(tab); i++) {
263 ret = af9033_wr_reg_mask(state, tab[i].reg, tab[i].val,
269 /* settings for TS interface */
270 if (state->cfg.ts_mode == AF9033_TS_MODE_USB) {
271 ret = af9033_wr_reg_mask(state, 0x80f9a5, 0x00, 0x01);
275 ret = af9033_wr_reg_mask(state, 0x80f9b5, 0x01, 0x01);
279 ret = af9033_wr_reg_mask(state, 0x80f990, 0x00, 0x01);
283 ret = af9033_wr_reg_mask(state, 0x80f9b5, 0x00, 0x01);
289 * FIXME: These inits are logically property of demodulator driver
290 * (that driver), but currently in case of IT9135 those are done by
294 /* load OFSM settings */
295 dev_dbg(&state->i2c->dev, "%s: load ofsm settings\n", __func__);
296 switch (state->cfg.tuner) {
297 case AF9033_TUNER_IT9135_38:
298 case AF9033_TUNER_IT9135_51:
299 case AF9033_TUNER_IT9135_52:
300 len = ARRAY_SIZE(ofsm_init_it9135_v1);
301 init = ofsm_init_it9135_v1;
303 case AF9033_TUNER_IT9135_60:
304 case AF9033_TUNER_IT9135_61:
305 case AF9033_TUNER_IT9135_62:
306 len = ARRAY_SIZE(ofsm_init_it9135_v2);
307 init = ofsm_init_it9135_v2;
310 len = ARRAY_SIZE(ofsm_init);
315 for (i = 0; i < len; i++) {
316 ret = af9033_wr_reg(state, init[i].reg, init[i].val);
321 /* load tuner specific settings */
322 dev_dbg(&state->i2c->dev, "%s: load tuner specific settings\n",
324 switch (state->cfg.tuner) {
325 case AF9033_TUNER_TUA9001:
326 len = ARRAY_SIZE(tuner_init_tua9001);
327 init = tuner_init_tua9001;
329 case AF9033_TUNER_FC0011:
330 len = ARRAY_SIZE(tuner_init_fc0011);
331 init = tuner_init_fc0011;
333 case AF9033_TUNER_MXL5007T:
334 len = ARRAY_SIZE(tuner_init_mxl5007t);
335 init = tuner_init_mxl5007t;
337 case AF9033_TUNER_TDA18218:
338 len = ARRAY_SIZE(tuner_init_tda18218);
339 init = tuner_init_tda18218;
341 case AF9033_TUNER_FC2580:
342 len = ARRAY_SIZE(tuner_init_fc2580);
343 init = tuner_init_fc2580;
345 case AF9033_TUNER_FC0012:
346 len = ARRAY_SIZE(tuner_init_fc0012);
347 init = tuner_init_fc0012;
349 case AF9033_TUNER_IT9135_38:
350 case AF9033_TUNER_IT9135_51:
351 case AF9033_TUNER_IT9135_52:
352 case AF9033_TUNER_IT9135_60:
353 case AF9033_TUNER_IT9135_61:
354 case AF9033_TUNER_IT9135_62:
358 dev_dbg(&state->i2c->dev, "%s: unsupported tuner ID=%d\n",
359 __func__, state->cfg.tuner);
364 for (i = 0; i < len; i++) {
365 ret = af9033_wr_reg(state, init[i].reg, init[i].val);
370 if (state->cfg.ts_mode == AF9033_TS_MODE_SERIAL) {
371 ret = af9033_wr_reg_mask(state, 0x00d91c, 0x01, 0x01);
375 ret = af9033_wr_reg_mask(state, 0x00d917, 0x00, 0x01);
379 ret = af9033_wr_reg_mask(state, 0x00d916, 0x00, 0x01);
384 state->bandwidth_hz = 0; /* force to program all parameters */
389 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
394 static int af9033_sleep(struct dvb_frontend *fe)
396 struct af9033_state *state = fe->demodulator_priv;
400 ret = af9033_wr_reg(state, 0x80004c, 1);
404 ret = af9033_wr_reg(state, 0x800000, 0);
408 for (i = 100, tmp = 1; i && tmp; i--) {
409 ret = af9033_rd_reg(state, 0x80004c, &tmp);
413 usleep_range(200, 10000);
416 dev_dbg(&state->i2c->dev, "%s: loop=%d\n", __func__, i);
423 ret = af9033_wr_reg_mask(state, 0x80fb24, 0x08, 0x08);
427 /* prevent current leak (?) */
428 if (state->cfg.ts_mode == AF9033_TS_MODE_SERIAL) {
429 /* enable parallel TS */
430 ret = af9033_wr_reg_mask(state, 0x00d917, 0x00, 0x01);
434 ret = af9033_wr_reg_mask(state, 0x00d916, 0x01, 0x01);
442 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
447 static int af9033_get_tune_settings(struct dvb_frontend *fe,
448 struct dvb_frontend_tune_settings *fesettings)
450 /* 800 => 2000 because IT9135 v2 is slow to gain lock */
451 fesettings->min_delay_ms = 2000;
452 fesettings->step_size = 0;
453 fesettings->max_drift = 0;
458 static int af9033_set_frontend(struct dvb_frontend *fe)
460 struct af9033_state *state = fe->demodulator_priv;
461 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
462 int ret, i, spec_inv, sampling_freq;
463 u8 tmp, buf[3], bandwidth_reg_val;
464 u32 if_frequency, freq_cw, adc_freq;
466 dev_dbg(&state->i2c->dev, "%s: frequency=%d bandwidth_hz=%d\n",
467 __func__, c->frequency, c->bandwidth_hz);
469 /* check bandwidth */
470 switch (c->bandwidth_hz) {
472 bandwidth_reg_val = 0x00;
475 bandwidth_reg_val = 0x01;
478 bandwidth_reg_val = 0x02;
481 dev_dbg(&state->i2c->dev, "%s: invalid bandwidth_hz\n",
488 if (fe->ops.tuner_ops.set_params)
489 fe->ops.tuner_ops.set_params(fe);
491 /* program CFOE coefficients */
492 if (c->bandwidth_hz != state->bandwidth_hz) {
493 for (i = 0; i < ARRAY_SIZE(coeff_lut); i++) {
494 if (coeff_lut[i].clock == state->cfg.clock &&
495 coeff_lut[i].bandwidth_hz == c->bandwidth_hz) {
499 ret = af9033_wr_regs(state, 0x800001,
500 coeff_lut[i].val, sizeof(coeff_lut[i].val));
503 /* program frequency control */
504 if (c->bandwidth_hz != state->bandwidth_hz) {
505 spec_inv = state->cfg.spec_inv ? -1 : 1;
507 for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) {
508 if (clock_adc_lut[i].clock == state->cfg.clock)
511 adc_freq = clock_adc_lut[i].adc;
513 /* get used IF frequency */
514 if (fe->ops.tuner_ops.get_if_frequency)
515 fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
519 sampling_freq = if_frequency;
521 while (sampling_freq > (adc_freq / 2))
522 sampling_freq -= adc_freq;
524 if (sampling_freq >= 0)
529 freq_cw = af9033_div(state, sampling_freq, adc_freq, 23ul);
532 freq_cw = 0x800000 - freq_cw;
534 if (state->cfg.adc_multiplier == AF9033_ADC_MULTIPLIER_2X)
537 buf[0] = (freq_cw >> 0) & 0xff;
538 buf[1] = (freq_cw >> 8) & 0xff;
539 buf[2] = (freq_cw >> 16) & 0x7f;
541 /* FIXME: there seems to be calculation error here... */
542 if (if_frequency == 0)
545 ret = af9033_wr_regs(state, 0x800029, buf, 3);
549 state->bandwidth_hz = c->bandwidth_hz;
552 ret = af9033_wr_reg_mask(state, 0x80f904, bandwidth_reg_val, 0x03);
556 ret = af9033_wr_reg(state, 0x800040, 0x00);
560 ret = af9033_wr_reg(state, 0x800047, 0x00);
564 ret = af9033_wr_reg_mask(state, 0x80f999, 0x00, 0x01);
568 if (c->frequency <= 230000000)
569 tmp = 0x00; /* VHF */
571 tmp = 0x01; /* UHF */
573 ret = af9033_wr_reg(state, 0x80004b, tmp);
577 ret = af9033_wr_reg(state, 0x800000, 0x00);
584 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
589 static int af9033_get_frontend(struct dvb_frontend *fe)
591 struct af9033_state *state = fe->demodulator_priv;
592 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
596 dev_dbg(&state->i2c->dev, "%s:\n", __func__);
598 /* read all needed registers */
599 ret = af9033_rd_regs(state, 0x80f900, buf, sizeof(buf));
603 switch ((buf[0] >> 0) & 3) {
605 c->transmission_mode = TRANSMISSION_MODE_2K;
608 c->transmission_mode = TRANSMISSION_MODE_8K;
612 switch ((buf[1] >> 0) & 3) {
614 c->guard_interval = GUARD_INTERVAL_1_32;
617 c->guard_interval = GUARD_INTERVAL_1_16;
620 c->guard_interval = GUARD_INTERVAL_1_8;
623 c->guard_interval = GUARD_INTERVAL_1_4;
627 switch ((buf[2] >> 0) & 7) {
629 c->hierarchy = HIERARCHY_NONE;
632 c->hierarchy = HIERARCHY_1;
635 c->hierarchy = HIERARCHY_2;
638 c->hierarchy = HIERARCHY_4;
642 switch ((buf[3] >> 0) & 3) {
644 c->modulation = QPSK;
647 c->modulation = QAM_16;
650 c->modulation = QAM_64;
654 switch ((buf[4] >> 0) & 3) {
656 c->bandwidth_hz = 6000000;
659 c->bandwidth_hz = 7000000;
662 c->bandwidth_hz = 8000000;
666 switch ((buf[6] >> 0) & 7) {
668 c->code_rate_HP = FEC_1_2;
671 c->code_rate_HP = FEC_2_3;
674 c->code_rate_HP = FEC_3_4;
677 c->code_rate_HP = FEC_5_6;
680 c->code_rate_HP = FEC_7_8;
683 c->code_rate_HP = FEC_NONE;
687 switch ((buf[7] >> 0) & 7) {
689 c->code_rate_LP = FEC_1_2;
692 c->code_rate_LP = FEC_2_3;
695 c->code_rate_LP = FEC_3_4;
698 c->code_rate_LP = FEC_5_6;
701 c->code_rate_LP = FEC_7_8;
704 c->code_rate_LP = FEC_NONE;
711 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
716 static int af9033_read_status(struct dvb_frontend *fe, fe_status_t *status)
718 struct af9033_state *state = fe->demodulator_priv;
724 /* radio channel status, 0=no result, 1=has signal, 2=no signal */
725 ret = af9033_rd_reg(state, 0x800047, &tmp);
731 *status |= FE_HAS_SIGNAL;
735 ret = af9033_rd_reg_mask(state, 0x80f5a9, &tmp, 0x01);
740 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
744 ret = af9033_rd_reg_mask(state, 0x80f999, &tmp, 0x01);
749 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
750 FE_HAS_VITERBI | FE_HAS_SYNC |
757 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
762 static int af9033_read_snr(struct dvb_frontend *fe, u16 *snr)
764 struct af9033_state *state = fe->demodulator_priv;
768 const struct val_snr *uninitialized_var(snr_lut);
771 ret = af9033_rd_regs(state, 0x80002c, buf, 3);
775 snr_val = (buf[2] << 16) | (buf[1] << 8) | buf[0];
777 /* read current modulation */
778 ret = af9033_rd_reg(state, 0x80f903, &tmp);
782 switch ((tmp >> 0) & 3) {
784 len = ARRAY_SIZE(qpsk_snr_lut);
785 snr_lut = qpsk_snr_lut;
788 len = ARRAY_SIZE(qam16_snr_lut);
789 snr_lut = qam16_snr_lut;
792 len = ARRAY_SIZE(qam64_snr_lut);
793 snr_lut = qam64_snr_lut;
799 for (i = 0; i < len; i++) {
800 tmp = snr_lut[i].snr;
802 if (snr_val < snr_lut[i].val)
806 *snr = tmp * 10; /* dB/10 */
811 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
816 static int af9033_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
818 struct af9033_state *state = fe->demodulator_priv;
822 /* read signal strength of 0-100 scale */
823 ret = af9033_rd_reg(state, 0x800048, &strength2);
827 /* scale value to 0x0000-0xffff */
828 *strength = strength2 * 0xffff / 100;
833 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
838 static int af9033_update_ch_stat(struct af9033_state *state)
841 u32 err_cnt, bit_cnt;
845 /* only update data every half second */
846 if (time_after(jiffies, state->last_stat_check + msecs_to_jiffies(500))) {
847 ret = af9033_rd_regs(state, 0x800032, buf, sizeof(buf));
850 /* in 8 byte packets? */
851 abort_cnt = (buf[1] << 8) + buf[0];
853 err_cnt = (buf[4] << 16) + (buf[3] << 8) + buf[2];
854 /* in 8 byte packets? always(?) 0x2710 = 10000 */
855 bit_cnt = (buf[6] << 8) + buf[5];
857 if (bit_cnt < abort_cnt) {
859 state->ber = 0xffffffff;
861 /* 8 byte packets, that have not been rejected already */
862 bit_cnt -= (u32)abort_cnt;
864 state->ber = 0xffffffff;
866 err_cnt -= (u32)abort_cnt * 8 * 8;
868 state->ber = err_cnt * (0xffffffff / bit_cnt);
871 state->ucb += abort_cnt;
872 state->last_stat_check = jiffies;
877 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
882 static int af9033_read_ber(struct dvb_frontend *fe, u32 *ber)
884 struct af9033_state *state = fe->demodulator_priv;
887 ret = af9033_update_ch_stat(state);
896 static int af9033_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
898 struct af9033_state *state = fe->demodulator_priv;
901 ret = af9033_update_ch_stat(state);
905 *ucblocks = state->ucb;
910 static int af9033_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
912 struct af9033_state *state = fe->demodulator_priv;
915 dev_dbg(&state->i2c->dev, "%s: enable=%d\n", __func__, enable);
917 ret = af9033_wr_reg_mask(state, 0x00fa04, enable, 0x01);
924 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
929 static struct dvb_frontend_ops af9033_ops;
931 struct dvb_frontend *af9033_attach(const struct af9033_config *config,
932 struct i2c_adapter *i2c)
935 struct af9033_state *state;
938 dev_dbg(&i2c->dev, "%s:\n", __func__);
940 /* allocate memory for the internal state */
941 state = kzalloc(sizeof(struct af9033_state), GFP_KERNEL);
945 /* setup the state */
947 memcpy(&state->cfg, config, sizeof(struct af9033_config));
949 if (state->cfg.clock != 12000000) {
950 dev_err(&state->i2c->dev, "%s: af9033: unsupported clock=%d, " \
951 "only 12000000 Hz is supported currently\n",
952 KBUILD_MODNAME, state->cfg.clock);
956 /* firmware version */
957 ret = af9033_rd_regs(state, 0x0083e9, &buf[0], 4);
961 ret = af9033_rd_regs(state, 0x804191, &buf[4], 4);
965 dev_info(&state->i2c->dev, "%s: firmware version: LINK=%d.%d.%d.%d " \
966 "OFDM=%d.%d.%d.%d\n", KBUILD_MODNAME, buf[0], buf[1],
967 buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]);
970 /* FIXME: Do not abuse adc_multiplier for detecting IT9135 */
971 if (state->cfg.adc_multiplier != AF9033_ADC_MULTIPLIER_2X) {
973 ret = af9033_wr_reg(state, 0x80004c, 1);
977 ret = af9033_wr_reg(state, 0x800000, 0);
982 /* configure internal TS mode */
983 switch (state->cfg.ts_mode) {
984 case AF9033_TS_MODE_PARALLEL:
985 state->ts_mode_parallel = true;
987 case AF9033_TS_MODE_SERIAL:
988 state->ts_mode_serial = true;
990 case AF9033_TS_MODE_USB:
991 /* usb mode for AF9035 */
996 /* create dvb_frontend */
997 memcpy(&state->fe.ops, &af9033_ops, sizeof(struct dvb_frontend_ops));
998 state->fe.demodulator_priv = state;
1006 EXPORT_SYMBOL(af9033_attach);
1008 static struct dvb_frontend_ops af9033_ops = {
1009 .delsys = { SYS_DVBT },
1011 .name = "Afatech AF9033 (DVB-T)",
1012 .frequency_min = 174000000,
1013 .frequency_max = 862000000,
1014 .frequency_stepsize = 250000,
1015 .frequency_tolerance = 0,
1016 .caps = FE_CAN_FEC_1_2 |
1026 FE_CAN_TRANSMISSION_MODE_AUTO |
1027 FE_CAN_GUARD_INTERVAL_AUTO |
1028 FE_CAN_HIERARCHY_AUTO |
1033 .release = af9033_release,
1035 .init = af9033_init,
1036 .sleep = af9033_sleep,
1038 .get_tune_settings = af9033_get_tune_settings,
1039 .set_frontend = af9033_set_frontend,
1040 .get_frontend = af9033_get_frontend,
1042 .read_status = af9033_read_status,
1043 .read_snr = af9033_read_snr,
1044 .read_signal_strength = af9033_read_signal_strength,
1045 .read_ber = af9033_read_ber,
1046 .read_ucblocks = af9033_read_ucblocks,
1048 .i2c_gate_ctrl = af9033_i2c_gate_ctrl,
1051 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1052 MODULE_DESCRIPTION("Afatech AF9033 DVB-T demodulator driver");
1053 MODULE_LICENSE("GPL");