2 * drxk_hard: DRX-K DVB-C/T demodulator driver
4 * Copyright (C) 2010-2011 Digital Devices GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/init.h>
28 #include <linux/delay.h>
29 #include <linux/firmware.h>
30 #include <linux/i2c.h>
31 #include <asm/div64.h>
33 #include "dvb_frontend.h"
35 #include "drxk_hard.h"
37 static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode);
38 static int PowerDownQAM(struct drxk_state *state);
39 static int SetDVBTStandard(struct drxk_state *state,
40 enum OperationMode oMode);
41 static int SetQAMStandard(struct drxk_state *state,
42 enum OperationMode oMode);
43 static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
45 static int SetDVBTStandard(struct drxk_state *state,
46 enum OperationMode oMode);
47 static int DVBTStart(struct drxk_state *state);
48 static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
50 static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus);
51 static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus);
52 static int SwitchAntennaToQAM(struct drxk_state *state);
53 static int SwitchAntennaToDVBT(struct drxk_state *state);
55 static bool IsDVBT(struct drxk_state *state)
57 return state->m_OperationMode == OM_DVBT;
60 static bool IsQAM(struct drxk_state *state)
62 return state->m_OperationMode == OM_QAM_ITU_A ||
63 state->m_OperationMode == OM_QAM_ITU_B ||
64 state->m_OperationMode == OM_QAM_ITU_C;
67 bool IsA1WithPatchCode(struct drxk_state *state)
69 return state->m_DRXK_A1_PATCH_CODE;
72 bool IsA1WithRomCode(struct drxk_state *state)
74 return state->m_DRXK_A1_ROM_CODE;
79 #define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0)
80 #define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0)
82 #define DEFAULT_MER_83 165
83 #define DEFAULT_MER_93 250
85 #ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
86 #define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02)
89 #ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
90 #define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03)
93 #define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700
94 #define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500
96 #ifndef DRXK_KI_RAGC_ATV
97 #define DRXK_KI_RAGC_ATV 4
99 #ifndef DRXK_KI_IAGC_ATV
100 #define DRXK_KI_IAGC_ATV 6
102 #ifndef DRXK_KI_DAGC_ATV
103 #define DRXK_KI_DAGC_ATV 7
106 #ifndef DRXK_KI_RAGC_QAM
107 #define DRXK_KI_RAGC_QAM 3
109 #ifndef DRXK_KI_IAGC_QAM
110 #define DRXK_KI_IAGC_QAM 4
112 #ifndef DRXK_KI_DAGC_QAM
113 #define DRXK_KI_DAGC_QAM 7
115 #ifndef DRXK_KI_RAGC_DVBT
116 #define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2)
118 #ifndef DRXK_KI_IAGC_DVBT
119 #define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2)
121 #ifndef DRXK_KI_DAGC_DVBT
122 #define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7)
125 #ifndef DRXK_AGC_DAC_OFFSET
126 #define DRXK_AGC_DAC_OFFSET (0x800)
129 #ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ
130 #define DRXK_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L)
133 #ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ
134 #define DRXK_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L)
137 #ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ
138 #define DRXK_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L)
141 #ifndef DRXK_QAM_SYMBOLRATE_MAX
142 #define DRXK_QAM_SYMBOLRATE_MAX (7233000)
145 #define DRXK_BL_ROM_OFFSET_TAPS_DVBT 56
146 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_A 64
147 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_C 0x5FE0
148 #define DRXK_BL_ROM_OFFSET_TAPS_BG 24
149 #define DRXK_BL_ROM_OFFSET_TAPS_DKILLP 32
150 #define DRXK_BL_ROM_OFFSET_TAPS_NTSC 40
151 #define DRXK_BL_ROM_OFFSET_TAPS_FM 48
152 #define DRXK_BL_ROM_OFFSET_UCODE 0
154 #define DRXK_BLC_TIMEOUT 100
156 #define DRXK_BLCC_NR_ELEMENTS_TAPS 2
157 #define DRXK_BLCC_NR_ELEMENTS_UCODE 6
159 #define DRXK_BLDC_NR_ELEMENTS_TAPS 28
161 #ifndef DRXK_OFDM_NE_NOTCH_WIDTH
162 #define DRXK_OFDM_NE_NOTCH_WIDTH (4)
165 #define DRXK_QAM_SL_SIG_POWER_QAM16 (40960)
166 #define DRXK_QAM_SL_SIG_POWER_QAM32 (20480)
167 #define DRXK_QAM_SL_SIG_POWER_QAM64 (43008)
168 #define DRXK_QAM_SL_SIG_POWER_QAM128 (20992)
169 #define DRXK_QAM_SL_SIG_POWER_QAM256 (43520)
171 static unsigned int debug;
172 module_param(debug, int, 0644);
173 MODULE_PARM_DESC(debug, "enable debug messages");
175 #define dprintk(level, fmt, arg...) do { \
176 if (debug >= level) \
177 printk(KERN_DEBUG "drxk: %s" fmt, __func__, ## arg); \
181 static inline u32 MulDiv32(u32 a, u32 b, u32 c)
185 tmp64 = (u64) a * (u64) b;
191 inline u32 Frac28a(u32 a, u32 c)
197 R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */
198 Q1 = a / c; /* integer part, only the 4 least significant bits
199 will be visible in the result */
201 /* division using radix 16, 7 nibbles in the result */
202 for (i = 0; i < 7; i++) {
203 Q1 = (Q1 << 4) | (R0 / c);
213 static u32 Log10Times100(u32 x)
215 static const u8 scale = 15;
216 static const u8 indexWidth = 5;
223 log2lut[n] = (1<<scale) * 200 * log2(1.0 + ((1.0/(1<<INDEXWIDTH)) * n))
224 0 <= n < ((1<<INDEXWIDTH)+1)
227 static const u32 log2lut[] = {
229 290941, /* 290941.300628 */
230 573196, /* 573196.476418 */
231 847269, /* 847269.179851 */
232 1113620, /* 1113620.489452 */
233 1372674, /* 1372673.576986 */
234 1624818, /* 1624817.752104 */
235 1870412, /* 1870411.981536 */
236 2109788, /* 2109787.962654 */
237 2343253, /* 2343252.817465 */
238 2571091, /* 2571091.461923 */
239 2793569, /* 2793568.696416 */
240 3010931, /* 3010931.055901 */
241 3223408, /* 3223408.452106 */
242 3431216, /* 3431215.635215 */
243 3634553, /* 3634553.498355 */
244 3833610, /* 3833610.244726 */
245 4028562, /* 4028562.434393 */
246 4219576, /* 4219575.925308 */
247 4406807, /* 4406806.721144 */
248 4590402, /* 4590401.736809 */
249 4770499, /* 4770499.491025 */
250 4947231, /* 4947230.734179 */
251 5120719, /* 5120719.018555 */
252 5291081, /* 5291081.217197 */
253 5458428, /* 5458427.996830 */
254 5622864, /* 5622864.249668 */
255 5784489, /* 5784489.488298 */
256 5943398, /* 5943398.207380 */
257 6099680, /* 6099680.215452 */
258 6253421, /* 6253420.939751 */
259 6404702, /* 6404701.706649 */
260 6553600, /* 6553600.000000 */
267 /* Scale x (normalize) */
268 /* computing y in log(x/y) = log(x) - log(y) */
269 if ((x & ((0xffffffff) << (scale + 1))) == 0) {
270 for (k = scale; k > 0; k--) {
271 if (x & (((u32) 1) << scale))
276 for (k = scale; k < 31; k++) {
277 if ((x & (((u32) (-1)) << (scale + 1))) == 0)
283 Now x has binary point between bit[scale] and bit[scale-1]
284 and 1.0 <= x < 2.0 */
286 /* correction for divison: log(x) = log(x/y)+log(y) */
287 y = k * ((((u32) 1) << scale) * 200);
289 /* remove integer part */
290 x &= ((((u32) 1) << scale) - 1);
292 i = (u8) (x >> (scale - indexWidth));
293 /* compute delta (x - a) */
294 d = x & ((((u32) 1) << (scale - indexWidth)) - 1);
295 /* compute log, multiplication (d* (..)) must be within range ! */
297 ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - indexWidth));
298 /* Conver to log10() */
299 y /= 108853; /* (log2(10) << scale) */
307 /****************************************************************************/
308 /* I2C **********************************************************************/
309 /****************************************************************************/
311 static int i2c_read1(struct i2c_adapter *adapter, u8 adr, u8 *val)
313 struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD,
314 .buf = val, .len = 1}
317 return i2c_transfer(adapter, msgs, 1);
320 static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len)
323 struct i2c_msg msg = {
324 .addr = adr, .flags = 0, .buf = data, .len = len };
329 for (i = 0; i < len; i++)
330 printk(KERN_CONT " %02x", data[i]);
331 printk(KERN_CONT "\n");
333 status = i2c_transfer(adap, &msg, 1);
334 if (status >= 0 && status != 1)
338 printk(KERN_ERR "drxk: i2c write error at addr 0x%02x\n", adr);
343 static int i2c_read(struct i2c_adapter *adap,
344 u8 adr, u8 *msg, int len, u8 *answ, int alen)
347 struct i2c_msg msgs[2] = {
348 {.addr = adr, .flags = 0,
349 .buf = msg, .len = len},
350 {.addr = adr, .flags = I2C_M_RD,
351 .buf = answ, .len = alen}
354 status = i2c_transfer(adap, msgs, 2);
357 printk(KERN_CONT ": ERROR!\n");
361 printk(KERN_ERR "drxk: i2c read error at addr 0x%02x\n", adr);
366 dprintk(2, ": read from");
367 for (i = 0; i < len; i++)
368 printk(KERN_CONT " %02x", msg[i]);
369 printk(KERN_CONT ", value = ");
370 for (i = 0; i < alen; i++)
371 printk(KERN_CONT " %02x", answ[i]);
372 printk(KERN_CONT "\n");
377 static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
380 u8 adr = state->demod_address, mm1[4], mm2[2], len;
382 if (state->single_master)
385 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
386 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
387 mm1[1] = ((reg >> 16) & 0xFF);
388 mm1[2] = ((reg >> 24) & 0xFF) | flags;
389 mm1[3] = ((reg >> 7) & 0xFF);
392 mm1[0] = ((reg << 1) & 0xFF);
393 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
396 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
397 status = i2c_read(state->i2c, adr, mm1, len, mm2, 2);
401 *data = mm2[0] | (mm2[1] << 8);
406 static int read16(struct drxk_state *state, u32 reg, u16 *data)
408 return read16_flags(state, reg, data, 0);
411 static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
414 u8 adr = state->demod_address, mm1[4], mm2[4], len;
416 if (state->single_master)
419 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
420 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
421 mm1[1] = ((reg >> 16) & 0xFF);
422 mm1[2] = ((reg >> 24) & 0xFF) | flags;
423 mm1[3] = ((reg >> 7) & 0xFF);
426 mm1[0] = ((reg << 1) & 0xFF);
427 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
430 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
431 status = i2c_read(state->i2c, adr, mm1, len, mm2, 4);
435 *data = mm2[0] | (mm2[1] << 8) |
436 (mm2[2] << 16) | (mm2[3] << 24);
441 static int read32(struct drxk_state *state, u32 reg, u32 *data)
443 return read32_flags(state, reg, data, 0);
446 static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)
448 u8 adr = state->demod_address, mm[6], len;
450 if (state->single_master)
452 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
453 mm[0] = (((reg << 1) & 0xFF) | 0x01);
454 mm[1] = ((reg >> 16) & 0xFF);
455 mm[2] = ((reg >> 24) & 0xFF) | flags;
456 mm[3] = ((reg >> 7) & 0xFF);
459 mm[0] = ((reg << 1) & 0xFF);
460 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
463 mm[len] = data & 0xff;
464 mm[len + 1] = (data >> 8) & 0xff;
466 dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags);
467 return i2c_write(state->i2c, adr, mm, len + 2);
470 static int write16(struct drxk_state *state, u32 reg, u16 data)
472 return write16_flags(state, reg, data, 0);
475 static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)
477 u8 adr = state->demod_address, mm[8], len;
479 if (state->single_master)
481 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
482 mm[0] = (((reg << 1) & 0xFF) | 0x01);
483 mm[1] = ((reg >> 16) & 0xFF);
484 mm[2] = ((reg >> 24) & 0xFF) | flags;
485 mm[3] = ((reg >> 7) & 0xFF);
488 mm[0] = ((reg << 1) & 0xFF);
489 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
492 mm[len] = data & 0xff;
493 mm[len + 1] = (data >> 8) & 0xff;
494 mm[len + 2] = (data >> 16) & 0xff;
495 mm[len + 3] = (data >> 24) & 0xff;
496 dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags);
498 return i2c_write(state->i2c, adr, mm, len + 4);
501 static int write32(struct drxk_state *state, u32 reg, u32 data)
503 return write32_flags(state, reg, data, 0);
506 static int write_block(struct drxk_state *state, u32 Address,
507 const int BlockSize, const u8 pBlock[])
509 int status = 0, BlkSize = BlockSize;
512 if (state->single_master)
515 while (BlkSize > 0) {
516 int Chunk = BlkSize > state->m_ChunkSize ?
517 state->m_ChunkSize : BlkSize;
518 u8 *AdrBuf = &state->Chunk[0];
521 if (DRXDAP_FASI_LONG_FORMAT(Address) || (Flags != 0)) {
522 AdrBuf[0] = (((Address << 1) & 0xFF) | 0x01);
523 AdrBuf[1] = ((Address >> 16) & 0xFF);
524 AdrBuf[2] = ((Address >> 24) & 0xFF);
525 AdrBuf[3] = ((Address >> 7) & 0xFF);
528 if (Chunk == state->m_ChunkSize)
531 AdrBuf[0] = ((Address << 1) & 0xFF);
532 AdrBuf[1] = (((Address >> 16) & 0x0F) |
533 ((Address >> 18) & 0xF0));
536 memcpy(&state->Chunk[AdrLength], pBlock, Chunk);
537 dprintk(2, "(0x%08x, 0x%02x)\n", Address, Flags);
541 for (i = 0; i < Chunk; i++)
542 printk(KERN_CONT " %02x", pBlock[i]);
543 printk(KERN_CONT "\n");
545 status = i2c_write(state->i2c, state->demod_address,
546 &state->Chunk[0], Chunk + AdrLength);
548 printk(KERN_ERR "drxk: %s: i2c write error at addr 0x%02x\n",
553 Address += (Chunk >> 1);
559 #ifndef DRXK_MAX_RETRIES_POWERUP
560 #define DRXK_MAX_RETRIES_POWERUP 20
563 int PowerUpDevice(struct drxk_state *state)
571 status = i2c_read1(state->i2c, state->demod_address, &data);
575 status = i2c_write(state->i2c, state->demod_address,
581 status = i2c_read1(state->i2c, state->demod_address,
583 } while (status < 0 &&
584 (retryCount < DRXK_MAX_RETRIES_POWERUP));
585 if (status < 0 && retryCount >= DRXK_MAX_RETRIES_POWERUP)
589 /* Make sure all clk domains are active */
590 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
593 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
596 /* Enable pll lock tests */
597 status = write16(state, SIO_CC_PLL_LOCK__A, 1);
601 state->m_currentPowerMode = DRX_POWER_UP;
605 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
611 static int init_state(struct drxk_state *state)
614 * FIXME: most (all?) of the values bellow should be moved into
615 * struct drxk_config, as they are probably board-specific
617 u32 ulVSBIfAgcMode = DRXK_AGC_CTRL_AUTO;
618 u32 ulVSBIfAgcOutputLevel = 0;
619 u32 ulVSBIfAgcMinLevel = 0;
620 u32 ulVSBIfAgcMaxLevel = 0x7FFF;
621 u32 ulVSBIfAgcSpeed = 3;
623 u32 ulVSBRfAgcMode = DRXK_AGC_CTRL_AUTO;
624 u32 ulVSBRfAgcOutputLevel = 0;
625 u32 ulVSBRfAgcMinLevel = 0;
626 u32 ulVSBRfAgcMaxLevel = 0x7FFF;
627 u32 ulVSBRfAgcSpeed = 3;
628 u32 ulVSBRfAgcTop = 9500;
629 u32 ulVSBRfAgcCutOffCurrent = 4000;
631 u32 ulATVIfAgcMode = DRXK_AGC_CTRL_AUTO;
632 u32 ulATVIfAgcOutputLevel = 0;
633 u32 ulATVIfAgcMinLevel = 0;
634 u32 ulATVIfAgcMaxLevel = 0;
635 u32 ulATVIfAgcSpeed = 3;
637 u32 ulATVRfAgcMode = DRXK_AGC_CTRL_OFF;
638 u32 ulATVRfAgcOutputLevel = 0;
639 u32 ulATVRfAgcMinLevel = 0;
640 u32 ulATVRfAgcMaxLevel = 0;
641 u32 ulATVRfAgcTop = 9500;
642 u32 ulATVRfAgcCutOffCurrent = 4000;
643 u32 ulATVRfAgcSpeed = 3;
645 u32 ulQual83 = DEFAULT_MER_83;
646 u32 ulQual93 = DEFAULT_MER_93;
648 u32 ulMpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
649 u32 ulDemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
651 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
652 /* io_pad_cfg_mode output mode is drive always */
653 /* io_pad_cfg_drive is set to power 2 (23 mA) */
654 u32 ulGPIOCfg = 0x0113;
655 u32 ulInvertTSClock = 0;
656 u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH;
657 u32 ulDVBTBitrate = 50000000;
658 u32 ulDVBCBitrate = DRXK_QAM_SYMBOLRATE_MAX * 8;
660 u32 ulInsertRSByte = 0;
667 state->m_hasLNA = false;
668 state->m_hasDVBT = false;
669 state->m_hasDVBC = false;
670 state->m_hasATV = false;
671 state->m_hasOOB = false;
672 state->m_hasAudio = false;
674 if (!state->m_ChunkSize)
675 state->m_ChunkSize = 124;
677 state->m_oscClockFreq = 0;
678 state->m_smartAntInverted = false;
679 state->m_bPDownOpenBridge = false;
681 /* real system clock frequency in kHz */
682 state->m_sysClockFreq = 151875;
683 /* Timing div, 250ns/Psys */
684 /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */
685 state->m_HICfgTimingDiv = ((state->m_sysClockFreq / 1000) *
686 HI_I2C_DELAY) / 1000;
688 if (state->m_HICfgTimingDiv > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
689 state->m_HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
690 state->m_HICfgWakeUpKey = (state->demod_address << 1);
691 /* port/bridge/power down ctrl */
692 state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
694 state->m_bPowerDown = (ulPowerDown != 0);
696 state->m_DRXK_A1_PATCH_CODE = false;
697 state->m_DRXK_A1_ROM_CODE = false;
698 state->m_DRXK_A2_ROM_CODE = false;
699 state->m_DRXK_A3_ROM_CODE = false;
700 state->m_DRXK_A2_PATCH_CODE = false;
701 state->m_DRXK_A3_PATCH_CODE = false;
703 /* Init AGC and PGA parameters */
705 state->m_vsbIfAgcCfg.ctrlMode = (ulVSBIfAgcMode);
706 state->m_vsbIfAgcCfg.outputLevel = (ulVSBIfAgcOutputLevel);
707 state->m_vsbIfAgcCfg.minOutputLevel = (ulVSBIfAgcMinLevel);
708 state->m_vsbIfAgcCfg.maxOutputLevel = (ulVSBIfAgcMaxLevel);
709 state->m_vsbIfAgcCfg.speed = (ulVSBIfAgcSpeed);
710 state->m_vsbPgaCfg = 140;
713 state->m_vsbRfAgcCfg.ctrlMode = (ulVSBRfAgcMode);
714 state->m_vsbRfAgcCfg.outputLevel = (ulVSBRfAgcOutputLevel);
715 state->m_vsbRfAgcCfg.minOutputLevel = (ulVSBRfAgcMinLevel);
716 state->m_vsbRfAgcCfg.maxOutputLevel = (ulVSBRfAgcMaxLevel);
717 state->m_vsbRfAgcCfg.speed = (ulVSBRfAgcSpeed);
718 state->m_vsbRfAgcCfg.top = (ulVSBRfAgcTop);
719 state->m_vsbRfAgcCfg.cutOffCurrent = (ulVSBRfAgcCutOffCurrent);
720 state->m_vsbPreSawCfg.reference = 0x07;
721 state->m_vsbPreSawCfg.usePreSaw = true;
723 state->m_Quality83percent = DEFAULT_MER_83;
724 state->m_Quality93percent = DEFAULT_MER_93;
725 if (ulQual93 <= 500 && ulQual83 < ulQual93) {
726 state->m_Quality83percent = ulQual83;
727 state->m_Quality93percent = ulQual93;
731 state->m_atvIfAgcCfg.ctrlMode = (ulATVIfAgcMode);
732 state->m_atvIfAgcCfg.outputLevel = (ulATVIfAgcOutputLevel);
733 state->m_atvIfAgcCfg.minOutputLevel = (ulATVIfAgcMinLevel);
734 state->m_atvIfAgcCfg.maxOutputLevel = (ulATVIfAgcMaxLevel);
735 state->m_atvIfAgcCfg.speed = (ulATVIfAgcSpeed);
738 state->m_atvRfAgcCfg.ctrlMode = (ulATVRfAgcMode);
739 state->m_atvRfAgcCfg.outputLevel = (ulATVRfAgcOutputLevel);
740 state->m_atvRfAgcCfg.minOutputLevel = (ulATVRfAgcMinLevel);
741 state->m_atvRfAgcCfg.maxOutputLevel = (ulATVRfAgcMaxLevel);
742 state->m_atvRfAgcCfg.speed = (ulATVRfAgcSpeed);
743 state->m_atvRfAgcCfg.top = (ulATVRfAgcTop);
744 state->m_atvRfAgcCfg.cutOffCurrent = (ulATVRfAgcCutOffCurrent);
745 state->m_atvPreSawCfg.reference = 0x04;
746 state->m_atvPreSawCfg.usePreSaw = true;
750 state->m_dvbtRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
751 state->m_dvbtRfAgcCfg.outputLevel = 0;
752 state->m_dvbtRfAgcCfg.minOutputLevel = 0;
753 state->m_dvbtRfAgcCfg.maxOutputLevel = 0xFFFF;
754 state->m_dvbtRfAgcCfg.top = 0x2100;
755 state->m_dvbtRfAgcCfg.cutOffCurrent = 4000;
756 state->m_dvbtRfAgcCfg.speed = 1;
760 state->m_dvbtIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
761 state->m_dvbtIfAgcCfg.outputLevel = 0;
762 state->m_dvbtIfAgcCfg.minOutputLevel = 0;
763 state->m_dvbtIfAgcCfg.maxOutputLevel = 9000;
764 state->m_dvbtIfAgcCfg.top = 13424;
765 state->m_dvbtIfAgcCfg.cutOffCurrent = 0;
766 state->m_dvbtIfAgcCfg.speed = 3;
767 state->m_dvbtIfAgcCfg.FastClipCtrlDelay = 30;
768 state->m_dvbtIfAgcCfg.IngainTgtMax = 30000;
769 /* state->m_dvbtPgaCfg = 140; */
771 state->m_dvbtPreSawCfg.reference = 4;
772 state->m_dvbtPreSawCfg.usePreSaw = false;
775 state->m_qamRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
776 state->m_qamRfAgcCfg.outputLevel = 0;
777 state->m_qamRfAgcCfg.minOutputLevel = 6023;
778 state->m_qamRfAgcCfg.maxOutputLevel = 27000;
779 state->m_qamRfAgcCfg.top = 0x2380;
780 state->m_qamRfAgcCfg.cutOffCurrent = 4000;
781 state->m_qamRfAgcCfg.speed = 3;
784 state->m_qamIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
785 state->m_qamIfAgcCfg.outputLevel = 0;
786 state->m_qamIfAgcCfg.minOutputLevel = 0;
787 state->m_qamIfAgcCfg.maxOutputLevel = 9000;
788 state->m_qamIfAgcCfg.top = 0x0511;
789 state->m_qamIfAgcCfg.cutOffCurrent = 0;
790 state->m_qamIfAgcCfg.speed = 3;
791 state->m_qamIfAgcCfg.IngainTgtMax = 5119;
792 state->m_qamIfAgcCfg.FastClipCtrlDelay = 50;
794 state->m_qamPgaCfg = 140;
795 state->m_qamPreSawCfg.reference = 4;
796 state->m_qamPreSawCfg.usePreSaw = false;
798 state->m_OperationMode = OM_NONE;
799 state->m_DrxkState = DRXK_UNINITIALIZED;
801 /* MPEG output configuration */
802 state->m_enableMPEGOutput = true; /* If TRUE; enable MPEG ouput */
803 state->m_insertRSByte = false; /* If TRUE; insert RS byte */
804 state->m_invertDATA = false; /* If TRUE; invert DATA signals */
805 state->m_invertERR = false; /* If TRUE; invert ERR signal */
806 state->m_invertSTR = false; /* If TRUE; invert STR signals */
807 state->m_invertVAL = false; /* If TRUE; invert VAL signals */
808 state->m_invertCLK = (ulInvertTSClock != 0); /* If TRUE; invert CLK signals */
810 /* If TRUE; static MPEG clockrate will be used;
811 otherwise clockrate will adapt to the bitrate of the TS */
813 state->m_DVBTBitrate = ulDVBTBitrate;
814 state->m_DVBCBitrate = ulDVBCBitrate;
816 state->m_TSDataStrength = (ulTSDataStrength & 0x07);
818 /* Maximum bitrate in b/s in case static clockrate is selected */
819 state->m_mpegTsStaticBitrate = 19392658;
820 state->m_disableTEIhandling = false;
823 state->m_insertRSByte = true;
825 state->m_MpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
826 if (ulMpegLockTimeOut < 10000)
827 state->m_MpegLockTimeOut = ulMpegLockTimeOut;
828 state->m_DemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
829 if (ulDemodLockTimeOut < 10000)
830 state->m_DemodLockTimeOut = ulDemodLockTimeOut;
833 state->m_Constellation = DRX_CONSTELLATION_AUTO;
834 state->m_qamInterleaveMode = DRXK_QAM_I12_J17;
835 state->m_fecRsPlen = 204 * 8; /* fecRsPlen annex A */
836 state->m_fecRsPrescale = 1;
838 state->m_sqiSpeed = DRXK_DVBT_SQI_SPEED_MEDIUM;
839 state->m_agcFastClipCtrlDelay = 0;
841 state->m_GPIOCfg = (ulGPIOCfg);
843 state->m_bPowerDown = false;
844 state->m_currentPowerMode = DRX_POWER_DOWN;
846 state->m_rfmirror = (ulRfMirror == 0);
847 state->m_IfAgcPol = false;
851 static int DRXX_Open(struct drxk_state *state)
859 /* stop lock indicator process */
860 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
863 /* Check device id */
864 status = read16(state, SIO_TOP_COMM_KEY__A, &key);
867 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
870 status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
873 status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);
876 status = write16(state, SIO_TOP_COMM_KEY__A, key);
879 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
883 static int GetDeviceCapabilities(struct drxk_state *state)
885 u16 sioPdrOhwCfg = 0;
886 u32 sioTopJtagidLo = 0;
888 const char *spin = "";
893 /* stop lock indicator process */
894 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
897 status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA);
900 status = read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg);
903 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
907 switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
909 /* ignore (bypass ?) */
913 state->m_oscClockFreq = 27000;
917 state->m_oscClockFreq = 20250;
921 state->m_oscClockFreq = 20250;
924 printk(KERN_ERR "drxk: Clock Frequency is unkonwn\n");
928 Determine device capabilities
931 status = read32(state, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo);
935 printk(KERN_ERR "drxk: status = 0x%08x\n", sioTopJtagidLo);
938 switch ((sioTopJtagidLo >> 29) & 0xF) {
940 state->m_deviceSpin = DRXK_SPIN_A1;
944 state->m_deviceSpin = DRXK_SPIN_A2;
948 state->m_deviceSpin = DRXK_SPIN_A3;
952 state->m_deviceSpin = DRXK_SPIN_UNKNOWN;
954 printk(KERN_ERR "drxk: Spin %d unknown\n",
955 (sioTopJtagidLo >> 29) & 0xF);
958 switch ((sioTopJtagidLo >> 12) & 0xFF) {
960 /* typeId = DRX3913K_TYPE_ID */
961 state->m_hasLNA = false;
962 state->m_hasOOB = false;
963 state->m_hasATV = false;
964 state->m_hasAudio = false;
965 state->m_hasDVBT = true;
966 state->m_hasDVBC = true;
967 state->m_hasSAWSW = true;
968 state->m_hasGPIO2 = false;
969 state->m_hasGPIO1 = false;
970 state->m_hasIRQN = false;
973 /* typeId = DRX3915K_TYPE_ID */
974 state->m_hasLNA = false;
975 state->m_hasOOB = false;
976 state->m_hasATV = true;
977 state->m_hasAudio = false;
978 state->m_hasDVBT = true;
979 state->m_hasDVBC = false;
980 state->m_hasSAWSW = true;
981 state->m_hasGPIO2 = true;
982 state->m_hasGPIO1 = true;
983 state->m_hasIRQN = false;
986 /* typeId = DRX3916K_TYPE_ID */
987 state->m_hasLNA = false;
988 state->m_hasOOB = false;
989 state->m_hasATV = true;
990 state->m_hasAudio = false;
991 state->m_hasDVBT = true;
992 state->m_hasDVBC = false;
993 state->m_hasSAWSW = true;
994 state->m_hasGPIO2 = true;
995 state->m_hasGPIO1 = true;
996 state->m_hasIRQN = false;
999 /* typeId = DRX3918K_TYPE_ID */
1000 state->m_hasLNA = false;
1001 state->m_hasOOB = false;
1002 state->m_hasATV = true;
1003 state->m_hasAudio = true;
1004 state->m_hasDVBT = true;
1005 state->m_hasDVBC = false;
1006 state->m_hasSAWSW = true;
1007 state->m_hasGPIO2 = true;
1008 state->m_hasGPIO1 = true;
1009 state->m_hasIRQN = false;
1012 /* typeId = DRX3921K_TYPE_ID */
1013 state->m_hasLNA = false;
1014 state->m_hasOOB = false;
1015 state->m_hasATV = true;
1016 state->m_hasAudio = true;
1017 state->m_hasDVBT = true;
1018 state->m_hasDVBC = true;
1019 state->m_hasSAWSW = true;
1020 state->m_hasGPIO2 = true;
1021 state->m_hasGPIO1 = true;
1022 state->m_hasIRQN = false;
1025 /* typeId = DRX3923K_TYPE_ID */
1026 state->m_hasLNA = false;
1027 state->m_hasOOB = false;
1028 state->m_hasATV = true;
1029 state->m_hasAudio = true;
1030 state->m_hasDVBT = true;
1031 state->m_hasDVBC = true;
1032 state->m_hasSAWSW = true;
1033 state->m_hasGPIO2 = true;
1034 state->m_hasGPIO1 = true;
1035 state->m_hasIRQN = false;
1038 /* typeId = DRX3925K_TYPE_ID */
1039 state->m_hasLNA = false;
1040 state->m_hasOOB = false;
1041 state->m_hasATV = true;
1042 state->m_hasAudio = true;
1043 state->m_hasDVBT = true;
1044 state->m_hasDVBC = true;
1045 state->m_hasSAWSW = true;
1046 state->m_hasGPIO2 = true;
1047 state->m_hasGPIO1 = true;
1048 state->m_hasIRQN = false;
1051 /* typeId = DRX3926K_TYPE_ID */
1052 state->m_hasLNA = false;
1053 state->m_hasOOB = false;
1054 state->m_hasATV = true;
1055 state->m_hasAudio = false;
1056 state->m_hasDVBT = true;
1057 state->m_hasDVBC = true;
1058 state->m_hasSAWSW = true;
1059 state->m_hasGPIO2 = true;
1060 state->m_hasGPIO1 = true;
1061 state->m_hasIRQN = false;
1064 printk(KERN_ERR "drxk: DeviceID 0x%02x not supported\n",
1065 ((sioTopJtagidLo >> 12) & 0xFF));
1071 "drxk: detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n",
1072 ((sioTopJtagidLo >> 12) & 0xFF), spin,
1073 state->m_oscClockFreq / 1000,
1074 state->m_oscClockFreq % 1000);
1078 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1084 static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult)
1092 status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);
1095 if (cmd == SIO_HI_RA_RAM_CMD_RESET)
1099 (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
1100 ((state->m_HICfgCtrl) &
1101 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) ==
1102 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ);
1103 if (powerdown_cmd == false) {
1104 /* Wait until command rdy */
1111 status = read16(state, SIO_HI_RA_RAM_CMD__A,
1113 } while ((status < 0) && (retryCount < DRXK_MAX_RETRIES)
1117 status = read16(state, SIO_HI_RA_RAM_RES__A, pResult);
1121 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1126 static int HI_CfgCommand(struct drxk_state *state)
1132 mutex_lock(&state->mutex);
1134 status = write16(state, SIO_HI_RA_RAM_PAR_6__A, state->m_HICfgTimeout);
1137 status = write16(state, SIO_HI_RA_RAM_PAR_5__A, state->m_HICfgCtrl);
1140 status = write16(state, SIO_HI_RA_RAM_PAR_4__A, state->m_HICfgWakeUpKey);
1143 status = write16(state, SIO_HI_RA_RAM_PAR_3__A, state->m_HICfgBridgeDelay);
1146 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, state->m_HICfgTimingDiv);
1149 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
1152 status = HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0);
1156 state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1158 mutex_unlock(&state->mutex);
1160 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1164 static int InitHI(struct drxk_state *state)
1168 state->m_HICfgWakeUpKey = (state->demod_address << 1);
1169 state->m_HICfgTimeout = 0x96FF;
1170 /* port/bridge/power down ctrl */
1171 state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
1173 return HI_CfgCommand(state);
1176 static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)
1179 u16 sioPdrMclkCfg = 0;
1180 u16 sioPdrMdxCfg = 0;
1183 dprintk(1, ": mpeg %s, %s mode\n",
1184 mpegEnable ? "enable" : "disable",
1185 state->m_enableParallel ? "parallel" : "serial");
1187 /* stop lock indicator process */
1188 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1192 /* MPEG TS pad configuration */
1193 status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA);
1197 if (mpegEnable == false) {
1198 /* Set MPEG TS pads to inputmode */
1199 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
1202 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);
1205 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);
1208 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);
1211 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);
1214 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1217 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1220 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1223 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1226 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1229 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1232 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1236 /* Enable MPEG output */
1238 ((state->m_TSDataStrength <<
1239 SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003);
1240 sioPdrMclkCfg = ((state->m_TSClockkStrength <<
1241 SIO_PDR_MCLK_CFG_DRIVE__B) |
1244 status = write16(state, SIO_PDR_MSTRT_CFG__A, sioPdrMdxCfg);
1248 if (state->enable_merr_cfg)
1249 err_cfg = sioPdrMdxCfg;
1251 status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg);
1254 status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg);
1258 if (state->m_enableParallel == true) {
1259 /* paralel -> enable MD1 to MD7 */
1260 status = write16(state, SIO_PDR_MD1_CFG__A, sioPdrMdxCfg);
1263 status = write16(state, SIO_PDR_MD2_CFG__A, sioPdrMdxCfg);
1266 status = write16(state, SIO_PDR_MD3_CFG__A, sioPdrMdxCfg);
1269 status = write16(state, SIO_PDR_MD4_CFG__A, sioPdrMdxCfg);
1272 status = write16(state, SIO_PDR_MD5_CFG__A, sioPdrMdxCfg);
1275 status = write16(state, SIO_PDR_MD6_CFG__A, sioPdrMdxCfg);
1278 status = write16(state, SIO_PDR_MD7_CFG__A, sioPdrMdxCfg);
1282 sioPdrMdxCfg = ((state->m_TSDataStrength <<
1283 SIO_PDR_MD0_CFG_DRIVE__B)
1285 /* serial -> disable MD1 to MD7 */
1286 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1289 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1292 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1295 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1298 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1301 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1304 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1308 status = write16(state, SIO_PDR_MCLK_CFG__A, sioPdrMclkCfg);
1311 status = write16(state, SIO_PDR_MD0_CFG__A, sioPdrMdxCfg);
1315 /* Enable MB output over MPEG pads and ctl input */
1316 status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
1319 /* Write nomagic word to enable pdr reg write */
1320 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
1323 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1327 static int MPEGTSDisable(struct drxk_state *state)
1331 return MPEGTSConfigurePins(state, false);
1334 static int BLChainCmd(struct drxk_state *state,
1335 u16 romOffset, u16 nrOfElements, u32 timeOut)
1342 mutex_lock(&state->mutex);
1343 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1346 status = write16(state, SIO_BL_CHAIN_ADDR__A, romOffset);
1349 status = write16(state, SIO_BL_CHAIN_LEN__A, nrOfElements);
1352 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1356 end = jiffies + msecs_to_jiffies(timeOut);
1359 status = read16(state, SIO_BL_STATUS__A, &blStatus);
1362 } while ((blStatus == 0x1) &&
1363 ((time_is_after_jiffies(end))));
1365 if (blStatus == 0x1) {
1366 printk(KERN_ERR "drxk: SIO not ready\n");
1372 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1374 mutex_unlock(&state->mutex);
1379 static int DownloadMicrocode(struct drxk_state *state,
1380 const u8 pMCImage[], u32 Length)
1382 const u8 *pSrc = pMCImage;
1395 /* down the drain (we don care about MAGIC_WORD) */
1396 Drain = (pSrc[0] << 8) | pSrc[1];
1397 pSrc += sizeof(u16);
1398 offset += sizeof(u16);
1399 nBlocks = (pSrc[0] << 8) | pSrc[1];
1400 pSrc += sizeof(u16);
1401 offset += sizeof(u16);
1403 for (i = 0; i < nBlocks; i += 1) {
1404 Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
1405 (pSrc[2] << 8) | pSrc[3];
1406 pSrc += sizeof(u32);
1407 offset += sizeof(u32);
1409 BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
1410 pSrc += sizeof(u16);
1411 offset += sizeof(u16);
1413 Flags = (pSrc[0] << 8) | pSrc[1];
1414 pSrc += sizeof(u16);
1415 offset += sizeof(u16);
1417 BlockCRC = (pSrc[0] << 8) | pSrc[1];
1418 pSrc += sizeof(u16);
1419 offset += sizeof(u16);
1421 if (offset + BlockSize > Length) {
1422 printk(KERN_ERR "drxk: Firmware is corrupted.\n");
1426 status = write_block(state, Address, BlockSize, pSrc);
1428 printk(KERN_ERR "drxk: Error %d while loading firmware\n", status);
1432 offset += BlockSize;
1437 static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable)
1441 u16 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON;
1442 u16 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED;
1447 if (enable == false) {
1448 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF;
1449 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN;
1452 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1453 if (status >= 0 && data == desiredStatus) {
1454 /* tokenring already has correct status */
1457 /* Disable/enable dvbt tokenring bridge */
1458 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl);
1460 end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
1462 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1463 if ((status >= 0 && data == desiredStatus) || time_is_after_jiffies(end))
1467 if (data != desiredStatus) {
1468 printk(KERN_ERR "drxk: SIO not ready\n");
1474 static int MPEGTSStop(struct drxk_state *state)
1477 u16 fecOcSncMode = 0;
1478 u16 fecOcIprMode = 0;
1482 /* Gracefull shutdown (byte boundaries) */
1483 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1486 fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M;
1487 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1491 /* Suppress MCLK during absence of data */
1492 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcIprMode);
1495 fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M;
1496 status = write16(state, FEC_OC_IPR_MODE__A, fecOcIprMode);
1500 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1505 static int scu_command(struct drxk_state *state,
1506 u16 cmd, u8 parameterLen,
1507 u16 *parameter, u8 resultLen, u16 *result)
1509 #if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15
1510 #error DRXK register mapping no longer compatible with this routine!
1513 int status = -EINVAL;
1522 if ((cmd == 0) || ((parameterLen > 0) && (parameter == NULL)) ||
1523 ((resultLen > 0) && (result == NULL))) {
1524 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1528 mutex_lock(&state->mutex);
1530 /* assume that the command register is ready
1531 since it is checked afterwards */
1532 for (ii = parameterLen - 1; ii >= 0; ii -= 1) {
1533 buffer[cnt++] = (parameter[ii] & 0xFF);
1534 buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF);
1536 buffer[cnt++] = (cmd & 0xFF);
1537 buffer[cnt++] = ((cmd >> 8) & 0xFF);
1539 write_block(state, SCU_RAM_PARAM_0__A -
1540 (parameterLen - 1), cnt, buffer);
1541 /* Wait until SCU has processed command */
1542 end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
1545 status = read16(state, SCU_RAM_COMMAND__A, &curCmd);
1548 } while (!(curCmd == DRX_SCU_READY) && (time_is_after_jiffies(end)));
1549 if (curCmd != DRX_SCU_READY) {
1550 printk(KERN_ERR "drxk: SCU not ready\n");
1555 if ((resultLen > 0) && (result != NULL)) {
1559 for (ii = resultLen - 1; ii >= 0; ii -= 1) {
1560 status = read16(state, SCU_RAM_PARAM_0__A - ii, &result[ii]);
1565 /* Check if an error was reported by SCU */
1566 err = (s16)result[0];
1570 /* check for the known error codes */
1572 case SCU_RESULT_UNKCMD:
1573 p = "SCU_RESULT_UNKCMD";
1575 case SCU_RESULT_UNKSTD:
1576 p = "SCU_RESULT_UNKSTD";
1578 case SCU_RESULT_SIZE:
1579 p = "SCU_RESULT_SIZE";
1581 case SCU_RESULT_INVPAR:
1582 p = "SCU_RESULT_INVPAR";
1584 default: /* Other negative values are errors */
1585 sprintf(errname, "ERROR: %d\n", err);
1588 printk(KERN_ERR "drxk: %s while sending cmd 0x%04x with params:", p, cmd);
1589 print_hex_dump_bytes("drxk: ", DUMP_PREFIX_NONE, buffer, cnt);
1596 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1598 mutex_unlock(&state->mutex);
1602 static int SetIqmAf(struct drxk_state *state, bool active)
1610 status = read16(state, IQM_AF_STDBY__A, &data);
1615 data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY
1616 | IQM_AF_STDBY_STDBY_AMP_STANDBY
1617 | IQM_AF_STDBY_STDBY_PD_STANDBY
1618 | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
1619 | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY);
1621 data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY)
1622 & (~IQM_AF_STDBY_STDBY_AMP_STANDBY)
1623 & (~IQM_AF_STDBY_STDBY_PD_STANDBY)
1624 & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY)
1625 & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY)
1628 status = write16(state, IQM_AF_STDBY__A, data);
1632 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1636 static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode)
1639 u16 sioCcPwdMode = 0;
1643 /* Check arguments */
1649 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_NONE;
1651 case DRXK_POWER_DOWN_OFDM:
1652 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OFDM;
1654 case DRXK_POWER_DOWN_CORE:
1655 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
1657 case DRXK_POWER_DOWN_PLL:
1658 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_PLL;
1660 case DRX_POWER_DOWN:
1661 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OSC;
1664 /* Unknow sleep mode */
1668 /* If already in requested power mode, do nothing */
1669 if (state->m_currentPowerMode == *mode)
1672 /* For next steps make sure to start from DRX_POWER_UP mode */
1673 if (state->m_currentPowerMode != DRX_POWER_UP) {
1674 status = PowerUpDevice(state);
1677 status = DVBTEnableOFDMTokenRing(state, true);
1682 if (*mode == DRX_POWER_UP) {
1683 /* Restore analog & pin configuartion */
1685 /* Power down to requested mode */
1686 /* Backup some register settings */
1687 /* Set pins with possible pull-ups connected
1688 to them in input mode */
1689 /* Analog power down */
1690 /* ADC power down */
1691 /* Power down device */
1692 /* stop all comm_exec */
1693 /* Stop and power down previous standard */
1694 switch (state->m_OperationMode) {
1696 status = MPEGTSStop(state);
1699 status = PowerDownDVBT(state, false);
1705 status = MPEGTSStop(state);
1708 status = PowerDownQAM(state);
1715 status = DVBTEnableOFDMTokenRing(state, false);
1718 status = write16(state, SIO_CC_PWD_MODE__A, sioCcPwdMode);
1721 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
1725 if (*mode != DRXK_POWER_DOWN_OFDM) {
1726 state->m_HICfgCtrl |=
1727 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1728 status = HI_CfgCommand(state);
1733 state->m_currentPowerMode = *mode;
1737 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1742 static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode)
1744 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
1751 status = read16(state, SCU_COMM_EXEC__A, &data);
1754 if (data == SCU_COMM_EXEC_ACTIVE) {
1755 /* Send OFDM stop command */
1756 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
1759 /* Send OFDM reset command */
1760 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
1765 /* Reset datapath for OFDM, processors first */
1766 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1769 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1772 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
1777 status = SetIqmAf(state, false);
1781 /* powerdown to OFDM mode */
1783 status = CtrlPowerMode(state, &powerMode);
1789 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1793 static int SetOperationMode(struct drxk_state *state,
1794 enum OperationMode oMode)
1800 Stop and power down previous standard
1801 TODO investigate total power down instead of partial
1802 power down depending on "previous" standard.
1805 /* disable HW lock indicator */
1806 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1810 /* Device is already at the required mode */
1811 if (state->m_OperationMode == oMode)
1814 switch (state->m_OperationMode) {
1815 /* OM_NONE was added for start up */
1819 status = MPEGTSStop(state);
1822 status = PowerDownDVBT(state, true);
1825 state->m_OperationMode = OM_NONE;
1827 case OM_QAM_ITU_A: /* fallthrough */
1829 status = MPEGTSStop(state);
1832 status = PowerDownQAM(state);
1835 state->m_OperationMode = OM_NONE;
1844 Power up new standard
1848 dprintk(1, ": DVB-T\n");
1849 state->m_OperationMode = oMode;
1850 status = SetDVBTStandard(state, oMode);
1854 case OM_QAM_ITU_A: /* fallthrough */
1856 dprintk(1, ": DVB-C Annex %c\n",
1857 (state->m_OperationMode == OM_QAM_ITU_A) ? 'A' : 'C');
1858 state->m_OperationMode = oMode;
1859 status = SetQAMStandard(state, oMode);
1869 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1873 static int Start(struct drxk_state *state, s32 offsetFreq,
1874 s32 IntermediateFrequency)
1876 int status = -EINVAL;
1879 s32 OffsetkHz = offsetFreq / 1000;
1882 if (state->m_DrxkState != DRXK_STOPPED &&
1883 state->m_DrxkState != DRXK_DTV_STARTED)
1886 state->m_bMirrorFreqSpect = (state->props.inversion == INVERSION_ON);
1888 if (IntermediateFrequency < 0) {
1889 state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect;
1890 IntermediateFrequency = -IntermediateFrequency;
1893 switch (state->m_OperationMode) {
1896 IFreqkHz = (IntermediateFrequency / 1000);
1897 status = SetQAM(state, IFreqkHz, OffsetkHz);
1900 state->m_DrxkState = DRXK_DTV_STARTED;
1903 IFreqkHz = (IntermediateFrequency / 1000);
1904 status = MPEGTSStop(state);
1907 status = SetDVBT(state, IFreqkHz, OffsetkHz);
1910 status = DVBTStart(state);
1913 state->m_DrxkState = DRXK_DTV_STARTED;
1920 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1924 static int ShutDown(struct drxk_state *state)
1932 static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus,
1935 int status = -EINVAL;
1939 if (pLockStatus == NULL)
1942 *pLockStatus = NOT_LOCKED;
1944 /* define the SCU command code */
1945 switch (state->m_OperationMode) {
1949 status = GetQAMLockStatus(state, pLockStatus);
1952 status = GetDVBTLockStatus(state, pLockStatus);
1959 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1963 static int MPEGTSStart(struct drxk_state *state)
1967 u16 fecOcSncMode = 0;
1969 /* Allow OC to sync again */
1970 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1973 fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M;
1974 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1977 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
1980 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1984 static int MPEGTSDtoInit(struct drxk_state *state)
1990 /* Rate integration settings */
1991 status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
1994 status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
1997 status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);
2000 status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);
2003 status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);
2006 status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
2009 status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
2012 status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);
2016 /* Additional configuration */
2017 status = write16(state, FEC_OC_OCR_INVERT__A, 0);
2020 status = write16(state, FEC_OC_SNC_LWM__A, 2);
2023 status = write16(state, FEC_OC_SNC_HWM__A, 12);
2026 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2031 static int MPEGTSDtoSetup(struct drxk_state *state,
2032 enum OperationMode oMode)
2036 u16 fecOcRegMode = 0; /* FEC_OC_MODE register value */
2037 u16 fecOcRegIprMode = 0; /* FEC_OC_IPR_MODE register value */
2038 u16 fecOcDtoMode = 0; /* FEC_OC_IPR_INVERT register value */
2039 u16 fecOcFctMode = 0; /* FEC_OC_IPR_INVERT register value */
2040 u16 fecOcDtoPeriod = 2; /* FEC_OC_IPR_INVERT register value */
2041 u16 fecOcDtoBurstLen = 188; /* FEC_OC_IPR_INVERT register value */
2042 u32 fecOcRcnCtlRate = 0; /* FEC_OC_IPR_INVERT register value */
2043 u16 fecOcTmdMode = 0;
2044 u16 fecOcTmdIntUpdRate = 0;
2046 bool staticCLK = false;
2050 /* Check insertion of the Reed-Solomon parity bytes */
2051 status = read16(state, FEC_OC_MODE__A, &fecOcRegMode);
2054 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcRegIprMode);
2057 fecOcRegMode &= (~FEC_OC_MODE_PARITY__M);
2058 fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
2059 if (state->m_insertRSByte == true) {
2060 /* enable parity symbol forward */
2061 fecOcRegMode |= FEC_OC_MODE_PARITY__M;
2062 /* MVAL disable during parity bytes */
2063 fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
2064 /* TS burst length to 204 */
2065 fecOcDtoBurstLen = 204;
2068 /* Check serial or parrallel output */
2069 fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
2070 if (state->m_enableParallel == false) {
2071 /* MPEG data output is serial -> set ipr_mode[0] */
2072 fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M;
2077 maxBitRate = state->m_DVBTBitrate;
2079 fecOcRcnCtlRate = 0xC00000;
2080 staticCLK = state->m_DVBTStaticCLK;
2082 case OM_QAM_ITU_A: /* fallthrough */
2084 fecOcTmdMode = 0x0004;
2085 fecOcRcnCtlRate = 0xD2B4EE; /* good for >63 Mb/s */
2086 maxBitRate = state->m_DVBCBitrate;
2087 staticCLK = state->m_DVBCStaticCLK;
2091 } /* switch (standard) */
2095 /* Configure DTO's */
2099 /* Rational DTO for MCLK source (static MCLK rate),
2100 Dynamic DTO for optimal grouping
2101 (avoid intra-packet gaps),
2102 DTO offset enable to sync TS burst with MSTRT */
2103 fecOcDtoMode = (FEC_OC_DTO_MODE_DYNAMIC__M |
2104 FEC_OC_DTO_MODE_OFFSET_ENABLE__M);
2105 fecOcFctMode = (FEC_OC_FCT_MODE_RAT_ENA__M |
2106 FEC_OC_FCT_MODE_VIRT_ENA__M);
2108 /* Check user defined bitrate */
2109 bitRate = maxBitRate;
2110 if (bitRate > 75900000UL) { /* max is 75.9 Mb/s */
2111 bitRate = 75900000UL;
2113 /* Rational DTO period:
2114 dto_period = (Fsys / bitrate) - 2
2116 Result should be floored,
2117 to make sure >= requested bitrate
2119 fecOcDtoPeriod = (u16) (((state->m_sysClockFreq)
2121 if (fecOcDtoPeriod <= 2)
2124 fecOcDtoPeriod -= 2;
2125 fecOcTmdIntUpdRate = 8;
2127 /* (commonAttr->staticCLK == false) => dynamic mode */
2128 fecOcDtoMode = FEC_OC_DTO_MODE_DYNAMIC__M;
2129 fecOcFctMode = FEC_OC_FCT_MODE__PRE;
2130 fecOcTmdIntUpdRate = 5;
2133 /* Write appropriate registers with requested configuration */
2134 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fecOcDtoBurstLen);
2137 status = write16(state, FEC_OC_DTO_PERIOD__A, fecOcDtoPeriod);
2140 status = write16(state, FEC_OC_DTO_MODE__A, fecOcDtoMode);
2143 status = write16(state, FEC_OC_FCT_MODE__A, fecOcFctMode);
2146 status = write16(state, FEC_OC_MODE__A, fecOcRegMode);
2149 status = write16(state, FEC_OC_IPR_MODE__A, fecOcRegIprMode);
2153 /* Rate integration settings */
2154 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fecOcRcnCtlRate);
2157 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, fecOcTmdIntUpdRate);
2160 status = write16(state, FEC_OC_TMD_MODE__A, fecOcTmdMode);
2163 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2167 static int MPEGTSConfigurePolarity(struct drxk_state *state)
2169 u16 fecOcRegIprInvert = 0;
2171 /* Data mask for the output data byte */
2172 u16 InvertDataMask =
2173 FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
2174 FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
2175 FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
2176 FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
2180 /* Control selective inversion of output bits */
2181 fecOcRegIprInvert &= (~(InvertDataMask));
2182 if (state->m_invertDATA == true)
2183 fecOcRegIprInvert |= InvertDataMask;
2184 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M));
2185 if (state->m_invertERR == true)
2186 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M;
2187 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
2188 if (state->m_invertSTR == true)
2189 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M;
2190 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
2191 if (state->m_invertVAL == true)
2192 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M;
2193 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
2194 if (state->m_invertCLK == true)
2195 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M;
2197 return write16(state, FEC_OC_IPR_INVERT__A, fecOcRegIprInvert);
2200 #define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000
2202 static int SetAgcRf(struct drxk_state *state,
2203 struct SCfgAgc *pAgcCfg, bool isDTV)
2205 int status = -EINVAL;
2207 struct SCfgAgc *pIfAgcSettings;
2211 if (pAgcCfg == NULL)
2214 switch (pAgcCfg->ctrlMode) {
2215 case DRXK_AGC_CTRL_AUTO:
2216 /* Enable RF AGC DAC */
2217 status = read16(state, IQM_AF_STDBY__A, &data);
2220 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2221 status = write16(state, IQM_AF_STDBY__A, data);
2224 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2228 /* Enable SCU RF AGC loop */
2229 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2232 if (state->m_RfAgcPol)
2233 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2235 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2236 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2240 /* Set speed (using complementary reduction value) */
2241 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2245 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
2246 data |= (~(pAgcCfg->speed <<
2247 SCU_RAM_AGC_KI_RED_RAGC_RED__B)
2248 & SCU_RAM_AGC_KI_RED_RAGC_RED__M);
2250 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2255 pIfAgcSettings = &state->m_dvbtIfAgcCfg;
2256 else if (IsQAM(state))
2257 pIfAgcSettings = &state->m_qamIfAgcCfg;
2259 pIfAgcSettings = &state->m_atvIfAgcCfg;
2260 if (pIfAgcSettings == NULL) {
2265 /* Set TOP, only if IF-AGC is in AUTO mode */
2266 if (pIfAgcSettings->ctrlMode == DRXK_AGC_CTRL_AUTO)
2267 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->top);
2271 /* Cut-Off current */
2272 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, pAgcCfg->cutOffCurrent);
2276 /* Max. output level */
2277 status = write16(state, SCU_RAM_AGC_RF_MAX__A, pAgcCfg->maxOutputLevel);
2283 case DRXK_AGC_CTRL_USER:
2284 /* Enable RF AGC DAC */
2285 status = read16(state, IQM_AF_STDBY__A, &data);
2288 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2289 status = write16(state, IQM_AF_STDBY__A, data);
2293 /* Disable SCU RF AGC loop */
2294 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2297 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2298 if (state->m_RfAgcPol)
2299 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2301 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2302 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2306 /* SCU c.o.c. to 0, enabling full control range */
2307 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
2311 /* Write value to output pin */
2312 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, pAgcCfg->outputLevel);
2317 case DRXK_AGC_CTRL_OFF:
2318 /* Disable RF AGC DAC */
2319 status = read16(state, IQM_AF_STDBY__A, &data);
2322 data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2323 status = write16(state, IQM_AF_STDBY__A, data);
2327 /* Disable SCU RF AGC loop */
2328 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2331 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2332 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2343 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2347 #define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000
2349 static int SetAgcIf(struct drxk_state *state,
2350 struct SCfgAgc *pAgcCfg, bool isDTV)
2354 struct SCfgAgc *pRfAgcSettings;
2358 switch (pAgcCfg->ctrlMode) {
2359 case DRXK_AGC_CTRL_AUTO:
2361 /* Enable IF AGC DAC */
2362 status = read16(state, IQM_AF_STDBY__A, &data);
2365 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2366 status = write16(state, IQM_AF_STDBY__A, data);
2370 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2374 /* Enable SCU IF AGC loop */
2375 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2378 if (state->m_IfAgcPol)
2379 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2381 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2382 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2386 /* Set speed (using complementary reduction value) */
2387 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2390 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
2391 data |= (~(pAgcCfg->speed <<
2392 SCU_RAM_AGC_KI_RED_IAGC_RED__B)
2393 & SCU_RAM_AGC_KI_RED_IAGC_RED__M);
2395 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2400 pRfAgcSettings = &state->m_qamRfAgcCfg;
2402 pRfAgcSettings = &state->m_atvRfAgcCfg;
2403 if (pRfAgcSettings == NULL)
2406 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pRfAgcSettings->top);
2411 case DRXK_AGC_CTRL_USER:
2413 /* Enable IF AGC DAC */
2414 status = read16(state, IQM_AF_STDBY__A, &data);
2417 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2418 status = write16(state, IQM_AF_STDBY__A, data);
2422 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2426 /* Disable SCU IF AGC loop */
2427 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2430 if (state->m_IfAgcPol)
2431 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2433 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2434 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2438 /* Write value to output pin */
2439 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->outputLevel);
2444 case DRXK_AGC_CTRL_OFF:
2446 /* Disable If AGC DAC */
2447 status = read16(state, IQM_AF_STDBY__A, &data);
2450 data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2451 status = write16(state, IQM_AF_STDBY__A, data);
2455 /* Disable SCU IF AGC loop */
2456 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2459 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2460 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2464 } /* switch (agcSettingsIf->ctrlMode) */
2466 /* always set the top to support
2467 configurations without if-loop */
2468 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, pAgcCfg->top);
2471 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2475 static int ReadIFAgc(struct drxk_state *state, u32 *pValue)
2483 status = read16(state, IQM_AF_AGC_IF__A, &agcDacLvl);
2485 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2491 if (agcDacLvl > DRXK_AGC_DAC_OFFSET)
2492 Level = agcDacLvl - DRXK_AGC_DAC_OFFSET;
2494 *pValue = (14000 - Level) / 4;
2501 static int GetQAMSignalToNoise(struct drxk_state *state,
2502 s32 *pSignalToNoise)
2505 u16 qamSlErrPower = 0; /* accum. error between
2506 raw and sliced symbols */
2507 u32 qamSlSigPower = 0; /* used for MER, depends of
2509 u32 qamSlMer = 0; /* QAM MER */
2513 /* MER calculation */
2515 /* get the register value needed for MER */
2516 status = read16(state, QAM_SL_ERR_POWER__A, &qamSlErrPower);
2518 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2522 switch (state->props.modulation) {
2524 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2;
2527 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM32 << 2;
2530 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM64 << 2;
2533 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM128 << 2;
2537 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM256 << 2;
2541 if (qamSlErrPower > 0) {
2542 qamSlMer = Log10Times100(qamSlSigPower) -
2543 Log10Times100((u32) qamSlErrPower);
2545 *pSignalToNoise = qamSlMer;
2550 static int GetDVBTSignalToNoise(struct drxk_state *state,
2551 s32 *pSignalToNoise)
2555 u32 EqRegTdSqrErrI = 0;
2556 u32 EqRegTdSqrErrQ = 0;
2557 u16 EqRegTdSqrErrExp = 0;
2558 u16 EqRegTdTpsPwrOfs = 0;
2559 u16 EqRegTdReqSmbCnt = 0;
2566 u16 transmissionParams = 0;
2570 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &EqRegTdTpsPwrOfs);
2573 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, &EqRegTdReqSmbCnt);
2576 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, &EqRegTdSqrErrExp);
2579 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, ®Data);
2582 /* Extend SQR_ERR_I operational range */
2583 EqRegTdSqrErrI = (u32) regData;
2584 if ((EqRegTdSqrErrExp > 11) &&
2585 (EqRegTdSqrErrI < 0x00000FFFUL)) {
2586 EqRegTdSqrErrI += 0x00010000UL;
2588 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, ®Data);
2591 /* Extend SQR_ERR_Q operational range */
2592 EqRegTdSqrErrQ = (u32) regData;
2593 if ((EqRegTdSqrErrExp > 11) &&
2594 (EqRegTdSqrErrQ < 0x00000FFFUL))
2595 EqRegTdSqrErrQ += 0x00010000UL;
2597 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, &transmissionParams);
2601 /* Check input data for MER */
2603 /* MER calculation (in 0.1 dB) without math.h */
2604 if ((EqRegTdTpsPwrOfs == 0) || (EqRegTdReqSmbCnt == 0))
2606 else if ((EqRegTdSqrErrI + EqRegTdSqrErrQ) == 0) {
2607 /* No error at all, this must be the HW reset value
2608 * Apparently no first measurement yet
2612 SqrErrIQ = (EqRegTdSqrErrI + EqRegTdSqrErrQ) <<
2614 if ((transmissionParams &
2615 OFDM_SC_RA_RAM_OP_PARAM_MODE__M)
2616 == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K)
2621 /* IMER = 100 * log10 (x)
2622 where x = (EqRegTdTpsPwrOfs^2 *
2623 EqRegTdReqSmbCnt * tpsCnt)/SqrErrIQ
2626 where a = 100 * log10 (EqRegTdTpsPwrOfs^2)
2627 b = 100 * log10 (EqRegTdReqSmbCnt * tpsCnt)
2628 c = 100 * log10 (SqrErrIQ)
2631 /* log(x) x = 9bits * 9bits->18 bits */
2632 a = Log10Times100(EqRegTdTpsPwrOfs *
2634 /* log(x) x = 16bits * 7bits->23 bits */
2635 b = Log10Times100(EqRegTdReqSmbCnt * tpsCnt);
2636 /* log(x) x = (16bits + 16bits) << 15 ->32 bits */
2637 c = Log10Times100(SqrErrIQ);
2640 /* No negative MER, clip to zero */
2646 *pSignalToNoise = iMER;
2650 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2654 static int GetSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise)
2658 *pSignalToNoise = 0;
2659 switch (state->m_OperationMode) {
2661 return GetDVBTSignalToNoise(state, pSignalToNoise);
2664 return GetQAMSignalToNoise(state, pSignalToNoise);
2672 static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality)
2674 /* SNR Values for quasi errorfree reception rom Nordig 2.2 */
2679 static s32 QE_SN[] = {
2685 108, /* 16-QAM 1/2 */
2686 131, /* 16-QAM 2/3 */
2687 146, /* 16-QAM 3/4 */
2688 156, /* 16-QAM 5/6 */
2689 160, /* 16-QAM 7/8 */
2690 165, /* 64-QAM 1/2 */
2691 187, /* 64-QAM 2/3 */
2692 202, /* 64-QAM 3/4 */
2693 216, /* 64-QAM 5/6 */
2694 225, /* 64-QAM 7/8 */
2700 s32 SignalToNoise = 0;
2701 u16 Constellation = 0;
2703 u32 SignalToNoiseRel;
2706 status = GetDVBTSignalToNoise(state, &SignalToNoise);
2709 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A, &Constellation);
2712 Constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M;
2714 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, &CodeRate);
2717 CodeRate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M;
2719 if (Constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM ||
2720 CodeRate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8)
2722 SignalToNoiseRel = SignalToNoise -
2723 QE_SN[Constellation * 5 + CodeRate];
2726 if (SignalToNoiseRel < -70)
2728 else if (SignalToNoiseRel < 30)
2729 *pQuality = ((SignalToNoiseRel + 70) *
2732 *pQuality = BERQuality;
2737 static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality)
2745 u32 SignalToNoise = 0;
2746 u32 BERQuality = 100;
2747 u32 SignalToNoiseRel = 0;
2749 status = GetQAMSignalToNoise(state, &SignalToNoise);
2753 switch (state->props.modulation) {
2755 SignalToNoiseRel = SignalToNoise - 200;
2758 SignalToNoiseRel = SignalToNoise - 230;
2759 break; /* Not in NorDig */
2761 SignalToNoiseRel = SignalToNoise - 260;
2764 SignalToNoiseRel = SignalToNoise - 290;
2768 SignalToNoiseRel = SignalToNoise - 320;
2772 if (SignalToNoiseRel < -70)
2774 else if (SignalToNoiseRel < 30)
2775 *pQuality = ((SignalToNoiseRel + 70) *
2778 *pQuality = BERQuality;
2784 static int GetQuality(struct drxk_state *state, s32 *pQuality)
2788 switch (state->m_OperationMode) {
2790 return GetDVBTQuality(state, pQuality);
2792 return GetDVBCQuality(state, pQuality);
2801 /* Free data ram in SIO HI */
2802 #define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
2803 #define SIO_HI_RA_RAM_USR_END__A 0x420060
2805 #define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
2806 #define DRXK_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
2807 #define DRXK_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
2808 #define DRXK_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
2810 #define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr) >> 22) & 0x3F)
2811 #define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F)
2812 #define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF)
2814 static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge)
2816 int status = -EINVAL;
2820 if (state->m_DrxkState == DRXK_UNINITIALIZED)
2822 if (state->m_DrxkState == DRXK_POWERED_DOWN)
2825 if (state->no_i2c_bridge)
2828 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
2831 if (bEnableBridge) {
2832 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
2836 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
2841 status = HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, 0);
2845 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2849 static int SetPreSaw(struct drxk_state *state,
2850 struct SCfgPreSaw *pPreSawCfg)
2852 int status = -EINVAL;
2856 if ((pPreSawCfg == NULL)
2857 || (pPreSawCfg->reference > IQM_AF_PDREF__M))
2860 status = write16(state, IQM_AF_PDREF__A, pPreSawCfg->reference);
2863 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2867 static int BLDirectCmd(struct drxk_state *state, u32 targetAddr,
2868 u16 romOffset, u16 nrOfElements, u32 timeOut)
2871 u16 offset = (u16) ((targetAddr >> 0) & 0x00FFFF);
2872 u16 blockbank = (u16) ((targetAddr >> 16) & 0x000FFF);
2878 mutex_lock(&state->mutex);
2879 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
2882 status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
2885 status = write16(state, SIO_BL_TGT_ADDR__A, offset);
2888 status = write16(state, SIO_BL_SRC_ADDR__A, romOffset);
2891 status = write16(state, SIO_BL_SRC_LEN__A, nrOfElements);
2894 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2898 end = jiffies + msecs_to_jiffies(timeOut);
2900 status = read16(state, SIO_BL_STATUS__A, &blStatus);
2903 } while ((blStatus == 0x1) && time_is_after_jiffies(end));
2904 if (blStatus == 0x1) {
2905 printk(KERN_ERR "drxk: SIO not ready\n");
2911 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2913 mutex_unlock(&state->mutex);
2918 static int ADCSyncMeasurement(struct drxk_state *state, u16 *count)
2925 /* Start measurement */
2926 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2929 status = write16(state, IQM_AF_START_LOCK__A, 1);
2934 status = read16(state, IQM_AF_PHASE0__A, &data);
2938 *count = *count + 1;
2939 status = read16(state, IQM_AF_PHASE1__A, &data);
2943 *count = *count + 1;
2944 status = read16(state, IQM_AF_PHASE2__A, &data);
2948 *count = *count + 1;
2952 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2956 static int ADCSynchronization(struct drxk_state *state)
2963 status = ADCSyncMeasurement(state, &count);
2968 /* Try sampling on a diffrent edge */
2971 status = read16(state, IQM_AF_CLKNEG__A, &clkNeg);
2974 if ((clkNeg | IQM_AF_CLKNEG_CLKNEGDATA__M) ==
2975 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) {
2976 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2978 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG;
2980 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2982 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS;
2984 status = write16(state, IQM_AF_CLKNEG__A, clkNeg);
2987 status = ADCSyncMeasurement(state, &count);
2996 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3000 static int SetFrequencyShifter(struct drxk_state *state,
3001 u16 intermediateFreqkHz,
3002 s32 tunerFreqOffset, bool isDTV)
3004 bool selectPosImage = false;
3005 u32 rfFreqResidual = tunerFreqOffset;
3006 u32 fmFrequencyShift = 0;
3007 bool tunerMirror = !state->m_bMirrorFreqSpect;
3012 u32 samplingFrequency = (u32) (state->m_sysClockFreq / 3);
3019 Program frequency shifter
3020 No need to account for mirroring on RF
3023 if ((state->m_OperationMode == OM_QAM_ITU_A) ||
3024 (state->m_OperationMode == OM_QAM_ITU_C) ||
3025 (state->m_OperationMode == OM_DVBT))
3026 selectPosImage = true;
3028 selectPosImage = false;
3031 /* tuner doesn't mirror */
3032 ifFreqActual = intermediateFreqkHz +
3033 rfFreqResidual + fmFrequencyShift;
3036 ifFreqActual = intermediateFreqkHz -
3037 rfFreqResidual - fmFrequencyShift;
3038 if (ifFreqActual > samplingFrequency / 2) {
3040 adcFreq = samplingFrequency - ifFreqActual;
3043 /* adc doesn't mirror */
3044 adcFreq = ifFreqActual;
3048 frequencyShift = adcFreq;
3049 imageToSelect = state->m_rfmirror ^ tunerMirror ^
3050 adcFlip ^ selectPosImage;
3051 state->m_IqmFsRateOfs =
3052 Frac28a((frequencyShift), samplingFrequency);
3055 state->m_IqmFsRateOfs = ~state->m_IqmFsRateOfs + 1;
3057 /* Program frequency shifter with tuner offset compensation */
3058 /* frequencyShift += tunerFreqOffset; TODO */
3059 status = write32(state, IQM_FS_RATE_OFS_LO__A,
3060 state->m_IqmFsRateOfs);
3062 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3066 static int InitAGC(struct drxk_state *state, bool isDTV)
3069 u16 ingainTgtMin = 0;
3070 u16 ingainTgtMax = 0;
3078 u16 kiInnergainMin = 0;
3079 u16 ifIaccuHiTgt = 0;
3080 u16 ifIaccuHiTgtMin = 0;
3081 u16 ifIaccuHiTgtMax = 0;
3083 u16 fastClpCtrlDelay = 0;
3084 u16 clpCtrlMode = 0;
3089 /* Common settings */
3091 ifIaccuHiTgtMin = 2047;
3095 /* AGCInit() not available for DVBT; init done in microcode */
3096 if (!IsQAM(state)) {
3097 printk(KERN_ERR "drxk: %s: mode %d is not DVB-C\n", __func__, state->m_OperationMode);
3101 /* FIXME: Analog TV AGC require different settings */
3103 /* Standard specific settings */
3105 clpDirTo = (u16) -9;
3108 snsDirTo = (u16) -9;
3109 kiInnergainMin = (u16) -1030;
3110 ifIaccuHiTgtMax = 0x2380;
3111 ifIaccuHiTgt = 0x2380;
3112 ingainTgtMin = 0x0511;
3114 ingainTgtMax = 5119;
3115 fastClpCtrlDelay = state->m_qamIfAgcCfg.FastClipCtrlDelay;
3117 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, fastClpCtrlDelay);
3121 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clpCtrlMode);
3124 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingainTgt);
3127 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingainTgtMin);
3130 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingainTgtMax);
3133 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, ifIaccuHiTgtMin);
3136 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, ifIaccuHiTgtMax);
3139 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
3142 status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);
3145 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);
3148 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
3151 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clpSumMax);
3154 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, snsSumMax);
3158 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, kiInnergainMin);
3161 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, ifIaccuHiTgt);
3164 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clpCyclen);
3168 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);
3171 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);
3174 status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);
3178 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
3181 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clpSumMin);
3184 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, snsSumMin);
3187 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clpDirTo);
3190 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, snsDirTo);
3193 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
3196 status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);
3199 status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);
3202 status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);
3205 status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);
3208 status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);
3211 status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);
3214 status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);
3217 status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);
3220 status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);
3223 status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);
3226 status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);
3229 status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);
3232 status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);
3236 /* Initialize inner-loop KI gain factors */
3237 status = read16(state, SCU_RAM_AGC_KI__A, &data);
3242 data &= ~SCU_RAM_AGC_KI_RF__M;
3243 data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B);
3244 data &= ~SCU_RAM_AGC_KI_IF__M;
3245 data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B);
3247 status = write16(state, SCU_RAM_AGC_KI__A, data);
3250 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3254 static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 *packetErr)
3259 if (packetErr == NULL)
3260 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
3262 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, packetErr);
3264 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3268 static int DVBTScCommand(struct drxk_state *state,
3269 u16 cmd, u16 subcmd,
3270 u16 param0, u16 param1, u16 param2,
3271 u16 param3, u16 param4)
3280 status = read16(state, OFDM_SC_COMM_EXEC__A, &scExec);
3282 /* SC is not running */
3288 /* Wait until sc is ready to receive command */
3292 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
3294 } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
3295 if (retryCnt >= DRXK_MAX_RETRIES && (status < 0))
3298 /* Write sub-command */
3300 /* All commands using sub-cmd */
3301 case OFDM_SC_RA_RAM_CMD_PROC_START:
3302 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3303 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3304 status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
3313 /* Write needed parameters and the command */
3315 /* All commands using 5 parameters */
3316 /* All commands using 4 parameters */
3317 /* All commands using 3 parameters */
3318 /* All commands using 2 parameters */
3319 case OFDM_SC_RA_RAM_CMD_PROC_START:
3320 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3321 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3322 status = write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
3323 /* All commands using 1 parameters */
3324 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3325 case OFDM_SC_RA_RAM_CMD_USER_IO:
3326 status = write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
3327 /* All commands using 0 parameters */
3328 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3329 case OFDM_SC_RA_RAM_CMD_NULL:
3331 status = write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);
3334 /* Unknown command */
3340 /* Wait until sc is ready processing command */
3344 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
3346 } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
3347 if (retryCnt >= DRXK_MAX_RETRIES && (status < 0))
3350 /* Check for illegal cmd */
3351 status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &errCode);
3352 if (errCode == 0xFFFF) {
3353 /* illegal command */
3359 /* Retreive results parameters from SC */
3361 /* All commands yielding 5 results */
3362 /* All commands yielding 4 results */
3363 /* All commands yielding 3 results */
3364 /* All commands yielding 2 results */
3365 /* All commands yielding 1 result */
3366 case OFDM_SC_RA_RAM_CMD_USER_IO:
3367 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3368 status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
3369 /* All commands yielding 0 results */
3370 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3371 case OFDM_SC_RA_RAM_CMD_SET_TIMER:
3372 case OFDM_SC_RA_RAM_CMD_PROC_START:
3373 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3374 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3375 case OFDM_SC_RA_RAM_CMD_NULL:
3378 /* Unknown command */
3381 } /* switch (cmd->cmd) */
3384 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3388 static int PowerUpDVBT(struct drxk_state *state)
3390 enum DRXPowerMode powerMode = DRX_POWER_UP;
3394 status = CtrlPowerMode(state, &powerMode);
3396 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3400 static int DVBTCtrlSetIncEnable(struct drxk_state *state, bool *enabled)
3405 if (*enabled == true)
3406 status = write16(state, IQM_CF_BYPASSDET__A, 0);
3408 status = write16(state, IQM_CF_BYPASSDET__A, 1);
3410 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3414 #define DEFAULT_FR_THRES_8K 4000
3415 static int DVBTCtrlSetFrEnable(struct drxk_state *state, bool *enabled)
3421 if (*enabled == true) {
3422 /* write mask to 1 */
3423 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
3424 DEFAULT_FR_THRES_8K);
3426 /* write mask to 0 */
3427 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
3430 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3435 static int DVBTCtrlSetEchoThreshold(struct drxk_state *state,
3436 struct DRXKCfgDvbtEchoThres_t *echoThres)
3442 status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);
3446 switch (echoThres->fftMode) {
3447 case DRX_FFTMODE_2K:
3448 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M;
3449 data |= ((echoThres->threshold <<
3450 OFDM_SC_RA_RAM_ECHO_THRES_2K__B)
3451 & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M));
3453 case DRX_FFTMODE_8K:
3454 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M;
3455 data |= ((echoThres->threshold <<
3456 OFDM_SC_RA_RAM_ECHO_THRES_8K__B)
3457 & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M));
3463 status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
3466 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3470 static int DVBTCtrlSetSqiSpeed(struct drxk_state *state,
3471 enum DRXKCfgDvbtSqiSpeed *speed)
3473 int status = -EINVAL;
3478 case DRXK_DVBT_SQI_SPEED_FAST:
3479 case DRXK_DVBT_SQI_SPEED_MEDIUM:
3480 case DRXK_DVBT_SQI_SPEED_SLOW:
3485 status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
3489 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3493 /*============================================================================*/
3496 * \brief Activate DVBT specific presets
3497 * \param demod instance of demodulator.
3498 * \return DRXStatus_t.
3500 * Called in DVBTSetStandard
3503 static int DVBTActivatePresets(struct drxk_state *state)
3506 bool setincenable = false;
3507 bool setfrenable = true;
3509 struct DRXKCfgDvbtEchoThres_t echoThres2k = { 0, DRX_FFTMODE_2K };
3510 struct DRXKCfgDvbtEchoThres_t echoThres8k = { 0, DRX_FFTMODE_8K };
3513 status = DVBTCtrlSetIncEnable(state, &setincenable);
3516 status = DVBTCtrlSetFrEnable(state, &setfrenable);
3519 status = DVBTCtrlSetEchoThreshold(state, &echoThres2k);
3522 status = DVBTCtrlSetEchoThreshold(state, &echoThres8k);
3525 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, state->m_dvbtIfAgcCfg.IngainTgtMax);
3528 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3532 /*============================================================================*/
3535 * \brief Initialize channelswitch-independent settings for DVBT.
3536 * \param demod instance of demodulator.
3537 * \return DRXStatus_t.
3539 * For ROM code channel filter taps are loaded from the bootloader. For microcode
3540 * the DVB-T taps from the drxk_filters.h are used.
3542 static int SetDVBTStandard(struct drxk_state *state,
3543 enum OperationMode oMode)
3552 /* added antenna switch */
3553 SwitchAntennaToDVBT(state);
3554 /* send OFDM reset command */
3555 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
3559 /* send OFDM setenv command */
3560 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 0, NULL, 1, &cmdResult);
3564 /* reset datapath for OFDM, processors first */
3565 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3568 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3571 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
3576 /* synchronize on ofdstate->m_festart */
3577 status = write16(state, IQM_AF_UPD_SEL__A, 1);
3580 /* window size for clipping ADC detection */
3581 status = write16(state, IQM_AF_CLP_LEN__A, 0);
3584 /* window size for for sense pre-SAW detection */
3585 status = write16(state, IQM_AF_SNS_LEN__A, 0);
3588 /* sense threshold for sense pre-SAW detection */
3589 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
3592 status = SetIqmAf(state, true);
3596 status = write16(state, IQM_AF_AGC_RF__A, 0);
3600 /* Impulse noise cruncher setup */
3601 status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */
3604 status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */
3607 status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */
3611 status = write16(state, IQM_RC_STRETCH__A, 16);
3614 status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */
3617 status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */
3620 status = write16(state, IQM_CF_SCALE__A, 1600);
3623 status = write16(state, IQM_CF_SCALE_SH__A, 0);
3627 /* virtual clipping threshold for clipping ADC detection */
3628 status = write16(state, IQM_AF_CLP_TH__A, 448);
3631 status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */
3635 status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
3639 status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */
3642 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);
3645 /* enable power measurement interrupt */
3646 status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);
3649 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
3653 /* IQM will not be reset from here, sync ADC and update/init AGC */
3654 status = ADCSynchronization(state);
3657 status = SetPreSaw(state, &state->m_dvbtPreSawCfg);
3661 /* Halt SCU to enable safe non-atomic accesses */
3662 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3666 status = SetAgcRf(state, &state->m_dvbtRfAgcCfg, true);
3669 status = SetAgcIf(state, &state->m_dvbtIfAgcCfg, true);
3673 /* Set Noise Estimation notch width and enable DC fix */
3674 status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);
3677 data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M;
3678 status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);
3682 /* Activate SCU to enable SCU commands */
3683 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3687 if (!state->m_DRXK_A3_ROM_CODE) {
3688 /* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay */
3689 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, state->m_dvbtIfAgcCfg.FastClipCtrlDelay);
3695 #ifdef COMPILE_FOR_NONRT
3696 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
3699 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
3705 status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */
3710 #ifdef COMPILE_FOR_NONRT
3711 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
3715 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);
3719 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);
3723 /* Setup MPEG bus */
3724 status = MPEGTSDtoSetup(state, OM_DVBT);
3727 /* Set DVBT Presets */
3728 status = DVBTActivatePresets(state);
3734 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3738 /*============================================================================*/
3740 * \brief Start dvbt demodulating for channel.
3741 * \param demod instance of demodulator.
3742 * \return DRXStatus_t.
3744 static int DVBTStart(struct drxk_state *state)
3748 /* DRXKOfdmScCmd_t scCmd; */
3751 /* Start correct processes to get in lock */
3752 /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */
3753 param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;
3754 status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1, 0, 0, 0);
3758 status = MPEGTSStart(state);
3761 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
3766 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3771 /*============================================================================*/
3774 * \brief Set up dvbt demodulator for channel.
3775 * \param demod instance of demodulator.
3776 * \return DRXStatus_t.
3777 * // original DVBTSetChannel()
3779 static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3780 s32 tunerFreqOffset)
3783 u16 transmissionParams = 0;
3784 u16 operationMode = 0;
3785 u32 iqmRcRateOfs = 0;
3790 dprintk(1, "IF =%d, TFO = %d\n", IntermediateFreqkHz, tunerFreqOffset);
3792 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
3796 /* Halt SCU to enable safe non-atomic accesses */
3797 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3801 /* Stop processors */
3802 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3805 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3809 /* Mandatory fix, always stop CP, required to set spl offset back to
3810 hardware default (is set to 0 by ucode during pilot detection */
3811 status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
3815 /*== Write channel settings to device =====================================*/
3818 switch (state->props.transmission_mode) {
3819 case TRANSMISSION_MODE_AUTO:
3821 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M;
3822 /* fall through , try first guess DRX_FFTMODE_8K */
3823 case TRANSMISSION_MODE_8K:
3824 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K;
3826 case TRANSMISSION_MODE_2K:
3827 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K;
3832 switch (state->props.guard_interval) {
3834 case GUARD_INTERVAL_AUTO:
3835 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M;
3836 /* fall through , try first guess DRX_GUARD_1DIV4 */
3837 case GUARD_INTERVAL_1_4:
3838 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4;
3840 case GUARD_INTERVAL_1_32:
3841 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32;
3843 case GUARD_INTERVAL_1_16:
3844 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16;
3846 case GUARD_INTERVAL_1_8:
3847 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8;
3852 switch (state->props.hierarchy) {
3853 case HIERARCHY_AUTO:
3854 case HIERARCHY_NONE:
3856 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M;
3857 /* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */
3858 /* transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */
3861 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1;
3864 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2;
3867 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4;
3873 switch (state->props.modulation) {
3876 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M;
3877 /* fall through , try first guess DRX_CONSTELLATION_QAM64 */
3879 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64;
3882 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK;
3885 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16;
3889 /* No hierachical channels support in BDA */
3890 /* Priority (only for hierarchical channels) */
3891 switch (channel->priority) {
3892 case DRX_PRIORITY_LOW:
3893 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO;
3894 WR16(devAddr, OFDM_EC_SB_PRIOR__A,
3895 OFDM_EC_SB_PRIOR_LO);
3897 case DRX_PRIORITY_HIGH:
3898 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3899 WR16(devAddr, OFDM_EC_SB_PRIOR__A,
3900 OFDM_EC_SB_PRIOR_HI));
3902 case DRX_PRIORITY_UNKNOWN: /* fall through */
3908 /* Set Priorty high */
3909 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3910 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
3916 switch (state->props.code_rate_HP) {
3919 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M;
3920 /* fall through , try first guess DRX_CODERATE_2DIV3 */
3922 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3;
3925 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2;
3928 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4;
3931 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6;
3934 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8;
3938 /* SAW filter selection: normaly not necesarry, but if wanted
3939 the application can select a SAW filter via the driver by using UIOs */
3940 /* First determine real bandwidth (Hz) */
3941 /* Also set delay for impulse noise cruncher */
3942 /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed
3943 by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC
3945 switch (state->props.bandwidth_hz) {
3947 state->props.bandwidth_hz = 8000000;
3950 bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ;
3951 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052);
3954 /* cochannel protection for PAL 8 MHz */
3955 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7);
3958 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7);
3961 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7);
3964 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3969 bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ;
3970 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491);
3973 /* cochannel protection for PAL 7 MHz */
3974 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8);
3977 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8);
3980 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4);
3983 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3988 bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ;
3989 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073);
3992 /* cochannel protection for NTSC 6 MHz */
3993 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19);
3996 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19);
3999 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14);
4002 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
4011 if (iqmRcRateOfs == 0) {
4012 /* Now compute IQM_RC_RATE_OFS
4013 (((SysFreq/BandWidth)/2)/2) -1) * 2^23)
4015 ((SysFreq / BandWidth) * (2^21)) - (2^23)
4017 /* (SysFreq / BandWidth) * (2^28) */
4018 /* assert (MAX(sysClk)/MIN(bandwidth) < 16)
4019 => assert(MAX(sysClk) < 16*MIN(bandwidth))
4020 => assert(109714272 > 48000000) = true so Frac 28 can be used */
4021 iqmRcRateOfs = Frac28a((u32)
4022 ((state->m_sysClockFreq *
4023 1000) / 3), bandwidth);
4024 /* (SysFreq / BandWidth) * (2^21), rounding before truncating */
4025 if ((iqmRcRateOfs & 0x7fL) >= 0x40)
4026 iqmRcRateOfs += 0x80L;
4027 iqmRcRateOfs = iqmRcRateOfs >> 7;
4028 /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */
4029 iqmRcRateOfs = iqmRcRateOfs - (1 << 23);
4033 ((((u32) IQM_RC_RATE_OFS_HI__M) <<
4034 IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M);
4035 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRateOfs);
4039 /* Bandwidth setting done */
4042 status = DVBTSetFrequencyShift(demod, channel, tunerOffset);
4046 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
4050 /*== Start SC, write channel settings to SC ===============================*/
4052 /* Activate SCU to enable SCU commands */
4053 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
4057 /* Enable SC after setting all other parameters */
4058 status = write16(state, OFDM_SC_COMM_STATE__A, 0);
4061 status = write16(state, OFDM_SC_COMM_EXEC__A, 1);
4066 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult);
4070 /* Write SC parameter registers, set all AUTO flags in operation mode */
4071 param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M |
4072 OFDM_SC_RA_RAM_OP_AUTO_GUARD__M |
4073 OFDM_SC_RA_RAM_OP_AUTO_CONST__M |
4074 OFDM_SC_RA_RAM_OP_AUTO_HIER__M |
4075 OFDM_SC_RA_RAM_OP_AUTO_RATE__M);
4076 status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
4077 0, transmissionParams, param1, 0, 0, 0);
4081 if (!state->m_DRXK_A3_ROM_CODE)
4082 status = DVBTCtrlSetSqiSpeed(state, &state->m_sqiSpeed);
4085 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4091 /*============================================================================*/
4094 * \brief Retreive lock status .
4095 * \param demod Pointer to demodulator instance.
4096 * \param lockStat Pointer to lock status structure.
4097 * \return DRXStatus_t.
4100 static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus)
4103 const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M |
4104 OFDM_SC_RA_RAM_LOCK_FEC__M);
4105 const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M);
4106 const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M;
4108 u16 ScRaRamLock = 0;
4113 *pLockStatus = NOT_LOCKED;
4115 /* Check if SC is running */
4116 status = read16(state, OFDM_SC_COMM_EXEC__A, &ScCommExec);
4119 if (ScCommExec == OFDM_SC_COMM_EXEC_STOP)
4122 status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock);
4126 if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask)
4127 *pLockStatus = MPEG_LOCK;
4128 else if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
4129 *pLockStatus = FEC_LOCK;
4130 else if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
4131 *pLockStatus = DEMOD_LOCK;
4132 else if (ScRaRamLock & OFDM_SC_RA_RAM_LOCK_NODVBT__M)
4133 *pLockStatus = NEVER_LOCK;
4136 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4141 static int PowerUpQAM(struct drxk_state *state)
4143 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
4147 status = CtrlPowerMode(state, &powerMode);
4149 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4155 /** Power Down QAM */
4156 static int PowerDownQAM(struct drxk_state *state)
4163 status = read16(state, SCU_COMM_EXEC__A, &data);
4166 if (data == SCU_COMM_EXEC_ACTIVE) {
4171 /* stop all comstate->m_exec */
4172 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
4175 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
4180 status = SetIqmAf(state, false);
4184 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4189 /*============================================================================*/
4192 * \brief Setup of the QAM Measurement intervals for signal quality
4193 * \param demod instance of demod.
4194 * \param modulation current modulation.
4195 * \return DRXStatus_t.
4198 * Take into account that for certain settings the errorcounters can overflow.
4199 * The implementation does not check this.
4202 static int SetQAMMeasurement(struct drxk_state *state,
4203 enum EDrxkConstellation modulation,
4206 u32 fecBitsDesired = 0; /* BER accounting period */
4207 u32 fecRsPeriodTotal = 0; /* Total period */
4208 u16 fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */
4209 u16 fecRsPeriod = 0; /* Value for corresponding I2C register */
4215 /* fecBitsDesired = symbolRate [kHz] *
4221 switch (modulation) {
4222 case DRX_CONSTELLATION_QAM16:
4223 fecBitsDesired = 4 * symbolRate;
4225 case DRX_CONSTELLATION_QAM32:
4226 fecBitsDesired = 5 * symbolRate;
4228 case DRX_CONSTELLATION_QAM64:
4229 fecBitsDesired = 6 * symbolRate;
4231 case DRX_CONSTELLATION_QAM128:
4232 fecBitsDesired = 7 * symbolRate;
4234 case DRX_CONSTELLATION_QAM256:
4235 fecBitsDesired = 8 * symbolRate;
4243 fecBitsDesired /= 1000; /* symbolRate [Hz] -> symbolRate [kHz] */
4244 fecBitsDesired *= 500; /* meas. period [ms] */
4246 /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */
4247 /* fecRsPeriodTotal = fecBitsDesired / 1632 */
4248 fecRsPeriodTotal = (fecBitsDesired / 1632UL) + 1; /* roughly ceil */
4250 /* fecRsPeriodTotal = fecRsPrescale * fecRsPeriod */
4251 fecRsPrescale = 1 + (u16) (fecRsPeriodTotal >> 16);
4252 if (fecRsPrescale == 0) {
4253 /* Divide by zero (though impossible) */
4259 ((u16) fecRsPeriodTotal +
4260 (fecRsPrescale >> 1)) / fecRsPrescale;
4262 /* write corresponding registers */
4263 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod);
4266 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale);
4269 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod);
4272 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4276 static int SetQAM16(struct drxk_state *state)
4281 /* QAM Equalizer Setup */
4283 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);
4286 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);
4289 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);
4292 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);
4295 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);
4298 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);
4301 /* Decision Feedback Equalizer */
4302 status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);
4305 status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);
4308 status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);
4311 status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);
4314 status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);
4317 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4321 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4324 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4327 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4331 /* QAM Slicer Settings */
4332 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16);
4336 /* QAM Loop Controller Coeficients */
4337 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4340 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4343 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4346 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4349 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4352 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4355 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4358 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4362 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4365 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4368 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4371 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4374 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4377 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4380 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4383 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4386 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);
4389 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4392 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4395 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4400 /* QAM State Machine (FSM) Thresholds */
4402 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);
4405 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4408 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);
4411 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);
4414 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);
4417 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);
4421 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4424 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4427 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);
4432 /* QAM FSM Tracking Parameters */
4434 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);
4437 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);
4440 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);
4443 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);
4446 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);
4449 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);
4452 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);
4458 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4462 /*============================================================================*/
4465 * \brief QAM32 specific setup
4466 * \param demod instance of demod.
4467 * \return DRXStatus_t.
4469 static int SetQAM32(struct drxk_state *state)
4475 /* QAM Equalizer Setup */
4477 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
4480 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
4483 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
4486 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
4489 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
4492 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
4496 /* Decision Feedback Equalizer */
4497 status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);
4500 status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);
4503 status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);
4506 status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);
4509 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4512 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4516 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4519 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4522 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4526 /* QAM Slicer Settings */
4528 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32);
4533 /* QAM Loop Controller Coeficients */
4535 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4538 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4541 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4544 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4547 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4550 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4553 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4556 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4560 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4563 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4566 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4569 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4572 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4575 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4578 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4581 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4584 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
4587 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4590 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4593 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4598 /* QAM State Machine (FSM) Thresholds */
4600 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);
4603 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4606 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4609 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4612 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);
4615 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4619 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4622 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4625 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);
4630 /* QAM FSM Tracking Parameters */
4632 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4635 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
4638 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
4641 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
4644 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
4647 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
4650 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
4653 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4657 /*============================================================================*/
4660 * \brief QAM64 specific setup
4661 * \param demod instance of demod.
4662 * \return DRXStatus_t.
4664 static int SetQAM64(struct drxk_state *state)
4669 /* QAM Equalizer Setup */
4671 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);
4674 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);
4677 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);
4680 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);
4683 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);
4686 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);
4690 /* Decision Feedback Equalizer */
4691 status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);
4694 status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);
4697 status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);
4700 status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);
4703 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4706 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4710 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4713 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4716 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4720 /* QAM Slicer Settings */
4721 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64);
4726 /* QAM Loop Controller Coeficients */
4728 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4731 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4734 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4737 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4740 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4743 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4746 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4749 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4753 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4756 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);
4759 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);
4762 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4765 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);
4768 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4771 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4774 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4777 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
4780 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4783 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4786 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4791 /* QAM State Machine (FSM) Thresholds */
4793 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);
4796 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4799 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4802 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);
4805 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);
4808 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);
4812 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4815 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4818 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);
4823 /* QAM FSM Tracking Parameters */
4825 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4828 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);
4831 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);
4834 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);
4837 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);
4840 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);
4843 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);
4846 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4851 /*============================================================================*/
4854 * \brief QAM128 specific setup
4855 * \param demod: instance of demod.
4856 * \return DRXStatus_t.
4858 static int SetQAM128(struct drxk_state *state)
4863 /* QAM Equalizer Setup */
4865 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);
4868 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);
4871 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);
4874 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);
4877 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);
4880 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);
4884 /* Decision Feedback Equalizer */
4885 status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);
4888 status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);
4891 status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);
4894 status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);
4897 status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);
4900 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4904 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4907 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4910 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4915 /* QAM Slicer Settings */
4917 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM128);
4922 /* QAM Loop Controller Coeficients */
4924 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4927 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4930 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4933 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4936 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4939 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4942 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4945 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4949 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4952 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);
4955 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);
4958 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4961 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);
4964 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);
4967 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4970 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4973 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);
4976 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4979 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4982 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4987 /* QAM State Machine (FSM) Thresholds */
4989 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
4992 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4995 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4998 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5001 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);
5004 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
5008 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5011 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);
5015 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5019 /* QAM FSM Tracking Parameters */
5021 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5024 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);
5027 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);
5030 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);
5033 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);
5036 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);
5039 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);
5042 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5047 /*============================================================================*/
5050 * \brief QAM256 specific setup
5051 * \param demod: instance of demod.
5052 * \return DRXStatus_t.
5054 static int SetQAM256(struct drxk_state *state)
5059 /* QAM Equalizer Setup */
5061 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);
5064 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);
5067 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);
5070 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);
5073 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);
5076 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);
5080 /* Decision Feedback Equalizer */
5081 status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);
5084 status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);
5087 status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);
5090 status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);
5093 status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);
5096 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
5100 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
5103 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
5106 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
5110 /* QAM Slicer Settings */
5112 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM256);
5117 /* QAM Loop Controller Coeficients */
5119 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
5122 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
5125 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
5128 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
5131 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
5134 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
5137 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
5140 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
5144 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
5147 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);
5150 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);
5153 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
5156 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);
5159 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);
5162 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
5165 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
5168 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
5171 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
5174 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
5177 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
5182 /* QAM State Machine (FSM) Thresholds */
5184 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
5187 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5190 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5193 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5196 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);
5199 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);
5203 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5206 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
5209 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5214 /* QAM FSM Tracking Parameters */
5216 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5219 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
5222 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
5225 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
5228 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
5231 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
5234 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
5237 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5242 /*============================================================================*/
5244 * \brief Reset QAM block.
5245 * \param demod: instance of demod.
5246 * \param channel: pointer to channel data.
5247 * \return DRXStatus_t.
5249 static int QAMResetQAM(struct drxk_state *state)
5255 /* Stop QAM comstate->m_exec */
5256 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
5260 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
5263 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5267 /*============================================================================*/
5270 * \brief Set QAM symbolrate.
5271 * \param demod: instance of demod.
5272 * \param channel: pointer to channel data.
5273 * \return DRXStatus_t.
5275 static int QAMSetSymbolrate(struct drxk_state *state)
5277 u32 adcFrequency = 0;
5285 /* Select & calculate correct IQM rate */
5286 adcFrequency = (state->m_sysClockFreq * 1000) / 3;
5288 /* printk(KERN_DEBUG "drxk: SR %d\n", state->props.symbol_rate); */
5289 if (state->props.symbol_rate <= 1188750)
5291 else if (state->props.symbol_rate <= 2377500)
5293 else if (state->props.symbol_rate <= 4755000)
5295 status = write16(state, IQM_FD_RATESEL__A, ratesel);
5300 IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23)
5302 symbFreq = state->props.symbol_rate * (1 << ratesel);
5303 if (symbFreq == 0) {
5304 /* Divide by zero */
5308 iqmRcRate = (adcFrequency / symbFreq) * (1 << 21) +
5309 (Frac28a((adcFrequency % symbFreq), symbFreq) >> 7) -
5311 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate);
5314 state->m_iqmRcRate = iqmRcRate;
5316 LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15))
5318 symbFreq = state->props.symbol_rate;
5319 if (adcFrequency == 0) {
5320 /* Divide by zero */
5324 lcSymbRate = (symbFreq / adcFrequency) * (1 << 12) +
5325 (Frac28a((symbFreq % adcFrequency), adcFrequency) >>
5327 if (lcSymbRate > 511)
5329 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate);
5333 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5337 /*============================================================================*/
5340 * \brief Get QAM lock status.
5341 * \param demod: instance of demod.
5342 * \param channel: pointer to channel data.
5343 * \return DRXStatus_t.
5346 static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus)
5349 u16 Result[2] = { 0, 0 };
5352 *pLockStatus = NOT_LOCKED;
5353 status = scu_command(state,
5354 SCU_RAM_COMMAND_STANDARD_QAM |
5355 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2,
5358 printk(KERN_ERR "drxk: %s status = %08x\n", __func__, status);
5360 if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) {
5361 /* 0x0000 NOT LOCKED */
5362 } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) {
5363 /* 0x4000 DEMOD LOCKED */
5364 *pLockStatus = DEMOD_LOCK;
5365 } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) {
5366 /* 0x8000 DEMOD + FEC LOCKED (system lock) */
5367 *pLockStatus = MPEG_LOCK;
5369 /* 0xC000 NEVER LOCKED */
5370 /* (system will never be able to lock to the signal) */
5371 /* TODO: check this, intermediate & standard specific lock states are not
5372 taken into account here */
5373 *pLockStatus = NEVER_LOCK;
5378 #define QAM_MIRROR__M 0x03
5379 #define QAM_MIRROR_NORMAL 0x00
5380 #define QAM_MIRRORED 0x01
5381 #define QAM_MIRROR_AUTO_ON 0x02
5382 #define QAM_LOCKRANGE__M 0x10
5383 #define QAM_LOCKRANGE_NORMAL 0x10
5385 static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5386 s32 tunerFreqOffset)
5389 u16 setParamParameters[4] = { 0, 0, 0, 0 };
5394 * STEP 1: reset demodulator
5395 * resets FEC DI and FEC RS
5397 * resets SCU variables
5399 status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
5402 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
5405 status = QAMResetQAM(state);
5410 * STEP 2: configure demodulator
5411 * -set params; resets IQM,QAM,FEC HW; initializes some
5414 status = QAMSetSymbolrate(state);
5419 switch (state->props.modulation) {
5421 state->m_Constellation = DRX_CONSTELLATION_QAM256;
5425 state->m_Constellation = DRX_CONSTELLATION_QAM64;
5428 state->m_Constellation = DRX_CONSTELLATION_QAM16;
5431 state->m_Constellation = DRX_CONSTELLATION_QAM32;
5434 state->m_Constellation = DRX_CONSTELLATION_QAM128;
5442 setParamParameters[0] = state->m_Constellation; /* modulation */
5443 setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */
5444 if (state->m_OperationMode == OM_QAM_ITU_C)
5445 setParamParameters[2] = QAM_TOP_ANNEX_C;
5447 setParamParameters[2] = QAM_TOP_ANNEX_A;
5448 setParamParameters[3] |= (QAM_MIRROR_AUTO_ON);
5449 /* Env parameters */
5450 /* check for LOCKRANGE Extented */
5451 /* setParamParameters[3] |= QAM_LOCKRANGE_NORMAL; */
5453 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 4, setParamParameters, 1, &cmdResult);
5455 /* Fall-back to the simpler call */
5456 if (state->m_OperationMode == OM_QAM_ITU_C)
5457 setParamParameters[0] = QAM_TOP_ANNEX_C;
5459 setParamParameters[0] = QAM_TOP_ANNEX_A;
5460 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 1, setParamParameters, 1, &cmdResult);
5464 setParamParameters[0] = state->m_Constellation; /* modulation */
5465 setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */
5466 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 2, setParamParameters, 1, &cmdResult);
5472 * STEP 3: enable the system in a mode where the ADC provides valid
5473 * signal setup modulation independent registers
5476 status = SetFrequency(channel, tunerFreqOffset));
5480 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
5484 /* Setup BER measurement */
5485 status = SetQAMMeasurement(state, state->m_Constellation, state->props.symbol_rate);
5489 /* Reset default values */
5490 status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
5493 status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
5497 /* Reset default LC values */
5498 status = write16(state, QAM_LC_RATE_LIMIT__A, 3);
5501 status = write16(state, QAM_LC_LPF_FACTORP__A, 4);
5504 status = write16(state, QAM_LC_LPF_FACTORI__A, 4);
5507 status = write16(state, QAM_LC_MODE__A, 7);
5511 status = write16(state, QAM_LC_QUAL_TAB0__A, 1);
5514 status = write16(state, QAM_LC_QUAL_TAB1__A, 1);
5517 status = write16(state, QAM_LC_QUAL_TAB2__A, 1);
5520 status = write16(state, QAM_LC_QUAL_TAB3__A, 1);
5523 status = write16(state, QAM_LC_QUAL_TAB4__A, 2);
5526 status = write16(state, QAM_LC_QUAL_TAB5__A, 2);
5529 status = write16(state, QAM_LC_QUAL_TAB6__A, 2);
5532 status = write16(state, QAM_LC_QUAL_TAB8__A, 2);
5535 status = write16(state, QAM_LC_QUAL_TAB9__A, 2);
5538 status = write16(state, QAM_LC_QUAL_TAB10__A, 2);
5541 status = write16(state, QAM_LC_QUAL_TAB12__A, 2);
5544 status = write16(state, QAM_LC_QUAL_TAB15__A, 3);
5547 status = write16(state, QAM_LC_QUAL_TAB16__A, 3);
5550 status = write16(state, QAM_LC_QUAL_TAB20__A, 4);
5553 status = write16(state, QAM_LC_QUAL_TAB25__A, 4);
5557 /* Mirroring, QAM-block starting point not inverted */
5558 status = write16(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS);
5562 /* Halt SCU to enable safe non-atomic accesses */
5563 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5567 /* STEP 4: modulation specific setup */
5568 switch (state->props.modulation) {
5570 status = SetQAM16(state);
5573 status = SetQAM32(state);
5577 status = SetQAM64(state);
5580 status = SetQAM128(state);
5583 status = SetQAM256(state);
5592 /* Activate SCU to enable SCU commands */
5593 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5597 /* Re-configure MPEG output, requires knowledge of channel bitrate */
5598 /* extAttr->currentChannel.modulation = channel->modulation; */
5599 /* extAttr->currentChannel.symbolrate = channel->symbolrate; */
5600 status = MPEGTSDtoSetup(state, state->m_OperationMode);
5604 /* Start processes */
5605 status = MPEGTSStart(state);
5608 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
5611 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
5614 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
5618 /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
5619 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult);
5623 /* update global DRXK data container */
5624 /*? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */
5628 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5632 static int SetQAMStandard(struct drxk_state *state,
5633 enum OperationMode oMode)
5636 #ifdef DRXK_QAM_TAPS
5637 #define DRXK_QAMA_TAPS_SELECT
5638 #include "drxk_filters.h"
5639 #undef DRXK_QAMA_TAPS_SELECT
5644 /* added antenna switch */
5645 SwitchAntennaToQAM(state);
5647 /* Ensure correct power-up mode */
5648 status = PowerUpQAM(state);
5651 /* Reset QAM block */
5652 status = QAMResetQAM(state);
5658 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
5661 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
5665 /* Upload IQM Channel Filter settings by
5666 boot loader from ROM table */
5669 status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5672 status = BLDirectCmd(state, IQM_CF_TAP_RE0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5675 status = BLDirectCmd(state, IQM_CF_TAP_IM0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5683 status = write16(state, IQM_CF_OUT_ENA__A, (1 << IQM_CF_OUT_ENA_QAM__B));
5686 status = write16(state, IQM_CF_SYMMETRIC__A, 0);
5689 status = write16(state, IQM_CF_MIDTAP__A, ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B)));
5693 status = write16(state, IQM_RC_STRETCH__A, 21);
5696 status = write16(state, IQM_AF_CLP_LEN__A, 0);
5699 status = write16(state, IQM_AF_CLP_TH__A, 448);
5702 status = write16(state, IQM_AF_SNS_LEN__A, 0);
5705 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);
5709 status = write16(state, IQM_FS_ADJ_SEL__A, 1);
5712 status = write16(state, IQM_RC_ADJ_SEL__A, 1);
5715 status = write16(state, IQM_CF_ADJ_SEL__A, 1);
5718 status = write16(state, IQM_AF_UPD_SEL__A, 0);
5722 /* IQM Impulse Noise Processing Unit */
5723 status = write16(state, IQM_CF_CLP_VAL__A, 500);
5726 status = write16(state, IQM_CF_DATATH__A, 1000);
5729 status = write16(state, IQM_CF_BYPASSDET__A, 1);
5732 status = write16(state, IQM_CF_DET_LCT__A, 0);
5735 status = write16(state, IQM_CF_WND_LEN__A, 1);
5738 status = write16(state, IQM_CF_PKDTH__A, 1);
5741 status = write16(state, IQM_AF_INC_BYPASS__A, 1);
5745 /* turn on IQMAF. Must be done before setAgc**() */
5746 status = SetIqmAf(state, true);
5749 status = write16(state, IQM_AF_START_LOCK__A, 0x01);
5753 /* IQM will not be reset from here, sync ADC and update/init AGC */
5754 status = ADCSynchronization(state);
5758 /* Set the FSM step period */
5759 status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);
5763 /* Halt SCU to enable safe non-atomic accesses */
5764 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5768 /* No more resets of the IQM, current standard correctly set =>
5769 now AGCs can be configured. */
5771 status = InitAGC(state, true);
5774 status = SetPreSaw(state, &(state->m_qamPreSawCfg));
5778 /* Configure AGC's */
5779 status = SetAgcRf(state, &(state->m_qamRfAgcCfg), true);
5782 status = SetAgcIf(state, &(state->m_qamIfAgcCfg), true);
5786 /* Activate SCU to enable SCU commands */
5787 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5790 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5794 static int WriteGPIO(struct drxk_state *state)
5800 /* stop lock indicator process */
5801 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
5805 /* Write magic word to enable pdr reg write */
5806 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
5810 if (state->m_hasSAWSW) {
5811 if (state->UIO_mask & 0x0001) { /* UIO-1 */
5812 /* write to io pad configuration register - output mode */
5813 status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg);
5817 /* use corresponding bit in io data output registar */
5818 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5821 if ((state->m_GPIO & 0x0001) == 0)
5822 value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */
5824 value |= 0x8000; /* write one to 15th bit - 1st UIO */
5825 /* write back to io data output register */
5826 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5830 if (state->UIO_mask & 0x0002) { /* UIO-2 */
5831 /* write to io pad configuration register - output mode */
5832 status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg);
5836 /* use corresponding bit in io data output registar */
5837 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5840 if ((state->m_GPIO & 0x0002) == 0)
5841 value &= 0xBFFF; /* write zero to 14th bit - 2st UIO */
5843 value |= 0x4000; /* write one to 14th bit - 2st UIO */
5844 /* write back to io data output register */
5845 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5849 if (state->UIO_mask & 0x0004) { /* UIO-3 */
5850 /* write to io pad configuration register - output mode */
5851 status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg);
5855 /* use corresponding bit in io data output registar */
5856 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5859 if ((state->m_GPIO & 0x0004) == 0)
5860 value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */
5862 value |= 0x0004; /* write one to 2nd bit - 3rd UIO */
5863 /* write back to io data output register */
5864 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5869 /* Write magic word to disable pdr reg write */
5870 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
5873 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5877 static int SwitchAntennaToQAM(struct drxk_state *state)
5884 if (!state->antenna_gpio)
5887 gpio_state = state->m_GPIO & state->antenna_gpio;
5889 if (state->antenna_dvbt ^ gpio_state) {
5890 /* Antenna is on DVB-T mode. Switch */
5891 if (state->antenna_dvbt)
5892 state->m_GPIO &= ~state->antenna_gpio;
5894 state->m_GPIO |= state->antenna_gpio;
5895 status = WriteGPIO(state);
5898 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5902 static int SwitchAntennaToDVBT(struct drxk_state *state)
5909 if (!state->antenna_gpio)
5912 gpio_state = state->m_GPIO & state->antenna_gpio;
5914 if (!(state->antenna_dvbt ^ gpio_state)) {
5915 /* Antenna is on DVB-C mode. Switch */
5916 if (state->antenna_dvbt)
5917 state->m_GPIO |= state->antenna_gpio;
5919 state->m_GPIO &= ~state->antenna_gpio;
5920 status = WriteGPIO(state);
5923 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5928 static int PowerDownDevice(struct drxk_state *state)
5930 /* Power down to requested mode */
5931 /* Backup some register settings */
5932 /* Set pins with possible pull-ups connected to them in input mode */
5933 /* Analog power down */
5934 /* ADC power down */
5935 /* Power down device */
5939 if (state->m_bPDownOpenBridge) {
5940 /* Open I2C bridge before power down of DRXK */
5941 status = ConfigureI2CBridge(state, true);
5946 status = DVBTEnableOFDMTokenRing(state, false);
5950 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK);
5953 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
5956 state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
5957 status = HI_CfgCommand(state);
5960 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5965 static int load_microcode(struct drxk_state *state, const char *mc_name)
5967 const struct firmware *fw = NULL;
5972 err = request_firmware(&fw, mc_name, state->i2c->dev.parent);
5975 "drxk: Could not load firmware file %s.\n", mc_name);
5977 "drxk: Copy %s to your hotplug directory!\n", mc_name);
5980 err = DownloadMicrocode(state, fw->data, fw->size);
5981 release_firmware(fw);
5985 static int init_drxk(struct drxk_state *state)
5988 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
5992 if ((state->m_DrxkState == DRXK_UNINITIALIZED)) {
5993 status = PowerUpDevice(state);
5996 status = DRXX_Open(state);
5999 /* Soft reset of OFDM-, sys- and osc-clockdomain */
6000 status = write16(state, SIO_CC_SOFT_RST__A, SIO_CC_SOFT_RST_OFDM__M | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M);
6003 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6006 /* TODO is this needed, if yes how much delay in worst case scenario */
6008 state->m_DRXK_A3_PATCH_CODE = true;
6009 status = GetDeviceCapabilities(state);
6013 /* Bridge delay, uses oscilator clock */
6014 /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */
6015 /* SDA brdige delay */
6016 state->m_HICfgBridgeDelay =
6017 (u16) ((state->m_oscClockFreq / 1000) *
6018 HI_I2C_BRIDGE_DELAY) / 1000;
6020 if (state->m_HICfgBridgeDelay >
6021 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) {
6022 state->m_HICfgBridgeDelay =
6023 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
6025 /* SCL bridge delay, same as SDA for now */
6026 state->m_HICfgBridgeDelay +=
6027 state->m_HICfgBridgeDelay <<
6028 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B;
6030 status = InitHI(state);
6033 /* disable various processes */
6035 if (!(state->m_DRXK_A1_ROM_CODE)
6036 && !(state->m_DRXK_A2_ROM_CODE))
6039 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
6044 /* disable MPEG port */
6045 status = MPEGTSDisable(state);
6049 /* Stop AUD and SCU */
6050 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
6053 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
6057 /* enable token-ring bus through OFDM block for possible ucode upload */
6058 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON);
6062 /* include boot loader section */
6063 status = write16(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE);
6066 status = BLChainCmd(state, 0, 6, 100);
6070 if (state->microcode_name)
6071 load_microcode(state, state->microcode_name);
6073 /* disable token-ring bus through OFDM block for possible ucode upload */
6074 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF);
6078 /* Run SCU for a little while to initialize microcode version numbers */
6079 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
6082 status = DRXX_Open(state);
6085 /* added for test */
6088 powerMode = DRXK_POWER_DOWN_OFDM;
6089 status = CtrlPowerMode(state, &powerMode);
6093 /* Stamp driver version number in SCU data RAM in BCD code
6094 Done to enable field application engineers to retreive drxdriver version
6095 via I2C from SCU RAM.
6096 Not using SCU command interface for SCU register access since no
6097 microcode may be present.
6100 (((DRXK_VERSION_MAJOR / 100) % 10) << 12) +
6101 (((DRXK_VERSION_MAJOR / 10) % 10) << 8) +
6102 ((DRXK_VERSION_MAJOR % 10) << 4) +
6103 (DRXK_VERSION_MINOR % 10);
6104 status = write16(state, SCU_RAM_DRIVER_VER_HI__A, driverVersion);
6108 (((DRXK_VERSION_PATCH / 1000) % 10) << 12) +
6109 (((DRXK_VERSION_PATCH / 100) % 10) << 8) +
6110 (((DRXK_VERSION_PATCH / 10) % 10) << 4) +
6111 (DRXK_VERSION_PATCH % 10);
6112 status = write16(state, SCU_RAM_DRIVER_VER_LO__A, driverVersion);
6116 printk(KERN_INFO "DRXK driver version %d.%d.%d\n",
6117 DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR,
6118 DRXK_VERSION_PATCH);
6120 /* Dirty fix of default values for ROM/PATCH microcode
6121 Dirty because this fix makes it impossible to setup suitable values
6122 before calling DRX_Open. This solution requires changes to RF AGC speed
6123 to be done via the CTRL function after calling DRX_Open */
6125 /* m_dvbtRfAgcCfg.speed = 3; */
6127 /* Reset driver debug flags to 0 */
6128 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);
6133 NOTE: No more full FEC resets allowed afterwards!! */
6134 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
6137 /* MPEGTS functions are still the same */
6138 status = MPEGTSDtoInit(state);
6141 status = MPEGTSStop(state);
6144 status = MPEGTSConfigurePolarity(state);
6147 status = MPEGTSConfigurePins(state, state->m_enableMPEGOutput);
6150 /* added: configure GPIO */
6151 status = WriteGPIO(state);
6155 state->m_DrxkState = DRXK_STOPPED;
6157 if (state->m_bPowerDown) {
6158 status = PowerDownDevice(state);
6161 state->m_DrxkState = DRXK_POWERED_DOWN;
6163 state->m_DrxkState = DRXK_STOPPED;
6167 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
6172 static void drxk_release(struct dvb_frontend *fe)
6174 struct drxk_state *state = fe->demodulator_priv;
6180 static int drxk_sleep(struct dvb_frontend *fe)
6182 struct drxk_state *state = fe->demodulator_priv;
6189 static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
6191 struct drxk_state *state = fe->demodulator_priv;
6193 dprintk(1, "%s\n", enable ? "enable" : "disable");
6194 return ConfigureI2CBridge(state, enable ? true : false);
6197 static int drxk_set_parameters(struct dvb_frontend *fe)
6199 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6200 u32 delsys = p->delivery_system, old_delsys;
6201 struct drxk_state *state = fe->demodulator_priv;
6206 if (!fe->ops.tuner_ops.get_if_frequency) {
6208 "drxk: Error: get_if_frequency() not defined at tuner. Can't work without it!\n");
6212 if (fe->ops.i2c_gate_ctrl)
6213 fe->ops.i2c_gate_ctrl(fe, 1);
6214 if (fe->ops.tuner_ops.set_params)
6215 fe->ops.tuner_ops.set_params(fe);
6216 if (fe->ops.i2c_gate_ctrl)
6217 fe->ops.i2c_gate_ctrl(fe, 0);
6219 old_delsys = state->props.delivery_system;
6222 if (old_delsys != delsys) {
6225 case SYS_DVBC_ANNEX_A:
6226 case SYS_DVBC_ANNEX_C:
6227 if (!state->m_hasDVBC)
6229 state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ? true : false;
6230 if (state->m_itut_annex_c)
6231 SetOperationMode(state, OM_QAM_ITU_C);
6233 SetOperationMode(state, OM_QAM_ITU_A);
6236 if (!state->m_hasDVBT)
6238 SetOperationMode(state, OM_DVBT);
6245 fe->ops.tuner_ops.get_if_frequency(fe, &IF);
6246 Start(state, 0, IF);
6248 /* printk(KERN_DEBUG "drxk: %s IF=%d done\n", __func__, IF); */
6253 static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status)
6255 struct drxk_state *state = fe->demodulator_priv;
6260 GetLockStatus(state, &stat, 0);
6261 if (stat == MPEG_LOCK)
6263 if (stat == FEC_LOCK)
6265 if (stat == DEMOD_LOCK)
6270 static int drxk_read_ber(struct dvb_frontend *fe, u32 *ber)
6278 static int drxk_read_signal_strength(struct dvb_frontend *fe,
6281 struct drxk_state *state = fe->demodulator_priv;
6285 ReadIFAgc(state, &val);
6286 *strength = val & 0xffff;
6290 static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr)
6292 struct drxk_state *state = fe->demodulator_priv;
6296 GetSignalToNoise(state, &snr2);
6297 *snr = snr2 & 0xffff;
6301 static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
6303 struct drxk_state *state = fe->demodulator_priv;
6307 DVBTQAMGetAccPktErr(state, &err);
6308 *ucblocks = (u32) err;
6312 static int drxk_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings
6315 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6318 switch (p->delivery_system) {
6319 case SYS_DVBC_ANNEX_A:
6320 case SYS_DVBC_ANNEX_C:
6322 sets->min_delay_ms = 3000;
6323 sets->max_drift = 0;
6324 sets->step_size = 0;
6331 static struct dvb_frontend_ops drxk_ops = {
6332 /* .delsys will be filled dynamically */
6335 .frequency_min = 47000000,
6336 .frequency_max = 865000000,
6338 .symbol_rate_min = 870000,
6339 .symbol_rate_max = 11700000,
6341 .frequency_stepsize = 166667,
6343 .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
6344 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO |
6345 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
6346 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_MUTE_TS |
6347 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
6348 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO
6351 .release = drxk_release,
6352 .sleep = drxk_sleep,
6353 .i2c_gate_ctrl = drxk_gate_ctrl,
6355 .set_frontend = drxk_set_parameters,
6356 .get_tune_settings = drxk_get_tune_settings,
6358 .read_status = drxk_read_status,
6359 .read_ber = drxk_read_ber,
6360 .read_signal_strength = drxk_read_signal_strength,
6361 .read_snr = drxk_read_snr,
6362 .read_ucblocks = drxk_read_ucblocks,
6365 struct dvb_frontend *drxk_attach(const struct drxk_config *config,
6366 struct i2c_adapter *i2c)
6370 struct drxk_state *state = NULL;
6371 u8 adr = config->adr;
6374 state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL);
6379 state->demod_address = adr;
6380 state->single_master = config->single_master;
6381 state->microcode_name = config->microcode_name;
6382 state->no_i2c_bridge = config->no_i2c_bridge;
6383 state->antenna_gpio = config->antenna_gpio;
6384 state->antenna_dvbt = config->antenna_dvbt;
6385 state->m_ChunkSize = config->chunk_size;
6386 state->enable_merr_cfg = config->enable_merr_cfg;
6388 if (config->dynamic_clk) {
6389 state->m_DVBTStaticCLK = 0;
6390 state->m_DVBCStaticCLK = 0;
6392 state->m_DVBTStaticCLK = 1;
6393 state->m_DVBCStaticCLK = 1;
6397 if (config->mpeg_out_clk_strength)
6398 state->m_TSClockkStrength = config->mpeg_out_clk_strength & 0x07;
6400 state->m_TSClockkStrength = 0x06;
6402 if (config->parallel_ts)
6403 state->m_enableParallel = true;
6405 state->m_enableParallel = false;
6407 /* NOTE: as more UIO bits will be used, add them to the mask */
6408 state->UIO_mask = config->antenna_gpio;
6410 /* Default gpio to DVB-C */
6411 if (!state->antenna_dvbt && state->antenna_gpio)
6412 state->m_GPIO |= state->antenna_gpio;
6414 state->m_GPIO &= ~state->antenna_gpio;
6416 mutex_init(&state->mutex);
6418 memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops));
6419 state->frontend.demodulator_priv = state;
6422 if (init_drxk(state) < 0)
6425 /* Initialize the supported delivery systems */
6427 if (state->m_hasDVBC) {
6428 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A;
6429 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C;
6430 strlcat(state->frontend.ops.info.name, " DVB-C",
6431 sizeof(state->frontend.ops.info.name));
6433 if (state->m_hasDVBT) {
6434 state->frontend.ops.delsys[n++] = SYS_DVBT;
6435 strlcat(state->frontend.ops.info.name, " DVB-T",
6436 sizeof(state->frontend.ops.info.name));
6439 printk(KERN_INFO "drxk: frontend initialized.\n");
6440 return &state->frontend;
6443 printk(KERN_ERR "drxk: not found\n");
6447 EXPORT_SYMBOL(drxk_attach);
6449 MODULE_DESCRIPTION("DRX-K driver");
6450 MODULE_AUTHOR("Ralph Metzler");
6451 MODULE_LICENSE("GPL");