2 * drxk_hard: DRX-K DVB-C/T demodulator driver
4 * Copyright (C) 2010-2011 Digital Devices GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/init.h>
28 #include <linux/delay.h>
29 #include <linux/firmware.h>
30 #include <linux/i2c.h>
31 #include <asm/div64.h>
33 #include "dvb_frontend.h"
35 #include "drxk_hard.h"
37 static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode);
38 static int PowerDownQAM(struct drxk_state *state);
39 static int SetDVBTStandard(struct drxk_state *state,
40 enum OperationMode oMode);
41 static int SetQAMStandard(struct drxk_state *state,
42 enum OperationMode oMode);
43 static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
45 static int SetDVBTStandard(struct drxk_state *state,
46 enum OperationMode oMode);
47 static int DVBTStart(struct drxk_state *state);
48 static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
50 static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus);
51 static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus);
52 static int SwitchAntennaToQAM(struct drxk_state *state);
53 static int SwitchAntennaToDVBT(struct drxk_state *state);
55 static bool IsDVBT(struct drxk_state *state)
57 return state->m_OperationMode == OM_DVBT;
60 static bool IsQAM(struct drxk_state *state)
62 return state->m_OperationMode == OM_QAM_ITU_A ||
63 state->m_OperationMode == OM_QAM_ITU_B ||
64 state->m_OperationMode == OM_QAM_ITU_C;
67 bool IsA1WithPatchCode(struct drxk_state *state)
69 return state->m_DRXK_A1_PATCH_CODE;
72 bool IsA1WithRomCode(struct drxk_state *state)
74 return state->m_DRXK_A1_ROM_CODE;
79 #define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0)
80 #define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0)
82 #define DEFAULT_MER_83 165
83 #define DEFAULT_MER_93 250
85 #ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
86 #define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02)
89 #ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
90 #define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03)
93 #define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700
94 #define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500
96 #ifndef DRXK_KI_RAGC_ATV
97 #define DRXK_KI_RAGC_ATV 4
99 #ifndef DRXK_KI_IAGC_ATV
100 #define DRXK_KI_IAGC_ATV 6
102 #ifndef DRXK_KI_DAGC_ATV
103 #define DRXK_KI_DAGC_ATV 7
106 #ifndef DRXK_KI_RAGC_QAM
107 #define DRXK_KI_RAGC_QAM 3
109 #ifndef DRXK_KI_IAGC_QAM
110 #define DRXK_KI_IAGC_QAM 4
112 #ifndef DRXK_KI_DAGC_QAM
113 #define DRXK_KI_DAGC_QAM 7
115 #ifndef DRXK_KI_RAGC_DVBT
116 #define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2)
118 #ifndef DRXK_KI_IAGC_DVBT
119 #define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2)
121 #ifndef DRXK_KI_DAGC_DVBT
122 #define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7)
125 #ifndef DRXK_AGC_DAC_OFFSET
126 #define DRXK_AGC_DAC_OFFSET (0x800)
129 #ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ
130 #define DRXK_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L)
133 #ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ
134 #define DRXK_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L)
137 #ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ
138 #define DRXK_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L)
141 #ifndef DRXK_QAM_SYMBOLRATE_MAX
142 #define DRXK_QAM_SYMBOLRATE_MAX (7233000)
145 #define DRXK_BL_ROM_OFFSET_TAPS_DVBT 56
146 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_A 64
147 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_C 0x5FE0
148 #define DRXK_BL_ROM_OFFSET_TAPS_BG 24
149 #define DRXK_BL_ROM_OFFSET_TAPS_DKILLP 32
150 #define DRXK_BL_ROM_OFFSET_TAPS_NTSC 40
151 #define DRXK_BL_ROM_OFFSET_TAPS_FM 48
152 #define DRXK_BL_ROM_OFFSET_UCODE 0
154 #define DRXK_BLC_TIMEOUT 100
156 #define DRXK_BLCC_NR_ELEMENTS_TAPS 2
157 #define DRXK_BLCC_NR_ELEMENTS_UCODE 6
159 #define DRXK_BLDC_NR_ELEMENTS_TAPS 28
161 #ifndef DRXK_OFDM_NE_NOTCH_WIDTH
162 #define DRXK_OFDM_NE_NOTCH_WIDTH (4)
165 #define DRXK_QAM_SL_SIG_POWER_QAM16 (40960)
166 #define DRXK_QAM_SL_SIG_POWER_QAM32 (20480)
167 #define DRXK_QAM_SL_SIG_POWER_QAM64 (43008)
168 #define DRXK_QAM_SL_SIG_POWER_QAM128 (20992)
169 #define DRXK_QAM_SL_SIG_POWER_QAM256 (43520)
171 static unsigned int debug;
172 module_param(debug, int, 0644);
173 MODULE_PARM_DESC(debug, "enable debug messages");
175 #define dprintk(level, fmt, arg...) do { \
176 if (debug >= level) \
177 printk(KERN_DEBUG "drxk: %s" fmt, __func__, ## arg); \
181 static inline u32 MulDiv32(u32 a, u32 b, u32 c)
185 tmp64 = (u64) a * (u64) b;
191 inline u32 Frac28a(u32 a, u32 c)
197 R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */
198 Q1 = a / c; /* integer part, only the 4 least significant bits
199 will be visible in the result */
201 /* division using radix 16, 7 nibbles in the result */
202 for (i = 0; i < 7; i++) {
203 Q1 = (Q1 << 4) | (R0 / c);
213 static u32 Log10Times100(u32 x)
215 static const u8 scale = 15;
216 static const u8 indexWidth = 5;
223 log2lut[n] = (1<<scale) * 200 * log2(1.0 + ((1.0/(1<<INDEXWIDTH)) * n))
224 0 <= n < ((1<<INDEXWIDTH)+1)
227 static const u32 log2lut[] = {
229 290941, /* 290941.300628 */
230 573196, /* 573196.476418 */
231 847269, /* 847269.179851 */
232 1113620, /* 1113620.489452 */
233 1372674, /* 1372673.576986 */
234 1624818, /* 1624817.752104 */
235 1870412, /* 1870411.981536 */
236 2109788, /* 2109787.962654 */
237 2343253, /* 2343252.817465 */
238 2571091, /* 2571091.461923 */
239 2793569, /* 2793568.696416 */
240 3010931, /* 3010931.055901 */
241 3223408, /* 3223408.452106 */
242 3431216, /* 3431215.635215 */
243 3634553, /* 3634553.498355 */
244 3833610, /* 3833610.244726 */
245 4028562, /* 4028562.434393 */
246 4219576, /* 4219575.925308 */
247 4406807, /* 4406806.721144 */
248 4590402, /* 4590401.736809 */
249 4770499, /* 4770499.491025 */
250 4947231, /* 4947230.734179 */
251 5120719, /* 5120719.018555 */
252 5291081, /* 5291081.217197 */
253 5458428, /* 5458427.996830 */
254 5622864, /* 5622864.249668 */
255 5784489, /* 5784489.488298 */
256 5943398, /* 5943398.207380 */
257 6099680, /* 6099680.215452 */
258 6253421, /* 6253420.939751 */
259 6404702, /* 6404701.706649 */
260 6553600, /* 6553600.000000 */
267 /* Scale x (normalize) */
268 /* computing y in log(x/y) = log(x) - log(y) */
269 if ((x & ((0xffffffff) << (scale + 1))) == 0) {
270 for (k = scale; k > 0; k--) {
271 if (x & (((u32) 1) << scale))
276 for (k = scale; k < 31; k++) {
277 if ((x & (((u32) (-1)) << (scale + 1))) == 0)
283 Now x has binary point between bit[scale] and bit[scale-1]
284 and 1.0 <= x < 2.0 */
286 /* correction for divison: log(x) = log(x/y)+log(y) */
287 y = k * ((((u32) 1) << scale) * 200);
289 /* remove integer part */
290 x &= ((((u32) 1) << scale) - 1);
292 i = (u8) (x >> (scale - indexWidth));
293 /* compute delta (x - a) */
294 d = x & ((((u32) 1) << (scale - indexWidth)) - 1);
295 /* compute log, multiplication (d* (..)) must be within range ! */
297 ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - indexWidth));
298 /* Conver to log10() */
299 y /= 108853; /* (log2(10) << scale) */
307 /****************************************************************************/
308 /* I2C **********************************************************************/
309 /****************************************************************************/
311 static int i2c_read1(struct i2c_adapter *adapter, u8 adr, u8 *val)
313 struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD,
314 .buf = val, .len = 1}
317 return i2c_transfer(adapter, msgs, 1);
320 static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len)
323 struct i2c_msg msg = {
324 .addr = adr, .flags = 0, .buf = data, .len = len };
329 for (i = 0; i < len; i++)
330 printk(KERN_CONT " %02x", data[i]);
331 printk(KERN_CONT "\n");
333 status = i2c_transfer(adap, &msg, 1);
334 if (status >= 0 && status != 1)
338 printk(KERN_ERR "drxk: i2c write error at addr 0x%02x\n", adr);
343 static int i2c_read(struct i2c_adapter *adap,
344 u8 adr, u8 *msg, int len, u8 *answ, int alen)
347 struct i2c_msg msgs[2] = {
348 {.addr = adr, .flags = 0,
349 .buf = msg, .len = len},
350 {.addr = adr, .flags = I2C_M_RD,
351 .buf = answ, .len = alen}
354 status = i2c_transfer(adap, msgs, 2);
357 printk(KERN_CONT ": ERROR!\n");
361 printk(KERN_ERR "drxk: i2c read error at addr 0x%02x\n", adr);
366 dprintk(2, ": read from");
367 for (i = 0; i < len; i++)
368 printk(KERN_CONT " %02x", msg[i]);
369 printk(KERN_CONT ", value = ");
370 for (i = 0; i < alen; i++)
371 printk(KERN_CONT " %02x", answ[i]);
372 printk(KERN_CONT "\n");
377 static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
380 u8 adr = state->demod_address, mm1[4], mm2[2], len;
382 if (state->single_master)
385 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
386 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
387 mm1[1] = ((reg >> 16) & 0xFF);
388 mm1[2] = ((reg >> 24) & 0xFF) | flags;
389 mm1[3] = ((reg >> 7) & 0xFF);
392 mm1[0] = ((reg << 1) & 0xFF);
393 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
396 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
397 status = i2c_read(state->i2c, adr, mm1, len, mm2, 2);
401 *data = mm2[0] | (mm2[1] << 8);
406 static int read16(struct drxk_state *state, u32 reg, u16 *data)
408 return read16_flags(state, reg, data, 0);
411 static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
414 u8 adr = state->demod_address, mm1[4], mm2[4], len;
416 if (state->single_master)
419 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
420 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
421 mm1[1] = ((reg >> 16) & 0xFF);
422 mm1[2] = ((reg >> 24) & 0xFF) | flags;
423 mm1[3] = ((reg >> 7) & 0xFF);
426 mm1[0] = ((reg << 1) & 0xFF);
427 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
430 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
431 status = i2c_read(state->i2c, adr, mm1, len, mm2, 4);
435 *data = mm2[0] | (mm2[1] << 8) |
436 (mm2[2] << 16) | (mm2[3] << 24);
441 static int read32(struct drxk_state *state, u32 reg, u32 *data)
443 return read32_flags(state, reg, data, 0);
446 static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)
448 u8 adr = state->demod_address, mm[6], len;
450 if (state->single_master)
452 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
453 mm[0] = (((reg << 1) & 0xFF) | 0x01);
454 mm[1] = ((reg >> 16) & 0xFF);
455 mm[2] = ((reg >> 24) & 0xFF) | flags;
456 mm[3] = ((reg >> 7) & 0xFF);
459 mm[0] = ((reg << 1) & 0xFF);
460 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
463 mm[len] = data & 0xff;
464 mm[len + 1] = (data >> 8) & 0xff;
466 dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags);
467 return i2c_write(state->i2c, adr, mm, len + 2);
470 static int write16(struct drxk_state *state, u32 reg, u16 data)
472 return write16_flags(state, reg, data, 0);
475 static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)
477 u8 adr = state->demod_address, mm[8], len;
479 if (state->single_master)
481 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
482 mm[0] = (((reg << 1) & 0xFF) | 0x01);
483 mm[1] = ((reg >> 16) & 0xFF);
484 mm[2] = ((reg >> 24) & 0xFF) | flags;
485 mm[3] = ((reg >> 7) & 0xFF);
488 mm[0] = ((reg << 1) & 0xFF);
489 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
492 mm[len] = data & 0xff;
493 mm[len + 1] = (data >> 8) & 0xff;
494 mm[len + 2] = (data >> 16) & 0xff;
495 mm[len + 3] = (data >> 24) & 0xff;
496 dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags);
498 return i2c_write(state->i2c, adr, mm, len + 4);
501 static int write32(struct drxk_state *state, u32 reg, u32 data)
503 return write32_flags(state, reg, data, 0);
506 static int write_block(struct drxk_state *state, u32 Address,
507 const int BlockSize, const u8 pBlock[])
509 int status = 0, BlkSize = BlockSize;
512 if (state->single_master)
515 while (BlkSize > 0) {
516 int Chunk = BlkSize > state->m_ChunkSize ?
517 state->m_ChunkSize : BlkSize;
518 u8 *AdrBuf = &state->Chunk[0];
521 if (DRXDAP_FASI_LONG_FORMAT(Address) || (Flags != 0)) {
522 AdrBuf[0] = (((Address << 1) & 0xFF) | 0x01);
523 AdrBuf[1] = ((Address >> 16) & 0xFF);
524 AdrBuf[2] = ((Address >> 24) & 0xFF);
525 AdrBuf[3] = ((Address >> 7) & 0xFF);
528 if (Chunk == state->m_ChunkSize)
531 AdrBuf[0] = ((Address << 1) & 0xFF);
532 AdrBuf[1] = (((Address >> 16) & 0x0F) |
533 ((Address >> 18) & 0xF0));
536 memcpy(&state->Chunk[AdrLength], pBlock, Chunk);
537 dprintk(2, "(0x%08x, 0x%02x)\n", Address, Flags);
541 for (i = 0; i < Chunk; i++)
542 printk(KERN_CONT " %02x", pBlock[i]);
543 printk(KERN_CONT "\n");
545 status = i2c_write(state->i2c, state->demod_address,
546 &state->Chunk[0], Chunk + AdrLength);
548 printk(KERN_ERR "drxk: %s: i2c write error at addr 0x%02x\n",
553 Address += (Chunk >> 1);
559 #ifndef DRXK_MAX_RETRIES_POWERUP
560 #define DRXK_MAX_RETRIES_POWERUP 20
563 int PowerUpDevice(struct drxk_state *state)
571 status = i2c_read1(state->i2c, state->demod_address, &data);
575 status = i2c_write(state->i2c, state->demod_address,
581 status = i2c_read1(state->i2c, state->demod_address,
583 } while (status < 0 &&
584 (retryCount < DRXK_MAX_RETRIES_POWERUP));
585 if (status < 0 && retryCount >= DRXK_MAX_RETRIES_POWERUP)
589 /* Make sure all clk domains are active */
590 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
593 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
596 /* Enable pll lock tests */
597 status = write16(state, SIO_CC_PLL_LOCK__A, 1);
601 state->m_currentPowerMode = DRX_POWER_UP;
605 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
611 static int init_state(struct drxk_state *state)
614 * FIXME: most (all?) of the values bellow should be moved into
615 * struct drxk_config, as they are probably board-specific
617 u32 ulVSBIfAgcMode = DRXK_AGC_CTRL_AUTO;
618 u32 ulVSBIfAgcOutputLevel = 0;
619 u32 ulVSBIfAgcMinLevel = 0;
620 u32 ulVSBIfAgcMaxLevel = 0x7FFF;
621 u32 ulVSBIfAgcSpeed = 3;
623 u32 ulVSBRfAgcMode = DRXK_AGC_CTRL_AUTO;
624 u32 ulVSBRfAgcOutputLevel = 0;
625 u32 ulVSBRfAgcMinLevel = 0;
626 u32 ulVSBRfAgcMaxLevel = 0x7FFF;
627 u32 ulVSBRfAgcSpeed = 3;
628 u32 ulVSBRfAgcTop = 9500;
629 u32 ulVSBRfAgcCutOffCurrent = 4000;
631 u32 ulATVIfAgcMode = DRXK_AGC_CTRL_AUTO;
632 u32 ulATVIfAgcOutputLevel = 0;
633 u32 ulATVIfAgcMinLevel = 0;
634 u32 ulATVIfAgcMaxLevel = 0;
635 u32 ulATVIfAgcSpeed = 3;
637 u32 ulATVRfAgcMode = DRXK_AGC_CTRL_OFF;
638 u32 ulATVRfAgcOutputLevel = 0;
639 u32 ulATVRfAgcMinLevel = 0;
640 u32 ulATVRfAgcMaxLevel = 0;
641 u32 ulATVRfAgcTop = 9500;
642 u32 ulATVRfAgcCutOffCurrent = 4000;
643 u32 ulATVRfAgcSpeed = 3;
645 u32 ulQual83 = DEFAULT_MER_83;
646 u32 ulQual93 = DEFAULT_MER_93;
648 u32 ulMpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
649 u32 ulDemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
651 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
652 /* io_pad_cfg_mode output mode is drive always */
653 /* io_pad_cfg_drive is set to power 2 (23 mA) */
654 u32 ulGPIOCfg = 0x0113;
655 u32 ulInvertTSClock = 0;
656 u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH;
657 u32 ulDVBTBitrate = 50000000;
658 u32 ulDVBCBitrate = DRXK_QAM_SYMBOLRATE_MAX * 8;
660 u32 ulInsertRSByte = 0;
667 state->m_hasLNA = false;
668 state->m_hasDVBT = false;
669 state->m_hasDVBC = false;
670 state->m_hasATV = false;
671 state->m_hasOOB = false;
672 state->m_hasAudio = false;
674 if (!state->m_ChunkSize)
675 state->m_ChunkSize = 124;
677 state->m_oscClockFreq = 0;
678 state->m_smartAntInverted = false;
679 state->m_bPDownOpenBridge = false;
681 /* real system clock frequency in kHz */
682 state->m_sysClockFreq = 151875;
683 /* Timing div, 250ns/Psys */
684 /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */
685 state->m_HICfgTimingDiv = ((state->m_sysClockFreq / 1000) *
686 HI_I2C_DELAY) / 1000;
688 if (state->m_HICfgTimingDiv > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
689 state->m_HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
690 state->m_HICfgWakeUpKey = (state->demod_address << 1);
691 /* port/bridge/power down ctrl */
692 state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
694 state->m_bPowerDown = (ulPowerDown != 0);
696 state->m_DRXK_A1_PATCH_CODE = false;
697 state->m_DRXK_A1_ROM_CODE = false;
698 state->m_DRXK_A2_ROM_CODE = false;
699 state->m_DRXK_A3_ROM_CODE = false;
700 state->m_DRXK_A2_PATCH_CODE = false;
701 state->m_DRXK_A3_PATCH_CODE = false;
703 /* Init AGC and PGA parameters */
705 state->m_vsbIfAgcCfg.ctrlMode = (ulVSBIfAgcMode);
706 state->m_vsbIfAgcCfg.outputLevel = (ulVSBIfAgcOutputLevel);
707 state->m_vsbIfAgcCfg.minOutputLevel = (ulVSBIfAgcMinLevel);
708 state->m_vsbIfAgcCfg.maxOutputLevel = (ulVSBIfAgcMaxLevel);
709 state->m_vsbIfAgcCfg.speed = (ulVSBIfAgcSpeed);
710 state->m_vsbPgaCfg = 140;
713 state->m_vsbRfAgcCfg.ctrlMode = (ulVSBRfAgcMode);
714 state->m_vsbRfAgcCfg.outputLevel = (ulVSBRfAgcOutputLevel);
715 state->m_vsbRfAgcCfg.minOutputLevel = (ulVSBRfAgcMinLevel);
716 state->m_vsbRfAgcCfg.maxOutputLevel = (ulVSBRfAgcMaxLevel);
717 state->m_vsbRfAgcCfg.speed = (ulVSBRfAgcSpeed);
718 state->m_vsbRfAgcCfg.top = (ulVSBRfAgcTop);
719 state->m_vsbRfAgcCfg.cutOffCurrent = (ulVSBRfAgcCutOffCurrent);
720 state->m_vsbPreSawCfg.reference = 0x07;
721 state->m_vsbPreSawCfg.usePreSaw = true;
723 state->m_Quality83percent = DEFAULT_MER_83;
724 state->m_Quality93percent = DEFAULT_MER_93;
725 if (ulQual93 <= 500 && ulQual83 < ulQual93) {
726 state->m_Quality83percent = ulQual83;
727 state->m_Quality93percent = ulQual93;
731 state->m_atvIfAgcCfg.ctrlMode = (ulATVIfAgcMode);
732 state->m_atvIfAgcCfg.outputLevel = (ulATVIfAgcOutputLevel);
733 state->m_atvIfAgcCfg.minOutputLevel = (ulATVIfAgcMinLevel);
734 state->m_atvIfAgcCfg.maxOutputLevel = (ulATVIfAgcMaxLevel);
735 state->m_atvIfAgcCfg.speed = (ulATVIfAgcSpeed);
738 state->m_atvRfAgcCfg.ctrlMode = (ulATVRfAgcMode);
739 state->m_atvRfAgcCfg.outputLevel = (ulATVRfAgcOutputLevel);
740 state->m_atvRfAgcCfg.minOutputLevel = (ulATVRfAgcMinLevel);
741 state->m_atvRfAgcCfg.maxOutputLevel = (ulATVRfAgcMaxLevel);
742 state->m_atvRfAgcCfg.speed = (ulATVRfAgcSpeed);
743 state->m_atvRfAgcCfg.top = (ulATVRfAgcTop);
744 state->m_atvRfAgcCfg.cutOffCurrent = (ulATVRfAgcCutOffCurrent);
745 state->m_atvPreSawCfg.reference = 0x04;
746 state->m_atvPreSawCfg.usePreSaw = true;
750 state->m_dvbtRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
751 state->m_dvbtRfAgcCfg.outputLevel = 0;
752 state->m_dvbtRfAgcCfg.minOutputLevel = 0;
753 state->m_dvbtRfAgcCfg.maxOutputLevel = 0xFFFF;
754 state->m_dvbtRfAgcCfg.top = 0x2100;
755 state->m_dvbtRfAgcCfg.cutOffCurrent = 4000;
756 state->m_dvbtRfAgcCfg.speed = 1;
760 state->m_dvbtIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
761 state->m_dvbtIfAgcCfg.outputLevel = 0;
762 state->m_dvbtIfAgcCfg.minOutputLevel = 0;
763 state->m_dvbtIfAgcCfg.maxOutputLevel = 9000;
764 state->m_dvbtIfAgcCfg.top = 13424;
765 state->m_dvbtIfAgcCfg.cutOffCurrent = 0;
766 state->m_dvbtIfAgcCfg.speed = 3;
767 state->m_dvbtIfAgcCfg.FastClipCtrlDelay = 30;
768 state->m_dvbtIfAgcCfg.IngainTgtMax = 30000;
769 /* state->m_dvbtPgaCfg = 140; */
771 state->m_dvbtPreSawCfg.reference = 4;
772 state->m_dvbtPreSawCfg.usePreSaw = false;
775 state->m_qamRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
776 state->m_qamRfAgcCfg.outputLevel = 0;
777 state->m_qamRfAgcCfg.minOutputLevel = 6023;
778 state->m_qamRfAgcCfg.maxOutputLevel = 27000;
779 state->m_qamRfAgcCfg.top = 0x2380;
780 state->m_qamRfAgcCfg.cutOffCurrent = 4000;
781 state->m_qamRfAgcCfg.speed = 3;
784 state->m_qamIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
785 state->m_qamIfAgcCfg.outputLevel = 0;
786 state->m_qamIfAgcCfg.minOutputLevel = 0;
787 state->m_qamIfAgcCfg.maxOutputLevel = 9000;
788 state->m_qamIfAgcCfg.top = 0x0511;
789 state->m_qamIfAgcCfg.cutOffCurrent = 0;
790 state->m_qamIfAgcCfg.speed = 3;
791 state->m_qamIfAgcCfg.IngainTgtMax = 5119;
792 state->m_qamIfAgcCfg.FastClipCtrlDelay = 50;
794 state->m_qamPgaCfg = 140;
795 state->m_qamPreSawCfg.reference = 4;
796 state->m_qamPreSawCfg.usePreSaw = false;
798 state->m_OperationMode = OM_NONE;
799 state->m_DrxkState = DRXK_UNINITIALIZED;
801 /* MPEG output configuration */
802 state->m_enableMPEGOutput = true; /* If TRUE; enable MPEG ouput */
803 state->m_insertRSByte = false; /* If TRUE; insert RS byte */
804 state->m_invertDATA = false; /* If TRUE; invert DATA signals */
805 state->m_invertERR = false; /* If TRUE; invert ERR signal */
806 state->m_invertSTR = false; /* If TRUE; invert STR signals */
807 state->m_invertVAL = false; /* If TRUE; invert VAL signals */
808 state->m_invertCLK = (ulInvertTSClock != 0); /* If TRUE; invert CLK signals */
810 /* If TRUE; static MPEG clockrate will be used;
811 otherwise clockrate will adapt to the bitrate of the TS */
813 state->m_DVBTBitrate = ulDVBTBitrate;
814 state->m_DVBCBitrate = ulDVBCBitrate;
816 state->m_TSDataStrength = (ulTSDataStrength & 0x07);
818 /* Maximum bitrate in b/s in case static clockrate is selected */
819 state->m_mpegTsStaticBitrate = 19392658;
820 state->m_disableTEIhandling = false;
823 state->m_insertRSByte = true;
825 state->m_MpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
826 if (ulMpegLockTimeOut < 10000)
827 state->m_MpegLockTimeOut = ulMpegLockTimeOut;
828 state->m_DemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
829 if (ulDemodLockTimeOut < 10000)
830 state->m_DemodLockTimeOut = ulDemodLockTimeOut;
833 state->m_Constellation = DRX_CONSTELLATION_AUTO;
834 state->m_qamInterleaveMode = DRXK_QAM_I12_J17;
835 state->m_fecRsPlen = 204 * 8; /* fecRsPlen annex A */
836 state->m_fecRsPrescale = 1;
838 state->m_sqiSpeed = DRXK_DVBT_SQI_SPEED_MEDIUM;
839 state->m_agcFastClipCtrlDelay = 0;
841 state->m_GPIOCfg = (ulGPIOCfg);
843 state->m_bPowerDown = false;
844 state->m_currentPowerMode = DRX_POWER_DOWN;
846 state->m_rfmirror = (ulRfMirror == 0);
847 state->m_IfAgcPol = false;
851 static int DRXX_Open(struct drxk_state *state)
859 /* stop lock indicator process */
860 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
863 /* Check device id */
864 status = read16(state, SIO_TOP_COMM_KEY__A, &key);
867 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
870 status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
873 status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);
876 status = write16(state, SIO_TOP_COMM_KEY__A, key);
879 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
883 static int GetDeviceCapabilities(struct drxk_state *state)
885 u16 sioPdrOhwCfg = 0;
886 u32 sioTopJtagidLo = 0;
888 const char *spin = "";
893 /* stop lock indicator process */
894 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
897 status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA);
900 status = read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg);
903 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
907 switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
909 /* ignore (bypass ?) */
913 state->m_oscClockFreq = 27000;
917 state->m_oscClockFreq = 20250;
921 state->m_oscClockFreq = 20250;
924 printk(KERN_ERR "drxk: Clock Frequency is unkonwn\n");
928 Determine device capabilities
931 status = read32(state, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo);
935 printk(KERN_ERR "drxk: status = 0x%08x\n", sioTopJtagidLo);
938 switch ((sioTopJtagidLo >> 29) & 0xF) {
940 state->m_deviceSpin = DRXK_SPIN_A1;
944 state->m_deviceSpin = DRXK_SPIN_A2;
948 state->m_deviceSpin = DRXK_SPIN_A3;
952 state->m_deviceSpin = DRXK_SPIN_UNKNOWN;
954 printk(KERN_ERR "drxk: Spin %d unknown\n",
955 (sioTopJtagidLo >> 29) & 0xF);
958 switch ((sioTopJtagidLo >> 12) & 0xFF) {
960 /* typeId = DRX3913K_TYPE_ID */
961 state->m_hasLNA = false;
962 state->m_hasOOB = false;
963 state->m_hasATV = false;
964 state->m_hasAudio = false;
965 state->m_hasDVBT = true;
966 state->m_hasDVBC = true;
967 state->m_hasSAWSW = true;
968 state->m_hasGPIO2 = false;
969 state->m_hasGPIO1 = false;
970 state->m_hasIRQN = false;
973 /* typeId = DRX3915K_TYPE_ID */
974 state->m_hasLNA = false;
975 state->m_hasOOB = false;
976 state->m_hasATV = true;
977 state->m_hasAudio = false;
978 state->m_hasDVBT = true;
979 state->m_hasDVBC = false;
980 state->m_hasSAWSW = true;
981 state->m_hasGPIO2 = true;
982 state->m_hasGPIO1 = true;
983 state->m_hasIRQN = false;
986 /* typeId = DRX3916K_TYPE_ID */
987 state->m_hasLNA = false;
988 state->m_hasOOB = false;
989 state->m_hasATV = true;
990 state->m_hasAudio = false;
991 state->m_hasDVBT = true;
992 state->m_hasDVBC = false;
993 state->m_hasSAWSW = true;
994 state->m_hasGPIO2 = true;
995 state->m_hasGPIO1 = true;
996 state->m_hasIRQN = false;
999 /* typeId = DRX3918K_TYPE_ID */
1000 state->m_hasLNA = false;
1001 state->m_hasOOB = false;
1002 state->m_hasATV = true;
1003 state->m_hasAudio = true;
1004 state->m_hasDVBT = true;
1005 state->m_hasDVBC = false;
1006 state->m_hasSAWSW = true;
1007 state->m_hasGPIO2 = true;
1008 state->m_hasGPIO1 = true;
1009 state->m_hasIRQN = false;
1012 /* typeId = DRX3921K_TYPE_ID */
1013 state->m_hasLNA = false;
1014 state->m_hasOOB = false;
1015 state->m_hasATV = true;
1016 state->m_hasAudio = true;
1017 state->m_hasDVBT = true;
1018 state->m_hasDVBC = true;
1019 state->m_hasSAWSW = true;
1020 state->m_hasGPIO2 = true;
1021 state->m_hasGPIO1 = true;
1022 state->m_hasIRQN = false;
1025 /* typeId = DRX3923K_TYPE_ID */
1026 state->m_hasLNA = false;
1027 state->m_hasOOB = false;
1028 state->m_hasATV = true;
1029 state->m_hasAudio = true;
1030 state->m_hasDVBT = true;
1031 state->m_hasDVBC = true;
1032 state->m_hasSAWSW = true;
1033 state->m_hasGPIO2 = true;
1034 state->m_hasGPIO1 = true;
1035 state->m_hasIRQN = false;
1038 /* typeId = DRX3925K_TYPE_ID */
1039 state->m_hasLNA = false;
1040 state->m_hasOOB = false;
1041 state->m_hasATV = true;
1042 state->m_hasAudio = true;
1043 state->m_hasDVBT = true;
1044 state->m_hasDVBC = true;
1045 state->m_hasSAWSW = true;
1046 state->m_hasGPIO2 = true;
1047 state->m_hasGPIO1 = true;
1048 state->m_hasIRQN = false;
1051 /* typeId = DRX3926K_TYPE_ID */
1052 state->m_hasLNA = false;
1053 state->m_hasOOB = false;
1054 state->m_hasATV = true;
1055 state->m_hasAudio = false;
1056 state->m_hasDVBT = true;
1057 state->m_hasDVBC = true;
1058 state->m_hasSAWSW = true;
1059 state->m_hasGPIO2 = true;
1060 state->m_hasGPIO1 = true;
1061 state->m_hasIRQN = false;
1064 printk(KERN_ERR "drxk: DeviceID 0x%02x not supported\n",
1065 ((sioTopJtagidLo >> 12) & 0xFF));
1071 "drxk: detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n",
1072 ((sioTopJtagidLo >> 12) & 0xFF), spin,
1073 state->m_oscClockFreq / 1000,
1074 state->m_oscClockFreq % 1000);
1078 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1084 static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult)
1092 status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);
1095 if (cmd == SIO_HI_RA_RAM_CMD_RESET)
1099 (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
1100 ((state->m_HICfgCtrl) &
1101 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) ==
1102 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ);
1103 if (powerdown_cmd == false) {
1104 /* Wait until command rdy */
1111 status = read16(state, SIO_HI_RA_RAM_CMD__A,
1113 } while ((status < 0) && (retryCount < DRXK_MAX_RETRIES)
1117 status = read16(state, SIO_HI_RA_RAM_RES__A, pResult);
1121 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1126 static int HI_CfgCommand(struct drxk_state *state)
1132 mutex_lock(&state->mutex);
1134 status = write16(state, SIO_HI_RA_RAM_PAR_6__A, state->m_HICfgTimeout);
1137 status = write16(state, SIO_HI_RA_RAM_PAR_5__A, state->m_HICfgCtrl);
1140 status = write16(state, SIO_HI_RA_RAM_PAR_4__A, state->m_HICfgWakeUpKey);
1143 status = write16(state, SIO_HI_RA_RAM_PAR_3__A, state->m_HICfgBridgeDelay);
1146 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, state->m_HICfgTimingDiv);
1149 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
1152 status = HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0);
1156 state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1158 mutex_unlock(&state->mutex);
1160 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1164 static int InitHI(struct drxk_state *state)
1168 state->m_HICfgWakeUpKey = (state->demod_address << 1);
1169 state->m_HICfgTimeout = 0x96FF;
1170 /* port/bridge/power down ctrl */
1171 state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
1173 return HI_CfgCommand(state);
1176 static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)
1179 u16 sioPdrMclkCfg = 0;
1180 u16 sioPdrMdxCfg = 0;
1183 dprintk(1, ": mpeg %s, %s mode\n",
1184 mpegEnable ? "enable" : "disable",
1185 state->m_enableParallel ? "parallel" : "serial");
1187 /* stop lock indicator process */
1188 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1192 /* MPEG TS pad configuration */
1193 status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA);
1197 if (mpegEnable == false) {
1198 /* Set MPEG TS pads to inputmode */
1199 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
1202 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);
1205 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);
1208 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);
1211 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);
1214 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1217 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1220 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1223 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1226 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1229 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1232 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1236 /* Enable MPEG output */
1238 ((state->m_TSDataStrength <<
1239 SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003);
1240 sioPdrMclkCfg = ((state->m_TSClockkStrength <<
1241 SIO_PDR_MCLK_CFG_DRIVE__B) |
1244 status = write16(state, SIO_PDR_MSTRT_CFG__A, sioPdrMdxCfg);
1248 if (state->enable_merr_cfg)
1249 err_cfg = sioPdrMdxCfg;
1251 status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg);
1254 status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg);
1258 if (state->m_enableParallel == true) {
1259 /* paralel -> enable MD1 to MD7 */
1260 status = write16(state, SIO_PDR_MD1_CFG__A, sioPdrMdxCfg);
1263 status = write16(state, SIO_PDR_MD2_CFG__A, sioPdrMdxCfg);
1266 status = write16(state, SIO_PDR_MD3_CFG__A, sioPdrMdxCfg);
1269 status = write16(state, SIO_PDR_MD4_CFG__A, sioPdrMdxCfg);
1272 status = write16(state, SIO_PDR_MD5_CFG__A, sioPdrMdxCfg);
1275 status = write16(state, SIO_PDR_MD6_CFG__A, sioPdrMdxCfg);
1278 status = write16(state, SIO_PDR_MD7_CFG__A, sioPdrMdxCfg);
1282 sioPdrMdxCfg = ((state->m_TSDataStrength <<
1283 SIO_PDR_MD0_CFG_DRIVE__B)
1285 /* serial -> disable MD1 to MD7 */
1286 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1289 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1292 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1295 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1298 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1301 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1304 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1308 status = write16(state, SIO_PDR_MCLK_CFG__A, sioPdrMclkCfg);
1311 status = write16(state, SIO_PDR_MD0_CFG__A, sioPdrMdxCfg);
1315 /* Enable MB output over MPEG pads and ctl input */
1316 status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
1319 /* Write nomagic word to enable pdr reg write */
1320 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
1323 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1327 static int MPEGTSDisable(struct drxk_state *state)
1331 return MPEGTSConfigurePins(state, false);
1334 static int BLChainCmd(struct drxk_state *state,
1335 u16 romOffset, u16 nrOfElements, u32 timeOut)
1342 mutex_lock(&state->mutex);
1343 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1346 status = write16(state, SIO_BL_CHAIN_ADDR__A, romOffset);
1349 status = write16(state, SIO_BL_CHAIN_LEN__A, nrOfElements);
1352 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1356 end = jiffies + msecs_to_jiffies(timeOut);
1359 status = read16(state, SIO_BL_STATUS__A, &blStatus);
1362 } while ((blStatus == 0x1) &&
1363 ((time_is_after_jiffies(end))));
1365 if (blStatus == 0x1) {
1366 printk(KERN_ERR "drxk: SIO not ready\n");
1372 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1374 mutex_unlock(&state->mutex);
1379 static int DownloadMicrocode(struct drxk_state *state,
1380 const u8 pMCImage[], u32 Length)
1382 const u8 *pSrc = pMCImage;
1392 /* down the drain (we don't care about MAGIC_WORD) */
1394 /* For future reference */
1395 Drain = (pSrc[0] << 8) | pSrc[1];
1397 pSrc += sizeof(u16);
1398 offset += sizeof(u16);
1399 nBlocks = (pSrc[0] << 8) | pSrc[1];
1400 pSrc += sizeof(u16);
1401 offset += sizeof(u16);
1403 for (i = 0; i < nBlocks; i += 1) {
1404 Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
1405 (pSrc[2] << 8) | pSrc[3];
1406 pSrc += sizeof(u32);
1407 offset += sizeof(u32);
1409 BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
1410 pSrc += sizeof(u16);
1411 offset += sizeof(u16);
1414 /* For future reference */
1415 Flags = (pSrc[0] << 8) | pSrc[1];
1417 pSrc += sizeof(u16);
1418 offset += sizeof(u16);
1421 /* For future reference */
1422 BlockCRC = (pSrc[0] << 8) | pSrc[1];
1424 pSrc += sizeof(u16);
1425 offset += sizeof(u16);
1427 if (offset + BlockSize > Length) {
1428 printk(KERN_ERR "drxk: Firmware is corrupted.\n");
1432 status = write_block(state, Address, BlockSize, pSrc);
1434 printk(KERN_ERR "drxk: Error %d while loading firmware\n", status);
1438 offset += BlockSize;
1443 static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable)
1447 u16 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON;
1448 u16 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED;
1453 if (enable == false) {
1454 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF;
1455 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN;
1458 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1459 if (status >= 0 && data == desiredStatus) {
1460 /* tokenring already has correct status */
1463 /* Disable/enable dvbt tokenring bridge */
1464 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl);
1466 end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
1468 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1469 if ((status >= 0 && data == desiredStatus) || time_is_after_jiffies(end))
1473 if (data != desiredStatus) {
1474 printk(KERN_ERR "drxk: SIO not ready\n");
1480 static int MPEGTSStop(struct drxk_state *state)
1483 u16 fecOcSncMode = 0;
1484 u16 fecOcIprMode = 0;
1488 /* Gracefull shutdown (byte boundaries) */
1489 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1492 fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M;
1493 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1497 /* Suppress MCLK during absence of data */
1498 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcIprMode);
1501 fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M;
1502 status = write16(state, FEC_OC_IPR_MODE__A, fecOcIprMode);
1506 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1511 static int scu_command(struct drxk_state *state,
1512 u16 cmd, u8 parameterLen,
1513 u16 *parameter, u8 resultLen, u16 *result)
1515 #if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15
1516 #error DRXK register mapping no longer compatible with this routine!
1519 int status = -EINVAL;
1528 if ((cmd == 0) || ((parameterLen > 0) && (parameter == NULL)) ||
1529 ((resultLen > 0) && (result == NULL))) {
1530 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1534 mutex_lock(&state->mutex);
1536 /* assume that the command register is ready
1537 since it is checked afterwards */
1538 for (ii = parameterLen - 1; ii >= 0; ii -= 1) {
1539 buffer[cnt++] = (parameter[ii] & 0xFF);
1540 buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF);
1542 buffer[cnt++] = (cmd & 0xFF);
1543 buffer[cnt++] = ((cmd >> 8) & 0xFF);
1545 write_block(state, SCU_RAM_PARAM_0__A -
1546 (parameterLen - 1), cnt, buffer);
1547 /* Wait until SCU has processed command */
1548 end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
1551 status = read16(state, SCU_RAM_COMMAND__A, &curCmd);
1554 } while (!(curCmd == DRX_SCU_READY) && (time_is_after_jiffies(end)));
1555 if (curCmd != DRX_SCU_READY) {
1556 printk(KERN_ERR "drxk: SCU not ready\n");
1561 if ((resultLen > 0) && (result != NULL)) {
1565 for (ii = resultLen - 1; ii >= 0; ii -= 1) {
1566 status = read16(state, SCU_RAM_PARAM_0__A - ii, &result[ii]);
1571 /* Check if an error was reported by SCU */
1572 err = (s16)result[0];
1576 /* check for the known error codes */
1578 case SCU_RESULT_UNKCMD:
1579 p = "SCU_RESULT_UNKCMD";
1581 case SCU_RESULT_UNKSTD:
1582 p = "SCU_RESULT_UNKSTD";
1584 case SCU_RESULT_SIZE:
1585 p = "SCU_RESULT_SIZE";
1587 case SCU_RESULT_INVPAR:
1588 p = "SCU_RESULT_INVPAR";
1590 default: /* Other negative values are errors */
1591 sprintf(errname, "ERROR: %d\n", err);
1594 printk(KERN_ERR "drxk: %s while sending cmd 0x%04x with params:", p, cmd);
1595 print_hex_dump_bytes("drxk: ", DUMP_PREFIX_NONE, buffer, cnt);
1602 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1604 mutex_unlock(&state->mutex);
1608 static int SetIqmAf(struct drxk_state *state, bool active)
1616 status = read16(state, IQM_AF_STDBY__A, &data);
1621 data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY
1622 | IQM_AF_STDBY_STDBY_AMP_STANDBY
1623 | IQM_AF_STDBY_STDBY_PD_STANDBY
1624 | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
1625 | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY);
1627 data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY)
1628 & (~IQM_AF_STDBY_STDBY_AMP_STANDBY)
1629 & (~IQM_AF_STDBY_STDBY_PD_STANDBY)
1630 & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY)
1631 & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY)
1634 status = write16(state, IQM_AF_STDBY__A, data);
1638 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1642 static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode)
1645 u16 sioCcPwdMode = 0;
1649 /* Check arguments */
1655 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_NONE;
1657 case DRXK_POWER_DOWN_OFDM:
1658 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OFDM;
1660 case DRXK_POWER_DOWN_CORE:
1661 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
1663 case DRXK_POWER_DOWN_PLL:
1664 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_PLL;
1666 case DRX_POWER_DOWN:
1667 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OSC;
1670 /* Unknow sleep mode */
1674 /* If already in requested power mode, do nothing */
1675 if (state->m_currentPowerMode == *mode)
1678 /* For next steps make sure to start from DRX_POWER_UP mode */
1679 if (state->m_currentPowerMode != DRX_POWER_UP) {
1680 status = PowerUpDevice(state);
1683 status = DVBTEnableOFDMTokenRing(state, true);
1688 if (*mode == DRX_POWER_UP) {
1689 /* Restore analog & pin configuartion */
1691 /* Power down to requested mode */
1692 /* Backup some register settings */
1693 /* Set pins with possible pull-ups connected
1694 to them in input mode */
1695 /* Analog power down */
1696 /* ADC power down */
1697 /* Power down device */
1698 /* stop all comm_exec */
1699 /* Stop and power down previous standard */
1700 switch (state->m_OperationMode) {
1702 status = MPEGTSStop(state);
1705 status = PowerDownDVBT(state, false);
1711 status = MPEGTSStop(state);
1714 status = PowerDownQAM(state);
1721 status = DVBTEnableOFDMTokenRing(state, false);
1724 status = write16(state, SIO_CC_PWD_MODE__A, sioCcPwdMode);
1727 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
1731 if (*mode != DRXK_POWER_DOWN_OFDM) {
1732 state->m_HICfgCtrl |=
1733 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1734 status = HI_CfgCommand(state);
1739 state->m_currentPowerMode = *mode;
1743 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1748 static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode)
1750 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
1757 status = read16(state, SCU_COMM_EXEC__A, &data);
1760 if (data == SCU_COMM_EXEC_ACTIVE) {
1761 /* Send OFDM stop command */
1762 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
1765 /* Send OFDM reset command */
1766 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
1771 /* Reset datapath for OFDM, processors first */
1772 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1775 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1778 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
1783 status = SetIqmAf(state, false);
1787 /* powerdown to OFDM mode */
1789 status = CtrlPowerMode(state, &powerMode);
1795 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1799 static int SetOperationMode(struct drxk_state *state,
1800 enum OperationMode oMode)
1806 Stop and power down previous standard
1807 TODO investigate total power down instead of partial
1808 power down depending on "previous" standard.
1811 /* disable HW lock indicator */
1812 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1816 /* Device is already at the required mode */
1817 if (state->m_OperationMode == oMode)
1820 switch (state->m_OperationMode) {
1821 /* OM_NONE was added for start up */
1825 status = MPEGTSStop(state);
1828 status = PowerDownDVBT(state, true);
1831 state->m_OperationMode = OM_NONE;
1833 case OM_QAM_ITU_A: /* fallthrough */
1835 status = MPEGTSStop(state);
1838 status = PowerDownQAM(state);
1841 state->m_OperationMode = OM_NONE;
1850 Power up new standard
1854 dprintk(1, ": DVB-T\n");
1855 state->m_OperationMode = oMode;
1856 status = SetDVBTStandard(state, oMode);
1860 case OM_QAM_ITU_A: /* fallthrough */
1862 dprintk(1, ": DVB-C Annex %c\n",
1863 (state->m_OperationMode == OM_QAM_ITU_A) ? 'A' : 'C');
1864 state->m_OperationMode = oMode;
1865 status = SetQAMStandard(state, oMode);
1875 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1879 static int Start(struct drxk_state *state, s32 offsetFreq,
1880 s32 IntermediateFrequency)
1882 int status = -EINVAL;
1885 s32 OffsetkHz = offsetFreq / 1000;
1888 if (state->m_DrxkState != DRXK_STOPPED &&
1889 state->m_DrxkState != DRXK_DTV_STARTED)
1892 state->m_bMirrorFreqSpect = (state->props.inversion == INVERSION_ON);
1894 if (IntermediateFrequency < 0) {
1895 state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect;
1896 IntermediateFrequency = -IntermediateFrequency;
1899 switch (state->m_OperationMode) {
1902 IFreqkHz = (IntermediateFrequency / 1000);
1903 status = SetQAM(state, IFreqkHz, OffsetkHz);
1906 state->m_DrxkState = DRXK_DTV_STARTED;
1909 IFreqkHz = (IntermediateFrequency / 1000);
1910 status = MPEGTSStop(state);
1913 status = SetDVBT(state, IFreqkHz, OffsetkHz);
1916 status = DVBTStart(state);
1919 state->m_DrxkState = DRXK_DTV_STARTED;
1926 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1930 static int ShutDown(struct drxk_state *state)
1938 static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus,
1941 int status = -EINVAL;
1945 if (pLockStatus == NULL)
1948 *pLockStatus = NOT_LOCKED;
1950 /* define the SCU command code */
1951 switch (state->m_OperationMode) {
1955 status = GetQAMLockStatus(state, pLockStatus);
1958 status = GetDVBTLockStatus(state, pLockStatus);
1965 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1969 static int MPEGTSStart(struct drxk_state *state)
1973 u16 fecOcSncMode = 0;
1975 /* Allow OC to sync again */
1976 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1979 fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M;
1980 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1983 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
1986 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1990 static int MPEGTSDtoInit(struct drxk_state *state)
1996 /* Rate integration settings */
1997 status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
2000 status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
2003 status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);
2006 status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);
2009 status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);
2012 status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
2015 status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
2018 status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);
2022 /* Additional configuration */
2023 status = write16(state, FEC_OC_OCR_INVERT__A, 0);
2026 status = write16(state, FEC_OC_SNC_LWM__A, 2);
2029 status = write16(state, FEC_OC_SNC_HWM__A, 12);
2032 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2037 static int MPEGTSDtoSetup(struct drxk_state *state,
2038 enum OperationMode oMode)
2042 u16 fecOcRegMode = 0; /* FEC_OC_MODE register value */
2043 u16 fecOcRegIprMode = 0; /* FEC_OC_IPR_MODE register value */
2044 u16 fecOcDtoMode = 0; /* FEC_OC_IPR_INVERT register value */
2045 u16 fecOcFctMode = 0; /* FEC_OC_IPR_INVERT register value */
2046 u16 fecOcDtoPeriod = 2; /* FEC_OC_IPR_INVERT register value */
2047 u16 fecOcDtoBurstLen = 188; /* FEC_OC_IPR_INVERT register value */
2048 u32 fecOcRcnCtlRate = 0; /* FEC_OC_IPR_INVERT register value */
2049 u16 fecOcTmdMode = 0;
2050 u16 fecOcTmdIntUpdRate = 0;
2052 bool staticCLK = false;
2056 /* Check insertion of the Reed-Solomon parity bytes */
2057 status = read16(state, FEC_OC_MODE__A, &fecOcRegMode);
2060 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcRegIprMode);
2063 fecOcRegMode &= (~FEC_OC_MODE_PARITY__M);
2064 fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
2065 if (state->m_insertRSByte == true) {
2066 /* enable parity symbol forward */
2067 fecOcRegMode |= FEC_OC_MODE_PARITY__M;
2068 /* MVAL disable during parity bytes */
2069 fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
2070 /* TS burst length to 204 */
2071 fecOcDtoBurstLen = 204;
2074 /* Check serial or parrallel output */
2075 fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
2076 if (state->m_enableParallel == false) {
2077 /* MPEG data output is serial -> set ipr_mode[0] */
2078 fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M;
2083 maxBitRate = state->m_DVBTBitrate;
2085 fecOcRcnCtlRate = 0xC00000;
2086 staticCLK = state->m_DVBTStaticCLK;
2088 case OM_QAM_ITU_A: /* fallthrough */
2090 fecOcTmdMode = 0x0004;
2091 fecOcRcnCtlRate = 0xD2B4EE; /* good for >63 Mb/s */
2092 maxBitRate = state->m_DVBCBitrate;
2093 staticCLK = state->m_DVBCStaticCLK;
2097 } /* switch (standard) */
2101 /* Configure DTO's */
2105 /* Rational DTO for MCLK source (static MCLK rate),
2106 Dynamic DTO for optimal grouping
2107 (avoid intra-packet gaps),
2108 DTO offset enable to sync TS burst with MSTRT */
2109 fecOcDtoMode = (FEC_OC_DTO_MODE_DYNAMIC__M |
2110 FEC_OC_DTO_MODE_OFFSET_ENABLE__M);
2111 fecOcFctMode = (FEC_OC_FCT_MODE_RAT_ENA__M |
2112 FEC_OC_FCT_MODE_VIRT_ENA__M);
2114 /* Check user defined bitrate */
2115 bitRate = maxBitRate;
2116 if (bitRate > 75900000UL) { /* max is 75.9 Mb/s */
2117 bitRate = 75900000UL;
2119 /* Rational DTO period:
2120 dto_period = (Fsys / bitrate) - 2
2122 Result should be floored,
2123 to make sure >= requested bitrate
2125 fecOcDtoPeriod = (u16) (((state->m_sysClockFreq)
2127 if (fecOcDtoPeriod <= 2)
2130 fecOcDtoPeriod -= 2;
2131 fecOcTmdIntUpdRate = 8;
2133 /* (commonAttr->staticCLK == false) => dynamic mode */
2134 fecOcDtoMode = FEC_OC_DTO_MODE_DYNAMIC__M;
2135 fecOcFctMode = FEC_OC_FCT_MODE__PRE;
2136 fecOcTmdIntUpdRate = 5;
2139 /* Write appropriate registers with requested configuration */
2140 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fecOcDtoBurstLen);
2143 status = write16(state, FEC_OC_DTO_PERIOD__A, fecOcDtoPeriod);
2146 status = write16(state, FEC_OC_DTO_MODE__A, fecOcDtoMode);
2149 status = write16(state, FEC_OC_FCT_MODE__A, fecOcFctMode);
2152 status = write16(state, FEC_OC_MODE__A, fecOcRegMode);
2155 status = write16(state, FEC_OC_IPR_MODE__A, fecOcRegIprMode);
2159 /* Rate integration settings */
2160 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fecOcRcnCtlRate);
2163 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, fecOcTmdIntUpdRate);
2166 status = write16(state, FEC_OC_TMD_MODE__A, fecOcTmdMode);
2169 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2173 static int MPEGTSConfigurePolarity(struct drxk_state *state)
2175 u16 fecOcRegIprInvert = 0;
2177 /* Data mask for the output data byte */
2178 u16 InvertDataMask =
2179 FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
2180 FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
2181 FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
2182 FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
2186 /* Control selective inversion of output bits */
2187 fecOcRegIprInvert &= (~(InvertDataMask));
2188 if (state->m_invertDATA == true)
2189 fecOcRegIprInvert |= InvertDataMask;
2190 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M));
2191 if (state->m_invertERR == true)
2192 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M;
2193 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
2194 if (state->m_invertSTR == true)
2195 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M;
2196 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
2197 if (state->m_invertVAL == true)
2198 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M;
2199 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
2200 if (state->m_invertCLK == true)
2201 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M;
2203 return write16(state, FEC_OC_IPR_INVERT__A, fecOcRegIprInvert);
2206 #define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000
2208 static int SetAgcRf(struct drxk_state *state,
2209 struct SCfgAgc *pAgcCfg, bool isDTV)
2211 int status = -EINVAL;
2213 struct SCfgAgc *pIfAgcSettings;
2217 if (pAgcCfg == NULL)
2220 switch (pAgcCfg->ctrlMode) {
2221 case DRXK_AGC_CTRL_AUTO:
2222 /* Enable RF AGC DAC */
2223 status = read16(state, IQM_AF_STDBY__A, &data);
2226 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2227 status = write16(state, IQM_AF_STDBY__A, data);
2230 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2234 /* Enable SCU RF AGC loop */
2235 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2238 if (state->m_RfAgcPol)
2239 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2241 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2242 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2246 /* Set speed (using complementary reduction value) */
2247 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2251 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
2252 data |= (~(pAgcCfg->speed <<
2253 SCU_RAM_AGC_KI_RED_RAGC_RED__B)
2254 & SCU_RAM_AGC_KI_RED_RAGC_RED__M);
2256 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2261 pIfAgcSettings = &state->m_dvbtIfAgcCfg;
2262 else if (IsQAM(state))
2263 pIfAgcSettings = &state->m_qamIfAgcCfg;
2265 pIfAgcSettings = &state->m_atvIfAgcCfg;
2266 if (pIfAgcSettings == NULL) {
2271 /* Set TOP, only if IF-AGC is in AUTO mode */
2272 if (pIfAgcSettings->ctrlMode == DRXK_AGC_CTRL_AUTO)
2273 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->top);
2277 /* Cut-Off current */
2278 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, pAgcCfg->cutOffCurrent);
2282 /* Max. output level */
2283 status = write16(state, SCU_RAM_AGC_RF_MAX__A, pAgcCfg->maxOutputLevel);
2289 case DRXK_AGC_CTRL_USER:
2290 /* Enable RF AGC DAC */
2291 status = read16(state, IQM_AF_STDBY__A, &data);
2294 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2295 status = write16(state, IQM_AF_STDBY__A, data);
2299 /* Disable SCU RF AGC loop */
2300 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2303 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2304 if (state->m_RfAgcPol)
2305 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2307 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2308 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2312 /* SCU c.o.c. to 0, enabling full control range */
2313 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
2317 /* Write value to output pin */
2318 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, pAgcCfg->outputLevel);
2323 case DRXK_AGC_CTRL_OFF:
2324 /* Disable RF AGC DAC */
2325 status = read16(state, IQM_AF_STDBY__A, &data);
2328 data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2329 status = write16(state, IQM_AF_STDBY__A, data);
2333 /* Disable SCU RF AGC loop */
2334 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2337 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2338 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2349 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2353 #define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000
2355 static int SetAgcIf(struct drxk_state *state,
2356 struct SCfgAgc *pAgcCfg, bool isDTV)
2360 struct SCfgAgc *pRfAgcSettings;
2364 switch (pAgcCfg->ctrlMode) {
2365 case DRXK_AGC_CTRL_AUTO:
2367 /* Enable IF AGC DAC */
2368 status = read16(state, IQM_AF_STDBY__A, &data);
2371 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2372 status = write16(state, IQM_AF_STDBY__A, data);
2376 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2380 /* Enable SCU IF AGC loop */
2381 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2384 if (state->m_IfAgcPol)
2385 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2387 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2388 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2392 /* Set speed (using complementary reduction value) */
2393 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2396 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
2397 data |= (~(pAgcCfg->speed <<
2398 SCU_RAM_AGC_KI_RED_IAGC_RED__B)
2399 & SCU_RAM_AGC_KI_RED_IAGC_RED__M);
2401 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2406 pRfAgcSettings = &state->m_qamRfAgcCfg;
2408 pRfAgcSettings = &state->m_atvRfAgcCfg;
2409 if (pRfAgcSettings == NULL)
2412 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pRfAgcSettings->top);
2417 case DRXK_AGC_CTRL_USER:
2419 /* Enable IF AGC DAC */
2420 status = read16(state, IQM_AF_STDBY__A, &data);
2423 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2424 status = write16(state, IQM_AF_STDBY__A, data);
2428 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2432 /* Disable SCU IF AGC loop */
2433 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2436 if (state->m_IfAgcPol)
2437 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2439 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2440 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2444 /* Write value to output pin */
2445 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->outputLevel);
2450 case DRXK_AGC_CTRL_OFF:
2452 /* Disable If AGC DAC */
2453 status = read16(state, IQM_AF_STDBY__A, &data);
2456 data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2457 status = write16(state, IQM_AF_STDBY__A, data);
2461 /* Disable SCU IF AGC loop */
2462 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2465 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2466 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2470 } /* switch (agcSettingsIf->ctrlMode) */
2472 /* always set the top to support
2473 configurations without if-loop */
2474 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, pAgcCfg->top);
2477 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2481 static int ReadIFAgc(struct drxk_state *state, u32 *pValue)
2489 status = read16(state, IQM_AF_AGC_IF__A, &agcDacLvl);
2491 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2497 if (agcDacLvl > DRXK_AGC_DAC_OFFSET)
2498 Level = agcDacLvl - DRXK_AGC_DAC_OFFSET;
2500 *pValue = (14000 - Level) / 4;
2507 static int GetQAMSignalToNoise(struct drxk_state *state,
2508 s32 *pSignalToNoise)
2511 u16 qamSlErrPower = 0; /* accum. error between
2512 raw and sliced symbols */
2513 u32 qamSlSigPower = 0; /* used for MER, depends of
2515 u32 qamSlMer = 0; /* QAM MER */
2519 /* MER calculation */
2521 /* get the register value needed for MER */
2522 status = read16(state, QAM_SL_ERR_POWER__A, &qamSlErrPower);
2524 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2528 switch (state->props.modulation) {
2530 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2;
2533 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM32 << 2;
2536 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM64 << 2;
2539 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM128 << 2;
2543 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM256 << 2;
2547 if (qamSlErrPower > 0) {
2548 qamSlMer = Log10Times100(qamSlSigPower) -
2549 Log10Times100((u32) qamSlErrPower);
2551 *pSignalToNoise = qamSlMer;
2556 static int GetDVBTSignalToNoise(struct drxk_state *state,
2557 s32 *pSignalToNoise)
2561 u32 EqRegTdSqrErrI = 0;
2562 u32 EqRegTdSqrErrQ = 0;
2563 u16 EqRegTdSqrErrExp = 0;
2564 u16 EqRegTdTpsPwrOfs = 0;
2565 u16 EqRegTdReqSmbCnt = 0;
2572 u16 transmissionParams = 0;
2576 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &EqRegTdTpsPwrOfs);
2579 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, &EqRegTdReqSmbCnt);
2582 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, &EqRegTdSqrErrExp);
2585 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, ®Data);
2588 /* Extend SQR_ERR_I operational range */
2589 EqRegTdSqrErrI = (u32) regData;
2590 if ((EqRegTdSqrErrExp > 11) &&
2591 (EqRegTdSqrErrI < 0x00000FFFUL)) {
2592 EqRegTdSqrErrI += 0x00010000UL;
2594 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, ®Data);
2597 /* Extend SQR_ERR_Q operational range */
2598 EqRegTdSqrErrQ = (u32) regData;
2599 if ((EqRegTdSqrErrExp > 11) &&
2600 (EqRegTdSqrErrQ < 0x00000FFFUL))
2601 EqRegTdSqrErrQ += 0x00010000UL;
2603 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, &transmissionParams);
2607 /* Check input data for MER */
2609 /* MER calculation (in 0.1 dB) without math.h */
2610 if ((EqRegTdTpsPwrOfs == 0) || (EqRegTdReqSmbCnt == 0))
2612 else if ((EqRegTdSqrErrI + EqRegTdSqrErrQ) == 0) {
2613 /* No error at all, this must be the HW reset value
2614 * Apparently no first measurement yet
2618 SqrErrIQ = (EqRegTdSqrErrI + EqRegTdSqrErrQ) <<
2620 if ((transmissionParams &
2621 OFDM_SC_RA_RAM_OP_PARAM_MODE__M)
2622 == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K)
2627 /* IMER = 100 * log10 (x)
2628 where x = (EqRegTdTpsPwrOfs^2 *
2629 EqRegTdReqSmbCnt * tpsCnt)/SqrErrIQ
2632 where a = 100 * log10 (EqRegTdTpsPwrOfs^2)
2633 b = 100 * log10 (EqRegTdReqSmbCnt * tpsCnt)
2634 c = 100 * log10 (SqrErrIQ)
2637 /* log(x) x = 9bits * 9bits->18 bits */
2638 a = Log10Times100(EqRegTdTpsPwrOfs *
2640 /* log(x) x = 16bits * 7bits->23 bits */
2641 b = Log10Times100(EqRegTdReqSmbCnt * tpsCnt);
2642 /* log(x) x = (16bits + 16bits) << 15 ->32 bits */
2643 c = Log10Times100(SqrErrIQ);
2646 /* No negative MER, clip to zero */
2652 *pSignalToNoise = iMER;
2656 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2660 static int GetSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise)
2664 *pSignalToNoise = 0;
2665 switch (state->m_OperationMode) {
2667 return GetDVBTSignalToNoise(state, pSignalToNoise);
2670 return GetQAMSignalToNoise(state, pSignalToNoise);
2678 static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality)
2680 /* SNR Values for quasi errorfree reception rom Nordig 2.2 */
2685 static s32 QE_SN[] = {
2691 108, /* 16-QAM 1/2 */
2692 131, /* 16-QAM 2/3 */
2693 146, /* 16-QAM 3/4 */
2694 156, /* 16-QAM 5/6 */
2695 160, /* 16-QAM 7/8 */
2696 165, /* 64-QAM 1/2 */
2697 187, /* 64-QAM 2/3 */
2698 202, /* 64-QAM 3/4 */
2699 216, /* 64-QAM 5/6 */
2700 225, /* 64-QAM 7/8 */
2706 s32 SignalToNoise = 0;
2707 u16 Constellation = 0;
2709 u32 SignalToNoiseRel;
2712 status = GetDVBTSignalToNoise(state, &SignalToNoise);
2715 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A, &Constellation);
2718 Constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M;
2720 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, &CodeRate);
2723 CodeRate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M;
2725 if (Constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM ||
2726 CodeRate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8)
2728 SignalToNoiseRel = SignalToNoise -
2729 QE_SN[Constellation * 5 + CodeRate];
2732 if (SignalToNoiseRel < -70)
2734 else if (SignalToNoiseRel < 30)
2735 *pQuality = ((SignalToNoiseRel + 70) *
2738 *pQuality = BERQuality;
2743 static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality)
2751 u32 SignalToNoise = 0;
2752 u32 BERQuality = 100;
2753 u32 SignalToNoiseRel = 0;
2755 status = GetQAMSignalToNoise(state, &SignalToNoise);
2759 switch (state->props.modulation) {
2761 SignalToNoiseRel = SignalToNoise - 200;
2764 SignalToNoiseRel = SignalToNoise - 230;
2765 break; /* Not in NorDig */
2767 SignalToNoiseRel = SignalToNoise - 260;
2770 SignalToNoiseRel = SignalToNoise - 290;
2774 SignalToNoiseRel = SignalToNoise - 320;
2778 if (SignalToNoiseRel < -70)
2780 else if (SignalToNoiseRel < 30)
2781 *pQuality = ((SignalToNoiseRel + 70) *
2784 *pQuality = BERQuality;
2790 static int GetQuality(struct drxk_state *state, s32 *pQuality)
2794 switch (state->m_OperationMode) {
2796 return GetDVBTQuality(state, pQuality);
2798 return GetDVBCQuality(state, pQuality);
2807 /* Free data ram in SIO HI */
2808 #define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
2809 #define SIO_HI_RA_RAM_USR_END__A 0x420060
2811 #define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
2812 #define DRXK_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
2813 #define DRXK_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
2814 #define DRXK_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
2816 #define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr) >> 22) & 0x3F)
2817 #define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F)
2818 #define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF)
2820 static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge)
2822 int status = -EINVAL;
2826 if (state->m_DrxkState == DRXK_UNINITIALIZED)
2828 if (state->m_DrxkState == DRXK_POWERED_DOWN)
2831 if (state->no_i2c_bridge)
2834 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
2837 if (bEnableBridge) {
2838 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
2842 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
2847 status = HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, 0);
2851 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2855 static int SetPreSaw(struct drxk_state *state,
2856 struct SCfgPreSaw *pPreSawCfg)
2858 int status = -EINVAL;
2862 if ((pPreSawCfg == NULL)
2863 || (pPreSawCfg->reference > IQM_AF_PDREF__M))
2866 status = write16(state, IQM_AF_PDREF__A, pPreSawCfg->reference);
2869 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2873 static int BLDirectCmd(struct drxk_state *state, u32 targetAddr,
2874 u16 romOffset, u16 nrOfElements, u32 timeOut)
2877 u16 offset = (u16) ((targetAddr >> 0) & 0x00FFFF);
2878 u16 blockbank = (u16) ((targetAddr >> 16) & 0x000FFF);
2884 mutex_lock(&state->mutex);
2885 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
2888 status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
2891 status = write16(state, SIO_BL_TGT_ADDR__A, offset);
2894 status = write16(state, SIO_BL_SRC_ADDR__A, romOffset);
2897 status = write16(state, SIO_BL_SRC_LEN__A, nrOfElements);
2900 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2904 end = jiffies + msecs_to_jiffies(timeOut);
2906 status = read16(state, SIO_BL_STATUS__A, &blStatus);
2909 } while ((blStatus == 0x1) && time_is_after_jiffies(end));
2910 if (blStatus == 0x1) {
2911 printk(KERN_ERR "drxk: SIO not ready\n");
2917 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2919 mutex_unlock(&state->mutex);
2924 static int ADCSyncMeasurement(struct drxk_state *state, u16 *count)
2931 /* Start measurement */
2932 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2935 status = write16(state, IQM_AF_START_LOCK__A, 1);
2940 status = read16(state, IQM_AF_PHASE0__A, &data);
2944 *count = *count + 1;
2945 status = read16(state, IQM_AF_PHASE1__A, &data);
2949 *count = *count + 1;
2950 status = read16(state, IQM_AF_PHASE2__A, &data);
2954 *count = *count + 1;
2958 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2962 static int ADCSynchronization(struct drxk_state *state)
2969 status = ADCSyncMeasurement(state, &count);
2974 /* Try sampling on a diffrent edge */
2977 status = read16(state, IQM_AF_CLKNEG__A, &clkNeg);
2980 if ((clkNeg | IQM_AF_CLKNEG_CLKNEGDATA__M) ==
2981 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) {
2982 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2984 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG;
2986 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2988 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS;
2990 status = write16(state, IQM_AF_CLKNEG__A, clkNeg);
2993 status = ADCSyncMeasurement(state, &count);
3002 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3006 static int SetFrequencyShifter(struct drxk_state *state,
3007 u16 intermediateFreqkHz,
3008 s32 tunerFreqOffset, bool isDTV)
3010 bool selectPosImage = false;
3011 u32 rfFreqResidual = tunerFreqOffset;
3012 u32 fmFrequencyShift = 0;
3013 bool tunerMirror = !state->m_bMirrorFreqSpect;
3018 u32 samplingFrequency = (u32) (state->m_sysClockFreq / 3);
3025 Program frequency shifter
3026 No need to account for mirroring on RF
3029 if ((state->m_OperationMode == OM_QAM_ITU_A) ||
3030 (state->m_OperationMode == OM_QAM_ITU_C) ||
3031 (state->m_OperationMode == OM_DVBT))
3032 selectPosImage = true;
3034 selectPosImage = false;
3037 /* tuner doesn't mirror */
3038 ifFreqActual = intermediateFreqkHz +
3039 rfFreqResidual + fmFrequencyShift;
3042 ifFreqActual = intermediateFreqkHz -
3043 rfFreqResidual - fmFrequencyShift;
3044 if (ifFreqActual > samplingFrequency / 2) {
3046 adcFreq = samplingFrequency - ifFreqActual;
3049 /* adc doesn't mirror */
3050 adcFreq = ifFreqActual;
3054 frequencyShift = adcFreq;
3055 imageToSelect = state->m_rfmirror ^ tunerMirror ^
3056 adcFlip ^ selectPosImage;
3057 state->m_IqmFsRateOfs =
3058 Frac28a((frequencyShift), samplingFrequency);
3061 state->m_IqmFsRateOfs = ~state->m_IqmFsRateOfs + 1;
3063 /* Program frequency shifter with tuner offset compensation */
3064 /* frequencyShift += tunerFreqOffset; TODO */
3065 status = write32(state, IQM_FS_RATE_OFS_LO__A,
3066 state->m_IqmFsRateOfs);
3068 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3072 static int InitAGC(struct drxk_state *state, bool isDTV)
3075 u16 ingainTgtMin = 0;
3076 u16 ingainTgtMax = 0;
3084 u16 kiInnergainMin = 0;
3085 u16 ifIaccuHiTgt = 0;
3086 u16 ifIaccuHiTgtMin = 0;
3087 u16 ifIaccuHiTgtMax = 0;
3089 u16 fastClpCtrlDelay = 0;
3090 u16 clpCtrlMode = 0;
3095 /* Common settings */
3097 ifIaccuHiTgtMin = 2047;
3101 /* AGCInit() not available for DVBT; init done in microcode */
3102 if (!IsQAM(state)) {
3103 printk(KERN_ERR "drxk: %s: mode %d is not DVB-C\n", __func__, state->m_OperationMode);
3107 /* FIXME: Analog TV AGC require different settings */
3109 /* Standard specific settings */
3111 clpDirTo = (u16) -9;
3114 snsDirTo = (u16) -9;
3115 kiInnergainMin = (u16) -1030;
3116 ifIaccuHiTgtMax = 0x2380;
3117 ifIaccuHiTgt = 0x2380;
3118 ingainTgtMin = 0x0511;
3120 ingainTgtMax = 5119;
3121 fastClpCtrlDelay = state->m_qamIfAgcCfg.FastClipCtrlDelay;
3123 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, fastClpCtrlDelay);
3127 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clpCtrlMode);
3130 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingainTgt);
3133 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingainTgtMin);
3136 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingainTgtMax);
3139 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, ifIaccuHiTgtMin);
3142 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, ifIaccuHiTgtMax);
3145 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
3148 status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);
3151 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);
3154 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
3157 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clpSumMax);
3160 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, snsSumMax);
3164 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, kiInnergainMin);
3167 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, ifIaccuHiTgt);
3170 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clpCyclen);
3174 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);
3177 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);
3180 status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);
3184 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
3187 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clpSumMin);
3190 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, snsSumMin);
3193 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clpDirTo);
3196 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, snsDirTo);
3199 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
3202 status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);
3205 status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);
3208 status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);
3211 status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);
3214 status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);
3217 status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);
3220 status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);
3223 status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);
3226 status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);
3229 status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);
3232 status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);
3235 status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);
3238 status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);
3242 /* Initialize inner-loop KI gain factors */
3243 status = read16(state, SCU_RAM_AGC_KI__A, &data);
3248 data &= ~SCU_RAM_AGC_KI_RF__M;
3249 data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B);
3250 data &= ~SCU_RAM_AGC_KI_IF__M;
3251 data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B);
3253 status = write16(state, SCU_RAM_AGC_KI__A, data);
3256 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3260 static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 *packetErr)
3265 if (packetErr == NULL)
3266 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
3268 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, packetErr);
3270 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3274 static int DVBTScCommand(struct drxk_state *state,
3275 u16 cmd, u16 subcmd,
3276 u16 param0, u16 param1, u16 param2,
3277 u16 param3, u16 param4)
3286 status = read16(state, OFDM_SC_COMM_EXEC__A, &scExec);
3288 /* SC is not running */
3294 /* Wait until sc is ready to receive command */
3298 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
3300 } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
3301 if (retryCnt >= DRXK_MAX_RETRIES && (status < 0))
3304 /* Write sub-command */
3306 /* All commands using sub-cmd */
3307 case OFDM_SC_RA_RAM_CMD_PROC_START:
3308 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3309 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3310 status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
3319 /* Write needed parameters and the command */
3321 /* All commands using 5 parameters */
3322 /* All commands using 4 parameters */
3323 /* All commands using 3 parameters */
3324 /* All commands using 2 parameters */
3325 case OFDM_SC_RA_RAM_CMD_PROC_START:
3326 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3327 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3328 status = write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
3329 /* All commands using 1 parameters */
3330 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3331 case OFDM_SC_RA_RAM_CMD_USER_IO:
3332 status = write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
3333 /* All commands using 0 parameters */
3334 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3335 case OFDM_SC_RA_RAM_CMD_NULL:
3337 status = write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);
3340 /* Unknown command */
3346 /* Wait until sc is ready processing command */
3350 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
3352 } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
3353 if (retryCnt >= DRXK_MAX_RETRIES && (status < 0))
3356 /* Check for illegal cmd */
3357 status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &errCode);
3358 if (errCode == 0xFFFF) {
3359 /* illegal command */
3365 /* Retreive results parameters from SC */
3367 /* All commands yielding 5 results */
3368 /* All commands yielding 4 results */
3369 /* All commands yielding 3 results */
3370 /* All commands yielding 2 results */
3371 /* All commands yielding 1 result */
3372 case OFDM_SC_RA_RAM_CMD_USER_IO:
3373 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3374 status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
3375 /* All commands yielding 0 results */
3376 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3377 case OFDM_SC_RA_RAM_CMD_SET_TIMER:
3378 case OFDM_SC_RA_RAM_CMD_PROC_START:
3379 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3380 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3381 case OFDM_SC_RA_RAM_CMD_NULL:
3384 /* Unknown command */
3387 } /* switch (cmd->cmd) */
3390 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3394 static int PowerUpDVBT(struct drxk_state *state)
3396 enum DRXPowerMode powerMode = DRX_POWER_UP;
3400 status = CtrlPowerMode(state, &powerMode);
3402 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3406 static int DVBTCtrlSetIncEnable(struct drxk_state *state, bool *enabled)
3411 if (*enabled == true)
3412 status = write16(state, IQM_CF_BYPASSDET__A, 0);
3414 status = write16(state, IQM_CF_BYPASSDET__A, 1);
3416 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3420 #define DEFAULT_FR_THRES_8K 4000
3421 static int DVBTCtrlSetFrEnable(struct drxk_state *state, bool *enabled)
3427 if (*enabled == true) {
3428 /* write mask to 1 */
3429 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
3430 DEFAULT_FR_THRES_8K);
3432 /* write mask to 0 */
3433 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
3436 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3441 static int DVBTCtrlSetEchoThreshold(struct drxk_state *state,
3442 struct DRXKCfgDvbtEchoThres_t *echoThres)
3448 status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);
3452 switch (echoThres->fftMode) {
3453 case DRX_FFTMODE_2K:
3454 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M;
3455 data |= ((echoThres->threshold <<
3456 OFDM_SC_RA_RAM_ECHO_THRES_2K__B)
3457 & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M));
3459 case DRX_FFTMODE_8K:
3460 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M;
3461 data |= ((echoThres->threshold <<
3462 OFDM_SC_RA_RAM_ECHO_THRES_8K__B)
3463 & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M));
3469 status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
3472 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3476 static int DVBTCtrlSetSqiSpeed(struct drxk_state *state,
3477 enum DRXKCfgDvbtSqiSpeed *speed)
3479 int status = -EINVAL;
3484 case DRXK_DVBT_SQI_SPEED_FAST:
3485 case DRXK_DVBT_SQI_SPEED_MEDIUM:
3486 case DRXK_DVBT_SQI_SPEED_SLOW:
3491 status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
3495 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3499 /*============================================================================*/
3502 * \brief Activate DVBT specific presets
3503 * \param demod instance of demodulator.
3504 * \return DRXStatus_t.
3506 * Called in DVBTSetStandard
3509 static int DVBTActivatePresets(struct drxk_state *state)
3512 bool setincenable = false;
3513 bool setfrenable = true;
3515 struct DRXKCfgDvbtEchoThres_t echoThres2k = { 0, DRX_FFTMODE_2K };
3516 struct DRXKCfgDvbtEchoThres_t echoThres8k = { 0, DRX_FFTMODE_8K };
3519 status = DVBTCtrlSetIncEnable(state, &setincenable);
3522 status = DVBTCtrlSetFrEnable(state, &setfrenable);
3525 status = DVBTCtrlSetEchoThreshold(state, &echoThres2k);
3528 status = DVBTCtrlSetEchoThreshold(state, &echoThres8k);
3531 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, state->m_dvbtIfAgcCfg.IngainTgtMax);
3534 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3538 /*============================================================================*/
3541 * \brief Initialize channelswitch-independent settings for DVBT.
3542 * \param demod instance of demodulator.
3543 * \return DRXStatus_t.
3545 * For ROM code channel filter taps are loaded from the bootloader. For microcode
3546 * the DVB-T taps from the drxk_filters.h are used.
3548 static int SetDVBTStandard(struct drxk_state *state,
3549 enum OperationMode oMode)
3558 /* added antenna switch */
3559 SwitchAntennaToDVBT(state);
3560 /* send OFDM reset command */
3561 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
3565 /* send OFDM setenv command */
3566 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 0, NULL, 1, &cmdResult);
3570 /* reset datapath for OFDM, processors first */
3571 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3574 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3577 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
3582 /* synchronize on ofdstate->m_festart */
3583 status = write16(state, IQM_AF_UPD_SEL__A, 1);
3586 /* window size for clipping ADC detection */
3587 status = write16(state, IQM_AF_CLP_LEN__A, 0);
3590 /* window size for for sense pre-SAW detection */
3591 status = write16(state, IQM_AF_SNS_LEN__A, 0);
3594 /* sense threshold for sense pre-SAW detection */
3595 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
3598 status = SetIqmAf(state, true);
3602 status = write16(state, IQM_AF_AGC_RF__A, 0);
3606 /* Impulse noise cruncher setup */
3607 status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */
3610 status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */
3613 status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */
3617 status = write16(state, IQM_RC_STRETCH__A, 16);
3620 status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */
3623 status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */
3626 status = write16(state, IQM_CF_SCALE__A, 1600);
3629 status = write16(state, IQM_CF_SCALE_SH__A, 0);
3633 /* virtual clipping threshold for clipping ADC detection */
3634 status = write16(state, IQM_AF_CLP_TH__A, 448);
3637 status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */
3641 status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
3645 status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */
3648 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);
3651 /* enable power measurement interrupt */
3652 status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);
3655 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
3659 /* IQM will not be reset from here, sync ADC and update/init AGC */
3660 status = ADCSynchronization(state);
3663 status = SetPreSaw(state, &state->m_dvbtPreSawCfg);
3667 /* Halt SCU to enable safe non-atomic accesses */
3668 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3672 status = SetAgcRf(state, &state->m_dvbtRfAgcCfg, true);
3675 status = SetAgcIf(state, &state->m_dvbtIfAgcCfg, true);
3679 /* Set Noise Estimation notch width and enable DC fix */
3680 status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);
3683 data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M;
3684 status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);
3688 /* Activate SCU to enable SCU commands */
3689 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3693 if (!state->m_DRXK_A3_ROM_CODE) {
3694 /* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay */
3695 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, state->m_dvbtIfAgcCfg.FastClipCtrlDelay);
3701 #ifdef COMPILE_FOR_NONRT
3702 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
3705 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
3711 status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */
3716 #ifdef COMPILE_FOR_NONRT
3717 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
3721 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);
3725 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);
3729 /* Setup MPEG bus */
3730 status = MPEGTSDtoSetup(state, OM_DVBT);
3733 /* Set DVBT Presets */
3734 status = DVBTActivatePresets(state);
3740 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3744 /*============================================================================*/
3746 * \brief Start dvbt demodulating for channel.
3747 * \param demod instance of demodulator.
3748 * \return DRXStatus_t.
3750 static int DVBTStart(struct drxk_state *state)
3754 /* DRXKOfdmScCmd_t scCmd; */
3757 /* Start correct processes to get in lock */
3758 /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */
3759 param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;
3760 status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1, 0, 0, 0);
3764 status = MPEGTSStart(state);
3767 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
3772 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3777 /*============================================================================*/
3780 * \brief Set up dvbt demodulator for channel.
3781 * \param demod instance of demodulator.
3782 * \return DRXStatus_t.
3783 * // original DVBTSetChannel()
3785 static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3786 s32 tunerFreqOffset)
3789 u16 transmissionParams = 0;
3790 u16 operationMode = 0;
3791 u32 iqmRcRateOfs = 0;
3796 dprintk(1, "IF =%d, TFO = %d\n", IntermediateFreqkHz, tunerFreqOffset);
3798 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
3802 /* Halt SCU to enable safe non-atomic accesses */
3803 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3807 /* Stop processors */
3808 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3811 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3815 /* Mandatory fix, always stop CP, required to set spl offset back to
3816 hardware default (is set to 0 by ucode during pilot detection */
3817 status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
3821 /*== Write channel settings to device =====================================*/
3824 switch (state->props.transmission_mode) {
3825 case TRANSMISSION_MODE_AUTO:
3827 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M;
3828 /* fall through , try first guess DRX_FFTMODE_8K */
3829 case TRANSMISSION_MODE_8K:
3830 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K;
3832 case TRANSMISSION_MODE_2K:
3833 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K;
3838 switch (state->props.guard_interval) {
3840 case GUARD_INTERVAL_AUTO:
3841 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M;
3842 /* fall through , try first guess DRX_GUARD_1DIV4 */
3843 case GUARD_INTERVAL_1_4:
3844 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4;
3846 case GUARD_INTERVAL_1_32:
3847 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32;
3849 case GUARD_INTERVAL_1_16:
3850 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16;
3852 case GUARD_INTERVAL_1_8:
3853 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8;
3858 switch (state->props.hierarchy) {
3859 case HIERARCHY_AUTO:
3860 case HIERARCHY_NONE:
3862 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M;
3863 /* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */
3864 /* transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */
3867 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1;
3870 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2;
3873 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4;
3879 switch (state->props.modulation) {
3882 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M;
3883 /* fall through , try first guess DRX_CONSTELLATION_QAM64 */
3885 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64;
3888 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK;
3891 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16;
3895 /* No hierachical channels support in BDA */
3896 /* Priority (only for hierarchical channels) */
3897 switch (channel->priority) {
3898 case DRX_PRIORITY_LOW:
3899 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO;
3900 WR16(devAddr, OFDM_EC_SB_PRIOR__A,
3901 OFDM_EC_SB_PRIOR_LO);
3903 case DRX_PRIORITY_HIGH:
3904 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3905 WR16(devAddr, OFDM_EC_SB_PRIOR__A,
3906 OFDM_EC_SB_PRIOR_HI));
3908 case DRX_PRIORITY_UNKNOWN: /* fall through */
3914 /* Set Priorty high */
3915 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3916 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
3922 switch (state->props.code_rate_HP) {
3925 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M;
3926 /* fall through , try first guess DRX_CODERATE_2DIV3 */
3928 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3;
3931 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2;
3934 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4;
3937 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6;
3940 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8;
3944 /* SAW filter selection: normaly not necesarry, but if wanted
3945 the application can select a SAW filter via the driver by using UIOs */
3946 /* First determine real bandwidth (Hz) */
3947 /* Also set delay for impulse noise cruncher */
3948 /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed
3949 by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC
3951 switch (state->props.bandwidth_hz) {
3953 state->props.bandwidth_hz = 8000000;
3956 bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ;
3957 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052);
3960 /* cochannel protection for PAL 8 MHz */
3961 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7);
3964 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7);
3967 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7);
3970 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3975 bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ;
3976 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491);
3979 /* cochannel protection for PAL 7 MHz */
3980 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8);
3983 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8);
3986 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4);
3989 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3994 bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ;
3995 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073);
3998 /* cochannel protection for NTSC 6 MHz */
3999 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19);
4002 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19);
4005 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14);
4008 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
4017 if (iqmRcRateOfs == 0) {
4018 /* Now compute IQM_RC_RATE_OFS
4019 (((SysFreq/BandWidth)/2)/2) -1) * 2^23)
4021 ((SysFreq / BandWidth) * (2^21)) - (2^23)
4023 /* (SysFreq / BandWidth) * (2^28) */
4024 /* assert (MAX(sysClk)/MIN(bandwidth) < 16)
4025 => assert(MAX(sysClk) < 16*MIN(bandwidth))
4026 => assert(109714272 > 48000000) = true so Frac 28 can be used */
4027 iqmRcRateOfs = Frac28a((u32)
4028 ((state->m_sysClockFreq *
4029 1000) / 3), bandwidth);
4030 /* (SysFreq / BandWidth) * (2^21), rounding before truncating */
4031 if ((iqmRcRateOfs & 0x7fL) >= 0x40)
4032 iqmRcRateOfs += 0x80L;
4033 iqmRcRateOfs = iqmRcRateOfs >> 7;
4034 /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */
4035 iqmRcRateOfs = iqmRcRateOfs - (1 << 23);
4039 ((((u32) IQM_RC_RATE_OFS_HI__M) <<
4040 IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M);
4041 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRateOfs);
4045 /* Bandwidth setting done */
4048 status = DVBTSetFrequencyShift(demod, channel, tunerOffset);
4052 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
4056 /*== Start SC, write channel settings to SC ===============================*/
4058 /* Activate SCU to enable SCU commands */
4059 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
4063 /* Enable SC after setting all other parameters */
4064 status = write16(state, OFDM_SC_COMM_STATE__A, 0);
4067 status = write16(state, OFDM_SC_COMM_EXEC__A, 1);
4072 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult);
4076 /* Write SC parameter registers, set all AUTO flags in operation mode */
4077 param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M |
4078 OFDM_SC_RA_RAM_OP_AUTO_GUARD__M |
4079 OFDM_SC_RA_RAM_OP_AUTO_CONST__M |
4080 OFDM_SC_RA_RAM_OP_AUTO_HIER__M |
4081 OFDM_SC_RA_RAM_OP_AUTO_RATE__M);
4082 status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
4083 0, transmissionParams, param1, 0, 0, 0);
4087 if (!state->m_DRXK_A3_ROM_CODE)
4088 status = DVBTCtrlSetSqiSpeed(state, &state->m_sqiSpeed);
4091 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4097 /*============================================================================*/
4100 * \brief Retreive lock status .
4101 * \param demod Pointer to demodulator instance.
4102 * \param lockStat Pointer to lock status structure.
4103 * \return DRXStatus_t.
4106 static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus)
4109 const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M |
4110 OFDM_SC_RA_RAM_LOCK_FEC__M);
4111 const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M);
4112 const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M;
4114 u16 ScRaRamLock = 0;
4119 *pLockStatus = NOT_LOCKED;
4121 /* Check if SC is running */
4122 status = read16(state, OFDM_SC_COMM_EXEC__A, &ScCommExec);
4125 if (ScCommExec == OFDM_SC_COMM_EXEC_STOP)
4128 status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock);
4132 if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask)
4133 *pLockStatus = MPEG_LOCK;
4134 else if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
4135 *pLockStatus = FEC_LOCK;
4136 else if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
4137 *pLockStatus = DEMOD_LOCK;
4138 else if (ScRaRamLock & OFDM_SC_RA_RAM_LOCK_NODVBT__M)
4139 *pLockStatus = NEVER_LOCK;
4142 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4147 static int PowerUpQAM(struct drxk_state *state)
4149 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
4153 status = CtrlPowerMode(state, &powerMode);
4155 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4161 /** Power Down QAM */
4162 static int PowerDownQAM(struct drxk_state *state)
4169 status = read16(state, SCU_COMM_EXEC__A, &data);
4172 if (data == SCU_COMM_EXEC_ACTIVE) {
4177 /* stop all comstate->m_exec */
4178 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
4181 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
4186 status = SetIqmAf(state, false);
4190 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4195 /*============================================================================*/
4198 * \brief Setup of the QAM Measurement intervals for signal quality
4199 * \param demod instance of demod.
4200 * \param modulation current modulation.
4201 * \return DRXStatus_t.
4204 * Take into account that for certain settings the errorcounters can overflow.
4205 * The implementation does not check this.
4208 static int SetQAMMeasurement(struct drxk_state *state,
4209 enum EDrxkConstellation modulation,
4212 u32 fecBitsDesired = 0; /* BER accounting period */
4213 u32 fecRsPeriodTotal = 0; /* Total period */
4214 u16 fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */
4215 u16 fecRsPeriod = 0; /* Value for corresponding I2C register */
4221 /* fecBitsDesired = symbolRate [kHz] *
4227 switch (modulation) {
4228 case DRX_CONSTELLATION_QAM16:
4229 fecBitsDesired = 4 * symbolRate;
4231 case DRX_CONSTELLATION_QAM32:
4232 fecBitsDesired = 5 * symbolRate;
4234 case DRX_CONSTELLATION_QAM64:
4235 fecBitsDesired = 6 * symbolRate;
4237 case DRX_CONSTELLATION_QAM128:
4238 fecBitsDesired = 7 * symbolRate;
4240 case DRX_CONSTELLATION_QAM256:
4241 fecBitsDesired = 8 * symbolRate;
4249 fecBitsDesired /= 1000; /* symbolRate [Hz] -> symbolRate [kHz] */
4250 fecBitsDesired *= 500; /* meas. period [ms] */
4252 /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */
4253 /* fecRsPeriodTotal = fecBitsDesired / 1632 */
4254 fecRsPeriodTotal = (fecBitsDesired / 1632UL) + 1; /* roughly ceil */
4256 /* fecRsPeriodTotal = fecRsPrescale * fecRsPeriod */
4257 fecRsPrescale = 1 + (u16) (fecRsPeriodTotal >> 16);
4258 if (fecRsPrescale == 0) {
4259 /* Divide by zero (though impossible) */
4265 ((u16) fecRsPeriodTotal +
4266 (fecRsPrescale >> 1)) / fecRsPrescale;
4268 /* write corresponding registers */
4269 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod);
4272 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale);
4275 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod);
4278 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4282 static int SetQAM16(struct drxk_state *state)
4287 /* QAM Equalizer Setup */
4289 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);
4292 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);
4295 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);
4298 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);
4301 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);
4304 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);
4307 /* Decision Feedback Equalizer */
4308 status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);
4311 status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);
4314 status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);
4317 status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);
4320 status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);
4323 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4327 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4330 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4333 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4337 /* QAM Slicer Settings */
4338 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16);
4342 /* QAM Loop Controller Coeficients */
4343 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4346 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4349 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4352 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4355 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4358 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4361 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4364 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4368 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4371 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4374 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4377 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4380 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4383 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4386 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4389 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4392 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);
4395 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4398 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4401 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4406 /* QAM State Machine (FSM) Thresholds */
4408 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);
4411 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4414 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);
4417 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);
4420 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);
4423 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);
4427 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4430 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4433 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);
4438 /* QAM FSM Tracking Parameters */
4440 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);
4443 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);
4446 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);
4449 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);
4452 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);
4455 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);
4458 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);
4464 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4468 /*============================================================================*/
4471 * \brief QAM32 specific setup
4472 * \param demod instance of demod.
4473 * \return DRXStatus_t.
4475 static int SetQAM32(struct drxk_state *state)
4481 /* QAM Equalizer Setup */
4483 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
4486 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
4489 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
4492 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
4495 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
4498 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
4502 /* Decision Feedback Equalizer */
4503 status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);
4506 status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);
4509 status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);
4512 status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);
4515 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4518 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4522 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4525 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4528 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4532 /* QAM Slicer Settings */
4534 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32);
4539 /* QAM Loop Controller Coeficients */
4541 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4544 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4547 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4550 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4553 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4556 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4559 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4562 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4566 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4569 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4572 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4575 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4578 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4581 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4584 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4587 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4590 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
4593 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4596 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4599 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4604 /* QAM State Machine (FSM) Thresholds */
4606 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);
4609 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4612 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4615 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4618 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);
4621 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4625 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4628 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4631 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);
4636 /* QAM FSM Tracking Parameters */
4638 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4641 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
4644 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
4647 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
4650 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
4653 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
4656 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
4659 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4663 /*============================================================================*/
4666 * \brief QAM64 specific setup
4667 * \param demod instance of demod.
4668 * \return DRXStatus_t.
4670 static int SetQAM64(struct drxk_state *state)
4675 /* QAM Equalizer Setup */
4677 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);
4680 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);
4683 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);
4686 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);
4689 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);
4692 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);
4696 /* Decision Feedback Equalizer */
4697 status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);
4700 status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);
4703 status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);
4706 status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);
4709 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4712 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4716 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4719 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4722 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4726 /* QAM Slicer Settings */
4727 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64);
4732 /* QAM Loop Controller Coeficients */
4734 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4737 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4740 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4743 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4746 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4749 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4752 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4755 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4759 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4762 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);
4765 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);
4768 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4771 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);
4774 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4777 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4780 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4783 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
4786 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4789 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4792 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4797 /* QAM State Machine (FSM) Thresholds */
4799 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);
4802 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4805 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4808 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);
4811 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);
4814 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);
4818 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4821 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4824 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);
4829 /* QAM FSM Tracking Parameters */
4831 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4834 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);
4837 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);
4840 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);
4843 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);
4846 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);
4849 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);
4852 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4857 /*============================================================================*/
4860 * \brief QAM128 specific setup
4861 * \param demod: instance of demod.
4862 * \return DRXStatus_t.
4864 static int SetQAM128(struct drxk_state *state)
4869 /* QAM Equalizer Setup */
4871 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);
4874 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);
4877 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);
4880 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);
4883 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);
4886 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);
4890 /* Decision Feedback Equalizer */
4891 status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);
4894 status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);
4897 status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);
4900 status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);
4903 status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);
4906 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4910 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4913 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4916 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4921 /* QAM Slicer Settings */
4923 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM128);
4928 /* QAM Loop Controller Coeficients */
4930 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4933 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4936 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4939 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4942 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4945 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4948 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4951 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4955 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4958 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);
4961 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);
4964 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4967 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);
4970 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);
4973 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4976 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4979 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);
4982 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4985 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4988 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4993 /* QAM State Machine (FSM) Thresholds */
4995 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
4998 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5001 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5004 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5007 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);
5010 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
5014 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5017 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);
5021 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5025 /* QAM FSM Tracking Parameters */
5027 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5030 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);
5033 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);
5036 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);
5039 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);
5042 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);
5045 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);
5048 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5053 /*============================================================================*/
5056 * \brief QAM256 specific setup
5057 * \param demod: instance of demod.
5058 * \return DRXStatus_t.
5060 static int SetQAM256(struct drxk_state *state)
5065 /* QAM Equalizer Setup */
5067 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);
5070 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);
5073 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);
5076 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);
5079 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);
5082 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);
5086 /* Decision Feedback Equalizer */
5087 status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);
5090 status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);
5093 status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);
5096 status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);
5099 status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);
5102 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
5106 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
5109 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
5112 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
5116 /* QAM Slicer Settings */
5118 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM256);
5123 /* QAM Loop Controller Coeficients */
5125 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
5128 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
5131 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
5134 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
5137 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
5140 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
5143 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
5146 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
5150 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
5153 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);
5156 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);
5159 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
5162 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);
5165 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);
5168 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
5171 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
5174 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
5177 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
5180 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
5183 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
5188 /* QAM State Machine (FSM) Thresholds */
5190 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
5193 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5196 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5199 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5202 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);
5205 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);
5209 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5212 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
5215 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5220 /* QAM FSM Tracking Parameters */
5222 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5225 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
5228 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
5231 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
5234 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
5237 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
5240 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
5243 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5248 /*============================================================================*/
5250 * \brief Reset QAM block.
5251 * \param demod: instance of demod.
5252 * \param channel: pointer to channel data.
5253 * \return DRXStatus_t.
5255 static int QAMResetQAM(struct drxk_state *state)
5261 /* Stop QAM comstate->m_exec */
5262 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
5266 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
5269 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5273 /*============================================================================*/
5276 * \brief Set QAM symbolrate.
5277 * \param demod: instance of demod.
5278 * \param channel: pointer to channel data.
5279 * \return DRXStatus_t.
5281 static int QAMSetSymbolrate(struct drxk_state *state)
5283 u32 adcFrequency = 0;
5291 /* Select & calculate correct IQM rate */
5292 adcFrequency = (state->m_sysClockFreq * 1000) / 3;
5294 /* printk(KERN_DEBUG "drxk: SR %d\n", state->props.symbol_rate); */
5295 if (state->props.symbol_rate <= 1188750)
5297 else if (state->props.symbol_rate <= 2377500)
5299 else if (state->props.symbol_rate <= 4755000)
5301 status = write16(state, IQM_FD_RATESEL__A, ratesel);
5306 IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23)
5308 symbFreq = state->props.symbol_rate * (1 << ratesel);
5309 if (symbFreq == 0) {
5310 /* Divide by zero */
5314 iqmRcRate = (adcFrequency / symbFreq) * (1 << 21) +
5315 (Frac28a((adcFrequency % symbFreq), symbFreq) >> 7) -
5317 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate);
5320 state->m_iqmRcRate = iqmRcRate;
5322 LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15))
5324 symbFreq = state->props.symbol_rate;
5325 if (adcFrequency == 0) {
5326 /* Divide by zero */
5330 lcSymbRate = (symbFreq / adcFrequency) * (1 << 12) +
5331 (Frac28a((symbFreq % adcFrequency), adcFrequency) >>
5333 if (lcSymbRate > 511)
5335 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate);
5339 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5343 /*============================================================================*/
5346 * \brief Get QAM lock status.
5347 * \param demod: instance of demod.
5348 * \param channel: pointer to channel data.
5349 * \return DRXStatus_t.
5352 static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus)
5355 u16 Result[2] = { 0, 0 };
5358 *pLockStatus = NOT_LOCKED;
5359 status = scu_command(state,
5360 SCU_RAM_COMMAND_STANDARD_QAM |
5361 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2,
5364 printk(KERN_ERR "drxk: %s status = %08x\n", __func__, status);
5366 if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) {
5367 /* 0x0000 NOT LOCKED */
5368 } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) {
5369 /* 0x4000 DEMOD LOCKED */
5370 *pLockStatus = DEMOD_LOCK;
5371 } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) {
5372 /* 0x8000 DEMOD + FEC LOCKED (system lock) */
5373 *pLockStatus = MPEG_LOCK;
5375 /* 0xC000 NEVER LOCKED */
5376 /* (system will never be able to lock to the signal) */
5377 /* TODO: check this, intermediate & standard specific lock states are not
5378 taken into account here */
5379 *pLockStatus = NEVER_LOCK;
5384 #define QAM_MIRROR__M 0x03
5385 #define QAM_MIRROR_NORMAL 0x00
5386 #define QAM_MIRRORED 0x01
5387 #define QAM_MIRROR_AUTO_ON 0x02
5388 #define QAM_LOCKRANGE__M 0x10
5389 #define QAM_LOCKRANGE_NORMAL 0x10
5391 static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5392 s32 tunerFreqOffset)
5395 u16 setParamParameters[4] = { 0, 0, 0, 0 };
5400 * STEP 1: reset demodulator
5401 * resets FEC DI and FEC RS
5403 * resets SCU variables
5405 status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
5408 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
5411 status = QAMResetQAM(state);
5416 * STEP 2: configure demodulator
5417 * -set params; resets IQM,QAM,FEC HW; initializes some
5420 status = QAMSetSymbolrate(state);
5425 switch (state->props.modulation) {
5427 state->m_Constellation = DRX_CONSTELLATION_QAM256;
5431 state->m_Constellation = DRX_CONSTELLATION_QAM64;
5434 state->m_Constellation = DRX_CONSTELLATION_QAM16;
5437 state->m_Constellation = DRX_CONSTELLATION_QAM32;
5440 state->m_Constellation = DRX_CONSTELLATION_QAM128;
5448 setParamParameters[0] = state->m_Constellation; /* modulation */
5449 setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */
5450 if (state->m_OperationMode == OM_QAM_ITU_C)
5451 setParamParameters[2] = QAM_TOP_ANNEX_C;
5453 setParamParameters[2] = QAM_TOP_ANNEX_A;
5454 setParamParameters[3] |= (QAM_MIRROR_AUTO_ON);
5455 /* Env parameters */
5456 /* check for LOCKRANGE Extented */
5457 /* setParamParameters[3] |= QAM_LOCKRANGE_NORMAL; */
5459 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 4, setParamParameters, 1, &cmdResult);
5461 /* Fall-back to the simpler call */
5462 if (state->m_OperationMode == OM_QAM_ITU_C)
5463 setParamParameters[0] = QAM_TOP_ANNEX_C;
5465 setParamParameters[0] = QAM_TOP_ANNEX_A;
5466 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 1, setParamParameters, 1, &cmdResult);
5470 setParamParameters[0] = state->m_Constellation; /* modulation */
5471 setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */
5472 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 2, setParamParameters, 1, &cmdResult);
5478 * STEP 3: enable the system in a mode where the ADC provides valid
5479 * signal setup modulation independent registers
5482 status = SetFrequency(channel, tunerFreqOffset));
5486 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
5490 /* Setup BER measurement */
5491 status = SetQAMMeasurement(state, state->m_Constellation, state->props.symbol_rate);
5495 /* Reset default values */
5496 status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
5499 status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
5503 /* Reset default LC values */
5504 status = write16(state, QAM_LC_RATE_LIMIT__A, 3);
5507 status = write16(state, QAM_LC_LPF_FACTORP__A, 4);
5510 status = write16(state, QAM_LC_LPF_FACTORI__A, 4);
5513 status = write16(state, QAM_LC_MODE__A, 7);
5517 status = write16(state, QAM_LC_QUAL_TAB0__A, 1);
5520 status = write16(state, QAM_LC_QUAL_TAB1__A, 1);
5523 status = write16(state, QAM_LC_QUAL_TAB2__A, 1);
5526 status = write16(state, QAM_LC_QUAL_TAB3__A, 1);
5529 status = write16(state, QAM_LC_QUAL_TAB4__A, 2);
5532 status = write16(state, QAM_LC_QUAL_TAB5__A, 2);
5535 status = write16(state, QAM_LC_QUAL_TAB6__A, 2);
5538 status = write16(state, QAM_LC_QUAL_TAB8__A, 2);
5541 status = write16(state, QAM_LC_QUAL_TAB9__A, 2);
5544 status = write16(state, QAM_LC_QUAL_TAB10__A, 2);
5547 status = write16(state, QAM_LC_QUAL_TAB12__A, 2);
5550 status = write16(state, QAM_LC_QUAL_TAB15__A, 3);
5553 status = write16(state, QAM_LC_QUAL_TAB16__A, 3);
5556 status = write16(state, QAM_LC_QUAL_TAB20__A, 4);
5559 status = write16(state, QAM_LC_QUAL_TAB25__A, 4);
5563 /* Mirroring, QAM-block starting point not inverted */
5564 status = write16(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS);
5568 /* Halt SCU to enable safe non-atomic accesses */
5569 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5573 /* STEP 4: modulation specific setup */
5574 switch (state->props.modulation) {
5576 status = SetQAM16(state);
5579 status = SetQAM32(state);
5583 status = SetQAM64(state);
5586 status = SetQAM128(state);
5589 status = SetQAM256(state);
5598 /* Activate SCU to enable SCU commands */
5599 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5603 /* Re-configure MPEG output, requires knowledge of channel bitrate */
5604 /* extAttr->currentChannel.modulation = channel->modulation; */
5605 /* extAttr->currentChannel.symbolrate = channel->symbolrate; */
5606 status = MPEGTSDtoSetup(state, state->m_OperationMode);
5610 /* Start processes */
5611 status = MPEGTSStart(state);
5614 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
5617 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
5620 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
5624 /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
5625 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult);
5629 /* update global DRXK data container */
5630 /*? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */
5634 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5638 static int SetQAMStandard(struct drxk_state *state,
5639 enum OperationMode oMode)
5642 #ifdef DRXK_QAM_TAPS
5643 #define DRXK_QAMA_TAPS_SELECT
5644 #include "drxk_filters.h"
5645 #undef DRXK_QAMA_TAPS_SELECT
5650 /* added antenna switch */
5651 SwitchAntennaToQAM(state);
5653 /* Ensure correct power-up mode */
5654 status = PowerUpQAM(state);
5657 /* Reset QAM block */
5658 status = QAMResetQAM(state);
5664 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
5667 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
5671 /* Upload IQM Channel Filter settings by
5672 boot loader from ROM table */
5675 status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5678 status = BLDirectCmd(state, IQM_CF_TAP_RE0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5681 status = BLDirectCmd(state, IQM_CF_TAP_IM0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5689 status = write16(state, IQM_CF_OUT_ENA__A, (1 << IQM_CF_OUT_ENA_QAM__B));
5692 status = write16(state, IQM_CF_SYMMETRIC__A, 0);
5695 status = write16(state, IQM_CF_MIDTAP__A, ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B)));
5699 status = write16(state, IQM_RC_STRETCH__A, 21);
5702 status = write16(state, IQM_AF_CLP_LEN__A, 0);
5705 status = write16(state, IQM_AF_CLP_TH__A, 448);
5708 status = write16(state, IQM_AF_SNS_LEN__A, 0);
5711 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);
5715 status = write16(state, IQM_FS_ADJ_SEL__A, 1);
5718 status = write16(state, IQM_RC_ADJ_SEL__A, 1);
5721 status = write16(state, IQM_CF_ADJ_SEL__A, 1);
5724 status = write16(state, IQM_AF_UPD_SEL__A, 0);
5728 /* IQM Impulse Noise Processing Unit */
5729 status = write16(state, IQM_CF_CLP_VAL__A, 500);
5732 status = write16(state, IQM_CF_DATATH__A, 1000);
5735 status = write16(state, IQM_CF_BYPASSDET__A, 1);
5738 status = write16(state, IQM_CF_DET_LCT__A, 0);
5741 status = write16(state, IQM_CF_WND_LEN__A, 1);
5744 status = write16(state, IQM_CF_PKDTH__A, 1);
5747 status = write16(state, IQM_AF_INC_BYPASS__A, 1);
5751 /* turn on IQMAF. Must be done before setAgc**() */
5752 status = SetIqmAf(state, true);
5755 status = write16(state, IQM_AF_START_LOCK__A, 0x01);
5759 /* IQM will not be reset from here, sync ADC and update/init AGC */
5760 status = ADCSynchronization(state);
5764 /* Set the FSM step period */
5765 status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);
5769 /* Halt SCU to enable safe non-atomic accesses */
5770 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5774 /* No more resets of the IQM, current standard correctly set =>
5775 now AGCs can be configured. */
5777 status = InitAGC(state, true);
5780 status = SetPreSaw(state, &(state->m_qamPreSawCfg));
5784 /* Configure AGC's */
5785 status = SetAgcRf(state, &(state->m_qamRfAgcCfg), true);
5788 status = SetAgcIf(state, &(state->m_qamIfAgcCfg), true);
5792 /* Activate SCU to enable SCU commands */
5793 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5796 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5800 static int WriteGPIO(struct drxk_state *state)
5806 /* stop lock indicator process */
5807 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
5811 /* Write magic word to enable pdr reg write */
5812 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
5816 if (state->m_hasSAWSW) {
5817 if (state->UIO_mask & 0x0001) { /* UIO-1 */
5818 /* write to io pad configuration register - output mode */
5819 status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg);
5823 /* use corresponding bit in io data output registar */
5824 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5827 if ((state->m_GPIO & 0x0001) == 0)
5828 value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */
5830 value |= 0x8000; /* write one to 15th bit - 1st UIO */
5831 /* write back to io data output register */
5832 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5836 if (state->UIO_mask & 0x0002) { /* UIO-2 */
5837 /* write to io pad configuration register - output mode */
5838 status = write16(state, SIO_PDR_SMA_RX_CFG__A, state->m_GPIOCfg);
5842 /* use corresponding bit in io data output registar */
5843 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5846 if ((state->m_GPIO & 0x0002) == 0)
5847 value &= 0xBFFF; /* write zero to 14th bit - 2st UIO */
5849 value |= 0x4000; /* write one to 14th bit - 2st UIO */
5850 /* write back to io data output register */
5851 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5855 if (state->UIO_mask & 0x0004) { /* UIO-3 */
5856 /* write to io pad configuration register - output mode */
5857 status = write16(state, SIO_PDR_GPIO_CFG__A, state->m_GPIOCfg);
5861 /* use corresponding bit in io data output registar */
5862 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5865 if ((state->m_GPIO & 0x0004) == 0)
5866 value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */
5868 value |= 0x0004; /* write one to 2nd bit - 3rd UIO */
5869 /* write back to io data output register */
5870 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5875 /* Write magic word to disable pdr reg write */
5876 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
5879 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5883 static int SwitchAntennaToQAM(struct drxk_state *state)
5890 if (!state->antenna_gpio)
5893 gpio_state = state->m_GPIO & state->antenna_gpio;
5895 if (state->antenna_dvbt ^ gpio_state) {
5896 /* Antenna is on DVB-T mode. Switch */
5897 if (state->antenna_dvbt)
5898 state->m_GPIO &= ~state->antenna_gpio;
5900 state->m_GPIO |= state->antenna_gpio;
5901 status = WriteGPIO(state);
5904 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5908 static int SwitchAntennaToDVBT(struct drxk_state *state)
5915 if (!state->antenna_gpio)
5918 gpio_state = state->m_GPIO & state->antenna_gpio;
5920 if (!(state->antenna_dvbt ^ gpio_state)) {
5921 /* Antenna is on DVB-C mode. Switch */
5922 if (state->antenna_dvbt)
5923 state->m_GPIO |= state->antenna_gpio;
5925 state->m_GPIO &= ~state->antenna_gpio;
5926 status = WriteGPIO(state);
5929 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5934 static int PowerDownDevice(struct drxk_state *state)
5936 /* Power down to requested mode */
5937 /* Backup some register settings */
5938 /* Set pins with possible pull-ups connected to them in input mode */
5939 /* Analog power down */
5940 /* ADC power down */
5941 /* Power down device */
5945 if (state->m_bPDownOpenBridge) {
5946 /* Open I2C bridge before power down of DRXK */
5947 status = ConfigureI2CBridge(state, true);
5952 status = DVBTEnableOFDMTokenRing(state, false);
5956 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK);
5959 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
5962 state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
5963 status = HI_CfgCommand(state);
5966 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5971 static int load_microcode(struct drxk_state *state, const char *mc_name)
5973 const struct firmware *fw = NULL;
5978 err = request_firmware(&fw, mc_name, state->i2c->dev.parent);
5981 "drxk: Could not load firmware file %s.\n", mc_name);
5983 "drxk: Copy %s to your hotplug directory!\n", mc_name);
5986 err = DownloadMicrocode(state, fw->data, fw->size);
5987 release_firmware(fw);
5991 static int init_drxk(struct drxk_state *state)
5994 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
5998 if ((state->m_DrxkState == DRXK_UNINITIALIZED)) {
5999 status = PowerUpDevice(state);
6002 status = DRXX_Open(state);
6005 /* Soft reset of OFDM-, sys- and osc-clockdomain */
6006 status = write16(state, SIO_CC_SOFT_RST__A, SIO_CC_SOFT_RST_OFDM__M | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M);
6009 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6012 /* TODO is this needed, if yes how much delay in worst case scenario */
6014 state->m_DRXK_A3_PATCH_CODE = true;
6015 status = GetDeviceCapabilities(state);
6019 /* Bridge delay, uses oscilator clock */
6020 /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */
6021 /* SDA brdige delay */
6022 state->m_HICfgBridgeDelay =
6023 (u16) ((state->m_oscClockFreq / 1000) *
6024 HI_I2C_BRIDGE_DELAY) / 1000;
6026 if (state->m_HICfgBridgeDelay >
6027 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) {
6028 state->m_HICfgBridgeDelay =
6029 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
6031 /* SCL bridge delay, same as SDA for now */
6032 state->m_HICfgBridgeDelay +=
6033 state->m_HICfgBridgeDelay <<
6034 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B;
6036 status = InitHI(state);
6039 /* disable various processes */
6041 if (!(state->m_DRXK_A1_ROM_CODE)
6042 && !(state->m_DRXK_A2_ROM_CODE))
6045 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
6050 /* disable MPEG port */
6051 status = MPEGTSDisable(state);
6055 /* Stop AUD and SCU */
6056 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
6059 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
6063 /* enable token-ring bus through OFDM block for possible ucode upload */
6064 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON);
6068 /* include boot loader section */
6069 status = write16(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE);
6072 status = BLChainCmd(state, 0, 6, 100);
6076 if (state->microcode_name)
6077 load_microcode(state, state->microcode_name);
6079 /* disable token-ring bus through OFDM block for possible ucode upload */
6080 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF);
6084 /* Run SCU for a little while to initialize microcode version numbers */
6085 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
6088 status = DRXX_Open(state);
6091 /* added for test */
6094 powerMode = DRXK_POWER_DOWN_OFDM;
6095 status = CtrlPowerMode(state, &powerMode);
6099 /* Stamp driver version number in SCU data RAM in BCD code
6100 Done to enable field application engineers to retreive drxdriver version
6101 via I2C from SCU RAM.
6102 Not using SCU command interface for SCU register access since no
6103 microcode may be present.
6106 (((DRXK_VERSION_MAJOR / 100) % 10) << 12) +
6107 (((DRXK_VERSION_MAJOR / 10) % 10) << 8) +
6108 ((DRXK_VERSION_MAJOR % 10) << 4) +
6109 (DRXK_VERSION_MINOR % 10);
6110 status = write16(state, SCU_RAM_DRIVER_VER_HI__A, driverVersion);
6114 (((DRXK_VERSION_PATCH / 1000) % 10) << 12) +
6115 (((DRXK_VERSION_PATCH / 100) % 10) << 8) +
6116 (((DRXK_VERSION_PATCH / 10) % 10) << 4) +
6117 (DRXK_VERSION_PATCH % 10);
6118 status = write16(state, SCU_RAM_DRIVER_VER_LO__A, driverVersion);
6122 printk(KERN_INFO "DRXK driver version %d.%d.%d\n",
6123 DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR,
6124 DRXK_VERSION_PATCH);
6126 /* Dirty fix of default values for ROM/PATCH microcode
6127 Dirty because this fix makes it impossible to setup suitable values
6128 before calling DRX_Open. This solution requires changes to RF AGC speed
6129 to be done via the CTRL function after calling DRX_Open */
6131 /* m_dvbtRfAgcCfg.speed = 3; */
6133 /* Reset driver debug flags to 0 */
6134 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);
6139 NOTE: No more full FEC resets allowed afterwards!! */
6140 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
6143 /* MPEGTS functions are still the same */
6144 status = MPEGTSDtoInit(state);
6147 status = MPEGTSStop(state);
6150 status = MPEGTSConfigurePolarity(state);
6153 status = MPEGTSConfigurePins(state, state->m_enableMPEGOutput);
6156 /* added: configure GPIO */
6157 status = WriteGPIO(state);
6161 state->m_DrxkState = DRXK_STOPPED;
6163 if (state->m_bPowerDown) {
6164 status = PowerDownDevice(state);
6167 state->m_DrxkState = DRXK_POWERED_DOWN;
6169 state->m_DrxkState = DRXK_STOPPED;
6173 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
6178 static void drxk_release(struct dvb_frontend *fe)
6180 struct drxk_state *state = fe->demodulator_priv;
6186 static int drxk_sleep(struct dvb_frontend *fe)
6188 struct drxk_state *state = fe->demodulator_priv;
6195 static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
6197 struct drxk_state *state = fe->demodulator_priv;
6199 dprintk(1, "%s\n", enable ? "enable" : "disable");
6200 return ConfigureI2CBridge(state, enable ? true : false);
6203 static int drxk_set_parameters(struct dvb_frontend *fe)
6205 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6206 u32 delsys = p->delivery_system, old_delsys;
6207 struct drxk_state *state = fe->demodulator_priv;
6212 if (!fe->ops.tuner_ops.get_if_frequency) {
6214 "drxk: Error: get_if_frequency() not defined at tuner. Can't work without it!\n");
6218 if (fe->ops.i2c_gate_ctrl)
6219 fe->ops.i2c_gate_ctrl(fe, 1);
6220 if (fe->ops.tuner_ops.set_params)
6221 fe->ops.tuner_ops.set_params(fe);
6222 if (fe->ops.i2c_gate_ctrl)
6223 fe->ops.i2c_gate_ctrl(fe, 0);
6225 old_delsys = state->props.delivery_system;
6228 if (old_delsys != delsys) {
6231 case SYS_DVBC_ANNEX_A:
6232 case SYS_DVBC_ANNEX_C:
6233 if (!state->m_hasDVBC)
6235 state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ? true : false;
6236 if (state->m_itut_annex_c)
6237 SetOperationMode(state, OM_QAM_ITU_C);
6239 SetOperationMode(state, OM_QAM_ITU_A);
6242 if (!state->m_hasDVBT)
6244 SetOperationMode(state, OM_DVBT);
6251 fe->ops.tuner_ops.get_if_frequency(fe, &IF);
6252 Start(state, 0, IF);
6254 /* printk(KERN_DEBUG "drxk: %s IF=%d done\n", __func__, IF); */
6259 static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status)
6261 struct drxk_state *state = fe->demodulator_priv;
6266 GetLockStatus(state, &stat, 0);
6267 if (stat == MPEG_LOCK)
6269 if (stat == FEC_LOCK)
6271 if (stat == DEMOD_LOCK)
6276 static int drxk_read_ber(struct dvb_frontend *fe, u32 *ber)
6284 static int drxk_read_signal_strength(struct dvb_frontend *fe,
6287 struct drxk_state *state = fe->demodulator_priv;
6291 ReadIFAgc(state, &val);
6292 *strength = val & 0xffff;
6296 static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr)
6298 struct drxk_state *state = fe->demodulator_priv;
6302 GetSignalToNoise(state, &snr2);
6303 *snr = snr2 & 0xffff;
6307 static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
6309 struct drxk_state *state = fe->demodulator_priv;
6313 DVBTQAMGetAccPktErr(state, &err);
6314 *ucblocks = (u32) err;
6318 static int drxk_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings
6321 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6324 switch (p->delivery_system) {
6325 case SYS_DVBC_ANNEX_A:
6326 case SYS_DVBC_ANNEX_C:
6328 sets->min_delay_ms = 3000;
6329 sets->max_drift = 0;
6330 sets->step_size = 0;
6337 static struct dvb_frontend_ops drxk_ops = {
6338 /* .delsys will be filled dynamically */
6341 .frequency_min = 47000000,
6342 .frequency_max = 865000000,
6344 .symbol_rate_min = 870000,
6345 .symbol_rate_max = 11700000,
6347 .frequency_stepsize = 166667,
6349 .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
6350 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO |
6351 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
6352 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_MUTE_TS |
6353 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
6354 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO
6357 .release = drxk_release,
6358 .sleep = drxk_sleep,
6359 .i2c_gate_ctrl = drxk_gate_ctrl,
6361 .set_frontend = drxk_set_parameters,
6362 .get_tune_settings = drxk_get_tune_settings,
6364 .read_status = drxk_read_status,
6365 .read_ber = drxk_read_ber,
6366 .read_signal_strength = drxk_read_signal_strength,
6367 .read_snr = drxk_read_snr,
6368 .read_ucblocks = drxk_read_ucblocks,
6371 struct dvb_frontend *drxk_attach(const struct drxk_config *config,
6372 struct i2c_adapter *i2c)
6376 struct drxk_state *state = NULL;
6377 u8 adr = config->adr;
6380 state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL);
6385 state->demod_address = adr;
6386 state->single_master = config->single_master;
6387 state->microcode_name = config->microcode_name;
6388 state->no_i2c_bridge = config->no_i2c_bridge;
6389 state->antenna_gpio = config->antenna_gpio;
6390 state->antenna_dvbt = config->antenna_dvbt;
6391 state->m_ChunkSize = config->chunk_size;
6392 state->enable_merr_cfg = config->enable_merr_cfg;
6394 if (config->dynamic_clk) {
6395 state->m_DVBTStaticCLK = 0;
6396 state->m_DVBCStaticCLK = 0;
6398 state->m_DVBTStaticCLK = 1;
6399 state->m_DVBCStaticCLK = 1;
6403 if (config->mpeg_out_clk_strength)
6404 state->m_TSClockkStrength = config->mpeg_out_clk_strength & 0x07;
6406 state->m_TSClockkStrength = 0x06;
6408 if (config->parallel_ts)
6409 state->m_enableParallel = true;
6411 state->m_enableParallel = false;
6413 /* NOTE: as more UIO bits will be used, add them to the mask */
6414 state->UIO_mask = config->antenna_gpio;
6416 /* Default gpio to DVB-C */
6417 if (!state->antenna_dvbt && state->antenna_gpio)
6418 state->m_GPIO |= state->antenna_gpio;
6420 state->m_GPIO &= ~state->antenna_gpio;
6422 mutex_init(&state->mutex);
6424 memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops));
6425 state->frontend.demodulator_priv = state;
6428 if (init_drxk(state) < 0)
6431 /* Initialize the supported delivery systems */
6433 if (state->m_hasDVBC) {
6434 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A;
6435 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C;
6436 strlcat(state->frontend.ops.info.name, " DVB-C",
6437 sizeof(state->frontend.ops.info.name));
6439 if (state->m_hasDVBT) {
6440 state->frontend.ops.delsys[n++] = SYS_DVBT;
6441 strlcat(state->frontend.ops.info.name, " DVB-T",
6442 sizeof(state->frontend.ops.info.name));
6445 printk(KERN_INFO "drxk: frontend initialized.\n");
6446 return &state->frontend;
6449 printk(KERN_ERR "drxk: not found\n");
6453 EXPORT_SYMBOL(drxk_attach);
6455 MODULE_DESCRIPTION("DRX-K driver");
6456 MODULE_AUTHOR("Ralph Metzler");
6457 MODULE_LICENSE("GPL");