2 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/cpu.h>
19 #include <linux/delay.h>
20 #include <linux/interrupt.h>
22 #include <linux/of_address.h>
23 #include <linux/of_irq.h>
24 #include <linux/percpu.h>
25 #include <linux/slab.h>
27 #include <linux/irqchip/arm-gic-v3.h>
29 #include <asm/cputype.h>
30 #include <asm/exception.h>
31 #include <asm/smp_plat.h>
33 #include "irq-gic-common.h"
36 struct gic_chip_data {
37 void __iomem *dist_base;
38 void __iomem **redist_base;
39 void __percpu __iomem **rdist;
40 struct irq_domain *domain;
46 static struct gic_chip_data gic_data __read_mostly;
48 #define gic_data_rdist() (this_cpu_ptr(gic_data.rdist))
49 #define gic_data_rdist_rd_base() (*gic_data_rdist())
50 #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K)
52 /* Our default, arbitrary priority value. Linux only uses one anyway. */
53 #define DEFAULT_PMR_VALUE 0xf0
55 static inline unsigned int gic_irq(struct irq_data *d)
60 static inline int gic_irq_in_rdist(struct irq_data *d)
62 return gic_irq(d) < 32;
65 static inline void __iomem *gic_dist_base(struct irq_data *d)
67 if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */
68 return gic_data_rdist_sgi_base();
70 if (d->hwirq <= 1023) /* SPI -> dist_base */
71 return gic_data.dist_base;
74 BUG(); /* LPI Detected!!! */
79 static void gic_do_wait_for_rwp(void __iomem *base)
81 u32 count = 1000000; /* 1s! */
83 while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) {
86 pr_err_ratelimited("RWP timeout, gone fishing\n");
94 /* Wait for completion of a distributor change */
95 static void gic_dist_wait_for_rwp(void)
97 gic_do_wait_for_rwp(gic_data.dist_base);
100 /* Wait for completion of a redistributor change */
101 static void gic_redist_wait_for_rwp(void)
103 gic_do_wait_for_rwp(gic_data_rdist_rd_base());
106 /* Low level accessors */
107 static u64 gic_read_iar(void)
111 asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));
115 static void gic_write_pmr(u64 val)
117 asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val));
120 static void gic_write_ctlr(u64 val)
122 asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (val));
126 static void gic_write_grpen1(u64 val)
128 asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" (val));
132 static void gic_write_sgi1r(u64 val)
134 asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val));
137 static void gic_enable_sre(void)
141 asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
142 val |= ICC_SRE_EL1_SRE;
143 asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val));
147 * Need to check that the SRE bit has actually been set. If
148 * not, it means that SRE is disabled at EL2. We're going to
149 * die painfully, and there is nothing we can do about it.
151 * Kindly inform the luser.
153 asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
154 if (!(val & ICC_SRE_EL1_SRE))
155 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
158 static void gic_enable_redist(bool enable)
161 u32 count = 1000000; /* 1s! */
164 rbase = gic_data_rdist_rd_base();
166 val = readl_relaxed(rbase + GICR_WAKER);
168 /* Wake up this CPU redistributor */
169 val &= ~GICR_WAKER_ProcessorSleep;
171 val |= GICR_WAKER_ProcessorSleep;
172 writel_relaxed(val, rbase + GICR_WAKER);
174 if (!enable) { /* Check that GICR_WAKER is writeable */
175 val = readl_relaxed(rbase + GICR_WAKER);
176 if (!(val & GICR_WAKER_ProcessorSleep))
177 return; /* No PM support in this redistributor */
181 val = readl_relaxed(rbase + GICR_WAKER);
182 if (enable ^ (val & GICR_WAKER_ChildrenAsleep))
188 pr_err_ratelimited("redistributor failed to %s...\n",
189 enable ? "wakeup" : "sleep");
193 * Routines to disable, enable, EOI and route interrupts
195 static void gic_poke_irq(struct irq_data *d, u32 offset)
197 u32 mask = 1 << (gic_irq(d) % 32);
198 void (*rwp_wait)(void);
201 if (gic_irq_in_rdist(d)) {
202 base = gic_data_rdist_sgi_base();
203 rwp_wait = gic_redist_wait_for_rwp;
205 base = gic_data.dist_base;
206 rwp_wait = gic_dist_wait_for_rwp;
209 writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4);
213 static int gic_peek_irq(struct irq_data *d, u32 offset)
215 u32 mask = 1 << (gic_irq(d) % 32);
218 if (gic_irq_in_rdist(d))
219 base = gic_data_rdist_sgi_base();
221 base = gic_data.dist_base;
223 return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask);
226 static void gic_mask_irq(struct irq_data *d)
228 gic_poke_irq(d, GICD_ICENABLER);
231 static void gic_unmask_irq(struct irq_data *d)
233 gic_poke_irq(d, GICD_ISENABLER);
236 static void gic_eoi_irq(struct irq_data *d)
238 gic_write_eoir(gic_irq(d));
241 static int gic_set_type(struct irq_data *d, unsigned int type)
243 unsigned int irq = gic_irq(d);
244 void (*rwp_wait)(void);
247 /* Interrupt configuration for SGIs can't be changed */
251 if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
254 if (gic_irq_in_rdist(d)) {
255 base = gic_data_rdist_sgi_base();
256 rwp_wait = gic_redist_wait_for_rwp;
258 base = gic_data.dist_base;
259 rwp_wait = gic_dist_wait_for_rwp;
262 gic_configure_irq(irq, type, base, rwp_wait);
267 static u64 gic_mpidr_to_affinity(u64 mpidr)
271 aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
272 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
273 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
274 MPIDR_AFFINITY_LEVEL(mpidr, 0));
279 static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
284 irqnr = gic_read_iar();
286 if (likely(irqnr > 15 && irqnr < 1020)) {
287 u64 irq = irq_find_mapping(gic_data.domain, irqnr);
289 handle_IRQ(irq, regs);
293 WARN_ONCE(true, "Unexpected SPI received!\n");
294 gic_write_eoir(irqnr);
297 gic_write_eoir(irqnr);
299 handle_IPI(irqnr, regs);
301 WARN_ONCE(true, "Unexpected SGI received!\n");
305 } while (irqnr != ICC_IAR1_EL1_SPURIOUS);
308 static void __init gic_dist_init(void)
312 void __iomem *base = gic_data.dist_base;
314 /* Disable the distributor */
315 writel_relaxed(0, base + GICD_CTLR);
316 gic_dist_wait_for_rwp();
318 gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp);
320 /* Enable distributor with ARE, Group1 */
321 writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1,
325 * Set all global interrupts to the boot CPU only. ARE must be
328 affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
329 for (i = 32; i < gic_data.irq_nr; i++)
330 writeq_relaxed(affinity, base + GICD_IROUTER + i * 8);
333 static int gic_populate_rdist(void)
335 u64 mpidr = cpu_logical_map(smp_processor_id());
341 * Convert affinity to a 32bit value that can be matched to
342 * GICR_TYPER bits [63:32].
344 aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 |
345 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
346 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
347 MPIDR_AFFINITY_LEVEL(mpidr, 0));
349 for (i = 0; i < gic_data.redist_regions; i++) {
350 void __iomem *ptr = gic_data.redist_base[i];
353 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK;
354 if (reg != GIC_PIDR2_ARCH_GICv3 &&
355 reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */
356 pr_warn("No redistributor present @%p\n", ptr);
361 typer = readq_relaxed(ptr + GICR_TYPER);
362 if ((typer >> 32) == aff) {
363 gic_data_rdist_rd_base() = ptr;
364 pr_info("CPU%d: found redistributor %llx @%p\n",
366 (unsigned long long)mpidr, ptr);
370 if (gic_data.redist_stride) {
371 ptr += gic_data.redist_stride;
373 ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */
374 if (typer & GICR_TYPER_VLPIS)
375 ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */
377 } while (!(typer & GICR_TYPER_LAST));
380 /* We couldn't even deal with ourselves... */
381 WARN(true, "CPU%d: mpidr %llx has no re-distributor!\n",
382 smp_processor_id(), (unsigned long long)mpidr);
386 static void gic_cpu_init(void)
390 /* Register ourselves with the rest of the world */
391 if (gic_populate_rdist())
394 gic_enable_redist(true);
396 rbase = gic_data_rdist_sgi_base();
398 gic_cpu_config(rbase, gic_redist_wait_for_rwp);
400 /* Enable system registers */
403 /* Set priority mask register */
404 gic_write_pmr(DEFAULT_PMR_VALUE);
406 /* EOI deactivates interrupt too (mode 0) */
407 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir);
409 /* ... and let's hit the road... */
414 static int gic_secondary_init(struct notifier_block *nfb,
415 unsigned long action, void *hcpu)
417 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
423 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
424 * priority because the GIC needs to be up before the ARM generic timers.
426 static struct notifier_block gic_cpu_notifier = {
427 .notifier_call = gic_secondary_init,
431 static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask,
435 u64 mpidr = cpu_logical_map(cpu);
438 while (cpu < nr_cpu_ids) {
440 * If we ever get a cluster of more than 16 CPUs, just
441 * scream and skip that CPU.
443 if (WARN_ON((mpidr & 0xff) >= 16))
446 tlist |= 1 << (mpidr & 0xf);
448 cpu = cpumask_next(cpu, mask);
449 if (cpu == nr_cpu_ids)
452 mpidr = cpu_logical_map(cpu);
454 if (cluster_id != (mpidr & ~0xffUL)) {
464 static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq)
468 val = (MPIDR_AFFINITY_LEVEL(cluster_id, 3) << 48 |
469 MPIDR_AFFINITY_LEVEL(cluster_id, 2) << 32 |
471 MPIDR_AFFINITY_LEVEL(cluster_id, 1) << 16 |
474 pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val);
475 gic_write_sgi1r(val);
478 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
482 if (WARN_ON(irq >= 16))
486 * Ensure that stores to Normal memory are visible to the
487 * other CPUs before issuing the IPI.
491 for_each_cpu_mask(cpu, *mask) {
492 u64 cluster_id = cpu_logical_map(cpu) & ~0xffUL;
495 tlist = gic_compute_target_list(&cpu, mask, cluster_id);
496 gic_send_sgi(cluster_id, tlist, irq);
499 /* Force the above writes to ICC_SGI1R_EL1 to be executed */
503 static void gic_smp_init(void)
505 set_smp_cross_call(gic_raise_softirq);
506 register_cpu_notifier(&gic_cpu_notifier);
509 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
512 unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
517 if (gic_irq_in_rdist(d))
520 /* If interrupt was enabled, disable it first */
521 enabled = gic_peek_irq(d, GICD_ISENABLER);
525 reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8);
526 val = gic_mpidr_to_affinity(cpu_logical_map(cpu));
528 writeq_relaxed(val, reg);
531 * If the interrupt was enabled, enabled it again. Otherwise,
532 * just wait for the distributor to have digested our changes.
537 gic_dist_wait_for_rwp();
539 return IRQ_SET_MASK_OK;
542 #define gic_set_affinity NULL
543 #define gic_smp_init() do { } while(0)
546 static struct irq_chip gic_chip = {
548 .irq_mask = gic_mask_irq,
549 .irq_unmask = gic_unmask_irq,
550 .irq_eoi = gic_eoi_irq,
551 .irq_set_type = gic_set_type,
552 .irq_set_affinity = gic_set_affinity,
555 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
558 /* SGIs are private to the core kernel */
563 irq_set_percpu_devid(irq);
564 irq_set_chip_and_handler(irq, &gic_chip,
565 handle_percpu_devid_irq);
566 set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
569 if (hw >= 32 && hw < gic_data.irq_nr) {
570 irq_set_chip_and_handler(irq, &gic_chip,
572 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
574 irq_set_chip_data(irq, d->host_data);
578 static int gic_irq_domain_xlate(struct irq_domain *d,
579 struct device_node *controller,
580 const u32 *intspec, unsigned int intsize,
581 unsigned long *out_hwirq, unsigned int *out_type)
583 if (d->of_node != controller)
590 *out_hwirq = intspec[1] + 32;
593 *out_hwirq = intspec[1] + 16;
599 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
603 static const struct irq_domain_ops gic_irq_domain_ops = {
604 .map = gic_irq_domain_map,
605 .xlate = gic_irq_domain_xlate,
608 static int __init gic_of_init(struct device_node *node, struct device_node *parent)
610 void __iomem *dist_base;
611 void __iomem **redist_base;
619 dist_base = of_iomap(node, 0);
621 pr_err("%s: unable to map gic dist registers\n",
626 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
627 if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) {
628 pr_err("%s: no distributor detected, giving up\n",
634 if (of_property_read_u32(node, "#redistributor-regions", &redist_regions))
637 redist_base = kzalloc(sizeof(*redist_base) * redist_regions, GFP_KERNEL);
643 for (i = 0; i < redist_regions; i++) {
644 redist_base[i] = of_iomap(node, 1 + i);
645 if (!redist_base[i]) {
646 pr_err("%s: couldn't map region %d\n",
649 goto out_unmap_rdist;
653 if (of_property_read_u64(node, "redistributor-stride", &redist_stride))
656 gic_data.dist_base = dist_base;
657 gic_data.redist_base = redist_base;
658 gic_data.redist_regions = redist_regions;
659 gic_data.redist_stride = redist_stride;
662 * Find out how many interrupts are supported.
663 * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI)
665 gic_irqs = readl_relaxed(gic_data.dist_base + GICD_TYPER) & 0x1f;
666 gic_irqs = (gic_irqs + 1) * 32;
669 gic_data.irq_nr = gic_irqs;
671 gic_data.domain = irq_domain_add_tree(node, &gic_irq_domain_ops,
673 gic_data.rdist = alloc_percpu(typeof(*gic_data.rdist));
675 if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdist)) {
680 set_handle_irq(gic_handle_irq);
690 irq_domain_remove(gic_data.domain);
691 free_percpu(gic_data.rdist);
693 for (i = 0; i < redist_regions; i++)
695 iounmap(redist_base[i]);
702 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);