drivers/irqchip/irq-gic-v3-its.c

   1 /*
   2  * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/bitmap.h>
  19 #include <linux/cpu.h>
  20 #include <linux/delay.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/log2.h>
  23 #include <linux/mm.h>
  24 #include <linux/msi.h>
  25 #include <linux/of.h>
  26 #include <linux/of_address.h>
  27 #include <linux/of_irq.h>
  28 #include <linux/of_pci.h>
  29 #include <linux/of_platform.h>
  30 #include <linux/percpu.h>
  31 #include <linux/slab.h>
  32
  33 #include <linux/irqchip.h>
  34 #include <linux/irqchip/arm-gic-v3.h>
  35
  36 #include <asm/cacheflush.h>
  37 #include <asm/cputype.h>
  38 #include <asm/exception.h>
  39
  40 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING           (1 << 0)
  41
  42 #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING     (1 << 0)
  43
  44 /*
  45  * Collection structure - just an ID, and a redistributor address to
  46  * ping. We use one per CPU as a bag of interrupts assigned to this
  47  * CPU.
  48  */
  49 struct its_collection {
  50         u64                     target_address;
  51         u16                     col_id;
  52 };
  53
  54 /*
  55  * The ITS structure - contains most of the infrastructure, with the
  56  * msi_controller, the command queue, the collections, and the list of
  57  * devices writing to it.
  58  */
  59 struct its_node {
  60         raw_spinlock_t          lock;
  61         struct list_head        entry;
  62         struct msi_controller   msi_chip;
  63         struct irq_domain       *domain;
  64         void __iomem            *base;
  65         unsigned long           phys_base;
  66         struct its_cmd_block    *cmd_base;
  67         struct its_cmd_block    *cmd_write;
  68         void                    *tables[GITS_BASER_NR_REGS];
  69         struct its_collection   *collections;
  70         struct list_head        its_device_list;
  71         u64                     flags;
  72         u32                     ite_size;
  73 };
  74
  75 #define ITS_ITT_ALIGN           SZ_256
  76
  77 struct event_lpi_map {
  78         unsigned long           *lpi_map;
  79         u16                     *col_map;
  80         irq_hw_number_t         lpi_base;
  81         int                     nr_lpis;
  82 };
  83
  84 /*
  85  * The ITS view of a device - belongs to an ITS, a collection, owns an
  86  * interrupt translation table, and a list of interrupts.
  87  */
  88 struct its_device {
  89         struct list_head        entry;
  90         struct its_node         *its;
  91         struct event_lpi_map    event_map;
  92         void                    *itt;
  93         u32                     nr_ites;
  94         u32                     device_id;
  95 };
  96
  97 static LIST_HEAD(its_nodes);
  98 static DEFINE_SPINLOCK(its_lock);
  99 static struct device_node *gic_root_node;
 100 static struct rdists *gic_rdists;
 101
 102 #define gic_data_rdist()                (raw_cpu_ptr(gic_rdists->rdist))
 103 #define gic_data_rdist_rd_base()        (gic_data_rdist()->rd_base)
 104
 105 static struct its_collection *dev_event_to_col(struct its_device *its_dev,
 106                                                u32 event)
 107 {
 108         struct its_node *its = its_dev->its;
 109
 110         return its->collections + its_dev->event_map.col_map[event];
 111 }
 112
 113 /*
 114  * ITS command descriptors - parameters to be encoded in a command
 115  * block.
 116  */
 117 struct its_cmd_desc {
 118         union {
 119                 struct {
 120                         struct its_device *dev;
 121                         u32 event_id;
 122                 } its_inv_cmd;
 123
 124                 struct {
 125                         struct its_device *dev;
 126                         u32 event_id;
 127                 } its_int_cmd;
 128
 129                 struct {
 130                         struct its_device *dev;
 131                         int valid;
 132                 } its_mapd_cmd;
 133
 134                 struct {
 135                         struct its_collection *col;
 136                         int valid;
 137                 } its_mapc_cmd;
 138
 139                 struct {
 140                         struct its_device *dev;
 141                         u32 phys_id;
 142                         u32 event_id;
 143                 } its_mapvi_cmd;
 144
 145                 struct {
 146                         struct its_device *dev;
 147                         struct its_collection *col;
 148                         u32 event_id;
 149                 } its_movi_cmd;
 150
 151                 struct {
 152                         struct its_device *dev;
 153                         u32 event_id;
 154                 } its_discard_cmd;
 155
 156                 struct {
 157                         struct its_collection *col;
 158                 } its_invall_cmd;
 159         };
 160 };
 161
 162 /*
 163  * The ITS command block, which is what the ITS actually parses.
 164  */
 165 struct its_cmd_block {
 166         u64     raw_cmd[4];
 167 };
 168
 169 #define ITS_CMD_QUEUE_SZ                SZ_64K
 170 #define ITS_CMD_QUEUE_NR_ENTRIES        (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
 171
 172 typedef struct its_collection *(*its_cmd_builder_t)(struct its_cmd_block *,
 173                                                     struct its_cmd_desc *);
 174
 175 static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
 176 {
 177         cmd->raw_cmd[0] &= ~0xffUL;
 178         cmd->raw_cmd[0] |= cmd_nr;
 179 }
 180
 181 static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
 182 {
 183         cmd->raw_cmd[0] &= BIT_ULL(32) - 1;
 184         cmd->raw_cmd[0] |= ((u64)devid) << 32;
 185 }
 186
 187 static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
 188 {
 189         cmd->raw_cmd[1] &= ~0xffffffffUL;
 190         cmd->raw_cmd[1] |= id;
 191 }
 192
 193 static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
 194 {
 195         cmd->raw_cmd[1] &= 0xffffffffUL;
 196         cmd->raw_cmd[1] |= ((u64)phys_id) << 32;
 197 }
 198
 199 static void its_encode_size(struct its_cmd_block *cmd, u8 size)
 200 {
 201         cmd->raw_cmd[1] &= ~0x1fUL;
 202         cmd->raw_cmd[1] |= size & 0x1f;
 203 }
 204
 205 static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
 206 {
 207         cmd->raw_cmd[2] &= ~0xffffffffffffUL;
 208         cmd->raw_cmd[2] |= itt_addr & 0xffffffffff00UL;
 209 }
 210
 211 static void its_encode_valid(struct its_cmd_block *cmd, int valid)
 212 {
 213         cmd->raw_cmd[2] &= ~(1UL << 63);
 214         cmd->raw_cmd[2] |= ((u64)!!valid) << 63;
 215 }
 216
 217 static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
 218 {
 219         cmd->raw_cmd[2] &= ~(0xffffffffUL << 16);
 220         cmd->raw_cmd[2] |= (target_addr & (0xffffffffUL << 16));
 221 }
 222
 223 static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
 224 {
 225         cmd->raw_cmd[2] &= ~0xffffUL;
 226         cmd->raw_cmd[2] |= col;
 227 }
 228
 229 static inline void its_fixup_cmd(struct its_cmd_block *cmd)
 230 {
 231         /* Let's fixup BE commands */
 232         cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]);
 233         cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]);
 234         cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]);
 235         cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]);
 236 }
 237
 238 static struct its_collection *its_build_mapd_cmd(struct its_cmd_block *cmd,
 239                                                  struct its_cmd_desc *desc)
 240 {
 241         unsigned long itt_addr;
 242         u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
 243
 244         itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
 245         itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);
 246
 247         its_encode_cmd(cmd, GITS_CMD_MAPD);
 248         its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
 249         its_encode_size(cmd, size - 1);
 250         its_encode_itt(cmd, itt_addr);
 251         its_encode_valid(cmd, desc->its_mapd_cmd.valid);
 252
 253         its_fixup_cmd(cmd);
 254
 255         return NULL;
 256 }
 257
 258 static struct its_collection *its_build_mapc_cmd(struct its_cmd_block *cmd,
 259                                                  struct its_cmd_desc *desc)
 260 {
 261         its_encode_cmd(cmd, GITS_CMD_MAPC);
 262         its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
 263         its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
 264         its_encode_valid(cmd, desc->its_mapc_cmd.valid);
 265
 266         its_fixup_cmd(cmd);
 267
 268         return desc->its_mapc_cmd.col;
 269 }
 270
 271 static struct its_collection *its_build_mapvi_cmd(struct its_cmd_block *cmd,
 272                                                   struct its_cmd_desc *desc)
 273 {
 274         struct its_collection *col;
 275
 276         col = dev_event_to_col(desc->its_mapvi_cmd.dev,
 277                                desc->its_mapvi_cmd.event_id);
 278
 279         its_encode_cmd(cmd, GITS_CMD_MAPVI);
 280         its_encode_devid(cmd, desc->its_mapvi_cmd.dev->device_id);
 281         its_encode_event_id(cmd, desc->its_mapvi_cmd.event_id);
 282         its_encode_phys_id(cmd, desc->its_mapvi_cmd.phys_id);
 283         its_encode_collection(cmd, col->col_id);
 284
 285         its_fixup_cmd(cmd);
 286
 287         return col;
 288 }
 289
 290 static struct its_collection *its_build_movi_cmd(struct its_cmd_block *cmd,
 291                                                  struct its_cmd_desc *desc)
 292 {
 293         struct its_collection *col;
 294
 295         col = dev_event_to_col(desc->its_movi_cmd.dev,
 296                                desc->its_movi_cmd.event_id);
 297
 298         its_encode_cmd(cmd, GITS_CMD_MOVI);
 299         its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
 300         its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
 301         its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);
 302
 303         its_fixup_cmd(cmd);
 304
 305         return col;
 306 }
 307
 308 static struct its_collection *its_build_discard_cmd(struct its_cmd_block *cmd,
 309                                                     struct its_cmd_desc *desc)
 310 {
 311         struct its_collection *col;
 312
 313         col = dev_event_to_col(desc->its_discard_cmd.dev,
 314                                desc->its_discard_cmd.event_id);
 315
 316         its_encode_cmd(cmd, GITS_CMD_DISCARD);
 317         its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
 318         its_encode_event_id(cmd, desc->its_discard_cmd.event_id);
 319
 320         its_fixup_cmd(cmd);
 321
 322         return col;
 323 }
 324
 325 static struct its_collection *its_build_inv_cmd(struct its_cmd_block *cmd,
 326                                                 struct its_cmd_desc *desc)
 327 {
 328         struct its_collection *col;
 329
 330         col = dev_event_to_col(desc->its_inv_cmd.dev,
 331                                desc->its_inv_cmd.event_id);
 332
 333         its_encode_cmd(cmd, GITS_CMD_INV);
 334         its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
 335         its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
 336
 337         its_fixup_cmd(cmd);
 338
 339         return col;
 340 }
 341
 342 static struct its_collection *its_build_invall_cmd(struct its_cmd_block *cmd,
 343                                                    struct its_cmd_desc *desc)
 344 {
 345         its_encode_cmd(cmd, GITS_CMD_INVALL);
 346         its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
 347
 348         its_fixup_cmd(cmd);
 349
 350         return NULL;
 351 }
 352
 353 static u64 its_cmd_ptr_to_offset(struct its_node *its,
 354                                  struct its_cmd_block *ptr)
 355 {
 356         return (ptr - its->cmd_base) * sizeof(*ptr);
 357 }
 358
 359 static int its_queue_full(struct its_node *its)
 360 {
 361         int widx;
 362         int ridx;
 363
 364         widx = its->cmd_write - its->cmd_base;
 365         ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);
 366
 367         /* This is incredibly unlikely to happen, unless the ITS locks up. */
 368         if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
 369                 return 1;
 370
 371         return 0;
 372 }
 373
 374 static struct its_cmd_block *its_allocate_entry(struct its_node *its)
 375 {
 376         struct its_cmd_block *cmd;
 377         u32 count = 1000000;    /* 1s! */
 378
 379         while (its_queue_full(its)) {
 380                 count--;
 381                 if (!count) {
 382                         pr_err_ratelimited("ITS queue not draining\n");
 383                         return NULL;
 384                 }
 385                 cpu_relax();
 386                 udelay(1);
 387         }
 388
 389         cmd = its->cmd_write++;
 390
 391         /* Handle queue wrapping */
 392         if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
 393                 its->cmd_write = its->cmd_base;
 394
 395         return cmd;
 396 }
 397
 398 static struct its_cmd_block *its_post_commands(struct its_node *its)
 399 {
 400         u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);
 401
 402         writel_relaxed(wr, its->base + GITS_CWRITER);
 403
 404         return its->cmd_write;
 405 }
 406
 407 static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
 408 {
 409         /*
 410          * Make sure the commands written to memory are observable by
 411          * the ITS.
 412          */
 413         if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
 414                 __flush_dcache_area(cmd, sizeof(*cmd));
 415         else
 416                 dsb(ishst);
 417 }
 418
 419 static void its_wait_for_range_completion(struct its_node *its,
 420                                           struct its_cmd_block *from,
 421                                           struct its_cmd_block *to)
 422 {
 423         u64 rd_idx, from_idx, to_idx;
 424         u32 count = 1000000;    /* 1s! */
 425
 426         from_idx = its_cmd_ptr_to_offset(its, from);
 427         to_idx = its_cmd_ptr_to_offset(its, to);
 428
 429         while (1) {
 430                 rd_idx = readl_relaxed(its->base + GITS_CREADR);
 431                 if (rd_idx >= to_idx || rd_idx < from_idx)
 432                         break;
 433
 434                 count--;
 435                 if (!count) {
 436                         pr_err_ratelimited("ITS queue timeout\n");
 437                         return;
 438                 }
 439                 cpu_relax();
 440                 udelay(1);
 441         }
 442 }
 443
 444 static void its_send_single_command(struct its_node *its,
 445                                     its_cmd_builder_t builder,
 446                                     struct its_cmd_desc *desc)
 447 {
 448         struct its_cmd_block *cmd, *sync_cmd, *next_cmd;
 449         struct its_collection *sync_col;
 450         unsigned long flags;
 451
 452         raw_spin_lock_irqsave(&its->lock, flags);
 453
 454         cmd = its_allocate_entry(its);
 455         if (!cmd) {             /* We're soooooo screewed... */
 456                 pr_err_ratelimited("ITS can't allocate, dropping command\n");
 457                 raw_spin_unlock_irqrestore(&its->lock, flags);
 458                 return;
 459         }
 460         sync_col = builder(cmd, desc);
 461         its_flush_cmd(its, cmd);
 462
 463         if (sync_col) {
 464                 sync_cmd = its_allocate_entry(its);
 465                 if (!sync_cmd) {
 466                         pr_err_ratelimited("ITS can't SYNC, skipping\n");
 467                         goto post;
 468                 }
 469                 its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
 470                 its_encode_target(sync_cmd, sync_col->target_address);
 471                 its_fixup_cmd(sync_cmd);
 472                 its_flush_cmd(its, sync_cmd);
 473         }
 474
 475 post:
 476         next_cmd = its_post_commands(its);
 477         raw_spin_unlock_irqrestore(&its->lock, flags);
 478
 479         its_wait_for_range_completion(its, cmd, next_cmd);
 480 }
 481
 482 static void its_send_inv(struct its_device *dev, u32 event_id)
 483 {
 484         struct its_cmd_desc desc;
 485
 486         desc.its_inv_cmd.dev = dev;
 487         desc.its_inv_cmd.event_id = event_id;
 488
 489         its_send_single_command(dev->its, its_build_inv_cmd, &desc);
 490 }
 491
 492 static void its_send_mapd(struct its_device *dev, int valid)
 493 {
 494         struct its_cmd_desc desc;
 495
 496         desc.its_mapd_cmd.dev = dev;
 497         desc.its_mapd_cmd.valid = !!valid;
 498
 499         its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
 500 }
 501
 502 static void its_send_mapc(struct its_node *its, struct its_collection *col,
 503                           int valid)
 504 {
 505         struct its_cmd_desc desc;
 506
 507         desc.its_mapc_cmd.col = col;
 508         desc.its_mapc_cmd.valid = !!valid;
 509
 510         its_send_single_command(its, its_build_mapc_cmd, &desc);
 511 }
 512
 513 static void its_send_mapvi(struct its_device *dev, u32 irq_id, u32 id)
 514 {
 515         struct its_cmd_desc desc;
 516
 517         desc.its_mapvi_cmd.dev = dev;
 518         desc.its_mapvi_cmd.phys_id = irq_id;
 519         desc.its_mapvi_cmd.event_id = id;
 520
 521         its_send_single_command(dev->its, its_build_mapvi_cmd, &desc);
 522 }
 523
 524 static void its_send_movi(struct its_device *dev,
 525                           struct its_collection *col, u32 id)
 526 {
 527         struct its_cmd_desc desc;
 528
 529         desc.its_movi_cmd.dev = dev;
 530         desc.its_movi_cmd.col = col;
 531         desc.its_movi_cmd.event_id = id;
 532
 533         its_send_single_command(dev->its, its_build_movi_cmd, &desc);
 534 }
 535
 536 static void its_send_discard(struct its_device *dev, u32 id)
 537 {
 538         struct its_cmd_desc desc;
 539
 540         desc.its_discard_cmd.dev = dev;
 541         desc.its_discard_cmd.event_id = id;
 542
 543         its_send_single_command(dev->its, its_build_discard_cmd, &desc);
 544 }
 545
 546 static void its_send_invall(struct its_node *its, struct its_collection *col)
 547 {
 548         struct its_cmd_desc desc;
 549
 550         desc.its_invall_cmd.col = col;
 551
 552         its_send_single_command(its, its_build_invall_cmd, &desc);
 553 }
 554
 555 /*
 556  * irqchip functions - assumes MSI, mostly.
 557  */
 558
 559 static inline u32 its_get_event_id(struct irq_data *d)
 560 {
 561         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
 562         return d->hwirq - its_dev->event_map.lpi_base;
 563 }
 564
 565 static void lpi_set_config(struct irq_data *d, bool enable)
 566 {
 567         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
 568         irq_hw_number_t hwirq = d->hwirq;
 569         u32 id = its_get_event_id(d);
 570         u8 *cfg = page_address(gic_rdists->prop_page) + hwirq - 8192;
 571
 572         if (enable)
 573                 *cfg |= LPI_PROP_ENABLED;
 574         else
 575                 *cfg &= ~LPI_PROP_ENABLED;
 576
 577         /*
 578          * Make the above write visible to the redistributors.
 579          * And yes, we're flushing exactly: One. Single. Byte.
 580          * Humpf...
 581          */
 582         if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
 583                 __flush_dcache_area(cfg, sizeof(*cfg));
 584         else
 585                 dsb(ishst);
 586         its_send_inv(its_dev, id);
 587 }
 588
 589 static void its_mask_irq(struct irq_data *d)
 590 {
 591         lpi_set_config(d, false);
 592 }
 593
 594 static void its_unmask_irq(struct irq_data *d)
 595 {
 596         lpi_set_config(d, true);
 597 }
 598
 599 static void its_eoi_irq(struct irq_data *d)
 600 {
 601         gic_write_eoir(d->hwirq);
 602 }
 603
 604 static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
 605                             bool force)
 606 {
 607         unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
 608         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
 609         struct its_collection *target_col;
 610         u32 id = its_get_event_id(d);
 611
 612         if (cpu >= nr_cpu_ids)
 613                 return -EINVAL;
 614
 615         target_col = &its_dev->its->collections[cpu];
 616         its_send_movi(its_dev, target_col, id);
 617         its_dev->event_map.col_map[id] = cpu;
 618
 619         return IRQ_SET_MASK_OK_DONE;
 620 }
 621
 622 static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
 623 {
 624         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
 625         struct its_node *its;
 626         u64 addr;
 627
 628         its = its_dev->its;
 629         addr = its->phys_base + GITS_TRANSLATER;
 630
 631         msg->address_lo         = addr & ((1UL << 32) - 1);
 632         msg->address_hi         = addr >> 32;
 633         msg->data               = its_get_event_id(d);
 634 }
 635
 636 static struct irq_chip its_irq_chip = {
 637         .name                   = "ITS",
 638         .irq_mask               = its_mask_irq,
 639         .irq_unmask             = its_unmask_irq,
 640         .irq_eoi                = its_eoi_irq,
 641         .irq_set_affinity       = its_set_affinity,
 642         .irq_compose_msi_msg    = its_irq_compose_msi_msg,
 643 };
 644
 645 /*
 646  * How we allocate LPIs:
 647  *
 648  * The GIC has id_bits bits for interrupt identifiers. From there, we
 649  * must subtract 8192 which are reserved for SGIs/PPIs/SPIs. Then, as
 650  * we allocate LPIs by chunks of 32, we can shift the whole thing by 5
 651  * bits to the right.
 652  *
 653  * This gives us (((1UL << id_bits) - 8192) >> 5) possible allocations.
 654  */
 655 #define IRQS_PER_CHUNK_SHIFT    5
 656 #define IRQS_PER_CHUNK          (1 << IRQS_PER_CHUNK_SHIFT)
 657
 658 static unsigned long *lpi_bitmap;
 659 static u32 lpi_chunks;
 660 static DEFINE_SPINLOCK(lpi_lock);
 661
 662 static int its_lpi_to_chunk(int lpi)
 663 {
 664         return (lpi - 8192) >> IRQS_PER_CHUNK_SHIFT;
 665 }
 666
 667 static int its_chunk_to_lpi(int chunk)
 668 {
 669         return (chunk << IRQS_PER_CHUNK_SHIFT) + 8192;
 670 }
 671
 672 static int its_lpi_init(u32 id_bits)
 673 {
 674         lpi_chunks = its_lpi_to_chunk(1UL << id_bits);
 675
 676         lpi_bitmap = kzalloc(BITS_TO_LONGS(lpi_chunks) * sizeof(long),
 677                              GFP_KERNEL);
 678         if (!lpi_bitmap) {
 679                 lpi_chunks = 0;
 680                 return -ENOMEM;
 681         }
 682
 683         pr_info("ITS: Allocated %d chunks for LPIs\n", (int)lpi_chunks);
 684         return 0;
 685 }
 686
 687 static unsigned long *its_lpi_alloc_chunks(int nr_irqs, int *base, int *nr_ids)
 688 {
 689         unsigned long *bitmap = NULL;
 690         int chunk_id;
 691         int nr_chunks;
 692         int i;
 693
 694         nr_chunks = DIV_ROUND_UP(nr_irqs, IRQS_PER_CHUNK);
 695
 696         spin_lock(&lpi_lock);
 697
 698         do {
 699                 chunk_id = bitmap_find_next_zero_area(lpi_bitmap, lpi_chunks,
 700                                                       0, nr_chunks, 0);
 701                 if (chunk_id < lpi_chunks)
 702                         break;
 703
 704                 nr_chunks--;
 705         } while (nr_chunks > 0);
 706
 707         if (!nr_chunks)
 708                 goto out;
 709
 710         bitmap = kzalloc(BITS_TO_LONGS(nr_chunks * IRQS_PER_CHUNK) * sizeof (long),
 711                          GFP_ATOMIC);
 712         if (!bitmap)
 713                 goto out;
 714
 715         for (i = 0; i < nr_chunks; i++)
 716                 set_bit(chunk_id + i, lpi_bitmap);
 717
 718         *base = its_chunk_to_lpi(chunk_id);
 719         *nr_ids = nr_chunks * IRQS_PER_CHUNK;
 720
 721 out:
 722         spin_unlock(&lpi_lock);
 723
 724         return bitmap;
 725 }
 726
 727 static void its_lpi_free(struct event_lpi_map *map)
 728 {
 729         int base = map->lpi_base;
 730         int nr_ids = map->nr_lpis;
 731         int lpi;
 732
 733         spin_lock(&lpi_lock);
 734
 735         for (lpi = base; lpi < (base + nr_ids); lpi += IRQS_PER_CHUNK) {
 736                 int chunk = its_lpi_to_chunk(lpi);
 737                 BUG_ON(chunk > lpi_chunks);
 738                 if (test_bit(chunk, lpi_bitmap)) {
 739                         clear_bit(chunk, lpi_bitmap);
 740                 } else {
 741                         pr_err("Bad LPI chunk %d\n", chunk);
 742                 }
 743         }
 744
 745         spin_unlock(&lpi_lock);
 746
 747         kfree(map->lpi_map);
 748         kfree(map->col_map);
 749 }
 750
 751 /*
 752  * We allocate 64kB for PROPBASE. That gives us at most 64K LPIs to
 753  * deal with (one configuration byte per interrupt). PENDBASE has to
 754  * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
 755  */
 756 #define LPI_PROPBASE_SZ         SZ_64K
 757 #define LPI_PENDBASE_SZ         (LPI_PROPBASE_SZ / 8 + SZ_1K)
 758
 759 /*
 760  * This is how many bits of ID we need, including the useless ones.
 761  */
 762 #define LPI_NRBITS              ilog2(LPI_PROPBASE_SZ + SZ_8K)
 763
 764 #define LPI_PROP_DEFAULT_PRIO   0xa0
 765
 766 static int __init its_alloc_lpi_tables(void)
 767 {
 768         phys_addr_t paddr;
 769
 770         gic_rdists->prop_page = alloc_pages(GFP_NOWAIT,
 771                                            get_order(LPI_PROPBASE_SZ));
 772         if (!gic_rdists->prop_page) {
 773                 pr_err("Failed to allocate PROPBASE\n");
 774                 return -ENOMEM;
 775         }
 776
 777         paddr = page_to_phys(gic_rdists->prop_page);
 778         pr_info("GIC: using LPI property table @%pa\n", &paddr);
 779
 780         /* Priority 0xa0, Group-1, disabled */
 781         memset(page_address(gic_rdists->prop_page),
 782                LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1,
 783                LPI_PROPBASE_SZ);
 784
 785         /* Make sure the GIC will observe the written configuration */
 786         __flush_dcache_area(page_address(gic_rdists->prop_page), LPI_PROPBASE_SZ);
 787
 788         return 0;
 789 }
 790
 791 static const char *its_base_type_string[] = {
 792         [GITS_BASER_TYPE_DEVICE]        = "Devices",
 793         [GITS_BASER_TYPE_VCPU]          = "Virtual CPUs",
 794         [GITS_BASER_TYPE_CPU]           = "Physical CPUs",
 795         [GITS_BASER_TYPE_COLLECTION]    = "Interrupt Collections",
 796         [GITS_BASER_TYPE_RESERVED5]     = "Reserved (5)",
 797         [GITS_BASER_TYPE_RESERVED6]     = "Reserved (6)",
 798         [GITS_BASER_TYPE_RESERVED7]     = "Reserved (7)",
 799 };
 800
 801 static void its_free_tables(struct its_node *its)
 802 {
 803         int i;
 804
 805         for (i = 0; i < GITS_BASER_NR_REGS; i++) {
 806                 if (its->tables[i]) {
 807                         free_page((unsigned long)its->tables[i]);
 808                         its->tables[i] = NULL;
 809                 }
 810         }
 811 }
 812
 813 static int its_alloc_tables(struct its_node *its)
 814 {
 815         int err;
 816         int i;
 817         int psz = SZ_64K;
 818         u64 shr = GITS_BASER_InnerShareable;
 819         u64 cache = GITS_BASER_WaWb;
 820
 821         for (i = 0; i < GITS_BASER_NR_REGS; i++) {
 822                 u64 val = readq_relaxed(its->base + GITS_BASER + i * 8);
 823                 u64 type = GITS_BASER_TYPE(val);
 824                 u64 entry_size = GITS_BASER_ENTRY_SIZE(val);
 825                 int order = get_order(psz);
 826                 int alloc_size;
 827                 u64 tmp;
 828                 void *base;
 829
 830                 if (type == GITS_BASER_TYPE_NONE)
 831                         continue;
 832
 833                 /*
 834                  * Allocate as many entries as required to fit the
 835                  * range of device IDs that the ITS can grok... The ID
 836                  * space being incredibly sparse, this results in a
 837                  * massive waste of memory.
 838                  *
 839                  * For other tables, only allocate a single page.
 840                  */
 841                 if (type == GITS_BASER_TYPE_DEVICE) {
 842                         u64 typer = readq_relaxed(its->base + GITS_TYPER);
 843                         u32 ids = GITS_TYPER_DEVBITS(typer);
 844
 845                         /*
 846                          * 'order' was initialized earlier to the default page
 847                          * granule of the the ITS.  We can't have an allocation
 848                          * smaller than that.  If the requested allocation
 849                          * is smaller, round up to the default page granule.
 850                          */
 851                         order = max(get_order((1UL << ids) * entry_size),
 852                                     order);
 853                         if (order >= MAX_ORDER) {
 854                                 order = MAX_ORDER - 1;
 855                                 pr_warn("%s: Device Table too large, reduce its page order to %u\n",
 856                                         its->msi_chip.of_node->full_name, order);
 857                         }
 858                 }
 859
 860                 alloc_size = (1 << order) * PAGE_SIZE;
 861                 base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
 862                 if (!base) {
 863                         err = -ENOMEM;
 864                         goto out_free;
 865                 }
 866
 867                 its->tables[i] = base;
 868
 869 retry_baser:
 870                 val = (virt_to_phys(base)                                |
 871                        (type << GITS_BASER_TYPE_SHIFT)                   |
 872                        ((entry_size - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) |
 873                        cache                                             |
 874                        shr                                               |
 875                        GITS_BASER_VALID);
 876
 877                 switch (psz) {
 878                 case SZ_4K:
 879                         val |= GITS_BASER_PAGE_SIZE_4K;
 880                         break;
 881                 case SZ_16K:
 882                         val |= GITS_BASER_PAGE_SIZE_16K;
 883                         break;
 884                 case SZ_64K:
 885                         val |= GITS_BASER_PAGE_SIZE_64K;
 886                         break;
 887                 }
 888
 889                 val |= (alloc_size / psz) - 1;
 890
 891                 writeq_relaxed(val, its->base + GITS_BASER + i * 8);
 892                 tmp = readq_relaxed(its->base + GITS_BASER + i * 8);
 893
 894                 if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
 895                         /*
 896                          * Shareability didn't stick. Just use
 897                          * whatever the read reported, which is likely
 898                          * to be the only thing this redistributor
 899                          * supports. If that's zero, make it
 900                          * non-cacheable as well.
 901                          */
 902                         shr = tmp & GITS_BASER_SHAREABILITY_MASK;
 903                         if (!shr)
 904                                 cache = GITS_BASER_nC;
 905                         goto retry_baser;
 906                 }
 907
 908                 if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) {
 909                         /*
 910                          * Page size didn't stick. Let's try a smaller
 911                          * size and retry. If we reach 4K, then
 912                          * something is horribly wrong...
 913                          */
 914                         switch (psz) {
 915                         case SZ_16K:
 916                                 psz = SZ_4K;
 917                                 goto retry_baser;
 918                         case SZ_64K:
 919                                 psz = SZ_16K;
 920                                 goto retry_baser;
 921                         }
 922                 }
 923
 924                 if (val != tmp) {
 925                         pr_err("ITS: %s: GITS_BASER%d doesn't stick: %lx %lx\n",
 926                                its->msi_chip.of_node->full_name, i,
 927                                (unsigned long) val, (unsigned long) tmp);
 928                         err = -ENXIO;
 929                         goto out_free;
 930                 }
 931
 932                 pr_info("ITS: allocated %d %s @%lx (psz %dK, shr %d)\n",
 933                         (int)(alloc_size / entry_size),
 934                         its_base_type_string[type],
 935                         (unsigned long)virt_to_phys(base),
 936                         psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
 937         }
 938
 939         return 0;
 940
 941 out_free:
 942         its_free_tables(its);
 943
 944         return err;
 945 }
 946
 947 static int its_alloc_collections(struct its_node *its)
 948 {
 949         its->collections = kzalloc(nr_cpu_ids * sizeof(*its->collections),
 950                                    GFP_KERNEL);
 951         if (!its->collections)
 952                 return -ENOMEM;
 953
 954         return 0;
 955 }
 956
 957 static void its_cpu_init_lpis(void)
 958 {
 959         void __iomem *rbase = gic_data_rdist_rd_base();
 960         struct page *pend_page;
 961         u64 val, tmp;
 962
 963         /* If we didn't allocate the pending table yet, do it now */
 964         pend_page = gic_data_rdist()->pend_page;
 965         if (!pend_page) {
 966                 phys_addr_t paddr;
 967                 /*
 968                  * The pending pages have to be at least 64kB aligned,
 969                  * hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below.
 970                  */
 971                 pend_page = alloc_pages(GFP_NOWAIT | __GFP_ZERO,
 972                                         get_order(max(LPI_PENDBASE_SZ, SZ_64K)));
 973                 if (!pend_page) {
 974                         pr_err("Failed to allocate PENDBASE for CPU%d\n",
 975                                smp_processor_id());
 976                         return;
 977                 }
 978
 979                 /* Make sure the GIC will observe the zero-ed page */
 980                 __flush_dcache_area(page_address(pend_page), LPI_PENDBASE_SZ);
 981
 982                 paddr = page_to_phys(pend_page);
 983                 pr_info("CPU%d: using LPI pending table @%pa\n",
 984                         smp_processor_id(), &paddr);
 985                 gic_data_rdist()->pend_page = pend_page;
 986         }
 987
 988         /* Disable LPIs */
 989         val = readl_relaxed(rbase + GICR_CTLR);
 990         val &= ~GICR_CTLR_ENABLE_LPIS;
 991         writel_relaxed(val, rbase + GICR_CTLR);
 992
 993         /*
 994          * Make sure any change to the table is observable by the GIC.
 995          */
 996         dsb(sy);
 997
 998         /* set PROPBASE */
 999         val = (page_to_phys(gic_rdists->prop_page) |
1000                GICR_PROPBASER_InnerShareable |
1001                GICR_PROPBASER_WaWb |
1002                ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
1003
1004         writeq_relaxed(val, rbase + GICR_PROPBASER);
1005         tmp = readq_relaxed(rbase + GICR_PROPBASER);
1006
1007         if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
1008                 if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
1009                         /*
1010                          * The HW reports non-shareable, we must
1011                          * remove the cacheability attributes as
1012                          * well.
1013                          */
1014                         val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
1015                                  GICR_PROPBASER_CACHEABILITY_MASK);
1016                         val |= GICR_PROPBASER_nC;
1017                         writeq_relaxed(val, rbase + GICR_PROPBASER);
1018                 }
1019                 pr_info_once("GIC: using cache flushing for LPI property table\n");
1020                 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
1021         }
1022
1023         /* set PENDBASE */
1024         val = (page_to_phys(pend_page) |
1025                GICR_PENDBASER_InnerShareable |
1026                GICR_PENDBASER_WaWb);
1027
1028         writeq_relaxed(val, rbase + GICR_PENDBASER);
1029         tmp = readq_relaxed(rbase + GICR_PENDBASER);
1030
1031         if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
1032                 /*
1033                  * The HW reports non-shareable, we must remove the
1034                  * cacheability attributes as well.
1035                  */
1036                 val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
1037                          GICR_PENDBASER_CACHEABILITY_MASK);
1038                 val |= GICR_PENDBASER_nC;
1039                 writeq_relaxed(val, rbase + GICR_PENDBASER);
1040         }
1041
1042         /* Enable LPIs */
1043         val = readl_relaxed(rbase + GICR_CTLR);
1044         val |= GICR_CTLR_ENABLE_LPIS;
1045         writel_relaxed(val, rbase + GICR_CTLR);
1046
1047         /* Make sure the GIC has seen the above */
1048         dsb(sy);
1049 }
1050
1051 static void its_cpu_init_collection(void)
1052 {
1053         struct its_node *its;
1054         int cpu;
1055
1056         spin_lock(&its_lock);
1057         cpu = smp_processor_id();
1058
1059         list_for_each_entry(its, &its_nodes, entry) {
1060                 u64 target;
1061
1062                 /*
1063                  * We now have to bind each collection to its target
1064                  * redistributor.
1065                  */
1066                 if (readq_relaxed(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
1067                         /*
1068                          * This ITS wants the physical address of the
1069                          * redistributor.
1070                          */
1071                         target = gic_data_rdist()->phys_base;
1072                 } else {
1073                         /*
1074                          * This ITS wants a linear CPU number.
1075                          */
1076                         target = readq_relaxed(gic_data_rdist_rd_base() + GICR_TYPER);
1077                         target = GICR_TYPER_CPU_NUMBER(target) << 16;
1078                 }
1079
1080                 /* Perform collection mapping */
1081                 its->collections[cpu].target_address = target;
1082                 its->collections[cpu].col_id = cpu;
1083
1084                 its_send_mapc(its, &its->collections[cpu], 1);
1085                 its_send_invall(its, &its->collections[cpu]);
1086         }
1087
1088         spin_unlock(&its_lock);
1089 }
1090
1091 static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
1092 {
1093         struct its_device *its_dev = NULL, *tmp;
1094         unsigned long flags;
1095
1096         raw_spin_lock_irqsave(&its->lock, flags);
1097
1098         list_for_each_entry(tmp, &its->its_device_list, entry) {
1099                 if (tmp->device_id == dev_id) {
1100                         its_dev = tmp;
1101                         break;
1102                 }
1103         }
1104
1105         raw_spin_unlock_irqrestore(&its->lock, flags);
1106
1107         return its_dev;
1108 }
1109
1110 static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
1111                                             int nvecs)
1112 {
1113         struct its_device *dev;
1114         unsigned long *lpi_map;
1115         unsigned long flags;
1116         u16 *col_map = NULL;
1117         void *itt;
1118         int lpi_base;
1119         int nr_lpis;
1120         int nr_ites;
1121         int sz;
1122
1123         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1124         /*
1125          * At least one bit of EventID is being used, hence a minimum
1126          * of two entries. No, the architecture doesn't let you
1127          * express an ITT with a single entry.
1128          */
1129         nr_ites = max(2UL, roundup_pow_of_two(nvecs));
1130         sz = nr_ites * its->ite_size;
1131         sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
1132         itt = kzalloc(sz, GFP_KERNEL);
1133         lpi_map = its_lpi_alloc_chunks(nvecs, &lpi_base, &nr_lpis);
1134         if (lpi_map)
1135                 col_map = kzalloc(sizeof(*col_map) * nr_lpis, GFP_KERNEL);
1136
1137         if (!dev || !itt || !lpi_map || !col_map) {
1138                 kfree(dev);
1139                 kfree(itt);
1140                 kfree(lpi_map);
1141                 kfree(col_map);
1142                 return NULL;
1143         }
1144
1145         dev->its = its;
1146         dev->itt = itt;
1147         dev->nr_ites = nr_ites;
1148         dev->event_map.lpi_map = lpi_map;
1149         dev->event_map.col_map = col_map;
1150         dev->event_map.lpi_base = lpi_base;
1151         dev->event_map.nr_lpis = nr_lpis;
1152         dev->device_id = dev_id;
1153         INIT_LIST_HEAD(&dev->entry);
1154
1155         raw_spin_lock_irqsave(&its->lock, flags);
1156         list_add(&dev->entry, &its->its_device_list);
1157         raw_spin_unlock_irqrestore(&its->lock, flags);
1158
1159         /* Map device to its ITT */
1160         its_send_mapd(dev, 1);
1161
1162         return dev;
1163 }
1164
1165 static void its_free_device(struct its_device *its_dev)
1166 {
1167         unsigned long flags;
1168
1169         raw_spin_lock_irqsave(&its_dev->its->lock, flags);
1170         list_del(&its_dev->entry);
1171         raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
1172         kfree(its_dev->itt);
1173         kfree(its_dev);
1174 }
1175
1176 static int its_alloc_device_irq(struct its_device *dev, irq_hw_number_t *hwirq)
1177 {
1178         int idx;
1179
1180         idx = find_first_zero_bit(dev->event_map.lpi_map,
1181                                   dev->event_map.nr_lpis);
1182         if (idx == dev->event_map.nr_lpis)
1183                 return -ENOSPC;
1184
1185         *hwirq = dev->event_map.lpi_base + idx;
1186         set_bit(idx, dev->event_map.lpi_map);
1187
1188         return 0;
1189 }
1190
1191 int its_msi_prepare(struct irq_domain *domain, u32 dev_id,
1192                     int nvec, msi_alloc_info_t *info)
1193 {
1194         struct its_node *its;
1195         struct its_device *its_dev;
1196
1197         its = domain->parent->host_data;
1198         its_dev = its_find_device(its, dev_id);
1199         if (its_dev) {
1200                 /*
1201                  * We already have seen this ID, probably through
1202                  * another alias (PCI bridge of some sort). No need to
1203                  * create the device.
1204                  */
1205                 pr_debug("Reusing ITT for devID %x\n", dev_id);
1206                 goto out;
1207         }
1208
1209         its_dev = its_create_device(its, dev_id, nvec);
1210         if (!its_dev)
1211                 return -ENOMEM;
1212
1213         pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
1214 out:
1215         info->scratchpad[0].ptr = its_dev;
1216         return 0;
1217 }
1218
1219 static int its_irq_gic_domain_alloc(struct irq_domain *domain,
1220                                     unsigned int virq,
1221                                     irq_hw_number_t hwirq)
1222 {
1223         struct of_phandle_args args;
1224
1225         args.np = domain->parent->of_node;
1226         args.args_count = 3;
1227         args.args[0] = GIC_IRQ_TYPE_LPI;
1228         args.args[1] = hwirq;
1229         args.args[2] = IRQ_TYPE_EDGE_RISING;
1230
1231         return irq_domain_alloc_irqs_parent(domain, virq, 1, &args);
1232 }
1233
1234 static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1235                                 unsigned int nr_irqs, void *args)
1236 {
1237         msi_alloc_info_t *info = args;
1238         struct its_device *its_dev = info->scratchpad[0].ptr;
1239         irq_hw_number_t hwirq;
1240         int err;
1241         int i;
1242
1243         for (i = 0; i < nr_irqs; i++) {
1244                 err = its_alloc_device_irq(its_dev, &hwirq);
1245                 if (err)
1246                         return err;
1247
1248                 err = its_irq_gic_domain_alloc(domain, virq + i, hwirq);
1249                 if (err)
1250                         return err;
1251
1252                 irq_domain_set_hwirq_and_chip(domain, virq + i,
1253                                               hwirq, &its_irq_chip, its_dev);
1254                 pr_debug("ID:%d pID:%d vID:%d\n",
1255                          (int)(hwirq - its_dev->event_map.lpi_base),
1256                          (int) hwirq, virq + i);
1257         }
1258
1259         return 0;
1260 }
1261
1262 static void its_irq_domain_activate(struct irq_domain *domain,
1263                                     struct irq_data *d)
1264 {
1265         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1266         u32 event = its_get_event_id(d);
1267
1268         /* Bind the LPI to the first possible CPU */
1269         its_dev->event_map.col_map[event] = cpumask_first(cpu_online_mask);
1270
1271         /* Map the GIC IRQ and event to the device */
1272         its_send_mapvi(its_dev, d->hwirq, event);
1273 }
1274
1275 static void its_irq_domain_deactivate(struct irq_domain *domain,
1276                                       struct irq_data *d)
1277 {
1278         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1279         u32 event = its_get_event_id(d);
1280
1281         /* Stop the delivery of interrupts */
1282         its_send_discard(its_dev, event);
1283 }
1284
1285 static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
1286                                 unsigned int nr_irqs)
1287 {
1288         struct irq_data *d = irq_domain_get_irq_data(domain, virq);
1289         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1290         int i;
1291
1292         for (i = 0; i < nr_irqs; i++) {
1293                 struct irq_data *data = irq_domain_get_irq_data(domain,
1294                                                                 virq + i);
1295                 u32 event = its_get_event_id(data);
1296
1297                 /* Mark interrupt index as unused */
1298                 clear_bit(event, its_dev->event_map.lpi_map);
1299
1300                 /* Nuke the entry in the domain */
1301                 irq_domain_reset_irq_data(data);
1302         }
1303
1304         /* If all interrupts have been freed, start mopping the floor */
1305         if (bitmap_empty(its_dev->event_map.lpi_map,
1306                          its_dev->event_map.nr_lpis)) {
1307                 its_lpi_free(&its_dev->event_map);
1308
1309                 /* Unmap device/itt */
1310                 its_send_mapd(its_dev, 0);
1311                 its_free_device(its_dev);
1312         }
1313
1314         irq_domain_free_irqs_parent(domain, virq, nr_irqs);
1315 }
1316
1317 static const struct irq_domain_ops its_domain_ops = {
1318         .alloc                  = its_irq_domain_alloc,
1319         .free                   = its_irq_domain_free,
1320         .activate               = its_irq_domain_activate,
1321         .deactivate             = its_irq_domain_deactivate,
1322 };
1323
1324 static int its_force_quiescent(void __iomem *base)
1325 {
1326         u32 count = 1000000;    /* 1s */
1327         u32 val;
1328
1329         val = readl_relaxed(base + GITS_CTLR);
1330         if (val & GITS_CTLR_QUIESCENT)
1331                 return 0;
1332
1333         /* Disable the generation of all interrupts to this ITS */
1334         val &= ~GITS_CTLR_ENABLE;
1335         writel_relaxed(val, base + GITS_CTLR);
1336
1337         /* Poll GITS_CTLR and wait until ITS becomes quiescent */
1338         while (1) {
1339                 val = readl_relaxed(base + GITS_CTLR);
1340                 if (val & GITS_CTLR_QUIESCENT)
1341                         return 0;
1342
1343                 count--;
1344                 if (!count)
1345                         return -EBUSY;
1346
1347                 cpu_relax();
1348                 udelay(1);
1349         }
1350 }
1351
1352 static int its_probe(struct device_node *node, struct irq_domain *parent)
1353 {
1354         struct resource res;
1355         struct its_node *its;
1356         void __iomem *its_base;
1357         u32 val;
1358         u64 baser, tmp;
1359         int err;
1360
1361         err = of_address_to_resource(node, 0, &res);
1362         if (err) {
1363                 pr_warn("%s: no regs?\n", node->full_name);
1364                 return -ENXIO;
1365         }
1366
1367         its_base = ioremap(res.start, resource_size(&res));
1368         if (!its_base) {
1369                 pr_warn("%s: unable to map registers\n", node->full_name);
1370                 return -ENOMEM;
1371         }
1372
1373         val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
1374         if (val != 0x30 && val != 0x40) {
1375                 pr_warn("%s: no ITS detected, giving up\n", node->full_name);
1376                 err = -ENODEV;
1377                 goto out_unmap;
1378         }
1379
1380         err = its_force_quiescent(its_base);
1381         if (err) {
1382                 pr_warn("%s: failed to quiesce, giving up\n",
1383                         node->full_name);
1384                 goto out_unmap;
1385         }
1386
1387         pr_info("ITS: %s\n", node->full_name);
1388
1389         its = kzalloc(sizeof(*its), GFP_KERNEL);
1390         if (!its) {
1391                 err = -ENOMEM;
1392                 goto out_unmap;
1393         }
1394
1395         raw_spin_lock_init(&its->lock);
1396         INIT_LIST_HEAD(&its->entry);
1397         INIT_LIST_HEAD(&its->its_device_list);
1398         its->base = its_base;
1399         its->phys_base = res.start;
1400         its->msi_chip.of_node = node;
1401         its->ite_size = ((readl_relaxed(its_base + GITS_TYPER) >> 4) & 0xf) + 1;
1402
1403         its->cmd_base = kzalloc(ITS_CMD_QUEUE_SZ, GFP_KERNEL);
1404         if (!its->cmd_base) {
1405                 err = -ENOMEM;
1406                 goto out_free_its;
1407         }
1408         its->cmd_write = its->cmd_base;
1409
1410         err = its_alloc_tables(its);
1411         if (err)
1412                 goto out_free_cmd;
1413
1414         err = its_alloc_collections(its);
1415         if (err)
1416                 goto out_free_tables;
1417
1418         baser = (virt_to_phys(its->cmd_base)    |
1419                  GITS_CBASER_WaWb               |
1420                  GITS_CBASER_InnerShareable     |
1421                  (ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
1422                  GITS_CBASER_VALID);
1423
1424         writeq_relaxed(baser, its->base + GITS_CBASER);
1425         tmp = readq_relaxed(its->base + GITS_CBASER);
1426
1427         if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
1428                 if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
1429                         /*
1430                          * The HW reports non-shareable, we must
1431                          * remove the cacheability attributes as
1432                          * well.
1433                          */
1434                         baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
1435                                    GITS_CBASER_CACHEABILITY_MASK);
1436                         baser |= GITS_CBASER_nC;
1437                         writeq_relaxed(baser, its->base + GITS_CBASER);
1438                 }
1439                 pr_info("ITS: using cache flushing for cmd queue\n");
1440                 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
1441         }
1442
1443         writeq_relaxed(0, its->base + GITS_CWRITER);
1444         writel_relaxed(GITS_CTLR_ENABLE, its->base + GITS_CTLR);
1445
1446         if (of_property_read_bool(its->msi_chip.of_node, "msi-controller")) {
1447                 its->domain = irq_domain_add_tree(NULL, &its_domain_ops, its);
1448                 if (!its->domain) {
1449                         err = -ENOMEM;
1450                         goto out_free_tables;
1451                 }
1452
1453                 its->domain->parent = parent;
1454
1455                 its->msi_chip.domain = its_pci_msi_alloc_domain(node,
1456                                                                 its->domain);
1457                 if (!its->msi_chip.domain) {
1458                         err = -ENOMEM;
1459                         goto out_free_domains;
1460                 }
1461
1462                 err = of_pci_msi_chip_add(&its->msi_chip);
1463                 if (err)
1464                         goto out_free_domains;
1465         }
1466
1467         spin_lock(&its_lock);
1468         list_add(&its->entry, &its_nodes);
1469         spin_unlock(&its_lock);
1470
1471         return 0;
1472
1473 out_free_domains:
1474         if (its->msi_chip.domain)
1475                 irq_domain_remove(its->msi_chip.domain);
1476         if (its->domain)
1477                 irq_domain_remove(its->domain);
1478 out_free_tables:
1479         its_free_tables(its);
1480 out_free_cmd:
1481         kfree(its->cmd_base);
1482 out_free_its:
1483         kfree(its);
1484 out_unmap:
1485         iounmap(its_base);
1486         pr_err("ITS: failed probing %s (%d)\n", node->full_name, err);
1487         return err;
1488 }
1489
1490 static bool gic_rdists_supports_plpis(void)
1491 {
1492         return !!(readl_relaxed(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
1493 }
1494
1495 int its_cpu_init(void)
1496 {
1497         if (!list_empty(&its_nodes)) {
1498                 if (!gic_rdists_supports_plpis()) {
1499                         pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
1500                         return -ENXIO;
1501                 }
1502                 its_cpu_init_lpis();
1503                 its_cpu_init_collection();
1504         }
1505
1506         return 0;
1507 }
1508
1509 static struct of_device_id its_device_id[] = {
1510         {       .compatible     = "arm,gic-v3-its",     },
1511         {},
1512 };
1513
1514 int its_init(struct device_node *node, struct rdists *rdists,
1515              struct irq_domain *parent_domain)
1516 {
1517         struct device_node *np;
1518
1519         for (np = of_find_matching_node(node, its_device_id); np;
1520              np = of_find_matching_node(np, its_device_id)) {
1521                 its_probe(np, parent_domain);
1522         }
1523
1524         if (list_empty(&its_nodes)) {
1525                 pr_warn("ITS: No ITS available, not enabling LPIs\n");
1526                 return -ENXIO;
1527         }
1528
1529         gic_rdists = rdists;
1530         gic_root_node = node;
1531
1532         its_alloc_lpi_tables();
1533         its_lpi_init(rdists->id_bits);
1534
1535         return 0;
1536 }