8 select IRQ_DOMAIN_HIERARCHY
9 select MULTI_IRQ_HANDLER
14 depends on PCI && PCI_MSI
15 select PCI_MSI_IRQ_DOMAIN
23 select MULTI_IRQ_HANDLER
24 select IRQ_DOMAIN_HIERARCHY
28 select PCI_MSI_IRQ_DOMAIN
33 select GENERIC_IRQ_CHIP
38 select MULTI_IRQ_HANDLER
42 default 4 if ARCH_S5PV210
46 The maximum number of VICs available in the system, for
51 select GENERIC_IRQ_CHIP
53 select MULTI_IRQ_HANDLER
58 select GENERIC_IRQ_CHIP
60 select MULTI_IRQ_HANDLER
66 select GENERIC_IRQ_CHIP
75 select GENERIC_IRQ_CHIP
78 config CLPS711X_IRQCHIP
80 depends on ARCH_CLPS711X
82 select MULTI_IRQ_HANDLER
92 select GENERIC_IRQ_CHIP
98 select MULTI_IRQ_HANDLER
100 config RENESAS_INTC_IRQPIN
111 select GENERIC_IRQ_CHIP
113 config VERSATILE_FPGA_IRQ
117 config VERSATILE_FPGA_IRQ_NR
120 depends on VERSATILE_FPGA_IRQ
129 Support for a CROSSBAR ip that precedes the main interrupt controller.
130 The primary irqchip invokes the crossbar's callback which inturn allocates
131 a free irq and configures the IP. Thus the peripheral interrupts are
132 routed to one of the free irqchip interrupt lines.
135 tristate "Keystone 2 IRQ controller IP"
136 depends on ARCH_KEYSTONE
138 Support for Texas Instruments Keystone 2 IRQ controller IP which
139 is part of the Keystone 2 IPC mechanism