drivers/iommu/rockchip-iommu.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License version 2 as
   4  * published by the Free Software Foundation.
   5  */
   6
   7 #ifdef CONFIG_ROCKCHIP_IOMMU_DEBUG
   8 #define DEBUG
   9 #endif
  10
  11 #include <linux/io.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/slab.h>
  14 #include <linux/clk.h>
  15 #include <linux/err.h>
  16 #include <linux/mm.h>
  17 #include <linux/errno.h>
  18 #include <linux/memblock.h>
  19 #include <linux/export.h>
  20 #include <linux/module.h>
  21
  22 #include <asm/cacheflush.h>
  23 #include <asm/pgtable.h>
  24 #include <linux/of.h>
  25 #include <linux/rockchip-iovmm.h>
  26
  27 #include "rockchip-iommu.h"
  28
  29 /* We does not consider super section mapping (16MB) */
  30 #define SPAGE_ORDER 12
  31 #define SPAGE_SIZE (1 << SPAGE_ORDER)
  32 #define SPAGE_MASK (~(SPAGE_SIZE - 1))
  33
  34 enum iommu_entry_flags {
  35         IOMMU_FLAGS_PRESENT = 0x01,
  36         IOMMU_FLAGS_READ_PERMISSION = 0x02,
  37         IOMMU_FLAGS_WRITE_PERMISSION = 0x04,
  38         IOMMU_FLAGS_OVERRIDE_CACHE = 0x8,
  39         IOMMU_FLAGS_WRITE_CACHEABLE = 0x10,
  40         IOMMU_FLAGS_WRITE_ALLOCATE = 0x20,
  41         IOMMU_FLAGS_WRITE_BUFFERABLE = 0x40,
  42         IOMMU_FLAGS_READ_CACHEABLE = 0x80,
  43         IOMMU_FLAGS_READ_ALLOCATE = 0x100,
  44         IOMMU_FLAGS_MASK = 0x1FF,
  45 };
  46
  47 #define lv1ent_fault(sent) ((*(sent) & IOMMU_FLAGS_PRESENT) == 0)
  48 #define lv1ent_page(sent) ((*(sent) & IOMMU_FLAGS_PRESENT) == 1)
  49 #define lv2ent_fault(pent) ((*(pent) & IOMMU_FLAGS_PRESENT) == 0)
  50 #define spage_phys(pent) (*(pent) & SPAGE_MASK)
  51 #define spage_offs(iova) ((iova) & 0x0FFF)
  52
  53 #define lv1ent_offset(iova) (((iova)>>22) & 0x03FF)
  54 #define lv2ent_offset(iova) (((iova)>>12) & 0x03FF)
  55
  56 #define NUM_LV1ENTRIES 1024
  57 #define NUM_LV2ENTRIES 1024
  58
  59 #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(long))
  60
  61 #define lv2table_base(sent) (*(sent) & 0xFFFFFFFE)
  62
  63 #define mk_lv1ent_page(pa) ((pa) | IOMMU_FLAGS_PRESENT)
  64 /*write and read permission for level2 page default*/
  65 #define mk_lv2ent_spage(pa) ((pa) | IOMMU_FLAGS_PRESENT | \
  66                              IOMMU_FLAGS_READ_PERMISSION | \
  67                              IOMMU_FLAGS_WRITE_PERMISSION)
  68
  69 #define IOMMU_REG_POLL_COUNT_FAST 1000
  70
  71 /*rk3036:vpu and hevc share ahb interface*/
  72 #define BIT_VCODEC_SEL (1<<3)
  73
  74
  75 /**
  76  * MMU register numbers
  77  * Used in the register read/write routines.
  78  * See the hardware documentation for more information about each register
  79  */
  80 enum iommu_register {
  81         /**< Current Page Directory Pointer */
  82         IOMMU_REGISTER_DTE_ADDR = 0x0000,
  83         /**< Status of the MMU */
  84         IOMMU_REGISTER_STATUS = 0x0004,
  85         /**< Command register, used to control the MMU */
  86         IOMMU_REGISTER_COMMAND = 0x0008,
  87         /**< Logical address of the last page fault */
  88         IOMMU_REGISTER_PAGE_FAULT_ADDR = 0x000C,
  89         /**< Used to invalidate the mapping of a single page from the MMU */
  90         IOMMU_REGISTER_ZAP_ONE_LINE = 0x010,
  91         /**< Raw interrupt status, all interrupts visible */
  92         IOMMU_REGISTER_INT_RAWSTAT = 0x0014,
  93         /**< Indicate to the MMU that the interrupt has been received */
  94         IOMMU_REGISTER_INT_CLEAR = 0x0018,
  95         /**< Enable/disable types of interrupts */
  96         IOMMU_REGISTER_INT_MASK = 0x001C,
  97         /**< Interrupt status based on the mask */
  98         IOMMU_REGISTER_INT_STATUS = 0x0020,
  99         IOMMU_REGISTER_AUTO_GATING = 0x0024
 100 };
 101
 102 enum iommu_command {
 103         /**< Enable paging (memory translation) */
 104         IOMMU_COMMAND_ENABLE_PAGING = 0x00,
 105         /**< Disable paging (memory translation) */
 106         IOMMU_COMMAND_DISABLE_PAGING = 0x01,
 107         /**<  Enable stall on page fault */
 108         IOMMU_COMMAND_ENABLE_STALL = 0x02,
 109         /**< Disable stall on page fault */
 110         IOMMU_COMMAND_DISABLE_STALL = 0x03,
 111         /**< Zap the entire page table cache */
 112         IOMMU_COMMAND_ZAP_CACHE = 0x04,
 113         /**< Page fault processed */
 114         IOMMU_COMMAND_PAGE_FAULT_DONE = 0x05,
 115         /**< Reset the MMU back to power-on settings */
 116         IOMMU_COMMAND_HARD_RESET = 0x06
 117 };
 118
 119 /**
 120  * MMU interrupt register bits
 121  * Each cause of the interrupt is reported
 122  * through the (raw) interrupt status registers.
 123  * Multiple interrupts can be pending, so multiple bits
 124  * can be set at once.
 125  */
 126 enum iommu_interrupt {
 127         IOMMU_INTERRUPT_PAGE_FAULT = 0x01, /**< A page fault occured */
 128         IOMMU_INTERRUPT_READ_BUS_ERROR = 0x02 /**< A bus read error occured */
 129 };
 130
 131 enum iommu_status_bits {
 132         IOMMU_STATUS_BIT_PAGING_ENABLED      = 1 << 0,
 133         IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE   = 1 << 1,
 134         IOMMU_STATUS_BIT_STALL_ACTIVE        = 1 << 2,
 135         IOMMU_STATUS_BIT_IDLE                = 1 << 3,
 136         IOMMU_STATUS_BIT_REPLAY_BUFFER_EMPTY = 1 << 4,
 137         IOMMU_STATUS_BIT_PAGE_FAULT_IS_WRITE = 1 << 5,
 138         IOMMU_STATUS_BIT_STALL_NOT_ACTIVE    = 1 << 31,
 139 };
 140
 141 /**
 142  * Size of an MMU page in bytes
 143  */
 144 #define IOMMU_PAGE_SIZE 0x1000
 145
 146 /*
 147  * Size of the address space referenced by a page table page
 148  */
 149 #define IOMMU_VIRTUAL_PAGE_SIZE 0x400000 /* 4 MiB */
 150
 151 /**
 152  * Page directory index from address
 153  * Calculates the page directory index from the given address
 154  */
 155 #define IOMMU_PDE_ENTRY(address) (((address)>>22) & 0x03FF)
 156
 157 /**
 158  * Page table index from address
 159  * Calculates the page table index from the given address
 160  */
 161 #define IOMMU_PTE_ENTRY(address) (((address)>>12) & 0x03FF)
 162
 163 /**
 164  * Extract the memory address from an PDE/PTE entry
 165  */
 166 #define IOMMU_ENTRY_ADDRESS(value) ((value) & 0xFFFFFC00)
 167
 168 #define INVALID_PAGE ((u32)(~0))
 169
 170 static struct kmem_cache *lv2table_kmem_cache;
 171
 172 static unsigned long *section_entry(unsigned long *pgtable, unsigned long iova)
 173 {
 174         return pgtable + lv1ent_offset(iova);
 175 }
 176
 177 static unsigned long *page_entry(unsigned long *sent, unsigned long iova)
 178 {
 179         return (unsigned long *)__va(lv2table_base(sent)) + lv2ent_offset(iova);
 180 }
 181
 182 static char *iommu_fault_name[IOMMU_FAULTS_NUM] = {
 183         "PAGE FAULT",
 184         "BUS ERROR",
 185         "UNKNOWN FAULT"
 186 };
 187
 188 struct rk_iommu_domain {
 189         struct list_head clients; /* list of iommu_drvdata.node */
 190         unsigned long *pgtable; /* lv1 page table, 4KB */
 191         short *lv2entcnt; /* free lv2 entry counter for each section */
 192         spinlock_t lock; /* lock for this structure */
 193         spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
 194 };
 195
 196 static bool set_iommu_active(struct iommu_drvdata *data)
 197 {
 198         /* return true if the IOMMU was not active previously
 199            and it needs to be initialized */
 200         return ++data->activations == 1;
 201 }
 202
 203 static bool set_iommu_inactive(struct iommu_drvdata *data)
 204 {
 205         /* return true if the IOMMU is needed to be disabled */
 206         BUG_ON(data->activations < 1);
 207         return --data->activations == 0;
 208 }
 209
 210 static bool is_iommu_active(struct iommu_drvdata *data)
 211 {
 212         return data->activations > 0;
 213 }
 214
 215 static void iommu_disable_stall(void __iomem *base)
 216 {
 217         int i;
 218         u32 mmu_status = __raw_readl(base + IOMMU_REGISTER_STATUS);
 219
 220         if (0 == (mmu_status & IOMMU_STATUS_BIT_PAGING_ENABLED))
 221                 return;
 222         if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE) {
 223                 pr_err("Aborting MMU disable stall request since it is in pagefault state.\n");
 224                 return;
 225         }
 226         __raw_writel(IOMMU_COMMAND_DISABLE_STALL,
 227                      base + IOMMU_REGISTER_COMMAND);
 228
 229         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 230                 u32 status = __raw_readl(base + IOMMU_REGISTER_STATUS);
 231
 232                 if (0 == (status & IOMMU_STATUS_BIT_STALL_ACTIVE))
 233                         break;
 234                 if (status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE)
 235                         break;
 236                 if (0 == (mmu_status & IOMMU_STATUS_BIT_PAGING_ENABLED))
 237                         break;
 238         }
 239         if (IOMMU_REG_POLL_COUNT_FAST == i)
 240                 pr_err("Disable stall request failed, MMU status is 0x%08X\n",
 241                        __raw_readl(base + IOMMU_REGISTER_STATUS));
 242 }
 243
 244 static bool iommu_enable_stall(void __iomem *base)
 245 {
 246         int i;
 247
 248         u32 mmu_status = __raw_readl(base + IOMMU_REGISTER_STATUS);
 249
 250         if (0 == (mmu_status & IOMMU_STATUS_BIT_PAGING_ENABLED))
 251                 return true;
 252         if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE) {
 253                 pr_err("Aborting MMU stall request since it is in pagefault state.\n");
 254                 return false;
 255         }
 256         __raw_writel(IOMMU_COMMAND_ENABLE_STALL,
 257                      base + IOMMU_REGISTER_COMMAND);
 258
 259         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 260                 mmu_status = __raw_readl(base + IOMMU_REGISTER_STATUS);
 261                 if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE)
 262                         break;
 263                 if ((mmu_status & IOMMU_STATUS_BIT_STALL_ACTIVE) &&
 264                     (0 == (mmu_status & IOMMU_STATUS_BIT_STALL_NOT_ACTIVE)))
 265                         break;
 266                 if (0 == (mmu_status & (IOMMU_STATUS_BIT_PAGING_ENABLED)))
 267                         break;
 268         }
 269         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 270                 pr_err("Enable stall request failed, MMU status is 0x%08X\n",
 271                        __raw_readl(base + IOMMU_REGISTER_STATUS));
 272                 return false;
 273         }
 274         if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE) {
 275                 pr_err("Aborting MMU stall request since it has a pagefault.\n");
 276                 return false;
 277         }
 278         return true;
 279 }
 280
 281 static bool iommu_enable_paging(void __iomem *base)
 282 {
 283         int i;
 284
 285         __raw_writel(IOMMU_COMMAND_ENABLE_PAGING,
 286                      base + IOMMU_REGISTER_COMMAND);
 287
 288         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 289                 if (__raw_readl(base + IOMMU_REGISTER_STATUS) &
 290                                 IOMMU_STATUS_BIT_PAGING_ENABLED)
 291                         break;
 292         }
 293         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 294                 pr_err("Enable paging request failed, MMU status is 0x%08X\n",
 295                        __raw_readl(base + IOMMU_REGISTER_STATUS));
 296                 return false;
 297         }
 298         return true;
 299 }
 300
 301 static bool iommu_disable_paging(void __iomem *base)
 302 {
 303         int i;
 304
 305         __raw_writel(IOMMU_COMMAND_DISABLE_PAGING,
 306                      base + IOMMU_REGISTER_COMMAND);
 307
 308         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 309                 if (!(__raw_readl(base + IOMMU_REGISTER_STATUS) &
 310                                   IOMMU_STATUS_BIT_PAGING_ENABLED))
 311                         break;
 312         }
 313         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 314                 pr_err("Disable paging request failed, MMU status is 0x%08X\n",
 315                        __raw_readl(base + IOMMU_REGISTER_STATUS));
 316                 return false;
 317         }
 318         return true;
 319 }
 320
 321 static void iommu_page_fault_done(void __iomem *base, const char *dbgname)
 322 {
 323         pr_info("MMU: %s: Leaving page fault mode\n",
 324                 dbgname);
 325         __raw_writel(IOMMU_COMMAND_PAGE_FAULT_DONE,
 326                      base + IOMMU_REGISTER_COMMAND);
 327 }
 328
 329 static bool iommu_zap_tlb(void __iomem *base)
 330 {
 331         bool stall_success = iommu_enable_stall(base);
 332
 333         __raw_writel(IOMMU_COMMAND_ZAP_CACHE,
 334                      base + IOMMU_REGISTER_COMMAND);
 335         if (!stall_success)
 336                 return false;
 337         iommu_disable_stall(base);
 338         return true;
 339 }
 340
 341 static inline bool iommu_raw_reset(void __iomem *base)
 342 {
 343         int i;
 344
 345         __raw_writel(0xCAFEBABE, base + IOMMU_REGISTER_DTE_ADDR);
 346
 347         if (!(0xCAFEB000 == __raw_readl(base + IOMMU_REGISTER_DTE_ADDR))) {
 348                 pr_err("error when %s.\n", __func__);
 349                 return false;
 350         }
 351         __raw_writel(IOMMU_COMMAND_HARD_RESET,
 352                      base + IOMMU_REGISTER_COMMAND);
 353
 354         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 355                 if (__raw_readl(base + IOMMU_REGISTER_DTE_ADDR) == 0)
 356                         break;
 357         }
 358         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 359                 pr_err("%s,Reset request failed, MMU status is 0x%08X\n",
 360                        __func__, __raw_readl(base + IOMMU_REGISTER_DTE_ADDR));
 361                 return false;
 362         }
 363         return true;
 364 }
 365
 366 static void __iommu_set_ptbase(void __iomem *base, unsigned long pgd)
 367 {
 368         __raw_writel(pgd, base + IOMMU_REGISTER_DTE_ADDR);
 369 }
 370
 371 static bool iommu_reset(void __iomem *base, const char *dbgname)
 372 {
 373         bool err = true;
 374
 375         err = iommu_enable_stall(base);
 376         if (!err) {
 377                 pr_err("%s:stall failed: %s\n", __func__, dbgname);
 378                 return err;
 379         }
 380         err = iommu_raw_reset(base);
 381         if (err)
 382                 __raw_writel(IOMMU_INTERRUPT_PAGE_FAULT |
 383                              IOMMU_INTERRUPT_READ_BUS_ERROR,
 384                              base+IOMMU_REGISTER_INT_MASK);
 385         iommu_disable_stall(base);
 386         if (!err)
 387                 pr_err("%s: failed: %s\n", __func__, dbgname);
 388         return err;
 389 }
 390
 391 static inline void pgtable_flush(void *vastart, void *vaend)
 392 {
 393         dmac_flush_range(vastart, vaend);
 394         outer_flush_range(virt_to_phys(vastart), virt_to_phys(vaend));
 395 }
 396
 397 static void set_fault_handler(struct iommu_drvdata *data,
 398                                 rockchip_iommu_fault_handler_t handler)
 399 {
 400         unsigned long flags;
 401
 402         write_lock_irqsave(&data->lock, flags);
 403         data->fault_handler = handler;
 404         write_unlock_irqrestore(&data->lock, flags);
 405 }
 406
 407 static int default_fault_handler(struct device *dev,
 408                                  enum rk_iommu_inttype itype,
 409                                  unsigned long pgtable_base,
 410                                  unsigned long fault_addr,
 411                                  unsigned int status)
 412 {
 413         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 414
 415         if (!data) {
 416                 pr_err("%s,iommu device not assigned yet\n", __func__);
 417                 return 0;
 418         }
 419         if ((itype >= IOMMU_FAULTS_NUM) || (itype < IOMMU_PAGEFAULT))
 420                 itype = IOMMU_FAULT_UNKNOWN;
 421
 422         if (itype == IOMMU_BUSERROR)
 423                 pr_err("%s occured at 0x%lx(Page table base: 0x%lx)\n",
 424                        iommu_fault_name[itype], fault_addr, pgtable_base);
 425
 426         if (itype == IOMMU_PAGEFAULT)
 427                 pr_err("IOMMU:Page fault detected at 0x%lx from bus id %d of type %s on %s\n",
 428                        fault_addr,
 429                        (status >> 6) & 0x1F,
 430                        (status & 32) ? "write" : "read",
 431                        data->dbgname);
 432
 433         pr_err("Generating Kernel OOPS... because it is unrecoverable.\n");
 434
 435         BUG();
 436
 437         return 0;
 438 }
 439
 440 static void dump_pagetbl(u32 fault_address, u32 addr_dte)
 441 {
 442         u32 lv1_offset;
 443         u32 lv2_offset;
 444
 445         u32 *lv1_entry_pa;
 446         u32 *lv1_entry_va;
 447         u32 *lv1_entry_value;
 448
 449         u32 *lv2_base;
 450         u32 *lv2_entry_pa;
 451         u32 *lv2_entry_va;
 452         u32 *lv2_entry_value;
 453
 454
 455         lv1_offset = lv1ent_offset(fault_address);
 456         lv2_offset = lv2ent_offset(fault_address);
 457
 458         lv1_entry_pa = (u32 *)addr_dte + lv1_offset;
 459         lv1_entry_va = (u32 *)(__va(addr_dte)) + lv1_offset;
 460         lv1_entry_value = (u32 *)(*lv1_entry_va);
 461
 462         lv2_base = (u32 *)((*lv1_entry_va) & 0xfffffffe);
 463         lv2_entry_pa = (u32 *)lv2_base + lv2_offset;
 464         lv2_entry_va = (u32 *)(__va(lv2_base)) + lv2_offset;
 465         lv2_entry_value = (u32 *)(*lv2_entry_va);
 466
 467         pr_info("fault address = 0x%08x,dte addr pa = 0x%08x,va = 0x%08x\n",
 468                 fault_address, addr_dte, (u32)__va(addr_dte));
 469         pr_info("lv1_offset = 0x%x,lv1_entry_pa = 0x%08x,lv1_entry_va = 0x%08x\n",
 470                 lv1_offset, (u32)lv1_entry_pa, (u32)lv1_entry_va);
 471         pr_info("lv1_entry_value(*lv1_entry_va) = 0x%08x,lv2_base = 0x%08x\n",
 472                 (u32)lv1_entry_value, (u32)lv2_base);
 473         pr_info("lv2_offset = 0x%x,lv2_entry_pa = 0x%08x,lv2_entry_va = 0x%08x\n",
 474                 lv2_offset, (u32)lv2_entry_pa, (u32)lv2_entry_va);
 475         pr_info("lv2_entry value(*lv2_entry_va) = 0x%08x\n",
 476                 (u32)lv2_entry_value);
 477 }
 478
 479 static irqreturn_t rockchip_iommu_irq(int irq, void *dev_id)
 480 {
 481         /* SYSMMU is in blocked when interrupt occurred. */
 482         struct iommu_drvdata *data = dev_id;
 483         struct resource *irqres;
 484         struct platform_device *pdev;
 485         enum rk_iommu_inttype itype = IOMMU_FAULT_UNKNOWN;
 486         u32 status;
 487         u32 rawstat;
 488         u32 int_status;
 489         u32 fault_address;
 490         int i, ret = 0;
 491
 492         read_lock(&data->lock);
 493
 494         if (!is_iommu_active(data)) {
 495                 read_unlock(&data->lock);
 496                 return IRQ_HANDLED;
 497         }
 498         pdev = to_platform_device(data->iommu);
 499
 500         for (i = 0; i < data->num_res_irq; i++) {
 501                 irqres = platform_get_resource(pdev, IORESOURCE_IRQ, i);
 502                 if (irqres && ((int)irqres->start == irq))
 503                         break;
 504         }
 505
 506         if (i == data->num_res_irq) {
 507                 itype = IOMMU_FAULT_UNKNOWN;
 508         } else {
 509                 int_status = __raw_readl(data->res_bases[i] +
 510                                          IOMMU_REGISTER_INT_STATUS);
 511
 512                 if (int_status != 0) {
 513                         /*mask status*/
 514                         __raw_writel(0x00, data->res_bases[i] +
 515                                      IOMMU_REGISTER_INT_MASK);
 516
 517                         rawstat = __raw_readl(data->res_bases[i] +
 518                                               IOMMU_REGISTER_INT_RAWSTAT);
 519
 520                         if (rawstat & IOMMU_INTERRUPT_PAGE_FAULT) {
 521                                 fault_address = __raw_readl(data->res_bases[i] +
 522                                 IOMMU_REGISTER_PAGE_FAULT_ADDR);
 523                                 itype = IOMMU_PAGEFAULT;
 524                         } else if (rawstat & IOMMU_INTERRUPT_READ_BUS_ERROR) {
 525                                 itype = IOMMU_BUSERROR;
 526                         } else {
 527                                 goto out;
 528                         }
 529                         dump_pagetbl(fault_address,
 530                                      __raw_readl(data->res_bases[i] +
 531                                      IOMMU_REGISTER_DTE_ADDR));
 532                 } else {
 533                         goto out;
 534                 }
 535         }
 536
 537         if (data->fault_handler) {
 538                 unsigned long base = __raw_readl(data->res_bases[i] +
 539                                                  IOMMU_REGISTER_DTE_ADDR);
 540                 status = __raw_readl(data->res_bases[i] +
 541                                      IOMMU_REGISTER_STATUS);
 542                 ret = data->fault_handler(data->dev, itype, base,
 543                                           fault_address, status);
 544         }
 545
 546         if (!ret && (itype != IOMMU_FAULT_UNKNOWN)) {
 547                 if (IOMMU_PAGEFAULT == itype) {
 548                         iommu_zap_tlb(data->res_bases[i]);
 549                         iommu_page_fault_done(data->res_bases[i],
 550                                                data->dbgname);
 551                         __raw_writel(IOMMU_INTERRUPT_PAGE_FAULT |
 552                                      IOMMU_INTERRUPT_READ_BUS_ERROR,
 553                                      data->res_bases[i] +
 554                                      IOMMU_REGISTER_INT_MASK);
 555                 }
 556         } else {
 557                 pr_err("(%s) %s is not handled.\n",
 558                        data->dbgname, iommu_fault_name[itype]);
 559         }
 560
 561 out:
 562         read_unlock(&data->lock);
 563
 564         return IRQ_HANDLED;
 565 }
 566
 567 static bool __rockchip_iommu_disable(struct iommu_drvdata *data)
 568 {
 569         unsigned long flags;
 570         int i;
 571         bool disabled = false;
 572
 573         write_lock_irqsave(&data->lock, flags);
 574
 575         if (!set_iommu_inactive(data))
 576                 goto finish;
 577
 578         for (i = 0; i < data->num_res_mem; i++)
 579                 iommu_disable_paging(data->res_bases[i]);
 580
 581         disabled = true;
 582         data->pgtable = 0;
 583         data->domain = NULL;
 584 finish:
 585         write_unlock_irqrestore(&data->lock, flags);
 586
 587         if (disabled)
 588                 pr_info("(%s) Disabled\n", data->dbgname);
 589         else
 590                 pr_info("(%s) %d times left to be disabled\n",
 591                         data->dbgname, data->activations);
 592
 593         return disabled;
 594 }
 595
 596 /* __rk_sysmmu_enable: Enables System MMU
 597  *
 598  * returns -error if an error occurred and System MMU is not enabled,
 599  * 0 if the System MMU has been just enabled and 1 if System MMU was already
 600  * enabled before.
 601  */
 602 static int __rockchip_iommu_enable(struct iommu_drvdata *data,
 603                                     unsigned long pgtable,
 604                                     struct iommu_domain *domain)
 605 {
 606         int i, ret = 0;
 607         unsigned long flags;
 608
 609         write_lock_irqsave(&data->lock, flags);
 610
 611         if (!set_iommu_active(data)) {
 612                 if (WARN_ON(pgtable != data->pgtable)) {
 613                         ret = -EBUSY;
 614                         set_iommu_inactive(data);
 615                 } else {
 616                         ret = 1;
 617                 }
 618
 619                 pr_info("(%s) Already enabled\n", data->dbgname);
 620                 goto finish;
 621         }
 622
 623         data->pgtable = pgtable;
 624
 625         for (i = 0; i < data->num_res_mem; i++) {
 626                 bool status;
 627
 628                 status = iommu_enable_stall(data->res_bases[i]);
 629                 if (status) {
 630                         __iommu_set_ptbase(data->res_bases[i], pgtable);
 631                         __raw_writel(IOMMU_COMMAND_ZAP_CACHE,
 632                                      data->res_bases[i] +
 633                                      IOMMU_REGISTER_COMMAND);
 634                 }
 635                 __raw_writel(IOMMU_INTERRUPT_PAGE_FAULT |
 636                              IOMMU_INTERRUPT_READ_BUS_ERROR,
 637                              data->res_bases[i]+IOMMU_REGISTER_INT_MASK);
 638                 iommu_enable_paging(data->res_bases[i]);
 639                 iommu_disable_stall(data->res_bases[i]);
 640         }
 641
 642         data->domain = domain;
 643
 644         pr_info("(%s) Enabled\n", data->dbgname);
 645 finish:
 646         write_unlock_irqrestore(&data->lock, flags);
 647
 648         return ret;
 649 }
 650
 651 bool rockchip_iommu_disable(struct device *dev)
 652 {
 653         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 654         bool disabled;
 655
 656         disabled = __rockchip_iommu_disable(data);
 657
 658         return disabled;
 659 }
 660
 661 void rockchip_iommu_tlb_invalidate(struct device *dev)
 662 {
 663         unsigned long flags;
 664         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 665
 666         read_lock_irqsave(&data->lock, flags);
 667         if (is_iommu_active(data)) {
 668                 int i;
 669
 670                 for (i = 0; i < data->num_res_mem; i++) {
 671                         if (!iommu_zap_tlb(data->res_bases[i]))
 672                                 pr_err("%s,invalidating TLB failed\n",
 673                                        data->dbgname);
 674                 }
 675         } else {
 676                 pr_info("(%s) Disabled. Skipping invalidating TLB.\n",
 677                         data->dbgname);
 678         }
 679
 680         read_unlock_irqrestore(&data->lock, flags);
 681 }
 682
 683 static phys_addr_t rockchip_iommu_iova_to_phys(struct iommu_domain *domain,
 684                                                dma_addr_t iova)
 685 {
 686         struct rk_iommu_domain *priv = domain->priv;
 687         unsigned long *entry;
 688         unsigned long flags;
 689         phys_addr_t phys = 0;
 690
 691         spin_lock_irqsave(&priv->pgtablelock, flags);
 692
 693         entry = section_entry(priv->pgtable, iova);
 694         entry = page_entry(entry, iova);
 695         phys = spage_phys(entry) + spage_offs(iova);
 696
 697         spin_unlock_irqrestore(&priv->pgtablelock, flags);
 698
 699         return phys;
 700 }
 701
 702 static int lv2set_page(unsigned long *pent, phys_addr_t paddr,
 703                        size_t size, short *pgcnt)
 704 {
 705         if (!lv2ent_fault(pent))
 706                 return -EADDRINUSE;
 707
 708         *pent = mk_lv2ent_spage(paddr);
 709         pgtable_flush(pent, pent + 1);
 710         *pgcnt -= 1;
 711         return 0;
 712 }
 713
 714 static unsigned long *alloc_lv2entry(unsigned long *sent,
 715                                      unsigned long iova, short *pgcounter)
 716 {
 717         if (lv1ent_fault(sent)) {
 718                 unsigned long *pent;
 719
 720                 pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
 721                 BUG_ON((unsigned long)pent & (LV2TABLE_SIZE - 1));
 722                 if (!pent)
 723                         return NULL;
 724
 725                 *sent = mk_lv1ent_page(__pa(pent));
 726                 kmemleak_ignore(pent);
 727                 *pgcounter = NUM_LV2ENTRIES;
 728                 pgtable_flush(pent, pent + NUM_LV2ENTRIES);
 729                 pgtable_flush(sent, sent + 1);
 730         }
 731         return page_entry(sent, iova);
 732 }
 733
 734 static size_t rockchip_iommu_unmap(struct iommu_domain *domain,
 735                                    unsigned long iova, size_t size)
 736 {
 737         struct rk_iommu_domain *priv = domain->priv;
 738         unsigned long flags;
 739         unsigned long *ent;
 740
 741         BUG_ON(priv->pgtable == NULL);
 742
 743         spin_lock_irqsave(&priv->pgtablelock, flags);
 744
 745         ent = section_entry(priv->pgtable, iova);
 746
 747         if (unlikely(lv1ent_fault(ent))) {
 748                 if (size > SPAGE_SIZE)
 749                         size = SPAGE_SIZE;
 750                 goto done;
 751         }
 752
 753         /* lv1ent_page(sent) == true here */
 754
 755         ent = page_entry(ent, iova);
 756
 757         if (unlikely(lv2ent_fault(ent))) {
 758                 size = SPAGE_SIZE;
 759                 goto done;
 760         }
 761
 762         *ent = 0;
 763         size = SPAGE_SIZE;
 764         priv->lv2entcnt[lv1ent_offset(iova)] += 1;
 765         goto done;
 766
 767 done:
 768         /*pr_info("%s:unmap iova 0x%lx/0x%x bytes\n",
 769                   __func__, iova,size);
 770         */
 771         spin_unlock_irqrestore(&priv->pgtablelock, flags);
 772
 773         return size;
 774 }
 775
 776 static int rockchip_iommu_map(struct iommu_domain *domain, unsigned long iova,
 777                               phys_addr_t paddr, size_t size, int prot)
 778 {
 779         struct rk_iommu_domain *priv = domain->priv;
 780         unsigned long *entry;
 781         unsigned long flags;
 782         int ret = -ENOMEM;
 783         unsigned long *pent;
 784
 785         BUG_ON(priv->pgtable == NULL);
 786
 787         spin_lock_irqsave(&priv->pgtablelock, flags);
 788
 789         entry = section_entry(priv->pgtable, iova);
 790
 791         pent = alloc_lv2entry(entry, iova,
 792                               &priv->lv2entcnt[lv1ent_offset(iova)]);
 793         if (!pent)
 794                 ret = -ENOMEM;
 795         else
 796                 ret = lv2set_page(pent, paddr, size,
 797                                   &priv->lv2entcnt[lv1ent_offset(iova)]);
 798
 799         if (ret) {
 800                 pr_err("%s: Failed to map iova 0x%lx/0x%x bytes\n", __func__,
 801                        iova, size);
 802         }
 803         spin_unlock_irqrestore(&priv->pgtablelock, flags);
 804
 805         return ret;
 806 }
 807
 808 static void rockchip_iommu_detach_device(struct iommu_domain *domain,
 809                                          struct device *dev)
 810 {
 811         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 812         struct rk_iommu_domain *priv = domain->priv;
 813         struct list_head *pos;
 814         unsigned long flags;
 815         bool found = false;
 816
 817         spin_lock_irqsave(&priv->lock, flags);
 818
 819         list_for_each(pos, &priv->clients)
 820         {
 821                 if (list_entry(pos, struct iommu_drvdata, node) == data) {
 822                         found = true;
 823                         break;
 824                 }
 825         }
 826         if (!found)
 827                 goto finish;
 828         if (__rockchip_iommu_disable(data)) {
 829                 pr_info("%s: Detached IOMMU with pgtable %#lx\n",
 830                         __func__, __pa(priv->pgtable));
 831                 list_del(&data->node);
 832                 INIT_LIST_HEAD(&data->node);
 833
 834         } else
 835                 pr_info("%s: Detaching IOMMU with pgtable %#lx delayed",
 836                         __func__, __pa(priv->pgtable));
 837
 838 finish:
 839         spin_unlock_irqrestore(&priv->lock, flags);
 840 }
 841
 842 static int rockchip_iommu_attach_device(struct iommu_domain *domain,
 843                                         struct device *dev)
 844 {
 845         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 846         struct rk_iommu_domain *priv = domain->priv;
 847         unsigned long flags;
 848         int ret;
 849
 850         spin_lock_irqsave(&priv->lock, flags);
 851         ret = __rockchip_iommu_enable(data, __pa(priv->pgtable), domain);
 852
 853         if (ret == 0) {
 854                 /* 'data->node' must not be appeared in priv->clients */
 855                 BUG_ON(!list_empty(&data->node));
 856                 data->dev = dev;
 857                 list_add_tail(&data->node, &priv->clients);
 858         }
 859
 860         spin_unlock_irqrestore(&priv->lock, flags);
 861
 862         if (ret < 0) {
 863                 pr_err("%s: Failed to attach IOMMU with pgtable %#lx\n",
 864                        __func__, __pa(priv->pgtable));
 865         } else if (ret > 0) {
 866                 pr_info("%s: IOMMU with pgtable 0x%lx already attached\n",
 867                         __func__, __pa(priv->pgtable));
 868         } else {
 869                 pr_info("%s: Attached new IOMMU with pgtable 0x%lx\n",
 870                         __func__, __pa(priv->pgtable));
 871         }
 872
 873         return ret;
 874 }
 875
 876 static void rockchip_iommu_domain_destroy(struct iommu_domain *domain)
 877 {
 878         struct rk_iommu_domain *priv = domain->priv;
 879         struct iommu_drvdata *data;
 880         unsigned long flags;
 881         int i;
 882
 883         WARN_ON(!list_empty(&priv->clients));
 884
 885         spin_lock_irqsave(&priv->lock, flags);
 886
 887         list_for_each_entry(data, &priv->clients, node) {
 888                 while (!rockchip_iommu_disable(data->dev))
 889                         ; /* until System MMU is actually disabled */
 890         }
 891         spin_unlock_irqrestore(&priv->lock, flags);
 892
 893         for (i = 0; i < NUM_LV1ENTRIES; i++)
 894                 if (lv1ent_page(priv->pgtable + i))
 895                         kmem_cache_free(lv2table_kmem_cache,
 896                                         __va(lv2table_base(priv->pgtable + i)));
 897
 898         free_pages((unsigned long)priv->pgtable, 0);
 899         free_pages((unsigned long)priv->lv2entcnt, 0);
 900         kfree(domain->priv);
 901         domain->priv = NULL;
 902 }
 903
 904 static int rockchip_iommu_domain_init(struct iommu_domain *domain)
 905 {
 906         struct rk_iommu_domain *priv;
 907
 908         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 909         if (!priv)
 910                 return -ENOMEM;
 911
 912 /*rk32xx iommu use 2 level pagetable,
 913    level1 and leve2 both have 1024 entries,each entry  occupy 4 bytes,
 914    so alloc a page size for each page table
 915 */
 916         priv->pgtable = (unsigned long *)__get_free_pages(GFP_KERNEL |
 917                                                           __GFP_ZERO, 0);
 918         if (!priv->pgtable)
 919                 goto err_pgtable;
 920
 921         priv->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL |
 922                                                     __GFP_ZERO, 0);
 923         if (!priv->lv2entcnt)
 924                 goto err_counter;
 925
 926         pgtable_flush(priv->pgtable, priv->pgtable + NUM_LV1ENTRIES);
 927
 928         spin_lock_init(&priv->lock);
 929         spin_lock_init(&priv->pgtablelock);
 930         INIT_LIST_HEAD(&priv->clients);
 931
 932         domain->priv = priv;
 933         return 0;
 934
 935 err_counter:
 936         free_pages((unsigned long)priv->pgtable, 0);
 937 err_pgtable:
 938         kfree(priv);
 939         return -ENOMEM;
 940 }
 941
 942 static struct iommu_ops rk_iommu_ops = {
 943         .domain_init = &rockchip_iommu_domain_init,
 944         .domain_destroy = &rockchip_iommu_domain_destroy,
 945         .attach_dev = &rockchip_iommu_attach_device,
 946         .detach_dev = &rockchip_iommu_detach_device,
 947         .map = &rockchip_iommu_map,
 948         .unmap = &rockchip_iommu_unmap,
 949         .iova_to_phys = &rockchip_iommu_iova_to_phys,
 950         .pgsize_bitmap = SPAGE_SIZE,
 951 };
 952
 953 static int rockchip_iommu_prepare(void)
 954 {
 955         int ret = 0;
 956         static int registed;
 957
 958         if (registed)
 959                 return 0;
 960
 961         lv2table_kmem_cache = kmem_cache_create("rk-iommu-lv2table",
 962                                                 LV2TABLE_SIZE,
 963                                                 LV2TABLE_SIZE,
 964                                                 0, NULL);
 965         if (!lv2table_kmem_cache) {
 966                 pr_err("%s: failed to create kmem cache\n", __func__);
 967                 return -ENOMEM;
 968         }
 969         ret = bus_set_iommu(&platform_bus_type, &rk_iommu_ops);
 970         if (!ret)
 971                 registed = 1;
 972         else
 973                 pr_err("%s:failed to set iommu to bus\r\n", __func__);
 974         return ret;
 975 }
 976
 977 static int  rockchip_get_iommu_resource_num(struct platform_device *pdev,
 978                                              unsigned int type)
 979 {
 980         struct resource *info = NULL;
 981         int num_resources = 0;
 982
 983         /*get resouce info*/
 984 again:
 985         info = platform_get_resource(pdev, type, num_resources);
 986         while (info) {
 987                 num_resources++;
 988                 goto again;
 989         }
 990         return num_resources;
 991 }
 992
 993 static struct kobject *dump_mmu_object;
 994
 995 static int dump_mmu_pagetbl(struct device *dev, struct device_attribute *attr,
 996                             const char *buf, u32 count)
 997 {
 998         u32 fault_address;
 999         u32 iommu_dte;
1000         u32 mmu_base;
1001         void __iomem *base;
1002         u32 ret;
1003
1004         ret = kstrtouint(buf, 0, &mmu_base);
1005         if (ret)
1006                 pr_info("%s is not in hexdecimal form.\n", buf);
1007         base = ioremap(mmu_base, 0x100);
1008         iommu_dte = __raw_readl(base + IOMMU_REGISTER_DTE_ADDR);
1009         fault_address = __raw_readl(base + IOMMU_REGISTER_PAGE_FAULT_ADDR);
1010         dump_pagetbl(fault_address, iommu_dte);
1011         return count;
1012 }
1013
1014 static DEVICE_ATTR(dump_mmu_pgtable, 0644, NULL, dump_mmu_pagetbl);
1015
1016 void dump_iommu_sysfs_init(void)
1017 {
1018         u32 ret;
1019
1020         dump_mmu_object = kobject_create_and_add("rk_iommu", NULL);
1021         if (dump_mmu_object == NULL)
1022                 return;
1023         ret = sysfs_create_file(dump_mmu_object,
1024                                 &dev_attr_dump_mmu_pgtable.attr);
1025 }
1026
1027 static int rockchip_iommu_probe(struct platform_device *pdev)
1028 {
1029         int i, ret;
1030         struct device *dev;
1031         struct iommu_drvdata *data;
1032
1033         dev = &pdev->dev;
1034
1035         ret = rockchip_iommu_prepare();
1036         if (ret) {
1037                 pr_err("%s,failed\r\n", __func__);
1038                 goto err_alloc;
1039         }
1040
1041         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
1042         if (!data) {
1043                 dev_dbg(dev, "Not enough memory\n");
1044                 ret = -ENOMEM;
1045                 goto err_alloc;
1046         }
1047         dev_set_drvdata(dev, data);
1048 /*
1049         ret = dev_set_drvdata(dev, data);
1050         if (ret)
1051         {
1052                 dev_dbg(dev, "Unabled to initialize driver data\n");
1053                 goto err_init;
1054         }
1055 */
1056         if (pdev->dev.of_node) {
1057                 of_property_read_string(pdev->dev.of_node,
1058                                         "dbgname", &(data->dbgname));
1059         } else {
1060                 pr_info("dbgname not assigned in device tree or device node not exist\r\n");
1061         }
1062
1063         pr_info("(%s) Enter\n", data->dbgname);
1064
1065         data->num_res_mem = rockchip_get_iommu_resource_num(pdev,
1066                                 IORESOURCE_MEM);
1067         if (0 == data->num_res_mem) {
1068                 pr_err("can't find iommu memory resource \r\n");
1069                 goto err_init;
1070         }
1071         pr_info("data->num_res_mem=%d\n", data->num_res_mem);
1072         data->num_res_irq = rockchip_get_iommu_resource_num(pdev,
1073                                 IORESOURCE_IRQ);
1074         if (0 == data->num_res_irq) {
1075                 pr_err("can't find iommu irq resource \r\n");
1076                 goto err_init;
1077         }
1078
1079         data->res_bases = kmalloc_array(data->num_res_mem,
1080                                 sizeof(*data->res_bases), GFP_KERNEL);
1081         if (data->res_bases == NULL) {
1082                 dev_dbg(dev, "Not enough memory\n");
1083                 ret = -ENOMEM;
1084                 goto err_init;
1085         }
1086
1087         for (i = 0; i < data->num_res_mem; i++) {
1088                 struct resource *res;
1089
1090                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1091                 if (!res) {
1092                         pr_err("Unable to find IOMEM region\n");
1093                         ret = -ENOENT;
1094                         goto err_res;
1095                 }
1096                 data->res_bases[i] = ioremap(res->start, resource_size(res));
1097                 pr_info("res->start = 0x%08x  ioremap to  data->res_bases[%d] = 0x%08x\n",
1098                         res->start, i, (unsigned int)data->res_bases[i]);
1099                 if (!data->res_bases[i]) {
1100                         pr_err("Unable to map IOMEM @ PA:%#x\n", res->start);
1101                         ret = -ENOENT;
1102                         goto err_res;
1103                 }
1104                 if (!strstr(data->dbgname, "isp")) {
1105                         if (!iommu_reset(data->res_bases[i], data->dbgname)) {
1106                                 ret = -ENOENT;
1107                                 goto err_res;
1108                         }
1109                 }
1110         }
1111
1112         for (i = 0; i < data->num_res_irq; i++) {
1113                 ret = platform_get_irq(pdev, i);
1114                 if (ret <= 0) {
1115                         pr_err("Unable to find IRQ resource\n");
1116                         goto err_irq;
1117                 }
1118                 ret = request_irq(ret, rockchip_iommu_irq,
1119                                   IRQF_SHARED, dev_name(dev), data);
1120                 if (ret) {
1121                         pr_err("Unabled to register interrupt handler\n");
1122                         goto err_irq;
1123                 }
1124         }
1125         ret = rockchip_init_iovmm(dev, &data->vmm);
1126         if (ret)
1127                 goto err_irq;
1128
1129         data->iommu = dev;
1130         rwlock_init(&data->lock);
1131         INIT_LIST_HEAD(&data->node);
1132
1133         set_fault_handler(data, &default_fault_handler);
1134
1135         pr_info("(%s) Initialized\n", data->dbgname);
1136         return 0;
1137
1138 err_irq:
1139         while (i-- > 0) {
1140                 int irq;
1141
1142                 irq = platform_get_irq(pdev, i);
1143                 free_irq(irq, data);
1144         }
1145 err_res:
1146         while (data->num_res_mem-- > 0)
1147                 iounmap(data->res_bases[data->num_res_mem]);
1148         kfree(data->res_bases);
1149 err_init:
1150         kfree(data);
1151 err_alloc:
1152         dev_err(dev, "Failed to initialize\n");
1153         return ret;
1154 }
1155
1156 #ifdef CONFIG_OF
1157 static const struct of_device_id iommu_dt_ids[] = {
1158         { .compatible = IEP_IOMMU_COMPATIBLE_NAME},
1159         { .compatible = VIP_IOMMU_COMPATIBLE_NAME},
1160         { .compatible = VOPB_IOMMU_COMPATIBLE_NAME},
1161         { .compatible = VOPL_IOMMU_COMPATIBLE_NAME},
1162         { .compatible = HEVC_IOMMU_COMPATIBLE_NAME},
1163         { .compatible = VPU_IOMMU_COMPATIBLE_NAME},
1164         { .compatible = ISP_IOMMU_COMPATIBLE_NAME},
1165         { .compatible = VOP_IOMMU_COMPATIBLE_NAME},
1166         { /* end */ }
1167 };
1168
1169 MODULE_DEVICE_TABLE(of, iommu_dt_ids);
1170 #endif
1171
1172 static struct platform_driver rk_iommu_driver = {
1173         .probe = rockchip_iommu_probe,
1174         .remove = NULL,
1175         .driver = {
1176                    .name = "rk_iommu",
1177                    .owner = THIS_MODULE,
1178                    .of_match_table = of_match_ptr(iommu_dt_ids),
1179         },
1180 };
1181
1182 static int __init rockchip_iommu_init_driver(void)
1183 {
1184         dump_iommu_sysfs_init();
1185
1186         return platform_driver_register(&rk_iommu_driver);
1187 }
1188
1189 core_initcall(rockchip_iommu_init_driver);