drivers/iommu/rockchip-iommu.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License version 2 as
   4  * published by the Free Software Foundation.
   5  */
   6
   7 #ifdef CONFIG_ROCKCHIP_IOMMU_DEBUG
   8 #define DEBUG
   9 #endif
  10
  11 #include <linux/io.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/slab.h>
  14 #include <linux/clk.h>
  15 #include <linux/err.h>
  16 #include <linux/mm.h>
  17 #include <linux/errno.h>
  18 #include <linux/memblock.h>
  19 #include <linux/export.h>
  20 #include <linux/module.h>
  21
  22 #include <asm/cacheflush.h>
  23 #include <asm/pgtable.h>
  24 #include <linux/of.h>
  25 #include <linux/rockchip-iovmm.h>
  26 #include <linux/rockchip/grf.h>
  27 #include <linux/rockchip/cpu.h>
  28 #include <linux/rockchip/iomap.h>
  29 #include <linux/device.h>
  30 #include "rockchip-iommu.h"
  31
  32 /* We does not consider super section mapping (16MB) */
  33 #define SPAGE_ORDER 12
  34 #define SPAGE_SIZE (1 << SPAGE_ORDER)
  35 #define SPAGE_MASK (~(SPAGE_SIZE - 1))
  36
  37 void __iomem *vop_mmu_base;
  38
  39 enum iommu_entry_flags {
  40         IOMMU_FLAGS_PRESENT = 0x01,
  41         IOMMU_FLAGS_READ_PERMISSION = 0x02,
  42         IOMMU_FLAGS_WRITE_PERMISSION = 0x04,
  43         IOMMU_FLAGS_OVERRIDE_CACHE = 0x8,
  44         IOMMU_FLAGS_WRITE_CACHEABLE = 0x10,
  45         IOMMU_FLAGS_WRITE_ALLOCATE = 0x20,
  46         IOMMU_FLAGS_WRITE_BUFFERABLE = 0x40,
  47         IOMMU_FLAGS_READ_CACHEABLE = 0x80,
  48         IOMMU_FLAGS_READ_ALLOCATE = 0x100,
  49         IOMMU_FLAGS_MASK = 0x1FF,
  50 };
  51
  52 #define lv1ent_fault(sent) ((*(sent) & IOMMU_FLAGS_PRESENT) == 0)
  53 #define lv1ent_page(sent) ((*(sent) & IOMMU_FLAGS_PRESENT) == 1)
  54 #define lv2ent_fault(pent) ((*(pent) & IOMMU_FLAGS_PRESENT) == 0)
  55 #define spage_phys(pent) (*(pent) & SPAGE_MASK)
  56 #define spage_offs(iova) ((iova) & 0x0FFF)
  57
  58 #define lv1ent_offset(iova) (((iova)>>22) & 0x03FF)
  59 #define lv2ent_offset(iova) (((iova)>>12) & 0x03FF)
  60
  61 #define NUM_LV1ENTRIES 1024
  62 #define NUM_LV2ENTRIES 1024
  63
  64 #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(long))
  65
  66 #define lv2table_base(sent) (*(sent) & 0xFFFFFFFE)
  67
  68 #define mk_lv1ent_page(pa) ((pa) | IOMMU_FLAGS_PRESENT)
  69 /*write and read permission for level2 page default*/
  70 #define mk_lv2ent_spage(pa) ((pa) | IOMMU_FLAGS_PRESENT | \
  71                              IOMMU_FLAGS_READ_PERMISSION | \
  72                              IOMMU_FLAGS_WRITE_PERMISSION)
  73
  74 #define IOMMU_REG_POLL_COUNT_FAST 1000
  75
  76 /*rk3036:vpu and hevc share ahb interface*/
  77 #define BIT_VCODEC_SEL_3036 (1<<3)
  78 #define BIT_VCODEC_SEL_312x (1<<15)
  79
  80
  81 /**
  82  * MMU register numbers
  83  * Used in the register read/write routines.
  84  * See the hardware documentation for more information about each register
  85  */
  86 enum iommu_register {
  87         /**< Current Page Directory Pointer */
  88         IOMMU_REGISTER_DTE_ADDR = 0x0000,
  89         /**< Status of the MMU */
  90         IOMMU_REGISTER_STATUS = 0x0004,
  91         /**< Command register, used to control the MMU */
  92         IOMMU_REGISTER_COMMAND = 0x0008,
  93         /**< Logical address of the last page fault */
  94         IOMMU_REGISTER_PAGE_FAULT_ADDR = 0x000C,
  95         /**< Used to invalidate the mapping of a single page from the MMU */
  96         IOMMU_REGISTER_ZAP_ONE_LINE = 0x010,
  97         /**< Raw interrupt status, all interrupts visible */
  98         IOMMU_REGISTER_INT_RAWSTAT = 0x0014,
  99         /**< Indicate to the MMU that the interrupt has been received */
 100         IOMMU_REGISTER_INT_CLEAR = 0x0018,
 101         /**< Enable/disable types of interrupts */
 102         IOMMU_REGISTER_INT_MASK = 0x001C,
 103         /**< Interrupt status based on the mask */
 104         IOMMU_REGISTER_INT_STATUS = 0x0020,
 105         IOMMU_REGISTER_AUTO_GATING = 0x0024
 106 };
 107
 108 enum iommu_command {
 109         /**< Enable paging (memory translation) */
 110         IOMMU_COMMAND_ENABLE_PAGING = 0x00,
 111         /**< Disable paging (memory translation) */
 112         IOMMU_COMMAND_DISABLE_PAGING = 0x01,
 113         /**<  Enable stall on page fault */
 114         IOMMU_COMMAND_ENABLE_STALL = 0x02,
 115         /**< Disable stall on page fault */
 116         IOMMU_COMMAND_DISABLE_STALL = 0x03,
 117         /**< Zap the entire page table cache */
 118         IOMMU_COMMAND_ZAP_CACHE = 0x04,
 119         /**< Page fault processed */
 120         IOMMU_COMMAND_PAGE_FAULT_DONE = 0x05,
 121         /**< Reset the MMU back to power-on settings */
 122         IOMMU_COMMAND_HARD_RESET = 0x06
 123 };
 124
 125 /**
 126  * MMU interrupt register bits
 127  * Each cause of the interrupt is reported
 128  * through the (raw) interrupt status registers.
 129  * Multiple interrupts can be pending, so multiple bits
 130  * can be set at once.
 131  */
 132 enum iommu_interrupt {
 133         IOMMU_INTERRUPT_PAGE_FAULT = 0x01, /**< A page fault occured */
 134         IOMMU_INTERRUPT_READ_BUS_ERROR = 0x02 /**< A bus read error occured */
 135 };
 136
 137 enum iommu_status_bits {
 138         IOMMU_STATUS_BIT_PAGING_ENABLED      = 1 << 0,
 139         IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE   = 1 << 1,
 140         IOMMU_STATUS_BIT_STALL_ACTIVE        = 1 << 2,
 141         IOMMU_STATUS_BIT_IDLE                = 1 << 3,
 142         IOMMU_STATUS_BIT_REPLAY_BUFFER_EMPTY = 1 << 4,
 143         IOMMU_STATUS_BIT_PAGE_FAULT_IS_WRITE = 1 << 5,
 144         IOMMU_STATUS_BIT_STALL_NOT_ACTIVE    = 1 << 31,
 145 };
 146
 147 /**
 148  * Size of an MMU page in bytes
 149  */
 150 #define IOMMU_PAGE_SIZE 0x1000
 151
 152 /*
 153  * Size of the address space referenced by a page table page
 154  */
 155 #define IOMMU_VIRTUAL_PAGE_SIZE 0x400000 /* 4 MiB */
 156
 157 /**
 158  * Page directory index from address
 159  * Calculates the page directory index from the given address
 160  */
 161 #define IOMMU_PDE_ENTRY(address) (((address)>>22) & 0x03FF)
 162
 163 /**
 164  * Page table index from address
 165  * Calculates the page table index from the given address
 166  */
 167 #define IOMMU_PTE_ENTRY(address) (((address)>>12) & 0x03FF)
 168
 169 /**
 170  * Extract the memory address from an PDE/PTE entry
 171  */
 172 #define IOMMU_ENTRY_ADDRESS(value) ((value) & 0xFFFFFC00)
 173
 174 #define INVALID_PAGE ((u32)(~0))
 175
 176 static struct kmem_cache *lv2table_kmem_cache;
 177
 178 static void rockchip_vcodec_select(const char *string)
 179 {
 180         if (strstr(string,"hevc")) {
 181                 if (cpu_is_rk3036()) {
 182                         writel_relaxed(readl_relaxed(RK_GRF_VIRT + RK3036_GRF_SOC_CON1) |
 183                               (BIT_VCODEC_SEL_3036) | (BIT_VCODEC_SEL_3036 << 16),
 184                               RK_GRF_VIRT + RK3036_GRF_SOC_CON1);
 185                 } else {
 186                         writel_relaxed(readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_CON1) |
 187                               (BIT_VCODEC_SEL_312x) | (BIT_VCODEC_SEL_312x << 16),
 188                               RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
 189                 }
 190         } else if (strstr(string,"vpu")) {
 191                 if (cpu_is_rk3036()) {
 192                         writel_relaxed((readl_relaxed(RK_GRF_VIRT + RK3036_GRF_SOC_CON1) &
 193                                (~BIT_VCODEC_SEL_3036)) | (BIT_VCODEC_SEL_3036 << 16),
 194                                RK_GRF_VIRT + RK3036_GRF_SOC_CON1);
 195                 } else {
 196                         writel_relaxed((readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_CON1) &
 197                                (~BIT_VCODEC_SEL_312x)) | (BIT_VCODEC_SEL_312x << 16),
 198                                RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
 199                 }
 200         }
 201 }
 202 static unsigned long *section_entry(unsigned long *pgtable, unsigned long iova)
 203 {
 204         return pgtable + lv1ent_offset(iova);
 205 }
 206
 207 static unsigned long *page_entry(unsigned long *sent, unsigned long iova)
 208 {
 209         return (unsigned long *)__va(lv2table_base(sent)) + lv2ent_offset(iova);
 210 }
 211
 212 static char *iommu_fault_name[IOMMU_FAULTS_NUM] = {
 213         "PAGE FAULT",
 214         "BUS ERROR",
 215         "UNKNOWN FAULT"
 216 };
 217
 218 struct rk_iommu_domain {
 219         struct list_head clients; /* list of iommu_drvdata.node */
 220         unsigned long *pgtable; /* lv1 page table, 4KB */
 221         short *lv2entcnt; /* free lv2 entry counter for each section */
 222         spinlock_t lock; /* lock for this structure */
 223         spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
 224 };
 225
 226 static bool set_iommu_active(struct iommu_drvdata *data)
 227 {
 228         /* return true if the IOMMU was not active previously
 229            and it needs to be initialized */
 230         return ++data->activations == 1;
 231 }
 232
 233 static bool set_iommu_inactive(struct iommu_drvdata *data)
 234 {
 235         /* return true if the IOMMU is needed to be disabled */
 236         BUG_ON(data->activations < 1);
 237         return --data->activations == 0;
 238 }
 239
 240 static bool is_iommu_active(struct iommu_drvdata *data)
 241 {
 242         return data->activations > 0;
 243 }
 244
 245 static void iommu_disable_stall(void __iomem *base)
 246 {
 247         int i;
 248         u32 mmu_status;
 249
 250         if (base != vop_mmu_base) {
 251                 mmu_status = __raw_readl(base + IOMMU_REGISTER_STATUS);
 252         } else {
 253                 goto skip_vop_mmu_disable;
 254         }
 255         if (0 == (mmu_status & IOMMU_STATUS_BIT_PAGING_ENABLED))
 256                 return;
 257         if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE) {
 258                 pr_info("Aborting MMU disable stall request since it is in pagefault state.\n");
 259                 return;
 260         }
 261         skip_vop_mmu_disable:
 262         __raw_writel(IOMMU_COMMAND_DISABLE_STALL,
 263                      base + IOMMU_REGISTER_COMMAND);
 264
 265         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 266                 u32 status;
 267
 268                 if (base != vop_mmu_base) {
 269                         status = __raw_readl(base + IOMMU_REGISTER_STATUS);
 270                 } else {
 271                         int j;
 272                         while (j < 5)
 273                                 j++;
 274                         return;
 275                 }
 276                 if (0 == (status & IOMMU_STATUS_BIT_STALL_ACTIVE))
 277                         break;
 278                 if (status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE)
 279                         break;
 280                 if (0 == (mmu_status & IOMMU_STATUS_BIT_PAGING_ENABLED))
 281                         break;
 282         }
 283         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 284                 pr_info("Disable stall request failed, MMU status is 0x%08X\n",
 285                       __raw_readl(base + IOMMU_REGISTER_STATUS));
 286         }
 287 }
 288
 289 static bool iommu_enable_stall(void __iomem *base)
 290 {
 291         int i;
 292
 293         u32 mmu_status;
 294
 295         if (base != vop_mmu_base) {
 296                 mmu_status = __raw_readl(base + IOMMU_REGISTER_STATUS);
 297         } else {
 298                 goto skip_vop_mmu_enable;
 299         }
 300         if (0 == (mmu_status & IOMMU_STATUS_BIT_PAGING_ENABLED))
 301                 return true;
 302         if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE) {
 303                 pr_info("Aborting MMU stall request since it is in pagefault state.\n");
 304                 return false;
 305         }
 306         skip_vop_mmu_enable:
 307         __raw_writel(IOMMU_COMMAND_ENABLE_STALL,
 308                      base + IOMMU_REGISTER_COMMAND);
 309
 310         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 311                 if (base != vop_mmu_base) {
 312                         mmu_status = __raw_readl(base + IOMMU_REGISTER_STATUS);
 313                 } else {
 314                         int j;
 315                         while (j < 5)
 316                                 j++;
 317                         return true;
 318                 }
 319                 if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE)
 320                         break;
 321                 if ((mmu_status & IOMMU_STATUS_BIT_STALL_ACTIVE) &&
 322                     (0 == (mmu_status & IOMMU_STATUS_BIT_STALL_NOT_ACTIVE)))
 323                         break;
 324                 if (0 == (mmu_status & (IOMMU_STATUS_BIT_PAGING_ENABLED)))
 325                         break;
 326         }
 327         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 328                 pr_info("Enable stall request failed, MMU status is 0x%08X\n",
 329                        __raw_readl(base + IOMMU_REGISTER_STATUS));
 330                 return false;
 331         }
 332         if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE) {
 333                 pr_info("Aborting MMU stall request since it has a pagefault.\n");
 334                 return false;
 335         }
 336         return true;
 337 }
 338
 339 static bool iommu_enable_paging(void __iomem *base)
 340 {
 341         int i;
 342
 343         __raw_writel(IOMMU_COMMAND_ENABLE_PAGING,
 344                      base + IOMMU_REGISTER_COMMAND);
 345
 346         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 347                 if (base != vop_mmu_base) {
 348                         if (__raw_readl(base + IOMMU_REGISTER_STATUS) &
 349                                 IOMMU_STATUS_BIT_PAGING_ENABLED)
 350                         break;
 351                 } else {
 352                         int j;
 353                         while (j < 5)
 354                                 j++;
 355                         return true;
 356                 }
 357         }
 358         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 359                 pr_info("Enable paging request failed, MMU status is 0x%08X\n",
 360                        __raw_readl(base + IOMMU_REGISTER_STATUS));
 361                 return false;
 362         }
 363         return true;
 364 }
 365
 366 static bool iommu_disable_paging(void __iomem *base)
 367 {
 368         int i;
 369
 370         return true;
 371         __raw_writel(IOMMU_COMMAND_DISABLE_PAGING,
 372                      base + IOMMU_REGISTER_COMMAND);
 373
 374         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 375                 if (base != vop_mmu_base) {
 376                         if (!(__raw_readl(base + IOMMU_REGISTER_STATUS) &
 377                                   IOMMU_STATUS_BIT_PAGING_ENABLED))
 378                                 break;
 379                 } else {
 380                         int j;
 381                         while (j < 5)
 382                                 j++;
 383                         return true;
 384                 }
 385         }
 386         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 387                 pr_info("Disable paging request failed, MMU status is 0x%08X\n",
 388                        __raw_readl(base + IOMMU_REGISTER_STATUS));
 389                 return false;
 390         }
 391         return true;
 392 }
 393
 394 static void iommu_page_fault_done(void __iomem *base, const char *dbgname)
 395 {
 396         pr_info("MMU: %s: Leaving page fault mode\n",
 397                 dbgname);
 398         __raw_writel(IOMMU_COMMAND_PAGE_FAULT_DONE,
 399                      base + IOMMU_REGISTER_COMMAND);
 400 }
 401
 402 static bool iommu_zap_tlb(void __iomem *base)
 403 {
 404         bool stall_success = iommu_enable_stall(base);
 405
 406         __raw_writel(IOMMU_COMMAND_ZAP_CACHE,
 407                      base + IOMMU_REGISTER_COMMAND);
 408         if (!stall_success)
 409                 return false;
 410         iommu_disable_stall(base);
 411         return true;
 412 }
 413 extern bool __clk_is_enabled(struct clk *clk);
 414 static inline bool iommu_raw_reset(void __iomem *base)
 415 {
 416         int i;
 417         unsigned int ret;
 418
 419         __raw_writel(0xCAFEBABE, base + IOMMU_REGISTER_DTE_ADDR);
 420
 421         if (base != vop_mmu_base) {
 422                 ret = __raw_readl(base + IOMMU_REGISTER_DTE_ADDR);
 423                 if (!(0xCAFEB000 == ret)) {
 424                         pr_info("error when %s.\n", __func__);
 425                         return false;
 426                 }
 427         }
 428         __raw_writel(IOMMU_COMMAND_HARD_RESET,
 429                      base + IOMMU_REGISTER_COMMAND);
 430
 431         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 432                 if (base != vop_mmu_base) {
 433                         if (__raw_readl(base + IOMMU_REGISTER_DTE_ADDR) == 0)
 434                                 break;
 435                 } else {
 436                         int j;
 437                         while (j < 5)
 438                                 j++;
 439                         return true;
 440                 }
 441         }
 442         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 443                 pr_info("%s,Reset request failed, MMU status is 0x%08X\n",
 444                        __func__, __raw_readl(base + IOMMU_REGISTER_DTE_ADDR));
 445                 return false;
 446         }
 447         return true;
 448 }
 449
 450 static void __iommu_set_ptbase(void __iomem *base, unsigned long pgd)
 451 {
 452         __raw_writel(pgd, base + IOMMU_REGISTER_DTE_ADDR);
 453 }
 454
 455 static bool iommu_reset(void __iomem *base, const char *dbgname)
 456 {
 457         bool err = true;
 458
 459         err = iommu_enable_stall(base);
 460         if (!err) {
 461                 pr_info("%s:stall failed: %s\n", __func__, dbgname);
 462                 return err;
 463         }
 464         err = iommu_raw_reset(base);
 465         if (err)
 466                 __raw_writel(IOMMU_INTERRUPT_PAGE_FAULT |
 467                              IOMMU_INTERRUPT_READ_BUS_ERROR,
 468                              base+IOMMU_REGISTER_INT_MASK);
 469         iommu_disable_stall(base);
 470         if (!err)
 471                 pr_info("%s: failed: %s\n", __func__, dbgname);
 472         return err;
 473 }
 474
 475 static inline void pgtable_flush(void *vastart, void *vaend)
 476 {
 477         dmac_flush_range(vastart, vaend);
 478         outer_flush_range(virt_to_phys(vastart), virt_to_phys(vaend));
 479 }
 480
 481 static void set_fault_handler(struct iommu_drvdata *data,
 482                                 rockchip_iommu_fault_handler_t handler)
 483 {
 484         unsigned long flags;
 485
 486         write_lock_irqsave(&data->lock, flags);
 487         data->fault_handler = handler;
 488         write_unlock_irqrestore(&data->lock, flags);
 489 }
 490
 491 static int default_fault_handler(struct device *dev,
 492                                  enum rk_iommu_inttype itype,
 493                                  unsigned long pgtable_base,
 494                                  unsigned long fault_addr,
 495                                  unsigned int status)
 496 {
 497         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 498
 499         if (!data) {
 500                 dev_err(dev->archdata.iommu,"%s,iommu device not assigned yet\n", __func__);
 501                 return 0;
 502         }
 503         if ((itype >= IOMMU_FAULTS_NUM) || (itype < IOMMU_PAGEFAULT))
 504                 itype = IOMMU_FAULT_UNKNOWN;
 505
 506         if (itype == IOMMU_BUSERROR)
 507                 dev_err(dev->archdata.iommu,"%s occured at 0x%lx(Page table base: 0x%lx)\n",
 508                        iommu_fault_name[itype], fault_addr, pgtable_base);
 509
 510         if (itype == IOMMU_PAGEFAULT)
 511                 dev_err(dev->archdata.iommu,"IOMMU:Page fault detected at 0x%lx from bus id %d of type %s on %s\n",
 512                        fault_addr,
 513                        (status >> 6) & 0x1F,
 514                        (status & 32) ? "write" : "read",
 515                        data->dbgname);
 516
 517         dev_err(dev->archdata.iommu,"Generating Kernel OOPS... because it is unrecoverable.\n");
 518
 519         BUG();
 520
 521         return 0;
 522 }
 523
 524 static void dump_pagetbl(u32 fault_address, u32 addr_dte)
 525 {
 526         u32 lv1_offset;
 527         u32 lv2_offset;
 528
 529         u32 *lv1_entry_pa;
 530         u32 *lv1_entry_va;
 531         u32 *lv1_entry_value;
 532
 533         u32 *lv2_base;
 534         u32 *lv2_entry_pa;
 535         u32 *lv2_entry_va;
 536         u32 *lv2_entry_value;
 537
 538
 539         lv1_offset = lv1ent_offset(fault_address);
 540         lv2_offset = lv2ent_offset(fault_address);
 541
 542         lv1_entry_pa = (u32 *)addr_dte + lv1_offset;
 543         lv1_entry_va = (u32 *)(__va(addr_dte)) + lv1_offset;
 544         lv1_entry_value = (u32 *)(*lv1_entry_va);
 545
 546         lv2_base = (u32 *)((*lv1_entry_va) & 0xfffffffe);
 547         lv2_entry_pa = (u32 *)lv2_base + lv2_offset;
 548         lv2_entry_va = (u32 *)(__va(lv2_base)) + lv2_offset;
 549         lv2_entry_value = (u32 *)(*lv2_entry_va);
 550
 551         dev_info(NULL,"fault address = 0x%08x,dte addr pa = 0x%08x,va = 0x%08x\n",
 552                 fault_address, addr_dte, (u32)__va(addr_dte));
 553         dev_info(NULL,"lv1_offset = 0x%x,lv1_entry_pa = 0x%08x,lv1_entry_va = 0x%08x\n",
 554                 lv1_offset, (u32)lv1_entry_pa, (u32)lv1_entry_va);
 555         dev_info(NULL,"lv1_entry_value(*lv1_entry_va) = 0x%08x,lv2_base = 0x%08x\n",
 556                 (u32)lv1_entry_value, (u32)lv2_base);
 557         dev_info(NULL,"lv2_offset = 0x%x,lv2_entry_pa = 0x%08x,lv2_entry_va = 0x%08x\n",
 558                 lv2_offset, (u32)lv2_entry_pa, (u32)lv2_entry_va);
 559         dev_info(NULL,"lv2_entry value(*lv2_entry_va) = 0x%08x\n",
 560                 (u32)lv2_entry_value);
 561 }
 562
 563 static irqreturn_t rockchip_iommu_irq(int irq, void *dev_id)
 564 {
 565         /* SYSMMU is in blocked when interrupt occurred. */
 566         struct iommu_drvdata *data = dev_id;
 567         struct resource *irqres;
 568         struct platform_device *pdev;
 569         enum rk_iommu_inttype itype = IOMMU_FAULT_UNKNOWN;
 570         u32 status;
 571         u32 rawstat;
 572         u32 int_status;
 573         u32 fault_address;
 574         int i, ret = 0;
 575
 576         read_lock(&data->lock);
 577
 578         if (!is_iommu_active(data)) {
 579                 read_unlock(&data->lock);
 580                 return IRQ_HANDLED;
 581         }
 582
 583         if(cpu_is_rk312x() || cpu_is_rk3036())
 584                 rockchip_vcodec_select(data->dbgname);
 585
 586         pdev = to_platform_device(data->iommu);
 587
 588         for (i = 0; i < data->num_res_irq; i++) {
 589                 irqres = platform_get_resource(pdev, IORESOURCE_IRQ, i);
 590                 if (irqres && ((int)irqres->start == irq)) {
 591                         if (data->res_bases[i] == vop_mmu_base)
 592                         {
 593                                 //pr_info("not a vop mmu irq\n");
 594                                 read_unlock(&data->lock);
 595                                 return IRQ_HANDLED;
 596                         }
 597                         break;
 598                 }
 599         }
 600
 601         if (i == data->num_res_irq) {
 602                 itype = IOMMU_FAULT_UNKNOWN;
 603         } else {
 604                 int_status = __raw_readl(data->res_bases[i] +
 605                                          IOMMU_REGISTER_INT_STATUS);
 606
 607                 if (int_status != 0) {
 608                         /*mask status*/
 609                         __raw_writel(0x00, data->res_bases[i] +
 610                                      IOMMU_REGISTER_INT_MASK);
 611
 612                         rawstat = __raw_readl(data->res_bases[i] +
 613                                               IOMMU_REGISTER_INT_RAWSTAT);
 614
 615                         if (rawstat & IOMMU_INTERRUPT_PAGE_FAULT) {
 616                                 fault_address = __raw_readl(data->res_bases[i] +
 617                                 IOMMU_REGISTER_PAGE_FAULT_ADDR);
 618                                 itype = IOMMU_PAGEFAULT;
 619                         } else if (rawstat & IOMMU_INTERRUPT_READ_BUS_ERROR) {
 620                                 itype = IOMMU_BUSERROR;
 621                         } else {
 622                                 goto out;
 623                         }
 624                         dump_pagetbl(fault_address,
 625                                      __raw_readl(data->res_bases[i] +
 626                                      IOMMU_REGISTER_DTE_ADDR));
 627                 } else {
 628                         goto out;
 629                 }
 630         }
 631
 632         if (data->fault_handler) {
 633                 unsigned long base = __raw_readl(data->res_bases[i] +
 634                                                  IOMMU_REGISTER_DTE_ADDR);
 635                 status = __raw_readl(data->res_bases[i] +
 636                                      IOMMU_REGISTER_STATUS);
 637                 ret = data->fault_handler(data->dev, itype, base,
 638                                           fault_address, status);
 639         }
 640
 641         if (!ret && (itype != IOMMU_FAULT_UNKNOWN)) {
 642                 if (IOMMU_PAGEFAULT == itype) {
 643                         iommu_zap_tlb(data->res_bases[i]);
 644                         iommu_page_fault_done(data->res_bases[i],
 645                                                data->dbgname);
 646                         __raw_writel(IOMMU_INTERRUPT_PAGE_FAULT |
 647                                      IOMMU_INTERRUPT_READ_BUS_ERROR,
 648                                      data->res_bases[i] +
 649                                      IOMMU_REGISTER_INT_MASK);
 650                 }
 651         } else {
 652                 dev_err(data->iommu,"(%s) %s is not handled.\n",
 653                        data->dbgname, iommu_fault_name[itype]);
 654         }
 655
 656 out:
 657         read_unlock(&data->lock);
 658
 659         return IRQ_HANDLED;
 660 }
 661
 662 static bool __rockchip_iommu_disable(struct iommu_drvdata *data)
 663 {
 664         unsigned long flags;
 665         int i;
 666         bool disabled = false;
 667
 668         write_lock_irqsave(&data->lock, flags);
 669
 670         if (!set_iommu_inactive(data))
 671                 goto finish;
 672
 673         for (i = 0; i < data->num_res_mem; i++)
 674                 iommu_disable_paging(data->res_bases[i]);
 675
 676         disabled = true;
 677         data->pgtable = 0;
 678         data->domain = NULL;
 679 finish:
 680         write_unlock_irqrestore(&data->lock, flags);
 681
 682         if (disabled)
 683                 dev_info(data->iommu,"(%s) Disabled\n", data->dbgname);
 684         else
 685                 dev_info(data->iommu,"(%s) %d times left to be disabled\n",
 686                         data->dbgname, data->activations);
 687
 688         return disabled;
 689 }
 690
 691 /* __rk_sysmmu_enable: Enables System MMU
 692  *
 693  * returns -error if an error occurred and System MMU is not enabled,
 694  * 0 if the System MMU has been just enabled and 1 if System MMU was already
 695  * enabled before.
 696  */
 697 static int __rockchip_iommu_enable(struct iommu_drvdata *data,
 698                                     unsigned long pgtable,
 699                                     struct iommu_domain *domain)
 700 {
 701         int i, ret = 0;
 702         unsigned long flags;
 703
 704         write_lock_irqsave(&data->lock, flags);
 705
 706         if (!set_iommu_active(data)) {
 707                 if (WARN_ON(pgtable != data->pgtable)) {
 708                         ret = -EBUSY;
 709                         set_iommu_inactive(data);
 710                 } else {
 711                         ret = 1;
 712                 }
 713
 714                 dev_info(data->iommu,"(%s) Already enabled\n", data->dbgname);
 715                 goto finish;
 716         }
 717
 718         data->pgtable = pgtable;
 719
 720         for (i = 0; i < data->num_res_mem; i++) {
 721                 bool status;
 722
 723                 status = iommu_enable_stall(data->res_bases[i]);
 724                 if (status) {
 725                         __iommu_set_ptbase(data->res_bases[i], pgtable);
 726                         __raw_writel(IOMMU_COMMAND_ZAP_CACHE,
 727                                      data->res_bases[i] +
 728                                      IOMMU_REGISTER_COMMAND);
 729                 }
 730                 __raw_writel(IOMMU_INTERRUPT_PAGE_FAULT |
 731                              IOMMU_INTERRUPT_READ_BUS_ERROR,
 732                              data->res_bases[i]+IOMMU_REGISTER_INT_MASK);
 733                 iommu_enable_paging(data->res_bases[i]);
 734                 iommu_disable_stall(data->res_bases[i]);
 735         }
 736
 737         data->domain = domain;
 738
 739         dev_info(data->iommu,"(%s) Enabled\n", data->dbgname);
 740 finish:
 741         write_unlock_irqrestore(&data->lock, flags);
 742
 743         return ret;
 744 }
 745
 746 bool rockchip_iommu_disable(struct device *dev)
 747 {
 748         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 749         bool disabled;
 750
 751         disabled = __rockchip_iommu_disable(data);
 752
 753         return disabled;
 754 }
 755
 756 void rockchip_iommu_tlb_invalidate(struct device *dev)
 757 {
 758         unsigned long flags;
 759         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 760
 761         read_lock_irqsave(&data->lock, flags);
 762
 763         if(cpu_is_rk312x() || cpu_is_rk3036())
 764                 rockchip_vcodec_select(data->dbgname);
 765
 766         if (is_iommu_active(data)) {
 767                 int i;
 768
 769                 for (i = 0; i < data->num_res_mem; i++) {
 770                         if (!iommu_zap_tlb(data->res_bases[i]))
 771                                 dev_err(dev->archdata.iommu,"%s,invalidating TLB failed\n",
 772                                        data->dbgname);
 773                 }
 774         } else {
 775                 dev_dbg(dev->archdata.iommu,"(%s) Disabled. Skipping invalidating TLB.\n",
 776                         data->dbgname);
 777         }
 778
 779         read_unlock_irqrestore(&data->lock, flags);
 780 }
 781
 782 static phys_addr_t rockchip_iommu_iova_to_phys(struct iommu_domain *domain,
 783                                                dma_addr_t iova)
 784 {
 785         struct rk_iommu_domain *priv = domain->priv;
 786         unsigned long *entry;
 787         unsigned long flags;
 788         phys_addr_t phys = 0;
 789
 790         spin_lock_irqsave(&priv->pgtablelock, flags);
 791
 792         entry = section_entry(priv->pgtable, iova);
 793         entry = page_entry(entry, iova);
 794         phys = spage_phys(entry) + spage_offs(iova);
 795
 796         spin_unlock_irqrestore(&priv->pgtablelock, flags);
 797
 798         return phys;
 799 }
 800
 801 static int lv2set_page(unsigned long *pent, phys_addr_t paddr,
 802                        size_t size, short *pgcnt)
 803 {
 804         if (!lv2ent_fault(pent))
 805                 return -EADDRINUSE;
 806
 807         *pent = mk_lv2ent_spage(paddr);
 808         pgtable_flush(pent, pent + 1);
 809         *pgcnt -= 1;
 810         return 0;
 811 }
 812
 813 static unsigned long *alloc_lv2entry(unsigned long *sent,
 814                                      unsigned long iova, short *pgcounter)
 815 {
 816         if (lv1ent_fault(sent)) {
 817                 unsigned long *pent;
 818
 819                 pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
 820                 BUG_ON((unsigned long)pent & (LV2TABLE_SIZE - 1));
 821                 if (!pent)
 822                         return NULL;
 823
 824                 *sent = mk_lv1ent_page(__pa(pent));
 825                 kmemleak_ignore(pent);
 826                 *pgcounter = NUM_LV2ENTRIES;
 827                 pgtable_flush(pent, pent + NUM_LV2ENTRIES);
 828                 pgtable_flush(sent, sent + 1);
 829         }
 830         return page_entry(sent, iova);
 831 }
 832
 833 static size_t rockchip_iommu_unmap(struct iommu_domain *domain,
 834                                    unsigned long iova, size_t size)
 835 {
 836         struct rk_iommu_domain *priv = domain->priv;
 837         unsigned long flags;
 838         unsigned long *ent;
 839
 840         BUG_ON(priv->pgtable == NULL);
 841
 842         spin_lock_irqsave(&priv->pgtablelock, flags);
 843
 844         ent = section_entry(priv->pgtable, iova);
 845
 846         if (unlikely(lv1ent_fault(ent))) {
 847                 if (size > SPAGE_SIZE)
 848                         size = SPAGE_SIZE;
 849                 goto done;
 850         }
 851
 852         /* lv1ent_page(sent) == true here */
 853
 854         ent = page_entry(ent, iova);
 855
 856         if (unlikely(lv2ent_fault(ent))) {
 857                 size = SPAGE_SIZE;
 858                 goto done;
 859         }
 860
 861         *ent = 0;
 862         size = SPAGE_SIZE;
 863         priv->lv2entcnt[lv1ent_offset(iova)] += 1;
 864         goto done;
 865
 866 done:
 867         #if 0
 868         pr_info("%s:unmap iova 0x%lx/0x%x bytes\n",
 869                   __func__, iova,size);
 870         #endif
 871         spin_unlock_irqrestore(&priv->pgtablelock, flags);
 872
 873         return size;
 874 }
 875
 876 static int rockchip_iommu_map(struct iommu_domain *domain, unsigned long iova,
 877                               phys_addr_t paddr, size_t size, int prot)
 878 {
 879         struct rk_iommu_domain *priv = domain->priv;
 880         unsigned long *entry;
 881         unsigned long flags;
 882         int ret = -ENOMEM;
 883         unsigned long *pent;
 884
 885         BUG_ON(priv->pgtable == NULL);
 886
 887         spin_lock_irqsave(&priv->pgtablelock, flags);
 888
 889         entry = section_entry(priv->pgtable, iova);
 890
 891         pent = alloc_lv2entry(entry, iova,
 892                               &priv->lv2entcnt[lv1ent_offset(iova)]);
 893         if (!pent)
 894                 ret = -ENOMEM;
 895         else
 896                 ret = lv2set_page(pent, paddr, size,
 897                                   &priv->lv2entcnt[lv1ent_offset(iova)]);
 898
 899         if (ret) {
 900                 pr_info("%s: Failed to map iova 0x%lx/0x%x bytes\n", __func__,
 901                        iova, size);
 902         }
 903         spin_unlock_irqrestore(&priv->pgtablelock, flags);
 904
 905         return ret;
 906 }
 907
 908 static void rockchip_iommu_detach_device(struct iommu_domain *domain,
 909                                          struct device *dev)
 910 {
 911         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 912         struct rk_iommu_domain *priv = domain->priv;
 913         struct list_head *pos;
 914         unsigned long flags;
 915         bool found = false;
 916
 917         spin_lock_irqsave(&priv->lock, flags);
 918
 919         list_for_each(pos, &priv->clients)
 920         {
 921                 if (list_entry(pos, struct iommu_drvdata, node) == data) {
 922                         found = true;
 923                         break;
 924                 }
 925         }
 926         if (!found)
 927                 goto finish;
 928
 929         if(cpu_is_rk312x() || cpu_is_rk3036())
 930                 rockchip_vcodec_select(data->dbgname);
 931
 932         if (__rockchip_iommu_disable(data)) {
 933                 dev_info(dev->archdata.iommu,"%s: Detached IOMMU with pgtable %#lx\n",
 934                         __func__, __pa(priv->pgtable));
 935                 list_del(&data->node);
 936                 INIT_LIST_HEAD(&data->node);
 937
 938         } else
 939                 dev_info(dev->archdata.iommu,"%s: Detaching IOMMU with pgtable %#lx delayed",
 940                         __func__, __pa(priv->pgtable));
 941
 942 finish:
 943         spin_unlock_irqrestore(&priv->lock, flags);
 944 }
 945
 946 static int rockchip_iommu_attach_device(struct iommu_domain *domain,
 947                                         struct device *dev)
 948 {
 949         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 950         struct rk_iommu_domain *priv = domain->priv;
 951         unsigned long flags;
 952         int ret;
 953
 954         spin_lock_irqsave(&priv->lock, flags);
 955
 956         if(cpu_is_rk312x() || cpu_is_rk3036())
 957                 rockchip_vcodec_select(data->dbgname);
 958
 959         ret = __rockchip_iommu_enable(data, __pa(priv->pgtable), domain);
 960
 961         if (ret == 0) {
 962                 /* 'data->node' must not be appeared in priv->clients */
 963                 BUG_ON(!list_empty(&data->node));
 964                 data->dev = dev;
 965                 list_add_tail(&data->node, &priv->clients);
 966         }
 967
 968         spin_unlock_irqrestore(&priv->lock, flags);
 969
 970         if (ret < 0) {
 971                 dev_err(dev->archdata.iommu,"%s: Failed to attach IOMMU with pgtable %#lx\n",
 972                        __func__, __pa(priv->pgtable));
 973         } else if (ret > 0) {
 974                 dev_dbg(dev->archdata.iommu,"%s: IOMMU with pgtable 0x%lx already attached\n",
 975                         __func__, __pa(priv->pgtable));
 976         } else {
 977                 dev_dbg(dev->archdata.iommu,"%s: Attached new IOMMU with pgtable 0x%lx\n",
 978                         __func__, __pa(priv->pgtable));
 979         }
 980
 981         return ret;
 982 }
 983
 984 static void rockchip_iommu_domain_destroy(struct iommu_domain *domain)
 985 {
 986         struct rk_iommu_domain *priv = domain->priv;
 987         struct iommu_drvdata *data;
 988         unsigned long flags;
 989         int i;
 990
 991         WARN_ON(!list_empty(&priv->clients));
 992
 993         spin_lock_irqsave(&priv->lock, flags);
 994
 995         list_for_each_entry(data, &priv->clients, node) {
 996                 if(cpu_is_rk312x() || cpu_is_rk3036())
 997                         rockchip_vcodec_select(data->dbgname);
 998                 while (!rockchip_iommu_disable(data->dev))
 999                         ; /* until System MMU is actually disabled */
1000         }
1001         spin_unlock_irqrestore(&priv->lock, flags);
1002
1003         for (i = 0; i < NUM_LV1ENTRIES; i++)
1004                 if (lv1ent_page(priv->pgtable + i))
1005                         kmem_cache_free(lv2table_kmem_cache,
1006                                         __va(lv2table_base(priv->pgtable + i)));
1007
1008         free_pages((unsigned long)priv->pgtable, 0);
1009         free_pages((unsigned long)priv->lv2entcnt, 0);
1010         kfree(domain->priv);
1011         domain->priv = NULL;
1012 }
1013
1014 static int rockchip_iommu_domain_init(struct iommu_domain *domain)
1015 {
1016         struct rk_iommu_domain *priv;
1017
1018         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1019         if (!priv)
1020                 return -ENOMEM;
1021
1022 /*rk32xx iommu use 2 level pagetable,
1023    level1 and leve2 both have 1024 entries,each entry  occupy 4 bytes,
1024    so alloc a page size for each page table
1025 */
1026         priv->pgtable = (unsigned long *)__get_free_pages(GFP_KERNEL |
1027                                                           __GFP_ZERO, 0);
1028         if (!priv->pgtable)
1029                 goto err_pgtable;
1030
1031         priv->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL |
1032                                                     __GFP_ZERO, 0);
1033         if (!priv->lv2entcnt)
1034                 goto err_counter;
1035
1036         pgtable_flush(priv->pgtable, priv->pgtable + NUM_LV1ENTRIES);
1037
1038         spin_lock_init(&priv->lock);
1039         spin_lock_init(&priv->pgtablelock);
1040         INIT_LIST_HEAD(&priv->clients);
1041
1042         domain->priv = priv;
1043         return 0;
1044
1045 err_counter:
1046         free_pages((unsigned long)priv->pgtable, 0);
1047 err_pgtable:
1048         kfree(priv);
1049         return -ENOMEM;
1050 }
1051
1052 static struct iommu_ops rk_iommu_ops = {
1053         .domain_init = &rockchip_iommu_domain_init,
1054         .domain_destroy = &rockchip_iommu_domain_destroy,
1055         .attach_dev = &rockchip_iommu_attach_device,
1056         .detach_dev = &rockchip_iommu_detach_device,
1057         .map = &rockchip_iommu_map,
1058         .unmap = &rockchip_iommu_unmap,
1059         .iova_to_phys = &rockchip_iommu_iova_to_phys,
1060         .pgsize_bitmap = SPAGE_SIZE,
1061 };
1062
1063 static int rockchip_iommu_prepare(void)
1064 {
1065         int ret = 0;
1066         static int registed;
1067
1068         if (registed)
1069                 return 0;
1070
1071         lv2table_kmem_cache = kmem_cache_create("rk-iommu-lv2table",
1072                                                 LV2TABLE_SIZE,
1073                                                 LV2TABLE_SIZE,
1074                                                 0, NULL);
1075         if (!lv2table_kmem_cache) {
1076                 pr_info("%s: failed to create kmem cache\n", __func__);
1077                 return -ENOMEM;
1078         }
1079         ret = bus_set_iommu(&platform_bus_type, &rk_iommu_ops);
1080         if (!ret)
1081                 registed = 1;
1082         else
1083                 pr_info("%s:failed to set iommu to bus\r\n", __func__);
1084         return ret;
1085 }
1086
1087 static int  rockchip_get_iommu_resource_num(struct platform_device *pdev,
1088                                              unsigned int type)
1089 {
1090         int num = 0;
1091         int i;
1092 #if 0
1093         pr_info("dev num_resources %d type = 0x%08x\n",pdev->num_resources, type);
1094 #endif
1095         for (i = 0; i < pdev->num_resources; i++) {
1096                 struct resource *r = &pdev->resource[i];
1097 #if 0
1098 dev_info(&pdev->dev, "r[%d] start %08x end %08x flags %08lx name (%s) resource_type %08lx\n", i, r->start, r->end, r->flags, r->name, resource_type(r));
1099 #endif
1100                 if (type == resource_type(r))
1101                         num++;
1102         }
1103
1104         return num;
1105 }
1106
1107 static struct kobject *dump_mmu_object;
1108
1109 static int dump_mmu_pagetbl(struct device *dev, struct device_attribute *attr,
1110                             const char *buf, u32 count)
1111 {
1112         u32 fault_address;
1113         u32 iommu_dte;
1114         u32 mmu_base;
1115         void __iomem *base;
1116         u32 ret;
1117
1118         ret = kstrtouint(buf, 0, &mmu_base);
1119         if (ret)
1120                 dev_dbg(dev,"%s is not in hexdecimal form.\n", buf);
1121         base = ioremap(mmu_base, 0x100);
1122         if (base != vop_mmu_base) {
1123                 iommu_dte = __raw_readl(base + IOMMU_REGISTER_DTE_ADDR);
1124                 fault_address = __raw_readl(base + IOMMU_REGISTER_PAGE_FAULT_ADDR);
1125                 dump_pagetbl(fault_address, iommu_dte);
1126         } else {
1127                 dev_dbg(dev,"vop mmu not support\n");
1128         }
1129         return count;
1130 }
1131
1132 static DEVICE_ATTR(dump_mmu_pgtable, 0644, NULL, dump_mmu_pagetbl);
1133
1134 void dump_iommu_sysfs_init(void)
1135 {
1136         u32 ret;
1137
1138         dump_mmu_object = kobject_create_and_add("rk_iommu", NULL);
1139         if (dump_mmu_object == NULL)
1140                 return;
1141         ret = sysfs_create_file(dump_mmu_object,
1142                                 &dev_attr_dump_mmu_pgtable.attr);
1143 }
1144
1145 static int rockchip_iommu_probe(struct platform_device *pdev)
1146 {
1147         int i, ret;
1148         struct device *dev;
1149         struct iommu_drvdata *data;
1150
1151         dev = &pdev->dev;
1152
1153 #if 0
1154 struct resource *res = pdev->resource;
1155
1156 for (i = 0; i < pdev->num_resources; i++, res++) {
1157         pr_info("r[%d] start %08x end %08x flags %08lx name (%s) resource_type %08lx\n", i, res->start, res->end, res->flags, res->name,   resource_type(res));
1158 }
1159 #endif
1160         ret = rockchip_iommu_prepare();
1161         if (ret) {
1162                 dev_err(dev,"%s,failed\r\n", __func__);
1163                 goto err_alloc;
1164         }
1165
1166         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
1167         if (!data) {
1168                 dev_dbg(dev, "Not enough memory\n");
1169                 ret = -ENOMEM;
1170                 goto err_alloc;
1171         }
1172         dev_set_drvdata(dev, data);
1173 /*
1174         ret = dev_set_drvdata(dev, data);
1175         if (ret)
1176         {
1177                 dev_dbg(dev, "Unabled to initialize driver data\n");
1178                 goto err_init;
1179         }
1180 */
1181         if (pdev->dev.of_node) {
1182                 of_property_read_string(pdev->dev.of_node,
1183                                         "dbgname", &(data->dbgname));
1184         } else {
1185                 dev_dbg(dev,
1186                                 "dbgname not assigned in device tree or device node not exist\r\n");
1187         }
1188
1189         dev_info(dev,"(%s) Enter\n", data->dbgname);
1190
1191
1192         data->num_res_mem = rockchip_get_iommu_resource_num(pdev,
1193                                 IORESOURCE_MEM);
1194         if (0 == data->num_res_mem) {
1195                 dev_err(dev,"can't find iommu memory resource \r\n");
1196                 goto err_init;
1197         }
1198         dev_dbg(dev,"data->num_res_mem=%d\n", data->num_res_mem);
1199         data->num_res_irq = rockchip_get_iommu_resource_num(pdev,
1200                                 IORESOURCE_IRQ);
1201         if (0 == data->num_res_irq) {
1202                 dev_err(dev,"can't find iommu irq resource \r\n");
1203                 goto err_init;
1204         }
1205         dev_dbg(dev,"data->num_res_irq=%d\n", data->num_res_irq);
1206
1207         data->res_bases = devm_kmalloc_array(dev, data->num_res_mem,
1208                                 sizeof(*data->res_bases), GFP_KERNEL);
1209         if (data->res_bases == NULL) {
1210                 dev_err(dev, "Not enough memory\n");
1211                 ret = -ENOMEM;
1212                 goto err_init;
1213         }
1214
1215         for (i = 0; i < data->num_res_mem; i++) {
1216                 struct resource *res;
1217
1218                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1219                 if (!res) {
1220                         dev_err(dev,"Unable to find IOMEM region\n");
1221                         ret = -ENOENT;
1222                         goto err_res;
1223                 }
1224                 data->res_bases[i] = ioremap(res->start, resource_size(res));
1225                 dev_dbg(dev,"res->start = 0x%08x  ioremap to  data->res_bases[%d] = 0x%08x\n",
1226                         res->start, i, (unsigned int)data->res_bases[i]);
1227                 if (!data->res_bases[i]) {
1228                         pr_err("Unable to map IOMEM @ PA:%#x\n", res->start);
1229                         ret = -ENOENT;
1230                         goto err_res;
1231                 }
1232
1233                 if (cpu_is_rk312x() || cpu_is_rk3036()) {
1234                         rockchip_vcodec_select(data->dbgname);
1235                         if (strstr(data->dbgname, "vop")) {
1236                                 vop_mmu_base = data->res_bases[0];
1237                                 dev_dbg(dev,"vop_mmu_base = 0x%08x\n",(unsigned int)vop_mmu_base);
1238                         }
1239                 }
1240                 if (!strstr(data->dbgname, "isp")) {
1241                         if (!iommu_reset(data->res_bases[i], data->dbgname)) {
1242                                 ret = -ENOENT;
1243                                 goto err_res;
1244                         }
1245                 }
1246         }
1247
1248         for (i = 0; i < data->num_res_irq; i++) {
1249                 ret = platform_get_irq(pdev, i);
1250                 if (ret <= 0) {
1251                         dev_err(dev,"Unable to find IRQ resource\n");
1252                         goto err_irq;
1253                 }
1254                 ret = devm_request_irq(dev, ret, rockchip_iommu_irq,
1255                                   IRQF_SHARED, dev_name(dev), data);
1256                 if (ret) {
1257                         dev_err(dev,"Unabled to register interrupt handler\n");
1258                         goto err_irq;
1259                 }
1260         }
1261         ret = rockchip_init_iovmm(dev, &data->vmm);
1262         if (ret)
1263                 goto err_irq;
1264
1265         data->iommu = dev;
1266         rwlock_init(&data->lock);
1267         INIT_LIST_HEAD(&data->node);
1268
1269         set_fault_handler(data, &default_fault_handler);
1270
1271         dev_info(dev,"(%s) Initialized\n", data->dbgname);
1272         return 0;
1273
1274 err_irq:
1275 err_res:
1276         while (data->num_res_mem-- > 0)
1277                 iounmap(data->res_bases[data->num_res_mem]);
1278 err_init:
1279 err_alloc:
1280         dev_err(dev, "Failed to initialize\n");
1281         return ret;
1282 }
1283
1284 #ifdef CONFIG_OF
1285 static const struct of_device_id iommu_dt_ids[] = {
1286         { .compatible = IEP_IOMMU_COMPATIBLE_NAME},
1287         { .compatible = VIP_IOMMU_COMPATIBLE_NAME},
1288         { .compatible = VOPB_IOMMU_COMPATIBLE_NAME},
1289         { .compatible = VOPL_IOMMU_COMPATIBLE_NAME},
1290         { .compatible = HEVC_IOMMU_COMPATIBLE_NAME},
1291         { .compatible = VPU_IOMMU_COMPATIBLE_NAME},
1292         { .compatible = ISP_IOMMU_COMPATIBLE_NAME},
1293         { .compatible = VOP_IOMMU_COMPATIBLE_NAME},
1294         { /* end */ }
1295 };
1296
1297 MODULE_DEVICE_TABLE(of, iommu_dt_ids);
1298 #endif
1299
1300 static struct platform_driver rk_iommu_driver = {
1301         .probe = rockchip_iommu_probe,
1302         .remove = NULL,
1303         .driver = {
1304                    .name = "rk_iommu",
1305                    .owner = THIS_MODULE,
1306                    .of_match_table = of_match_ptr(iommu_dt_ids),
1307         },
1308 };
1309
1310 static int __init rockchip_iommu_init_driver(void)
1311 {
1312         dump_iommu_sysfs_init();
1313
1314         return platform_driver_register(&rk_iommu_driver);
1315 }
1316
1317 core_initcall(rockchip_iommu_init_driver);