drivers/iommu/rockchip-iommu.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License version 2 as
   4  * published by the Free Software Foundation.
   5  */
   6
   7 #ifdef CONFIG_ROCKCHIP_IOMMU_DEBUG
   8 #define DEBUG
   9 #endif
  10
  11 #include <linux/io.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/slab.h>
  14 #include <linux/clk.h>
  15 #include <linux/err.h>
  16 #include <linux/mm.h>
  17 #include <linux/errno.h>
  18 #include <linux/memblock.h>
  19 #include <linux/export.h>
  20 #include <linux/module.h>
  21
  22 #include <asm/cacheflush.h>
  23 #include <asm/pgtable.h>
  24 #include <linux/of.h>
  25 #include <linux/rockchip-iovmm.h>
  26 #include <linux/rockchip/grf.h>
  27 #include <linux/rockchip/cpu.h>
  28 #include <linux/rockchip/iomap.h>
  29 #include <linux/device.h>
  30 #include "rockchip-iommu.h"
  31
  32 /* We does not consider super section mapping (16MB) */
  33 #define SPAGE_ORDER 12
  34 #define SPAGE_SIZE (1 << SPAGE_ORDER)
  35 #define SPAGE_MASK (~(SPAGE_SIZE - 1))
  36
  37 static void __iomem *rk312x_vop_mmu_base;
  38
  39 enum iommu_entry_flags {
  40         IOMMU_FLAGS_PRESENT = 0x01,
  41         IOMMU_FLAGS_READ_PERMISSION = 0x02,
  42         IOMMU_FLAGS_WRITE_PERMISSION = 0x04,
  43         IOMMU_FLAGS_OVERRIDE_CACHE = 0x8,
  44         IOMMU_FLAGS_WRITE_CACHEABLE = 0x10,
  45         IOMMU_FLAGS_WRITE_ALLOCATE = 0x20,
  46         IOMMU_FLAGS_WRITE_BUFFERABLE = 0x40,
  47         IOMMU_FLAGS_READ_CACHEABLE = 0x80,
  48         IOMMU_FLAGS_READ_ALLOCATE = 0x100,
  49         IOMMU_FLAGS_MASK = 0x1FF,
  50 };
  51
  52 #define rockchip_lv1ent_fault(sent) ((*(sent) & IOMMU_FLAGS_PRESENT) == 0)
  53 #define rockchip_lv1ent_page(sent) ((*(sent) & IOMMU_FLAGS_PRESENT) == 1)
  54 #define rockchip_lv2ent_fault(pent) ((*(pent) & IOMMU_FLAGS_PRESENT) == 0)
  55 #define rockchip_spage_phys(pent) (*(pent) & SPAGE_MASK)
  56 #define rockchip_spage_offs(iova) ((iova) & 0x0FFF)
  57
  58 #define rockchip_lv1ent_offset(iova) (((iova)>>22) & 0x03FF)
  59 #define rockchip_lv2ent_offset(iova) (((iova)>>12) & 0x03FF)
  60
  61 #define NUM_LV1ENTRIES 1024
  62 #define NUM_LV2ENTRIES 1024
  63
  64 #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(long))
  65
  66 #define rockchip_lv2table_base(sent) (*(sent) & 0xFFFFFFFE)
  67
  68 #define rockchip_mk_lv1ent_page(pa) ((pa) | IOMMU_FLAGS_PRESENT)
  69 /*write and read permission for level2 page default*/
  70 #define rockchip_mk_lv2ent_spage(pa) ((pa) | IOMMU_FLAGS_PRESENT | \
  71                              IOMMU_FLAGS_READ_PERMISSION | \
  72                              IOMMU_FLAGS_WRITE_PERMISSION)
  73
  74 #define IOMMU_REG_POLL_COUNT_FAST 1000
  75
  76 /**
  77  * MMU register numbers
  78  * Used in the register read/write routines.
  79  * See the hardware documentation for more information about each register
  80  */
  81 enum iommu_register {
  82         /**< Current Page Directory Pointer */
  83         IOMMU_REGISTER_DTE_ADDR = 0x0000,
  84         /**< Status of the MMU */
  85         IOMMU_REGISTER_STATUS = 0x0004,
  86         /**< Command register, used to control the MMU */
  87         IOMMU_REGISTER_COMMAND = 0x0008,
  88         /**< Logical address of the last page fault */
  89         IOMMU_REGISTER_PAGE_FAULT_ADDR = 0x000C,
  90         /**< Used to invalidate the mapping of a single page from the MMU */
  91         IOMMU_REGISTER_ZAP_ONE_LINE = 0x010,
  92         /**< Raw interrupt status, all interrupts visible */
  93         IOMMU_REGISTER_INT_RAWSTAT = 0x0014,
  94         /**< Indicate to the MMU that the interrupt has been received */
  95         IOMMU_REGISTER_INT_CLEAR = 0x0018,
  96         /**< Enable/disable types of interrupts */
  97         IOMMU_REGISTER_INT_MASK = 0x001C,
  98         /**< Interrupt status based on the mask */
  99         IOMMU_REGISTER_INT_STATUS = 0x0020,
 100         IOMMU_REGISTER_AUTO_GATING = 0x0024
 101 };
 102
 103 enum iommu_command {
 104         /**< Enable paging (memory translation) */
 105         IOMMU_COMMAND_ENABLE_PAGING = 0x00,
 106         /**< Disable paging (memory translation) */
 107         IOMMU_COMMAND_DISABLE_PAGING = 0x01,
 108         /**<  Enable stall on page fault */
 109         IOMMU_COMMAND_ENABLE_STALL = 0x02,
 110         /**< Disable stall on page fault */
 111         IOMMU_COMMAND_DISABLE_STALL = 0x03,
 112         /**< Zap the entire page table cache */
 113         IOMMU_COMMAND_ZAP_CACHE = 0x04,
 114         /**< Page fault processed */
 115         IOMMU_COMMAND_PAGE_FAULT_DONE = 0x05,
 116         /**< Reset the MMU back to power-on settings */
 117         IOMMU_COMMAND_HARD_RESET = 0x06
 118 };
 119
 120 /**
 121  * MMU interrupt register bits
 122  * Each cause of the interrupt is reported
 123  * through the (raw) interrupt status registers.
 124  * Multiple interrupts can be pending, so multiple bits
 125  * can be set at once.
 126  */
 127 enum iommu_interrupt {
 128         IOMMU_INTERRUPT_PAGE_FAULT = 0x01, /**< A page fault occured */
 129         IOMMU_INTERRUPT_READ_BUS_ERROR = 0x02 /**< A bus read error occured */
 130 };
 131
 132 enum iommu_status_bits {
 133         IOMMU_STATUS_BIT_PAGING_ENABLED      = 1 << 0,
 134         IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE   = 1 << 1,
 135         IOMMU_STATUS_BIT_STALL_ACTIVE        = 1 << 2,
 136         IOMMU_STATUS_BIT_IDLE                = 1 << 3,
 137         IOMMU_STATUS_BIT_REPLAY_BUFFER_EMPTY = 1 << 4,
 138         IOMMU_STATUS_BIT_PAGE_FAULT_IS_WRITE = 1 << 5,
 139         IOMMU_STATUS_BIT_STALL_NOT_ACTIVE    = 1 << 31,
 140 };
 141
 142 /**
 143  * Size of an MMU page in bytes
 144  */
 145 #define IOMMU_PAGE_SIZE 0x1000
 146
 147 /*
 148  * Size of the address space referenced by a page table page
 149  */
 150 #define IOMMU_VIRTUAL_PAGE_SIZE 0x400000 /* 4 MiB */
 151
 152 /**
 153  * Page directory index from address
 154  * Calculates the page directory index from the given address
 155  */
 156 #define IOMMU_PDE_ENTRY(address) (((address)>>22) & 0x03FF)
 157
 158 /**
 159  * Page table index from address
 160  * Calculates the page table index from the given address
 161  */
 162 #define IOMMU_PTE_ENTRY(address) (((address)>>12) & 0x03FF)
 163
 164 /**
 165  * Extract the memory address from an PDE/PTE entry
 166  */
 167 #define IOMMU_ENTRY_ADDRESS(value) ((value) & 0xFFFFFC00)
 168
 169 #define INVALID_PAGE ((u32)(~0))
 170
 171 static struct kmem_cache *lv2table_kmem_cache;
 172
 173 static unsigned long *rockchip_section_entry(unsigned long *pgtable, unsigned long iova)
 174 {
 175         return pgtable + rockchip_lv1ent_offset(iova);
 176 }
 177
 178 static unsigned long *rockchip_page_entry(unsigned long *sent, unsigned long iova)
 179 {
 180         return (unsigned long *)__va(rockchip_lv2table_base(sent)) +
 181                 rockchip_lv2ent_offset(iova);
 182 }
 183
 184 struct rk_iommu_domain {
 185         struct list_head clients; /* list of iommu_drvdata.node */
 186         unsigned long *pgtable; /* lv1 page table, 4KB */
 187         short *lv2entcnt; /* free lv2 entry counter for each section */
 188         spinlock_t lock; /* lock for this structure */
 189         spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
 190 };
 191
 192 static bool rockchip_set_iommu_active(struct iommu_drvdata *data)
 193 {
 194         /* return true if the IOMMU was not active previously
 195            and it needs to be initialized */
 196         return ++data->activations == 1;
 197 }
 198
 199 static bool rockchip_set_iommu_inactive(struct iommu_drvdata *data)
 200 {
 201         /* return true if the IOMMU is needed to be disabled */
 202         BUG_ON(data->activations < 1);
 203         return --data->activations == 0;
 204 }
 205
 206 static bool rockchip_is_iommu_active(struct iommu_drvdata *data)
 207 {
 208         return data->activations > 0;
 209 }
 210
 211 static void rockchip_iommu_disable_stall(void __iomem *base)
 212 {
 213         int i;
 214         u32 mmu_status;
 215
 216         if (base != rk312x_vop_mmu_base) {
 217                 mmu_status = __raw_readl(base + IOMMU_REGISTER_STATUS);
 218         } else {
 219                 goto skip_vop_mmu_disable;
 220         }
 221
 222         if (0 == (mmu_status & IOMMU_STATUS_BIT_PAGING_ENABLED)) {
 223                 return;
 224         }
 225
 226         if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE) {
 227                 pr_info("Aborting MMU disable stall request since it is in pagefault state.\n");
 228                 return;
 229         }
 230
 231         if (!(mmu_status & IOMMU_STATUS_BIT_STALL_ACTIVE)) {
 232                 return;
 233         }
 234
 235         skip_vop_mmu_disable:
 236         __raw_writel(IOMMU_COMMAND_DISABLE_STALL, base + IOMMU_REGISTER_COMMAND);
 237
 238         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 239                 u32 status;
 240
 241                 if (base != rk312x_vop_mmu_base) {
 242                         status = __raw_readl(base + IOMMU_REGISTER_STATUS);
 243                 } else {
 244                         int j;
 245                         while (j < 5)
 246                                 j++;
 247                         return;
 248                 }
 249
 250                 if (0 == (status & IOMMU_STATUS_BIT_STALL_ACTIVE))
 251                         break;
 252
 253                 if (status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE)
 254                         break;
 255
 256                 if (0 == (mmu_status & IOMMU_STATUS_BIT_PAGING_ENABLED))
 257                         break;
 258         }
 259
 260         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 261                 pr_info("Disable stall request failed, MMU status is 0x%08X\n",
 262                       __raw_readl(base + IOMMU_REGISTER_STATUS));
 263         }
 264 }
 265
 266 static bool rockchip_iommu_enable_stall(void __iomem *base)
 267 {
 268         int i;
 269
 270         u32 mmu_status;
 271
 272         if (base != rk312x_vop_mmu_base) {
 273                 mmu_status = __raw_readl(base + IOMMU_REGISTER_STATUS);
 274         } else {
 275                 goto skip_vop_mmu_enable;
 276         }
 277
 278         if (0 == (mmu_status & IOMMU_STATUS_BIT_PAGING_ENABLED)) {
 279                 return true;
 280         }
 281
 282         if (mmu_status & IOMMU_STATUS_BIT_STALL_ACTIVE){
 283                 pr_info("MMU stall already enabled\n");
 284                 return true;
 285         }
 286
 287         if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE) {
 288                 pr_info("Aborting MMU stall request since it is in pagefault state. mmu status is 0x%08x\n",
 289                         mmu_status);
 290                 return false;
 291         }
 292
 293         skip_vop_mmu_enable:
 294         __raw_writel(IOMMU_COMMAND_ENABLE_STALL, base + IOMMU_REGISTER_COMMAND);
 295
 296         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 297                 if (base != rk312x_vop_mmu_base) {
 298                         mmu_status = __raw_readl(base + IOMMU_REGISTER_STATUS);
 299                 } else {
 300                         int j;
 301                         while (j < 5)
 302                                 j++;
 303                         return true;
 304                 }
 305
 306                 if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE)
 307                         break;
 308
 309                 if ((mmu_status & IOMMU_STATUS_BIT_STALL_ACTIVE) &&
 310                     (0 == (mmu_status & IOMMU_STATUS_BIT_STALL_NOT_ACTIVE)))
 311                         break;
 312
 313                 if (0 == (mmu_status & (IOMMU_STATUS_BIT_PAGING_ENABLED)))
 314                         break;
 315         }
 316
 317         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 318                 pr_info("Enable stall request failed, MMU status is 0x%08X\n",
 319                        __raw_readl(base + IOMMU_REGISTER_STATUS));
 320                 return false;
 321         }
 322
 323         if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE) {
 324                 pr_info("Aborting MMU stall request since it has a pagefault.\n");
 325                 return false;
 326         }
 327
 328         return true;
 329 }
 330
 331 static bool rockchip_iommu_enable_paging(void __iomem *base)
 332 {
 333         int i;
 334
 335         __raw_writel(IOMMU_COMMAND_ENABLE_PAGING,
 336                      base + IOMMU_REGISTER_COMMAND);
 337
 338         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 339                 if (base != rk312x_vop_mmu_base) {
 340                         if (__raw_readl(base + IOMMU_REGISTER_STATUS) &
 341                                 IOMMU_STATUS_BIT_PAGING_ENABLED)
 342                         break;
 343                 } else {
 344                         int j;
 345                         while (j < 5)
 346                                 j++;
 347                         return true;
 348                 }
 349         }
 350
 351         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 352                 pr_info("Enable paging request failed, MMU status is 0x%08X\n",
 353                        __raw_readl(base + IOMMU_REGISTER_STATUS));
 354                 return false;
 355         }
 356
 357         return true;
 358 }
 359
 360 static bool rockchip_iommu_disable_paging(void __iomem *base)
 361 {
 362         int i;
 363
 364         __raw_writel(IOMMU_COMMAND_DISABLE_PAGING,
 365                      base + IOMMU_REGISTER_COMMAND);
 366
 367         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 368                 if (base != rk312x_vop_mmu_base) {
 369                         if (!(__raw_readl(base + IOMMU_REGISTER_STATUS) &
 370                                   IOMMU_STATUS_BIT_PAGING_ENABLED))
 371                                 break;
 372                 } else {
 373                         int j;
 374                         while (j < 5)
 375                                 j++;
 376                         return true;
 377                 }
 378         }
 379
 380         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 381                 pr_info("Disable paging request failed, MMU status is 0x%08X\n",
 382                        __raw_readl(base + IOMMU_REGISTER_STATUS));
 383                 return false;
 384         }
 385
 386         return true;
 387 }
 388
 389 static void rockchip_iommu_page_fault_done(void __iomem *base, const char *dbgname)
 390 {
 391         pr_info("MMU: %s: Leaving page fault mode\n",
 392                 dbgname);
 393         __raw_writel(IOMMU_COMMAND_PAGE_FAULT_DONE,
 394                      base + IOMMU_REGISTER_COMMAND);
 395 }
 396
 397 static int rockchip_iommu_zap_tlb_without_stall (void __iomem *base)
 398 {
 399         __raw_writel(IOMMU_COMMAND_ZAP_CACHE, base + IOMMU_REGISTER_COMMAND);
 400
 401         return 0;
 402 }
 403
 404 static int rockchip_iommu_zap_tlb(void __iomem *base)
 405 {
 406         if (!rockchip_iommu_enable_stall(base)) {
 407                 pr_err("%s failed\n", __func__);
 408                 return -1;
 409         }
 410
 411         __raw_writel(IOMMU_COMMAND_ZAP_CACHE, base + IOMMU_REGISTER_COMMAND);
 412
 413         rockchip_iommu_disable_stall(base);
 414
 415         return 0;
 416 }
 417
 418 static inline bool rockchip_iommu_raw_reset(void __iomem *base)
 419 {
 420         int i;
 421         unsigned int ret;
 422         unsigned int grf_value;
 423
 424         __raw_writel(0xCAFEBABE, base + IOMMU_REGISTER_DTE_ADDR);
 425
 426         if (base != rk312x_vop_mmu_base) {
 427                 ret = __raw_readl(base + IOMMU_REGISTER_DTE_ADDR);
 428                 if (!(0xCAFEB000 == ret)) {
 429                         grf_value = readl_relaxed(RK_GRF_VIRT + RK3036_GRF_SOC_CON1);
 430                         pr_info("error when %s. grf = 0x%08x\n", __func__, grf_value);
 431                         return false;
 432                 }
 433         }
 434         __raw_writel(IOMMU_COMMAND_HARD_RESET,
 435                      base + IOMMU_REGISTER_COMMAND);
 436
 437         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 438                 if (base != rk312x_vop_mmu_base) {
 439                         if (__raw_readl(base + IOMMU_REGISTER_DTE_ADDR) == 0)
 440                                 break;
 441                 } else {
 442                         int j;
 443                         while (j < 5)
 444                                 j++;
 445                         return true;
 446                 }
 447         }
 448
 449         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 450                 pr_info("%s,Reset request failed, MMU status is 0x%08X\n",
 451                        __func__, __raw_readl(base + IOMMU_REGISTER_DTE_ADDR));
 452                 return false;
 453         }
 454         return true;
 455 }
 456
 457 static void rockchip_iommu_set_ptbase(void __iomem *base, unsigned long pgd)
 458 {
 459         __raw_writel(pgd, base + IOMMU_REGISTER_DTE_ADDR);
 460 }
 461
 462 static bool rockchip_iommu_reset(void __iomem *base, const char *dbgname)
 463 {
 464         bool ret = true;
 465
 466         ret = rockchip_iommu_raw_reset(base);
 467         if (!ret) {
 468                 pr_info("(%s), %s failed\n", dbgname, __func__);
 469                 return ret;
 470         }
 471
 472         if (base != rk312x_vop_mmu_base)
 473                 __raw_writel(IOMMU_INTERRUPT_PAGE_FAULT |
 474                              IOMMU_INTERRUPT_READ_BUS_ERROR,
 475                              base + IOMMU_REGISTER_INT_MASK);
 476         else
 477                 __raw_writel(0x00, base + IOMMU_REGISTER_INT_MASK);
 478
 479         return ret;
 480 }
 481
 482 static inline void rockchip_pgtable_flush(void *vastart, void *vaend)
 483 {
 484         dmac_flush_range(vastart, vaend);
 485         outer_flush_range(virt_to_phys(vastart), virt_to_phys(vaend));
 486 }
 487
 488 static void dump_pagetbl(dma_addr_t fault_address, u32 addr_dte)
 489 {
 490         u32 dte_index, pte_index, page_offset;
 491         u32 mmu_dte_addr;
 492         phys_addr_t mmu_dte_addr_phys, dte_addr_phys;
 493         u32 *dte_addr;
 494         u32 dte;
 495         phys_addr_t pte_addr_phys = 0;
 496         u32 *pte_addr = NULL;
 497         u32 pte = 0;
 498         phys_addr_t page_addr_phys = 0;
 499         u32 page_flags = 0;
 500
 501         dte_index = rockchip_lv1ent_offset(fault_address);
 502         pte_index = rockchip_lv2ent_offset(fault_address);
 503         page_offset = (u32)(fault_address & 0x00000fff);
 504
 505         mmu_dte_addr = addr_dte;
 506         mmu_dte_addr_phys = (phys_addr_t)mmu_dte_addr;
 507
 508         dte_addr_phys = mmu_dte_addr_phys + (4 * dte_index);
 509         dte_addr = phys_to_virt(dte_addr_phys);
 510         dte = *dte_addr;
 511
 512         if (!(IOMMU_FLAGS_PRESENT & dte))
 513                 goto print_it;
 514
 515         pte_addr_phys = ((phys_addr_t)dte & 0xfffff000) + (pte_index * 4);
 516         pte_addr = phys_to_virt(pte_addr_phys);
 517         pte = *pte_addr;
 518
 519         if (!(IOMMU_FLAGS_PRESENT & pte))
 520                 goto print_it;
 521
 522         page_addr_phys = ((phys_addr_t)pte & 0xfffff000) + page_offset;
 523         page_flags = pte & 0x000001fe;
 524
 525 print_it:
 526         pr_err("iova = %pad: dte_index: 0x%03x pte_index: 0x%03x page_offset: 0x%03x\n",
 527                 &fault_address, dte_index, pte_index, page_offset);
 528         pr_err("mmu_dte_addr: %pa dte@%pa: %#08x valid: %u pte@%pa: %#08x valid: %u page@%pa flags: %#03x\n",
 529                 &mmu_dte_addr_phys, &dte_addr_phys, dte,
 530                 (dte & IOMMU_FLAGS_PRESENT), &pte_addr_phys, pte,
 531                 (pte & IOMMU_FLAGS_PRESENT), &page_addr_phys, page_flags);
 532 }
 533
 534 static irqreturn_t rockchip_iommu_irq(int irq, void *dev_id)
 535 {
 536         /* SYSMMU is in blocked when interrupt occurred. */
 537         struct iommu_drvdata *data = dev_id;
 538         u32 status;
 539         u32 rawstat;
 540         dma_addr_t fault_address;
 541         int i;
 542         unsigned long flags;
 543         int ret;
 544         u32 reg_status;
 545
 546         spin_lock_irqsave(&data->data_lock, flags);
 547
 548         if (!rockchip_is_iommu_active(data)) {
 549                 spin_unlock_irqrestore(&data->data_lock, flags);
 550                 return IRQ_HANDLED;
 551         }
 552
 553         for (i = 0; i < data->num_res_mem; i++) {
 554                 status = __raw_readl(data->res_bases[i] +
 555                                      IOMMU_REGISTER_INT_STATUS);
 556                 if (status == 0)
 557                         continue;
 558
 559                 rawstat = __raw_readl(data->res_bases[i] +
 560                                       IOMMU_REGISTER_INT_RAWSTAT);
 561
 562                 reg_status = __raw_readl(data->res_bases[i] +
 563                                          IOMMU_REGISTER_STATUS);
 564
 565                 dev_info(data->iommu, "1.rawstat = 0x%08x,status = 0x%08x,reg_status = 0x%08x\n",
 566                          rawstat, status, reg_status);
 567
 568                 if (rawstat & IOMMU_INTERRUPT_PAGE_FAULT) {
 569                         u32 dte;
 570                         int flags;
 571
 572                         fault_address = __raw_readl(data->res_bases[i] +
 573                                             IOMMU_REGISTER_PAGE_FAULT_ADDR);
 574
 575                         dte = __raw_readl(data->res_bases[i] +
 576                                           IOMMU_REGISTER_DTE_ADDR);
 577
 578                         flags = (status & 32) ? 1 : 0;
 579
 580                         dev_err(data->iommu, "Page fault detected at %pad from bus id %d of type %s on %s\n",
 581                                 &fault_address, (status >> 6) & 0x1F,
 582                                 (flags == 1) ? "write" : "read", data->dbgname);
 583
 584                         dump_pagetbl(fault_address, dte);
 585
 586                         if (data->domain)
 587                                 report_iommu_fault(data->domain, data->iommu,
 588                                                    fault_address, flags);
 589
 590                         rockchip_iommu_page_fault_done(data->res_bases[i],
 591                                                        data->dbgname);
 592                 }
 593
 594                 if (rawstat & IOMMU_INTERRUPT_READ_BUS_ERROR) {
 595                         dev_err(data->iommu, "bus error occured at %pad\n",
 596                                 &fault_address);
 597                 }
 598
 599                 if (rawstat & ~(IOMMU_INTERRUPT_READ_BUS_ERROR |
 600                     IOMMU_INTERRUPT_PAGE_FAULT)) {
 601                         dev_err(data->iommu, "unexpected int_status: %#08x\n\n",
 602                                 rawstat);
 603                 }
 604
 605                 __raw_writel(rawstat, data->res_bases[i] +
 606                              IOMMU_REGISTER_INT_CLEAR);
 607
 608                 status = __raw_readl(data->res_bases[i] +
 609                                      IOMMU_REGISTER_INT_STATUS);
 610
 611                 rawstat = __raw_readl(data->res_bases[i] +
 612                                       IOMMU_REGISTER_INT_RAWSTAT);
 613
 614                 reg_status = __raw_readl(data->res_bases[i] +
 615                                          IOMMU_REGISTER_STATUS);
 616
 617                 dev_info(data->iommu, "2.rawstat = 0x%08x,status = 0x%08x,reg_status = 0x%08x\n",
 618                          rawstat, status, reg_status);
 619
 620                 ret = rockchip_iommu_zap_tlb_without_stall(data->res_bases[i]);
 621                 if (ret)
 622                         dev_err(data->iommu, "(%s) %s failed\n", data->dbgname,
 623                                 __func__);
 624         }
 625
 626         spin_unlock_irqrestore(&data->data_lock, flags);
 627         return IRQ_HANDLED;
 628 }
 629
 630 static bool rockchip_iommu_disable(struct iommu_drvdata *data)
 631 {
 632         unsigned long flags;
 633         int i;
 634         bool ret = false;
 635
 636         spin_lock_irqsave(&data->data_lock, flags);
 637
 638         if (!rockchip_set_iommu_inactive(data)) {
 639                 spin_unlock_irqrestore(&data->data_lock, flags);
 640                 dev_info(data->iommu,"(%s) %d times left to be disabled\n",
 641                          data->dbgname, data->activations);
 642                 return ret;
 643         }
 644
 645         for (i = 0; i < data->num_res_mem; i++) {
 646                 ret = rockchip_iommu_enable_stall(data->res_bases[i]);
 647                 if (!ret) {
 648                         dev_info(data->iommu, "(%s), %s failed\n",
 649                                  data->dbgname, __func__);
 650                         spin_unlock_irqrestore(&data->data_lock, flags);
 651                         return false;
 652                 }
 653
 654                 __raw_writel(0, data->res_bases[i] + IOMMU_REGISTER_INT_MASK);
 655
 656                 ret = rockchip_iommu_disable_paging(data->res_bases[i]);
 657                 if (!ret) {
 658                         rockchip_iommu_disable_stall(data->res_bases[i]);
 659                         spin_unlock_irqrestore(&data->data_lock, flags);
 660                         dev_info(data->iommu, "%s error\n", __func__);
 661                         return ret;
 662                 }
 663                 rockchip_iommu_disable_stall(data->res_bases[i]);
 664         }
 665
 666         data->pgtable = 0;
 667
 668         spin_unlock_irqrestore(&data->data_lock, flags);
 669
 670         dev_dbg(data->iommu,"(%s) Disabled\n", data->dbgname);
 671
 672         return ret;
 673 }
 674
 675 /* __rk_sysmmu_enable: Enables System MMU
 676  *
 677  * returns -error if an error occurred and System MMU is not enabled,
 678  * 0 if the System MMU has been just enabled and 1 if System MMU was already
 679  * enabled before.
 680  */
 681 static int rockchip_iommu_enable(struct iommu_drvdata *data, unsigned long pgtable)
 682 {
 683         int i, ret = 0;
 684         unsigned long flags;
 685
 686         spin_lock_irqsave(&data->data_lock, flags);
 687
 688         if (!rockchip_set_iommu_active(data)) {
 689                 if (WARN_ON(pgtable != data->pgtable)) {
 690                         ret = -EBUSY;
 691                         rockchip_set_iommu_inactive(data);
 692                 } else {
 693                         ret = 1;
 694                 }
 695
 696                 spin_unlock_irqrestore(&data->data_lock, flags);
 697                 dev_info(data->iommu, "(%s) Already enabled\n", data->dbgname);
 698
 699                 return ret;
 700         }
 701
 702         for (i = 0; i < data->num_res_mem; i++) {
 703                 ret = rockchip_iommu_enable_stall(data->res_bases[i]);
 704                 if (!ret) {
 705                         dev_info(data->iommu, "(%s), %s failed\n",
 706                                  data->dbgname, __func__);
 707                         spin_unlock_irqrestore(&data->data_lock, flags);
 708                         return -EBUSY;
 709                 }
 710
 711                 if (!strstr(data->dbgname, "isp")) {
 712                         if (!rockchip_iommu_reset(data->res_bases[i],
 713                              data->dbgname)) {
 714                                 spin_unlock_irqrestore(&data->data_lock, flags);
 715                                 return -ENOENT;
 716                         }
 717                 }
 718
 719                 rockchip_iommu_set_ptbase(data->res_bases[i], pgtable);
 720
 721                 __raw_writel(IOMMU_COMMAND_ZAP_CACHE, data->res_bases[i] +
 722                              IOMMU_REGISTER_COMMAND);
 723
 724                 __raw_writel(IOMMU_INTERRUPT_PAGE_FAULT |
 725                              IOMMU_INTERRUPT_READ_BUS_ERROR,
 726                              data->res_bases[i] + IOMMU_REGISTER_INT_MASK);
 727
 728                 ret = rockchip_iommu_enable_paging(data->res_bases[i]);
 729                 if (!ret) {
 730                         spin_unlock_irqrestore(&data->data_lock, flags);
 731                         dev_info(data->iommu, "(%s), %s failed\n",
 732                                  data->dbgname, __func__);
 733                         return -EBUSY;
 734                 }
 735
 736                 rockchip_iommu_disable_stall(data->res_bases[i]);
 737         }
 738
 739         data->pgtable = pgtable;
 740
 741         dev_dbg(data->iommu,"(%s) Enabled\n", data->dbgname);
 742
 743         spin_unlock_irqrestore(&data->data_lock, flags);
 744
 745         return 0;
 746 }
 747
 748 int rockchip_iommu_tlb_invalidate(struct device *dev)
 749 {
 750         unsigned long flags;
 751         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 752
 753         spin_lock_irqsave(&data->data_lock, flags);
 754
 755         if (rockchip_is_iommu_active(data)) {
 756                 int i;
 757                 int ret;
 758
 759                 for (i = 0; i < data->num_res_mem; i++) {
 760                         ret = rockchip_iommu_zap_tlb(data->res_bases[i]);
 761                         if (ret) {
 762                                 dev_err(dev->archdata.iommu, "(%s) %s failed\n",
 763                                         data->dbgname, __func__);
 764                                 spin_unlock_irqrestore(&data->data_lock, flags);
 765                                 return ret;
 766                         }
 767
 768                 }
 769         } else {
 770                 dev_dbg(dev->archdata.iommu, "(%s) Disabled. Skipping invalidating TLB.\n",
 771                         data->dbgname);
 772         }
 773
 774         spin_unlock_irqrestore(&data->data_lock, flags);
 775
 776         return 0;
 777 }
 778
 779 static phys_addr_t rockchip_iommu_iova_to_phys(struct iommu_domain *domain,
 780                                                dma_addr_t iova)
 781 {
 782         struct rk_iommu_domain *priv = domain->priv;
 783         unsigned long *entry;
 784         unsigned long flags;
 785         phys_addr_t phys = 0;
 786
 787         spin_lock_irqsave(&priv->pgtablelock, flags);
 788
 789         entry = rockchip_section_entry(priv->pgtable, iova);
 790         entry = rockchip_page_entry(entry, iova);
 791         phys = rockchip_spage_phys(entry) + rockchip_spage_offs(iova);
 792
 793         spin_unlock_irqrestore(&priv->pgtablelock, flags);
 794
 795         return phys;
 796 }
 797
 798 static int rockchip_lv2set_page(unsigned long *pent, phys_addr_t paddr,
 799                        size_t size, short *pgcnt)
 800 {
 801         if (!rockchip_lv2ent_fault(pent))
 802                 return -EADDRINUSE;
 803
 804         *pent = rockchip_mk_lv2ent_spage(paddr);
 805         rockchip_pgtable_flush(pent, pent + 1);
 806         *pgcnt -= 1;
 807         return 0;
 808 }
 809
 810 static unsigned long *rockchip_alloc_lv2entry(unsigned long *sent,
 811                                      unsigned long iova, short *pgcounter)
 812 {
 813         if (rockchip_lv1ent_fault(sent)) {
 814                 unsigned long *pent;
 815
 816                 pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
 817                 BUG_ON((unsigned long)pent & (LV2TABLE_SIZE - 1));
 818                 if (!pent)
 819                         return NULL;
 820
 821                 *sent = rockchip_mk_lv1ent_page(__pa(pent));
 822                 kmemleak_ignore(pent);
 823                 *pgcounter = NUM_LV2ENTRIES;
 824                 rockchip_pgtable_flush(pent, pent + NUM_LV2ENTRIES);
 825                 rockchip_pgtable_flush(sent, sent + 1);
 826         }
 827         return rockchip_page_entry(sent, iova);
 828 }
 829
 830 static size_t rockchip_iommu_unmap(struct iommu_domain *domain,
 831                                    unsigned long iova, size_t size)
 832 {
 833         struct rk_iommu_domain *priv = domain->priv;
 834         unsigned long flags;
 835         unsigned long *ent;
 836
 837         BUG_ON(priv->pgtable == NULL);
 838
 839         spin_lock_irqsave(&priv->pgtablelock, flags);
 840
 841         ent = rockchip_section_entry(priv->pgtable, iova);
 842
 843         if (unlikely(rockchip_lv1ent_fault(ent))) {
 844                 if (size > SPAGE_SIZE)
 845                         size = SPAGE_SIZE;
 846                 goto done;
 847         }
 848
 849         /* lv1ent_page(sent) == true here */
 850
 851         ent = rockchip_page_entry(ent, iova);
 852
 853         if (unlikely(rockchip_lv2ent_fault(ent))) {
 854                 size = SPAGE_SIZE;
 855                 goto done;
 856         }
 857
 858         *ent = 0;
 859         size = SPAGE_SIZE;
 860         priv->lv2entcnt[rockchip_lv1ent_offset(iova)] += 1;
 861         goto done;
 862
 863 done:
 864         #if 0
 865         pr_info("%s:unmap iova 0x%lx/0x%x bytes\n",
 866                   __func__, iova,size);
 867         #endif
 868         spin_unlock_irqrestore(&priv->pgtablelock, flags);
 869
 870         return size;
 871 }
 872
 873 static int rockchip_iommu_map(struct iommu_domain *domain, unsigned long iova,
 874                               phys_addr_t paddr, size_t size, int prot)
 875 {
 876         struct rk_iommu_domain *priv = domain->priv;
 877         unsigned long *entry;
 878         unsigned long flags;
 879         int ret = -ENOMEM;
 880         unsigned long *pent;
 881
 882         BUG_ON(priv->pgtable == NULL);
 883
 884         spin_lock_irqsave(&priv->pgtablelock, flags);
 885
 886         entry = rockchip_section_entry(priv->pgtable, iova);
 887
 888         pent = rockchip_alloc_lv2entry(entry, iova,
 889                               &priv->lv2entcnt[rockchip_lv1ent_offset(iova)]);
 890         if (!pent)
 891                 ret = -ENOMEM;
 892         else
 893                 ret = rockchip_lv2set_page(pent, paddr, size,
 894                                 &priv->lv2entcnt[rockchip_lv1ent_offset(iova)]);
 895
 896         if (ret) {
 897                 pr_info("%s: Failed to map iova 0x%lx/0x%x bytes\n", __func__,
 898                        iova, size);
 899         }
 900         spin_unlock_irqrestore(&priv->pgtablelock, flags);
 901
 902         return ret;
 903 }
 904
 905 static void rockchip_iommu_detach_device(struct iommu_domain *domain, struct device *dev)
 906 {
 907         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 908         struct rk_iommu_domain *priv = domain->priv;
 909         struct list_head *pos;
 910         unsigned long flags;
 911         bool found = false;
 912
 913         spin_lock_irqsave(&priv->lock, flags);
 914
 915         list_for_each(pos, &priv->clients) {
 916                 if (list_entry(pos, struct iommu_drvdata, node) == data) {
 917                         found = true;
 918                         break;
 919                 }
 920         }
 921
 922         if (!found) {
 923                 spin_unlock_irqrestore(&priv->lock, flags);
 924                 return;
 925         }
 926
 927         if (rockchip_iommu_disable(data)) {
 928                 dev_dbg(dev->archdata.iommu,"%s: Detached IOMMU with pgtable %#lx\n",
 929                         __func__, __pa(priv->pgtable));
 930                 data->domain = NULL;
 931                 list_del_init(&data->node);
 932
 933         } else
 934                 dev_err(dev->archdata.iommu,"%s: Detaching IOMMU with pgtable %#lx delayed",
 935                         __func__, __pa(priv->pgtable));
 936
 937         spin_unlock_irqrestore(&priv->lock, flags);
 938 }
 939
 940 static int rockchip_iommu_attach_device(struct iommu_domain *domain, struct device *dev)
 941 {
 942         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 943         struct rk_iommu_domain *priv = domain->priv;
 944         unsigned long flags;
 945         int ret;
 946
 947         spin_lock_irqsave(&priv->lock, flags);
 948
 949         ret = rockchip_iommu_enable(data, __pa(priv->pgtable));
 950
 951         if (ret == 0) {
 952                 /* 'data->node' must not be appeared in priv->clients */
 953                 BUG_ON(!list_empty(&data->node));
 954                 list_add_tail(&data->node, &priv->clients);
 955                 data->domain = domain;
 956         }
 957
 958         spin_unlock_irqrestore(&priv->lock, flags);
 959
 960         if (ret < 0) {
 961                 dev_err(dev->archdata.iommu,"%s: Failed to attach IOMMU with pgtable %#lx\n",
 962                        __func__, __pa(priv->pgtable));
 963         } else if (ret > 0) {
 964                 dev_dbg(dev->archdata.iommu,"%s: IOMMU with pgtable 0x%lx already attached\n",
 965                         __func__, __pa(priv->pgtable));
 966         } else {
 967                 dev_dbg(dev->archdata.iommu,"%s: Attached new IOMMU with pgtable 0x%lx\n",
 968                         __func__, __pa(priv->pgtable));
 969         }
 970
 971         return ret;
 972 }
 973
 974 static void rockchip_iommu_domain_destroy(struct iommu_domain *domain)
 975 {
 976         struct rk_iommu_domain *priv = domain->priv;
 977         int i;
 978
 979         WARN_ON(!list_empty(&priv->clients));
 980
 981         for (i = 0; i < NUM_LV1ENTRIES; i++)
 982                 if (rockchip_lv1ent_page(priv->pgtable + i))
 983                         kmem_cache_free(lv2table_kmem_cache,
 984                                         __va(rockchip_lv2table_base(priv->pgtable + i)));
 985
 986         free_pages((unsigned long)priv->pgtable, 0);
 987         free_pages((unsigned long)priv->lv2entcnt, 0);
 988         kfree(domain->priv);
 989         domain->priv = NULL;
 990 }
 991
 992 static int rockchip_iommu_domain_init(struct iommu_domain *domain)
 993 {
 994         struct rk_iommu_domain *priv;
 995
 996         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 997         if (!priv)
 998                 return -ENOMEM;
 999
1000 /*rk32xx iommu use 2 level pagetable,
1001    level1 and leve2 both have 1024 entries,each entry  occupy 4 bytes,
1002    so alloc a page size for each page table
1003 */
1004         priv->pgtable = (unsigned long *)__get_free_pages(GFP_KERNEL |
1005                                                           __GFP_ZERO, 0);
1006         if (!priv->pgtable)
1007                 goto err_pgtable;
1008
1009         priv->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL |
1010                                                     __GFP_ZERO, 0);
1011         if (!priv->lv2entcnt)
1012                 goto err_counter;
1013
1014         rockchip_pgtable_flush(priv->pgtable, priv->pgtable + NUM_LV1ENTRIES);
1015
1016         spin_lock_init(&priv->lock);
1017         spin_lock_init(&priv->pgtablelock);
1018         INIT_LIST_HEAD(&priv->clients);
1019
1020         domain->priv = priv;
1021         return 0;
1022
1023 err_counter:
1024         free_pages((unsigned long)priv->pgtable, 0);
1025 err_pgtable:
1026         kfree(priv);
1027         return -ENOMEM;
1028 }
1029
1030 static struct iommu_ops rk_iommu_ops = {
1031         .domain_init = &rockchip_iommu_domain_init,
1032         .domain_destroy = &rockchip_iommu_domain_destroy,
1033         .attach_dev = &rockchip_iommu_attach_device,
1034         .detach_dev = &rockchip_iommu_detach_device,
1035         .map = &rockchip_iommu_map,
1036         .unmap = &rockchip_iommu_unmap,
1037         .iova_to_phys = &rockchip_iommu_iova_to_phys,
1038         .pgsize_bitmap = SPAGE_SIZE,
1039 };
1040
1041 static int  rockchip_get_iommu_resource_num(struct platform_device *pdev,
1042                                              unsigned int type)
1043 {
1044         int num = 0;
1045         int i;
1046
1047         for (i = 0; i < pdev->num_resources; i++) {
1048                 struct resource *r = &pdev->resource[i];
1049                 if (type == resource_type(r))
1050                         num++;
1051         }
1052
1053         return num;
1054 }
1055
1056 static int rockchip_iommu_probe(struct platform_device *pdev)
1057 {
1058         int i, ret;
1059         struct device *dev;
1060         struct iommu_drvdata *data;
1061
1062         dev = &pdev->dev;
1063
1064         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
1065         if (!data) {
1066                 dev_dbg(dev, "Not enough memory\n");
1067                 return -ENOMEM;
1068         }
1069
1070         dev_set_drvdata(dev, data);
1071
1072         if (pdev->dev.of_node)
1073                 of_property_read_string(pdev->dev.of_node, "dbgname",
1074                                         &(data->dbgname));
1075         else
1076                 dev_dbg(dev, "dbgname not assigned in device tree or device node not exist\r\n");
1077
1078         dev_info(dev,"(%s) Enter\n", data->dbgname);
1079
1080         data->num_res_mem = rockchip_get_iommu_resource_num(pdev,
1081                                 IORESOURCE_MEM);
1082         if (0 == data->num_res_mem) {
1083                 dev_err(dev,"can't find iommu memory resource \r\n");
1084                 return -ENOMEM;
1085         }
1086         dev_dbg(dev,"data->num_res_mem=%d\n", data->num_res_mem);
1087
1088         data->num_res_irq = rockchip_get_iommu_resource_num(pdev,
1089                                 IORESOURCE_IRQ);
1090         if (0 == data->num_res_irq) {
1091                 dev_err(dev,"can't find iommu irq resource \r\n");
1092                 return -ENOMEM;
1093         }
1094         dev_dbg(dev,"data->num_res_irq=%d\n", data->num_res_irq);
1095
1096         data->res_bases = devm_kmalloc_array(dev, data->num_res_mem,
1097                                 sizeof(*data->res_bases), GFP_KERNEL);
1098         if (data->res_bases == NULL) {
1099                 dev_err(dev, "Not enough memory\n");
1100                 return -ENOMEM;
1101         }
1102
1103         for (i = 0; i < data->num_res_mem; i++) {
1104                 struct resource *res;
1105
1106                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1107                 if (!res) {
1108                         dev_err(dev,"Unable to find IOMEM region\n");
1109                         return -ENOENT;
1110                 }
1111
1112                 data->res_bases[i] = devm_ioremap(dev,res->start,
1113                                                   resource_size(res));
1114                 if (!data->res_bases[i]) {
1115                         dev_err(dev, "Unable to map IOMEM @ PA:%#x\n",
1116                                 res->start);
1117                         return -ENOMEM;
1118                 }
1119
1120                 dev_dbg(dev,"res->start = 0x%08x ioremap to data->res_bases[%d] = 0x%08x\n",
1121                         res->start, i, (unsigned int)data->res_bases[i]);
1122
1123                 if (strstr(data->dbgname, "vop") &&
1124                     (soc_is_rk3128() || soc_is_rk3126())) {
1125                         rk312x_vop_mmu_base = data->res_bases[0];
1126                         dev_dbg(dev, "rk312x_vop_mmu_base = 0x%08x\n",
1127                                 (unsigned int)rk312x_vop_mmu_base);
1128                 }
1129         }
1130
1131         for (i = 0; i < data->num_res_irq; i++) {
1132                 if ((soc_is_rk3128() || soc_is_rk3126()) &&
1133                     strstr(data->dbgname, "vop")) {
1134                         dev_info(dev, "skip request vop mmu irq\n");
1135                         continue;
1136                 }
1137
1138                 ret = platform_get_irq(pdev, i);
1139                 if (ret <= 0) {
1140                         dev_err(dev,"Unable to find IRQ resource\n");
1141                         return -ENOENT;
1142                 }
1143
1144                 ret = devm_request_irq(dev, ret, rockchip_iommu_irq,
1145                                   IRQF_SHARED, dev_name(dev), data);
1146                 if (ret) {
1147                         dev_err(dev, "Unabled to register interrupt handler\n");
1148                         return -ENOENT;
1149                 }
1150         }
1151
1152         ret = rockchip_init_iovmm(dev, &data->vmm);
1153         if (ret)
1154                 return ret;
1155
1156         data->iommu = dev;
1157         spin_lock_init(&data->data_lock);
1158         INIT_LIST_HEAD(&data->node);
1159
1160         dev_info(dev,"(%s) Initialized\n", data->dbgname);
1161
1162         return 0;
1163 }
1164
1165 #ifdef CONFIG_OF
1166 static const struct of_device_id iommu_dt_ids[] = {
1167         { .compatible = IEP_IOMMU_COMPATIBLE_NAME},
1168         { .compatible = VIP_IOMMU_COMPATIBLE_NAME},
1169         { .compatible = VOPB_IOMMU_COMPATIBLE_NAME},
1170         { .compatible = VOPL_IOMMU_COMPATIBLE_NAME},
1171         { .compatible = HEVC_IOMMU_COMPATIBLE_NAME},
1172         { .compatible = VPU_IOMMU_COMPATIBLE_NAME},
1173         { .compatible = ISP_IOMMU_COMPATIBLE_NAME},
1174         { .compatible = VOP_IOMMU_COMPATIBLE_NAME},
1175         { /* end */ }
1176 };
1177
1178 MODULE_DEVICE_TABLE(of, iommu_dt_ids);
1179 #endif
1180
1181 static struct platform_driver rk_iommu_driver = {
1182         .probe = rockchip_iommu_probe,
1183         .remove = NULL,
1184         .driver = {
1185                    .name = "rk_iommu",
1186                    .owner = THIS_MODULE,
1187                    .of_match_table = of_match_ptr(iommu_dt_ids),
1188         },
1189 };
1190
1191 static int __init rockchip_iommu_init_driver(void)
1192 {
1193         int ret;
1194
1195         lv2table_kmem_cache = kmem_cache_create("rk-iommu-lv2table",
1196                                                 LV2TABLE_SIZE, LV2TABLE_SIZE,
1197                                                 0, NULL);
1198         if (!lv2table_kmem_cache) {
1199                 pr_info("%s: failed to create kmem cache\n", __func__);
1200                 return -ENOMEM;
1201         }
1202
1203         ret = bus_set_iommu(&platform_bus_type, &rk_iommu_ops);
1204         if (ret)
1205                 return ret;
1206
1207         return platform_driver_register(&rk_iommu_driver);
1208 }
1209
1210 core_initcall(rockchip_iommu_init_driver);