drivers/iommu/rockchip-iommu.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License version 2 as
   4  * published by the Free Software Foundation.
   5  */
   6
   7 #ifdef CONFIG_ROCKCHIP_IOMMU_DEBUG
   8 #define DEBUG
   9 #endif
  10
  11 #include <linux/io.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/slab.h>
  14 #include <linux/clk.h>
  15 #include <linux/err.h>
  16 #include <linux/mm.h>
  17 #include <linux/errno.h>
  18 #include <linux/memblock.h>
  19 #include <linux/export.h>
  20 #include <linux/module.h>
  21
  22 #include <asm/cacheflush.h>
  23 #include <asm/pgtable.h>
  24 #include <linux/of.h>
  25 #include <linux/rockchip-iovmm.h>
  26 #include <linux/rockchip/grf.h>
  27 #include <linux/rockchip/cpu.h>
  28 #include <linux/rockchip/iomap.h>
  29 #include <linux/device.h>
  30 #include "rockchip-iommu.h"
  31
  32 /* We does not consider super section mapping (16MB) */
  33 #define SPAGE_ORDER 12
  34 #define SPAGE_SIZE (1 << SPAGE_ORDER)
  35 #define SPAGE_MASK (~(SPAGE_SIZE - 1))
  36
  37 static void __iomem *rk312x_vop_mmu_base;
  38
  39 enum iommu_entry_flags {
  40         IOMMU_FLAGS_PRESENT = 0x01,
  41         IOMMU_FLAGS_READ_PERMISSION = 0x02,
  42         IOMMU_FLAGS_WRITE_PERMISSION = 0x04,
  43         IOMMU_FLAGS_OVERRIDE_CACHE = 0x8,
  44         IOMMU_FLAGS_WRITE_CACHEABLE = 0x10,
  45         IOMMU_FLAGS_WRITE_ALLOCATE = 0x20,
  46         IOMMU_FLAGS_WRITE_BUFFERABLE = 0x40,
  47         IOMMU_FLAGS_READ_CACHEABLE = 0x80,
  48         IOMMU_FLAGS_READ_ALLOCATE = 0x100,
  49         IOMMU_FLAGS_MASK = 0x1FF,
  50 };
  51
  52 #define rockchip_lv1ent_fault(sent) ((*(sent) & IOMMU_FLAGS_PRESENT) == 0)
  53 #define rockchip_lv1ent_page(sent) ((*(sent) & IOMMU_FLAGS_PRESENT) == 1)
  54 #define rockchip_lv2ent_fault(pent) ((*(pent) & IOMMU_FLAGS_PRESENT) == 0)
  55 #define rockchip_spage_phys(pent) (*(pent) & SPAGE_MASK)
  56 #define rockchip_spage_offs(iova) ((iova) & 0x0FFF)
  57
  58 #define rockchip_lv1ent_offset(iova) (((iova)>>22) & 0x03FF)
  59 #define rockchip_lv2ent_offset(iova) (((iova)>>12) & 0x03FF)
  60
  61 #define NUM_LV1ENTRIES 1024
  62 #define NUM_LV2ENTRIES 1024
  63
  64 #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(long))
  65
  66 #define rockchip_lv2table_base(sent) (*(sent) & 0xFFFFFFFE)
  67
  68 #define rockchip_mk_lv1ent_page(pa) ((pa) | IOMMU_FLAGS_PRESENT)
  69 /*write and read permission for level2 page default*/
  70 #define rockchip_mk_lv2ent_spage(pa) ((pa) | IOMMU_FLAGS_PRESENT | \
  71                              IOMMU_FLAGS_READ_PERMISSION | \
  72                              IOMMU_FLAGS_WRITE_PERMISSION)
  73
  74 #define IOMMU_REG_POLL_COUNT_FAST 1000
  75
  76 /**
  77  * MMU register numbers
  78  * Used in the register read/write routines.
  79  * See the hardware documentation for more information about each register
  80  */
  81 enum iommu_register {
  82         /**< Current Page Directory Pointer */
  83         IOMMU_REGISTER_DTE_ADDR = 0x0000,
  84         /**< Status of the MMU */
  85         IOMMU_REGISTER_STATUS = 0x0004,
  86         /**< Command register, used to control the MMU */
  87         IOMMU_REGISTER_COMMAND = 0x0008,
  88         /**< Logical address of the last page fault */
  89         IOMMU_REGISTER_PAGE_FAULT_ADDR = 0x000C,
  90         /**< Used to invalidate the mapping of a single page from the MMU */
  91         IOMMU_REGISTER_ZAP_ONE_LINE = 0x010,
  92         /**< Raw interrupt status, all interrupts visible */
  93         IOMMU_REGISTER_INT_RAWSTAT = 0x0014,
  94         /**< Indicate to the MMU that the interrupt has been received */
  95         IOMMU_REGISTER_INT_CLEAR = 0x0018,
  96         /**< Enable/disable types of interrupts */
  97         IOMMU_REGISTER_INT_MASK = 0x001C,
  98         /**< Interrupt status based on the mask */
  99         IOMMU_REGISTER_INT_STATUS = 0x0020,
 100         IOMMU_REGISTER_AUTO_GATING = 0x0024
 101 };
 102
 103 enum iommu_command {
 104         /**< Enable paging (memory translation) */
 105         IOMMU_COMMAND_ENABLE_PAGING = 0x00,
 106         /**< Disable paging (memory translation) */
 107         IOMMU_COMMAND_DISABLE_PAGING = 0x01,
 108         /**<  Enable stall on page fault */
 109         IOMMU_COMMAND_ENABLE_STALL = 0x02,
 110         /**< Disable stall on page fault */
 111         IOMMU_COMMAND_DISABLE_STALL = 0x03,
 112         /**< Zap the entire page table cache */
 113         IOMMU_COMMAND_ZAP_CACHE = 0x04,
 114         /**< Page fault processed */
 115         IOMMU_COMMAND_PAGE_FAULT_DONE = 0x05,
 116         /**< Reset the MMU back to power-on settings */
 117         IOMMU_COMMAND_HARD_RESET = 0x06
 118 };
 119
 120 /**
 121  * MMU interrupt register bits
 122  * Each cause of the interrupt is reported
 123  * through the (raw) interrupt status registers.
 124  * Multiple interrupts can be pending, so multiple bits
 125  * can be set at once.
 126  */
 127 enum iommu_interrupt {
 128         IOMMU_INTERRUPT_PAGE_FAULT = 0x01, /**< A page fault occured */
 129         IOMMU_INTERRUPT_READ_BUS_ERROR = 0x02 /**< A bus read error occured */
 130 };
 131
 132 enum iommu_status_bits {
 133         IOMMU_STATUS_BIT_PAGING_ENABLED      = 1 << 0,
 134         IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE   = 1 << 1,
 135         IOMMU_STATUS_BIT_STALL_ACTIVE        = 1 << 2,
 136         IOMMU_STATUS_BIT_IDLE                = 1 << 3,
 137         IOMMU_STATUS_BIT_REPLAY_BUFFER_EMPTY = 1 << 4,
 138         IOMMU_STATUS_BIT_PAGE_FAULT_IS_WRITE = 1 << 5,
 139         IOMMU_STATUS_BIT_STALL_NOT_ACTIVE    = 1 << 31,
 140 };
 141
 142 /**
 143  * Size of an MMU page in bytes
 144  */
 145 #define IOMMU_PAGE_SIZE 0x1000
 146
 147 /*
 148  * Size of the address space referenced by a page table page
 149  */
 150 #define IOMMU_VIRTUAL_PAGE_SIZE 0x400000 /* 4 MiB */
 151
 152 /**
 153  * Page directory index from address
 154  * Calculates the page directory index from the given address
 155  */
 156 #define IOMMU_PDE_ENTRY(address) (((address)>>22) & 0x03FF)
 157
 158 /**
 159  * Page table index from address
 160  * Calculates the page table index from the given address
 161  */
 162 #define IOMMU_PTE_ENTRY(address) (((address)>>12) & 0x03FF)
 163
 164 /**
 165  * Extract the memory address from an PDE/PTE entry
 166  */
 167 #define IOMMU_ENTRY_ADDRESS(value) ((value) & 0xFFFFFC00)
 168
 169 #define INVALID_PAGE ((u32)(~0))
 170
 171 static struct kmem_cache *lv2table_kmem_cache;
 172
 173 static unsigned long *rockchip_section_entry(unsigned long *pgtable, unsigned long iova)
 174 {
 175         return pgtable + rockchip_lv1ent_offset(iova);
 176 }
 177
 178 static unsigned long *rockchip_page_entry(unsigned long *sent, unsigned long iova)
 179 {
 180         return (unsigned long *)__va(rockchip_lv2table_base(sent)) +
 181                 rockchip_lv2ent_offset(iova);
 182 }
 183
 184 struct rk_iommu_domain {
 185         struct list_head clients; /* list of iommu_drvdata.node */
 186         unsigned long *pgtable; /* lv1 page table, 4KB */
 187         short *lv2entcnt; /* free lv2 entry counter for each section */
 188         spinlock_t lock; /* lock for this structure */
 189         spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
 190 };
 191
 192 static bool rockchip_set_iommu_active(struct iommu_drvdata *data)
 193 {
 194         /* return true if the IOMMU was not active previously
 195            and it needs to be initialized */
 196         return ++data->activations == 1;
 197 }
 198
 199 static bool rockchip_set_iommu_inactive(struct iommu_drvdata *data)
 200 {
 201         /* return true if the IOMMU is needed to be disabled */
 202         BUG_ON(data->activations < 1);
 203         return --data->activations == 0;
 204 }
 205
 206 static bool rockchip_is_iommu_active(struct iommu_drvdata *data)
 207 {
 208         return data->activations > 0;
 209 }
 210
 211 static void rockchip_iommu_disable_stall(void __iomem *base)
 212 {
 213         int i;
 214         u32 mmu_status;
 215
 216         if (base != rk312x_vop_mmu_base) {
 217                 mmu_status = __raw_readl(base + IOMMU_REGISTER_STATUS);
 218         } else {
 219                 goto skip_vop_mmu_disable;
 220         }
 221
 222         if (0 == (mmu_status & IOMMU_STATUS_BIT_PAGING_ENABLED)) {
 223                 return;
 224         }
 225
 226         if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE) {
 227                 pr_info("Aborting MMU disable stall request since it is in pagefault state.\n");
 228                 return;
 229         }
 230
 231         if (!(mmu_status & IOMMU_STATUS_BIT_STALL_ACTIVE)) {
 232                 pr_info("MMU stall already disabled\n");
 233                 return;
 234         }
 235
 236         skip_vop_mmu_disable:
 237         __raw_writel(IOMMU_COMMAND_DISABLE_STALL, base + IOMMU_REGISTER_COMMAND);
 238
 239         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 240                 u32 status;
 241
 242                 if (base != rk312x_vop_mmu_base) {
 243                         status = __raw_readl(base + IOMMU_REGISTER_STATUS);
 244                 } else {
 245                         int j;
 246                         while (j < 5)
 247                                 j++;
 248                         return;
 249                 }
 250
 251                 if (0 == (status & IOMMU_STATUS_BIT_STALL_ACTIVE))
 252                         break;
 253
 254                 if (status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE)
 255                         break;
 256
 257                 if (0 == (mmu_status & IOMMU_STATUS_BIT_PAGING_ENABLED))
 258                         break;
 259         }
 260
 261         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 262                 pr_info("Disable stall request failed, MMU status is 0x%08X\n",
 263                       __raw_readl(base + IOMMU_REGISTER_STATUS));
 264         }
 265 }
 266
 267 static bool rockchip_iommu_enable_stall(void __iomem *base)
 268 {
 269         int i;
 270
 271         u32 mmu_status;
 272
 273         if (base != rk312x_vop_mmu_base) {
 274                 mmu_status = __raw_readl(base + IOMMU_REGISTER_STATUS);
 275         } else {
 276                 goto skip_vop_mmu_enable;
 277         }
 278
 279         if (0 == (mmu_status & IOMMU_STATUS_BIT_PAGING_ENABLED)) {
 280                 return true;
 281         }
 282
 283         if (mmu_status & IOMMU_STATUS_BIT_STALL_ACTIVE){
 284                 pr_info("MMU stall already enabled\n");
 285                 return true;
 286         }
 287
 288         if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE) {
 289                 pr_info("Aborting MMU stall request since it is in pagefault state. mmu status is 0x%08x\n",
 290                         mmu_status);
 291                 return false;
 292         }
 293
 294         skip_vop_mmu_enable:
 295         __raw_writel(IOMMU_COMMAND_ENABLE_STALL, base + IOMMU_REGISTER_COMMAND);
 296
 297         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 298                 if (base != rk312x_vop_mmu_base) {
 299                         mmu_status = __raw_readl(base + IOMMU_REGISTER_STATUS);
 300                 } else {
 301                         int j;
 302                         while (j < 5)
 303                                 j++;
 304                         return true;
 305                 }
 306
 307                 if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE)
 308                         break;
 309
 310                 if ((mmu_status & IOMMU_STATUS_BIT_STALL_ACTIVE) &&
 311                     (0 == (mmu_status & IOMMU_STATUS_BIT_STALL_NOT_ACTIVE)))
 312                         break;
 313
 314                 if (0 == (mmu_status & (IOMMU_STATUS_BIT_PAGING_ENABLED)))
 315                         break;
 316         }
 317
 318         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 319                 pr_info("Enable stall request failed, MMU status is 0x%08X\n",
 320                        __raw_readl(base + IOMMU_REGISTER_STATUS));
 321                 return false;
 322         }
 323
 324         if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE) {
 325                 pr_info("Aborting MMU stall request since it has a pagefault.\n");
 326                 return false;
 327         }
 328
 329         return true;
 330 }
 331
 332 static bool rockchip_iommu_enable_paging(void __iomem *base)
 333 {
 334         int i;
 335
 336         __raw_writel(IOMMU_COMMAND_ENABLE_PAGING,
 337                      base + IOMMU_REGISTER_COMMAND);
 338
 339         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 340                 if (base != rk312x_vop_mmu_base) {
 341                         if (__raw_readl(base + IOMMU_REGISTER_STATUS) &
 342                                 IOMMU_STATUS_BIT_PAGING_ENABLED)
 343                         break;
 344                 } else {
 345                         int j;
 346                         while (j < 5)
 347                                 j++;
 348                         return true;
 349                 }
 350         }
 351         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 352                 pr_info("Enable paging request failed, MMU status is 0x%08X\n",
 353                        __raw_readl(base + IOMMU_REGISTER_STATUS));
 354                 return false;
 355         }
 356         return true;
 357 }
 358
 359 static bool rockchip_iommu_disable_paging(void __iomem *base)
 360 {
 361         int i;
 362
 363         __raw_writel(IOMMU_COMMAND_DISABLE_PAGING,
 364                      base + IOMMU_REGISTER_COMMAND);
 365
 366         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 367                 if (base != rk312x_vop_mmu_base) {
 368                         if (!(__raw_readl(base + IOMMU_REGISTER_STATUS) &
 369                                   IOMMU_STATUS_BIT_PAGING_ENABLED))
 370                                 break;
 371                 } else {
 372                         int j;
 373                         while (j < 5)
 374                                 j++;
 375                         return true;
 376                 }
 377         }
 378         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 379                 pr_info("Disable paging request failed, MMU status is 0x%08X\n",
 380                        __raw_readl(base + IOMMU_REGISTER_STATUS));
 381                 return false;
 382         }
 383         return true;
 384 }
 385
 386 static void rockchip_iommu_page_fault_done(void __iomem *base, const char *dbgname)
 387 {
 388         pr_info("MMU: %s: Leaving page fault mode\n",
 389                 dbgname);
 390         __raw_writel(IOMMU_COMMAND_PAGE_FAULT_DONE,
 391                      base + IOMMU_REGISTER_COMMAND);
 392 }
 393
 394 static int rockchip_iommu_zap_tlb(void __iomem *base)
 395 {
 396         if (!rockchip_iommu_enable_stall(base)) {
 397                 pr_err("%s failed\n", __func__);
 398                 return -1;
 399         }
 400
 401         __raw_writel(IOMMU_COMMAND_ZAP_CACHE, base + IOMMU_REGISTER_COMMAND);
 402
 403         rockchip_iommu_disable_stall(base);
 404
 405         return 0;
 406 }
 407
 408 static inline bool rockchip_iommu_raw_reset(void __iomem *base)
 409 {
 410         int i;
 411         unsigned int ret;
 412
 413         __raw_writel(0xCAFEBABE, base + IOMMU_REGISTER_DTE_ADDR);
 414
 415         if (base != rk312x_vop_mmu_base) {
 416                 ret = __raw_readl(base + IOMMU_REGISTER_DTE_ADDR);
 417                 if (!(0xCAFEB000 == ret)) {
 418                         pr_info("error when %s.\n", __func__);
 419                         return false;
 420                 }
 421         }
 422         __raw_writel(IOMMU_COMMAND_HARD_RESET,
 423                      base + IOMMU_REGISTER_COMMAND);
 424
 425         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 426                 if (base != rk312x_vop_mmu_base) {
 427                         if (__raw_readl(base + IOMMU_REGISTER_DTE_ADDR) == 0)
 428                                 break;
 429                 } else {
 430                         int j;
 431                         while (j < 5)
 432                                 j++;
 433                         return true;
 434                 }
 435         }
 436
 437         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 438                 pr_info("%s,Reset request failed, MMU status is 0x%08X\n",
 439                        __func__, __raw_readl(base + IOMMU_REGISTER_DTE_ADDR));
 440                 return false;
 441         }
 442         return true;
 443 }
 444
 445 static void rockchip_iommu_set_ptbase(void __iomem *base, unsigned long pgd)
 446 {
 447         __raw_writel(pgd, base + IOMMU_REGISTER_DTE_ADDR);
 448 }
 449
 450 static bool rockchip_iommu_reset(void __iomem *base, const char *dbgname)
 451 {
 452         bool ret = true;
 453
 454         ret = rockchip_iommu_enable_stall(base);
 455         if (!ret) {
 456                 pr_info("%s:stall failed: %s\n", __func__, dbgname);
 457                 return ret;
 458         }
 459
 460         ret = rockchip_iommu_raw_reset(base);
 461         if (!ret) {
 462                 pr_info("(%s), %s failed\n", dbgname, __func__);
 463                 return ret;
 464         }
 465
 466         if (base != rk312x_vop_mmu_base)
 467                 __raw_writel(IOMMU_INTERRUPT_PAGE_FAULT |
 468                              IOMMU_INTERRUPT_READ_BUS_ERROR,
 469                              base + IOMMU_REGISTER_INT_MASK);
 470         else
 471                 __raw_writel(0x00, base + IOMMU_REGISTER_INT_MASK);
 472
 473         rockchip_iommu_disable_stall(base);
 474
 475         return ret;
 476 }
 477
 478 static inline void rockchip_pgtable_flush(void *vastart, void *vaend)
 479 {
 480         dmac_flush_range(vastart, vaend);
 481         outer_flush_range(virt_to_phys(vastart), virt_to_phys(vaend));
 482 }
 483
 484 static void dump_pagetbl(dma_addr_t fault_address, u32 addr_dte)
 485 {
 486         u32 dte_index, pte_index, page_offset;
 487         u32 mmu_dte_addr;
 488         phys_addr_t mmu_dte_addr_phys, dte_addr_phys;
 489         u32 *dte_addr;
 490         u32 dte;
 491         phys_addr_t pte_addr_phys = 0;
 492         u32 *pte_addr = NULL;
 493         u32 pte = 0;
 494         phys_addr_t page_addr_phys = 0;
 495         u32 page_flags = 0;
 496
 497         dte_index = rockchip_lv1ent_offset(fault_address);
 498         pte_index = rockchip_lv2ent_offset(fault_address);
 499         page_offset = (u32)(fault_address & 0x00000fff);
 500
 501         mmu_dte_addr = addr_dte;
 502         mmu_dte_addr_phys = (phys_addr_t)mmu_dte_addr;
 503
 504         dte_addr_phys = mmu_dte_addr_phys + (4 * dte_index);
 505         dte_addr = phys_to_virt(dte_addr_phys);
 506         dte = *dte_addr;
 507
 508         if (!(IOMMU_FLAGS_PRESENT & dte))
 509                 goto print_it;
 510
 511         pte_addr_phys = ((phys_addr_t)dte & 0xfffff000) + (pte_index * 4);
 512         pte_addr = phys_to_virt(pte_addr_phys);
 513         pte = *pte_addr;
 514
 515         if (!(IOMMU_FLAGS_PRESENT & pte))
 516                 goto print_it;
 517
 518         page_addr_phys = ((phys_addr_t)pte & 0xfffff000) + page_offset;
 519         page_flags = pte & 0x000001fe;
 520
 521 print_it:
 522         pr_err("iova = %pad: dte_index: 0x%03x pte_index: 0x%03x page_offset: 0x%03x\n",
 523                 &fault_address, dte_index, pte_index, page_offset);
 524         pr_err("mmu_dte_addr: %pa dte@%pa: %#08x valid: %u pte@%pa: %#08x valid: %u page@%pa flags: %#03x\n",
 525                 &mmu_dte_addr_phys, &dte_addr_phys, dte,
 526                 (dte & IOMMU_FLAGS_PRESENT), &pte_addr_phys, pte,
 527                 (pte & IOMMU_FLAGS_PRESENT), &page_addr_phys, page_flags);
 528 }
 529
 530 static irqreturn_t rockchip_iommu_irq(int irq, void *dev_id)
 531 {
 532         /* SYSMMU is in blocked when interrupt occurred. */
 533         struct iommu_drvdata *data = dev_id;
 534         u32 status;
 535         u32 rawstat;
 536         dma_addr_t fault_address;
 537         int i;
 538         unsigned long flags;
 539         int ret;
 540         u32 reg_status;
 541
 542         spin_lock_irqsave(&data->data_lock, flags);
 543
 544         if (!rockchip_is_iommu_active(data)) {
 545                 spin_unlock_irqrestore(&data->data_lock, flags);
 546                 return IRQ_HANDLED;
 547         }
 548
 549         for (i = 0; i < data->num_res_mem; i++) {
 550                 status = __raw_readl(data->res_bases[i] +
 551                                      IOMMU_REGISTER_INT_STATUS);
 552                 if (status == 0)
 553                         continue;
 554
 555                 rawstat = __raw_readl(data->res_bases[i] +
 556                                       IOMMU_REGISTER_INT_RAWSTAT);
 557
 558                 reg_status = __raw_readl(data->res_bases[i] +
 559                                          IOMMU_REGISTER_STATUS);
 560
 561                 dev_info(data->iommu, "1.rawstat = 0x%08x,status = 0x%08x,reg_status = 0x%08x\n",
 562                          rawstat, status, reg_status);
 563
 564                 if (rawstat & IOMMU_INTERRUPT_PAGE_FAULT) {
 565                         u32 dte;
 566                         int flags;
 567
 568                         fault_address = __raw_readl(data->res_bases[i] +
 569                                             IOMMU_REGISTER_PAGE_FAULT_ADDR);
 570
 571                         dte = __raw_readl(data->res_bases[i] +
 572                                           IOMMU_REGISTER_DTE_ADDR);
 573
 574                         flags = (status & 32) ? 1 : 0;
 575
 576                         dev_err(data->iommu, "Page fault detected at %pad from bus id %d of type %s on %s\n",
 577                                 &fault_address, (status >> 6) & 0x1F,
 578                                 (flags == 1) ? "write" : "read", data->dbgname);
 579
 580                         dump_pagetbl(fault_address, dte);
 581
 582                         if (data->domain)
 583                                 report_iommu_fault(data->domain, data->iommu,
 584                                                    fault_address, flags);
 585
 586                         rockchip_iommu_page_fault_done(data->res_bases[i],
 587                                                        data->dbgname);
 588                 }
 589
 590                 if (rawstat & IOMMU_INTERRUPT_READ_BUS_ERROR) {
 591                         dev_err(data->iommu, "bus error occured at %pad\n",
 592                                 &fault_address);
 593                 }
 594
 595                 if (rawstat & ~(IOMMU_INTERRUPT_READ_BUS_ERROR |
 596                     IOMMU_INTERRUPT_PAGE_FAULT)) {
 597                         dev_err(data->iommu, "unexpected int_status: %#08x\n\n",
 598                                 rawstat);
 599                 }
 600
 601                 __raw_writel(rawstat, data->res_bases[i] +
 602                              IOMMU_REGISTER_INT_CLEAR);
 603
 604                 status = __raw_readl(data->res_bases[i] +
 605                                      IOMMU_REGISTER_INT_STATUS);
 606
 607                 rawstat = __raw_readl(data->res_bases[i] +
 608                                       IOMMU_REGISTER_INT_RAWSTAT);
 609
 610                 reg_status = __raw_readl(data->res_bases[i] +
 611                                          IOMMU_REGISTER_STATUS);
 612
 613                 dev_info(data->iommu, "2.rawstat = 0x%08x,status = 0x%08x,reg_status = 0x%08x\n",
 614                          rawstat, status, reg_status);
 615
 616                 ret = rockchip_iommu_zap_tlb(data->res_bases[i]);
 617                 if (ret)
 618                         dev_err(data->iommu, "(%s) %s failed\n", data->dbgname,
 619                                 __func__);
 620         }
 621
 622         spin_unlock_irqrestore(&data->data_lock, flags);
 623         return IRQ_HANDLED;
 624 }
 625
 626 static bool rockchip_iommu_disable(struct iommu_drvdata *data)
 627 {
 628         unsigned long flags;
 629         int i;
 630         bool ret = false;
 631
 632         spin_lock_irqsave(&data->data_lock, flags);
 633
 634         if (!rockchip_set_iommu_inactive(data)) {
 635                 spin_unlock_irqrestore(&data->data_lock, flags);
 636                 dev_info(data->iommu,"(%s) %d times left to be disabled\n",
 637                          data->dbgname, data->activations);
 638                 return ret;
 639         }
 640
 641         for (i = 0; i < data->num_res_mem; i++) {
 642                 __raw_writel(0, data->res_bases[i] + IOMMU_REGISTER_INT_MASK);
 643                 ret = rockchip_iommu_disable_paging(data->res_bases[i]);
 644                 if (!ret) {
 645                         spin_unlock_irqrestore(&data->data_lock, flags);
 646                         dev_info(data->iommu, "%s error\n", __func__);
 647                         return ret;
 648                 }
 649         }
 650
 651         data->pgtable = 0;
 652
 653         spin_unlock_irqrestore(&data->data_lock, flags);
 654
 655         dev_info(data->iommu,"(%s) Disabled\n", data->dbgname);
 656
 657         return ret;
 658 }
 659
 660 /* __rk_sysmmu_enable: Enables System MMU
 661  *
 662  * returns -error if an error occurred and System MMU is not enabled,
 663  * 0 if the System MMU has been just enabled and 1 if System MMU was already
 664  * enabled before.
 665  */
 666 static int rockchip_iommu_enable(struct iommu_drvdata *data,
 667                                     unsigned long pgtable,
 668                                     struct iommu_domain *domain)
 669 {
 670         int i, ret = 0;
 671         unsigned long flags;
 672
 673         spin_lock_irqsave(&data->data_lock, flags);
 674
 675         if (!rockchip_set_iommu_active(data)) {
 676                 if (WARN_ON(pgtable != data->pgtable)) {
 677                         ret = -EBUSY;
 678                         rockchip_set_iommu_inactive(data);
 679                 } else {
 680                         ret = 1;
 681                 }
 682
 683                 spin_unlock_irqrestore(&data->data_lock, flags);
 684                 dev_info(data->iommu, "(%s) Already enabled\n", data->dbgname);
 685
 686                 return ret;
 687         }
 688
 689         data->pgtable = pgtable;
 690
 691         for (i = 0; i < data->num_res_mem; i++) {
 692                 ret = rockchip_iommu_enable_stall(data->res_bases[i]);
 693                 if (!ret) {
 694                         dev_info(data->iommu, "(%s), %s failed\n",
 695                                  data->dbgname, __func__);
 696                         spin_unlock_irqrestore(&data->data_lock, flags);
 697                         return -EBUSY;
 698                 }
 699
 700                 rockchip_iommu_set_ptbase(data->res_bases[i], pgtable);
 701                 __raw_writel(IOMMU_COMMAND_ZAP_CACHE, data->res_bases[i] +
 702                              IOMMU_REGISTER_COMMAND);
 703                 __raw_writel(IOMMU_INTERRUPT_PAGE_FAULT |
 704                              IOMMU_INTERRUPT_READ_BUS_ERROR,
 705                              data->res_bases[i] + IOMMU_REGISTER_INT_MASK);
 706                 ret = rockchip_iommu_enable_paging(data->res_bases[i]);
 707                 if (!ret) {
 708                         spin_unlock_irqrestore(&data->data_lock, flags);
 709                         dev_info(data->iommu, "(%s), %s failed\n",
 710                                  data->dbgname, __func__);
 711                         return -EBUSY;
 712                 }
 713                 rockchip_iommu_disable_stall(data->res_bases[i]);
 714         }
 715
 716         dev_info(data->iommu,"(%s) Enabled\n", data->dbgname);
 717
 718         spin_unlock_irqrestore(&data->data_lock, flags);
 719
 720         return 0;
 721 }
 722
 723 int rockchip_iommu_tlb_invalidate(struct device *dev)
 724 {
 725         unsigned long flags;
 726         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 727
 728         spin_lock_irqsave(&data->data_lock, flags);
 729
 730         if (rockchip_is_iommu_active(data)) {
 731                 int i;
 732                 int ret;
 733
 734                 for (i = 0; i < data->num_res_mem; i++) {
 735                         ret = rockchip_iommu_zap_tlb(data->res_bases[i]);
 736                         if (ret) {
 737                                 dev_err(dev->archdata.iommu, "(%s) %s failed\n",
 738                                         data->dbgname, __func__);
 739                                 spin_unlock_irqrestore(&data->data_lock, flags);
 740                                 return ret;
 741                         }
 742
 743                 }
 744         } else {
 745                 dev_dbg(dev->archdata.iommu, "(%s) Disabled. Skipping invalidating TLB.\n",
 746                         data->dbgname);
 747         }
 748
 749         spin_unlock_irqrestore(&data->data_lock, flags);
 750
 751         return 0;
 752 }
 753
 754 static phys_addr_t rockchip_iommu_iova_to_phys(struct iommu_domain *domain,
 755                                                dma_addr_t iova)
 756 {
 757         struct rk_iommu_domain *priv = domain->priv;
 758         unsigned long *entry;
 759         unsigned long flags;
 760         phys_addr_t phys = 0;
 761
 762         spin_lock_irqsave(&priv->pgtablelock, flags);
 763
 764         entry = rockchip_section_entry(priv->pgtable, iova);
 765         entry = rockchip_page_entry(entry, iova);
 766         phys = rockchip_spage_phys(entry) + rockchip_spage_offs(iova);
 767
 768         spin_unlock_irqrestore(&priv->pgtablelock, flags);
 769
 770         return phys;
 771 }
 772
 773 static int rockchip_lv2set_page(unsigned long *pent, phys_addr_t paddr,
 774                        size_t size, short *pgcnt)
 775 {
 776         if (!rockchip_lv2ent_fault(pent))
 777                 return -EADDRINUSE;
 778
 779         *pent = rockchip_mk_lv2ent_spage(paddr);
 780         rockchip_pgtable_flush(pent, pent + 1);
 781         *pgcnt -= 1;
 782         return 0;
 783 }
 784
 785 static unsigned long *rockchip_alloc_lv2entry(unsigned long *sent,
 786                                      unsigned long iova, short *pgcounter)
 787 {
 788         if (rockchip_lv1ent_fault(sent)) {
 789                 unsigned long *pent;
 790
 791                 pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
 792                 BUG_ON((unsigned long)pent & (LV2TABLE_SIZE - 1));
 793                 if (!pent)
 794                         return NULL;
 795
 796                 *sent = rockchip_mk_lv1ent_page(__pa(pent));
 797                 kmemleak_ignore(pent);
 798                 *pgcounter = NUM_LV2ENTRIES;
 799                 rockchip_pgtable_flush(pent, pent + NUM_LV2ENTRIES);
 800                 rockchip_pgtable_flush(sent, sent + 1);
 801         }
 802         return rockchip_page_entry(sent, iova);
 803 }
 804
 805 static size_t rockchip_iommu_unmap(struct iommu_domain *domain,
 806                                    unsigned long iova, size_t size)
 807 {
 808         struct rk_iommu_domain *priv = domain->priv;
 809         unsigned long flags;
 810         unsigned long *ent;
 811
 812         BUG_ON(priv->pgtable == NULL);
 813
 814         spin_lock_irqsave(&priv->pgtablelock, flags);
 815
 816         ent = rockchip_section_entry(priv->pgtable, iova);
 817
 818         if (unlikely(rockchip_lv1ent_fault(ent))) {
 819                 if (size > SPAGE_SIZE)
 820                         size = SPAGE_SIZE;
 821                 goto done;
 822         }
 823
 824         /* lv1ent_page(sent) == true here */
 825
 826         ent = rockchip_page_entry(ent, iova);
 827
 828         if (unlikely(rockchip_lv2ent_fault(ent))) {
 829                 size = SPAGE_SIZE;
 830                 goto done;
 831         }
 832
 833         *ent = 0;
 834         size = SPAGE_SIZE;
 835         priv->lv2entcnt[rockchip_lv1ent_offset(iova)] += 1;
 836         goto done;
 837
 838 done:
 839         #if 0
 840         pr_info("%s:unmap iova 0x%lx/0x%x bytes\n",
 841                   __func__, iova,size);
 842         #endif
 843         spin_unlock_irqrestore(&priv->pgtablelock, flags);
 844
 845         return size;
 846 }
 847
 848 static int rockchip_iommu_map(struct iommu_domain *domain, unsigned long iova,
 849                               phys_addr_t paddr, size_t size, int prot)
 850 {
 851         struct rk_iommu_domain *priv = domain->priv;
 852         unsigned long *entry;
 853         unsigned long flags;
 854         int ret = -ENOMEM;
 855         unsigned long *pent;
 856
 857         BUG_ON(priv->pgtable == NULL);
 858
 859         spin_lock_irqsave(&priv->pgtablelock, flags);
 860
 861         entry = rockchip_section_entry(priv->pgtable, iova);
 862
 863         pent = rockchip_alloc_lv2entry(entry, iova,
 864                               &priv->lv2entcnt[rockchip_lv1ent_offset(iova)]);
 865         if (!pent)
 866                 ret = -ENOMEM;
 867         else
 868                 ret = rockchip_lv2set_page(pent, paddr, size,
 869                                 &priv->lv2entcnt[rockchip_lv1ent_offset(iova)]);
 870
 871         if (ret) {
 872                 pr_info("%s: Failed to map iova 0x%lx/0x%x bytes\n", __func__,
 873                        iova, size);
 874         }
 875         spin_unlock_irqrestore(&priv->pgtablelock, flags);
 876
 877         return ret;
 878 }
 879
 880 static void rockchip_iommu_detach_device(struct iommu_domain *domain,
 881                                          struct device *dev)
 882 {
 883         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 884         struct rk_iommu_domain *priv = domain->priv;
 885         struct list_head *pos;
 886         unsigned long flags;
 887         bool found = false;
 888
 889         spin_lock_irqsave(&priv->lock, flags);
 890
 891         list_for_each(pos, &priv->clients) {
 892                 if (list_entry(pos, struct iommu_drvdata, node) == data) {
 893                         found = true;
 894                         break;
 895                 }
 896         }
 897
 898         if (!found) {
 899                 spin_unlock_irqrestore(&priv->lock, flags);
 900                 return;
 901         }
 902
 903         if (rockchip_iommu_disable(data)) {
 904                 dev_dbg(dev->archdata.iommu,"%s: Detached IOMMU with pgtable %#lx\n",
 905                         __func__, __pa(priv->pgtable));
 906                 data->domain = NULL;
 907                 list_del_init(&data->node);
 908
 909         } else
 910                 dev_err(dev->archdata.iommu,"%s: Detaching IOMMU with pgtable %#lx delayed",
 911                         __func__, __pa(priv->pgtable));
 912
 913         spin_unlock_irqrestore(&priv->lock, flags);
 914 }
 915
 916 static int rockchip_iommu_attach_device(struct iommu_domain *domain,
 917                                         struct device *dev)
 918 {
 919         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 920         struct rk_iommu_domain *priv = domain->priv;
 921         unsigned long flags;
 922         int ret;
 923
 924         spin_lock_irqsave(&priv->lock, flags);
 925
 926         ret = rockchip_iommu_enable(data, __pa(priv->pgtable), domain);
 927
 928         if (ret == 0) {
 929                 /* 'data->node' must not be appeared in priv->clients */
 930                 BUG_ON(!list_empty(&data->node));
 931                 list_add_tail(&data->node, &priv->clients);
 932                 data->domain = domain;
 933         }
 934
 935         spin_unlock_irqrestore(&priv->lock, flags);
 936
 937         if (ret < 0) {
 938                 dev_err(dev->archdata.iommu,"%s: Failed to attach IOMMU with pgtable %#lx\n",
 939                        __func__, __pa(priv->pgtable));
 940         } else if (ret > 0) {
 941                 dev_dbg(dev->archdata.iommu,"%s: IOMMU with pgtable 0x%lx already attached\n",
 942                         __func__, __pa(priv->pgtable));
 943         } else {
 944                 dev_dbg(dev->archdata.iommu,"%s: Attached new IOMMU with pgtable 0x%lx\n",
 945                         __func__, __pa(priv->pgtable));
 946         }
 947
 948         return ret;
 949 }
 950
 951 static void rockchip_iommu_domain_destroy(struct iommu_domain *domain)
 952 {
 953         struct rk_iommu_domain *priv = domain->priv;
 954         int i;
 955
 956         WARN_ON(!list_empty(&priv->clients));
 957
 958         for (i = 0; i < NUM_LV1ENTRIES; i++)
 959                 if (rockchip_lv1ent_page(priv->pgtable + i))
 960                         kmem_cache_free(lv2table_kmem_cache,
 961                                         __va(rockchip_lv2table_base(priv->pgtable + i)));
 962
 963         free_pages((unsigned long)priv->pgtable, 0);
 964         free_pages((unsigned long)priv->lv2entcnt, 0);
 965         kfree(domain->priv);
 966         domain->priv = NULL;
 967 }
 968
 969 static int rockchip_iommu_domain_init(struct iommu_domain *domain)
 970 {
 971         struct rk_iommu_domain *priv;
 972
 973         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 974         if (!priv)
 975                 return -ENOMEM;
 976
 977 /*rk32xx iommu use 2 level pagetable,
 978    level1 and leve2 both have 1024 entries,each entry  occupy 4 bytes,
 979    so alloc a page size for each page table
 980 */
 981         priv->pgtable = (unsigned long *)__get_free_pages(GFP_KERNEL |
 982                                                           __GFP_ZERO, 0);
 983         if (!priv->pgtable)
 984                 goto err_pgtable;
 985
 986         priv->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL |
 987                                                     __GFP_ZERO, 0);
 988         if (!priv->lv2entcnt)
 989                 goto err_counter;
 990
 991         rockchip_pgtable_flush(priv->pgtable, priv->pgtable + NUM_LV1ENTRIES);
 992
 993         spin_lock_init(&priv->lock);
 994         spin_lock_init(&priv->pgtablelock);
 995         INIT_LIST_HEAD(&priv->clients);
 996
 997         domain->priv = priv;
 998         return 0;
 999
1000 err_counter:
1001         free_pages((unsigned long)priv->pgtable, 0);
1002 err_pgtable:
1003         kfree(priv);
1004         return -ENOMEM;
1005 }
1006
1007 static struct iommu_ops rk_iommu_ops = {
1008         .domain_init = &rockchip_iommu_domain_init,
1009         .domain_destroy = &rockchip_iommu_domain_destroy,
1010         .attach_dev = &rockchip_iommu_attach_device,
1011         .detach_dev = &rockchip_iommu_detach_device,
1012         .map = &rockchip_iommu_map,
1013         .unmap = &rockchip_iommu_unmap,
1014         .iova_to_phys = &rockchip_iommu_iova_to_phys,
1015         .pgsize_bitmap = SPAGE_SIZE,
1016 };
1017
1018 static int  rockchip_get_iommu_resource_num(struct platform_device *pdev,
1019                                              unsigned int type)
1020 {
1021         int num = 0;
1022         int i;
1023 #if 0
1024         pr_info("dev num_resources %d type = 0x%08x\n",pdev->num_resources, type);
1025 #endif
1026         for (i = 0; i < pdev->num_resources; i++) {
1027                 struct resource *r = &pdev->resource[i];
1028 #if 0
1029 dev_info(&pdev->dev, "r[%d] start %08x end %08x flags %08lx name (%s) resource_type %08lx\n", i, r->start, r->end, r->flags, r->name, resource_type(r));
1030 #endif
1031                 if (type == resource_type(r))
1032                         num++;
1033         }
1034
1035         return num;
1036 }
1037
1038 static int rockchip_iommu_probe(struct platform_device *pdev)
1039 {
1040         int i, ret;
1041         struct device *dev;
1042         struct iommu_drvdata *data;
1043
1044         dev = &pdev->dev;
1045
1046 #if 0
1047 struct resource *res = pdev->resource;
1048
1049 for (i = 0; i < pdev->num_resources; i++, res++) {
1050         pr_info("r[%d] start %08x end %08x flags %08lx name (%s) resource_type %08lx\n", i, res->start, res->end, res->flags, res->name,   resource_type(res));
1051 }
1052 #endif
1053
1054         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
1055         if (!data) {
1056                 dev_dbg(dev, "Not enough memory\n");
1057                 return -ENOMEM;
1058         }
1059
1060         dev_set_drvdata(dev, data);
1061
1062         if (pdev->dev.of_node)
1063                 of_property_read_string(pdev->dev.of_node, "dbgname",
1064                                         &(data->dbgname));
1065         else
1066                 dev_dbg(dev, "dbgname not assigned in device tree or device node not exist\r\n");
1067
1068         dev_info(dev,"(%s) Enter\n", data->dbgname);
1069
1070         data->num_res_mem = rockchip_get_iommu_resource_num(pdev,
1071                                 IORESOURCE_MEM);
1072         if (0 == data->num_res_mem) {
1073                 dev_err(dev,"can't find iommu memory resource \r\n");
1074                 return -ENOMEM;
1075         }
1076         dev_dbg(dev,"data->num_res_mem=%d\n", data->num_res_mem);
1077
1078         data->num_res_irq = rockchip_get_iommu_resource_num(pdev,
1079                                 IORESOURCE_IRQ);
1080         if (0 == data->num_res_irq) {
1081                 dev_err(dev,"can't find iommu irq resource \r\n");
1082                 return -ENOMEM;
1083         }
1084         dev_dbg(dev,"data->num_res_irq=%d\n", data->num_res_irq);
1085
1086         data->res_bases = devm_kmalloc_array(dev, data->num_res_mem,
1087                                 sizeof(*data->res_bases), GFP_KERNEL);
1088         if (data->res_bases == NULL) {
1089                 dev_err(dev, "Not enough memory\n");
1090                 return -ENOMEM;
1091         }
1092
1093         for (i = 0; i < data->num_res_mem; i++) {
1094                 struct resource *res;
1095
1096                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1097                 if (!res) {
1098                         dev_err(dev,"Unable to find IOMEM region\n");
1099                         return -ENOENT;
1100                 }
1101
1102                 data->res_bases[i] = devm_ioremap(dev,res->start,
1103                                                   resource_size(res));
1104                 if (!data->res_bases[i]) {
1105                         dev_err(dev, "Unable to map IOMEM @ PA:%#x\n",
1106                                 res->start);
1107                         return -ENOMEM;
1108                 }
1109
1110                 dev_dbg(dev,"res->start = 0x%08x ioremap to data->res_bases[%d] = 0x%08x\n",
1111                         res->start, i, (unsigned int)data->res_bases[i]);
1112
1113                 if (strstr(data->dbgname, "vop") && cpu_is_rk312x()) {
1114                         rk312x_vop_mmu_base = data->res_bases[0];
1115                         dev_dbg(dev, "rk312x_vop_mmu_base = 0x%08x\n",
1116                                 (unsigned int)rk312x_vop_mmu_base);
1117                 }
1118
1119                 if (!strstr(data->dbgname, "isp"))
1120                         if (!rockchip_iommu_reset(data->res_bases[i],
1121                             data->dbgname))
1122                                 return -ENOENT;
1123         }
1124
1125         for (i = 0; i < data->num_res_irq; i++) {
1126                 if (cpu_is_rk312x() && strstr(data->dbgname, "vop")) {
1127                         dev_info(dev, "skip request vop mmu irq\n");
1128                         continue;
1129                 }
1130
1131                 ret = platform_get_irq(pdev, i);
1132                 if (ret <= 0) {
1133                         dev_err(dev,"Unable to find IRQ resource\n");
1134                         return -ENOENT;
1135                 }
1136
1137                 ret = devm_request_irq(dev, ret, rockchip_iommu_irq,
1138                                   IRQF_SHARED, dev_name(dev), data);
1139                 if (ret) {
1140                         dev_err(dev, "Unabled to register interrupt handler\n");
1141                         return -ENOENT;
1142                 }
1143         }
1144
1145         ret = rockchip_init_iovmm(dev, &data->vmm);
1146         if (ret)
1147                 return ret;
1148
1149         data->iommu = dev;
1150         spin_lock_init(&data->data_lock);
1151         INIT_LIST_HEAD(&data->node);
1152
1153         dev_info(dev,"(%s) Initialized\n", data->dbgname);
1154
1155         return 0;
1156 }
1157
1158 #ifdef CONFIG_OF
1159 static const struct of_device_id iommu_dt_ids[] = {
1160         { .compatible = IEP_IOMMU_COMPATIBLE_NAME},
1161         { .compatible = VIP_IOMMU_COMPATIBLE_NAME},
1162         { .compatible = VOPB_IOMMU_COMPATIBLE_NAME},
1163         { .compatible = VOPL_IOMMU_COMPATIBLE_NAME},
1164         { .compatible = HEVC_IOMMU_COMPATIBLE_NAME},
1165         { .compatible = VPU_IOMMU_COMPATIBLE_NAME},
1166         { .compatible = ISP_IOMMU_COMPATIBLE_NAME},
1167         { .compatible = VOP_IOMMU_COMPATIBLE_NAME},
1168         { /* end */ }
1169 };
1170
1171 MODULE_DEVICE_TABLE(of, iommu_dt_ids);
1172 #endif
1173
1174 static struct platform_driver rk_iommu_driver = {
1175         .probe = rockchip_iommu_probe,
1176         .remove = NULL,
1177         .driver = {
1178                    .name = "rk_iommu",
1179                    .owner = THIS_MODULE,
1180                    .of_match_table = of_match_ptr(iommu_dt_ids),
1181         },
1182 };
1183
1184 static int __init rockchip_iommu_init_driver(void)
1185 {
1186         int ret;
1187
1188         lv2table_kmem_cache = kmem_cache_create("rk-iommu-lv2table",
1189                                                 LV2TABLE_SIZE, LV2TABLE_SIZE,
1190                                                 0, NULL);
1191         if (!lv2table_kmem_cache) {
1192                 pr_info("%s: failed to create kmem cache\n", __func__);
1193                 return -ENOMEM;
1194         }
1195
1196         ret = bus_set_iommu(&platform_bus_type, &rk_iommu_ops);
1197         if (ret)
1198                 return ret;
1199
1200         return platform_driver_register(&rk_iommu_driver);
1201 }
1202
1203 core_initcall(rockchip_iommu_init_driver);