drivers/iommu/rockchip-iommu.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License version 2 as
   4  * published by the Free Software Foundation.
   5  */
   6
   7 #ifdef CONFIG_ROCKCHIP_IOMMU_DEBUG
   8 #define DEBUG
   9 #endif
  10
  11 #include <linux/io.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/slab.h>
  14 #include <linux/clk.h>
  15 #include <linux/err.h>
  16 #include <linux/mm.h>
  17 #include <linux/errno.h>
  18 #include <linux/memblock.h>
  19 #include <linux/export.h>
  20 #include <linux/module.h>
  21
  22 #include <asm/cacheflush.h>
  23 #include <asm/pgtable.h>
  24 #include <linux/of.h>
  25 #include <linux/rockchip-iovmm.h>
  26 #include <linux/rockchip/grf.h>
  27 #include <linux/rockchip/cpu.h>
  28 #include <linux/rockchip/iomap.h>
  29
  30 #include "rockchip-iommu.h"
  31
  32 /* We does not consider super section mapping (16MB) */
  33 #define SPAGE_ORDER 12
  34 #define SPAGE_SIZE (1 << SPAGE_ORDER)
  35 #define SPAGE_MASK (~(SPAGE_SIZE - 1))
  36
  37 enum iommu_entry_flags {
  38         IOMMU_FLAGS_PRESENT = 0x01,
  39         IOMMU_FLAGS_READ_PERMISSION = 0x02,
  40         IOMMU_FLAGS_WRITE_PERMISSION = 0x04,
  41         IOMMU_FLAGS_OVERRIDE_CACHE = 0x8,
  42         IOMMU_FLAGS_WRITE_CACHEABLE = 0x10,
  43         IOMMU_FLAGS_WRITE_ALLOCATE = 0x20,
  44         IOMMU_FLAGS_WRITE_BUFFERABLE = 0x40,
  45         IOMMU_FLAGS_READ_CACHEABLE = 0x80,
  46         IOMMU_FLAGS_READ_ALLOCATE = 0x100,
  47         IOMMU_FLAGS_MASK = 0x1FF,
  48 };
  49
  50 #define lv1ent_fault(sent) ((*(sent) & IOMMU_FLAGS_PRESENT) == 0)
  51 #define lv1ent_page(sent) ((*(sent) & IOMMU_FLAGS_PRESENT) == 1)
  52 #define lv2ent_fault(pent) ((*(pent) & IOMMU_FLAGS_PRESENT) == 0)
  53 #define spage_phys(pent) (*(pent) & SPAGE_MASK)
  54 #define spage_offs(iova) ((iova) & 0x0FFF)
  55
  56 #define lv1ent_offset(iova) (((iova)>>22) & 0x03FF)
  57 #define lv2ent_offset(iova) (((iova)>>12) & 0x03FF)
  58
  59 #define NUM_LV1ENTRIES 1024
  60 #define NUM_LV2ENTRIES 1024
  61
  62 #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(long))
  63
  64 #define lv2table_base(sent) (*(sent) & 0xFFFFFFFE)
  65
  66 #define mk_lv1ent_page(pa) ((pa) | IOMMU_FLAGS_PRESENT)
  67 /*write and read permission for level2 page default*/
  68 #define mk_lv2ent_spage(pa) ((pa) | IOMMU_FLAGS_PRESENT | \
  69                              IOMMU_FLAGS_READ_PERMISSION | \
  70                              IOMMU_FLAGS_WRITE_PERMISSION)
  71
  72 #define IOMMU_REG_POLL_COUNT_FAST 1000
  73
  74 /*rk3036:vpu and hevc share ahb interface*/
  75 #define BIT_VCODEC_SEL (1<<3)
  76
  77
  78 /**
  79  * MMU register numbers
  80  * Used in the register read/write routines.
  81  * See the hardware documentation for more information about each register
  82  */
  83 enum iommu_register {
  84         /**< Current Page Directory Pointer */
  85         IOMMU_REGISTER_DTE_ADDR = 0x0000,
  86         /**< Status of the MMU */
  87         IOMMU_REGISTER_STATUS = 0x0004,
  88         /**< Command register, used to control the MMU */
  89         IOMMU_REGISTER_COMMAND = 0x0008,
  90         /**< Logical address of the last page fault */
  91         IOMMU_REGISTER_PAGE_FAULT_ADDR = 0x000C,
  92         /**< Used to invalidate the mapping of a single page from the MMU */
  93         IOMMU_REGISTER_ZAP_ONE_LINE = 0x010,
  94         /**< Raw interrupt status, all interrupts visible */
  95         IOMMU_REGISTER_INT_RAWSTAT = 0x0014,
  96         /**< Indicate to the MMU that the interrupt has been received */
  97         IOMMU_REGISTER_INT_CLEAR = 0x0018,
  98         /**< Enable/disable types of interrupts */
  99         IOMMU_REGISTER_INT_MASK = 0x001C,
 100         /**< Interrupt status based on the mask */
 101         IOMMU_REGISTER_INT_STATUS = 0x0020,
 102         IOMMU_REGISTER_AUTO_GATING = 0x0024
 103 };
 104
 105 enum iommu_command {
 106         /**< Enable paging (memory translation) */
 107         IOMMU_COMMAND_ENABLE_PAGING = 0x00,
 108         /**< Disable paging (memory translation) */
 109         IOMMU_COMMAND_DISABLE_PAGING = 0x01,
 110         /**<  Enable stall on page fault */
 111         IOMMU_COMMAND_ENABLE_STALL = 0x02,
 112         /**< Disable stall on page fault */
 113         IOMMU_COMMAND_DISABLE_STALL = 0x03,
 114         /**< Zap the entire page table cache */
 115         IOMMU_COMMAND_ZAP_CACHE = 0x04,
 116         /**< Page fault processed */
 117         IOMMU_COMMAND_PAGE_FAULT_DONE = 0x05,
 118         /**< Reset the MMU back to power-on settings */
 119         IOMMU_COMMAND_HARD_RESET = 0x06
 120 };
 121
 122 /**
 123  * MMU interrupt register bits
 124  * Each cause of the interrupt is reported
 125  * through the (raw) interrupt status registers.
 126  * Multiple interrupts can be pending, so multiple bits
 127  * can be set at once.
 128  */
 129 enum iommu_interrupt {
 130         IOMMU_INTERRUPT_PAGE_FAULT = 0x01, /**< A page fault occured */
 131         IOMMU_INTERRUPT_READ_BUS_ERROR = 0x02 /**< A bus read error occured */
 132 };
 133
 134 enum iommu_status_bits {
 135         IOMMU_STATUS_BIT_PAGING_ENABLED      = 1 << 0,
 136         IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE   = 1 << 1,
 137         IOMMU_STATUS_BIT_STALL_ACTIVE        = 1 << 2,
 138         IOMMU_STATUS_BIT_IDLE                = 1 << 3,
 139         IOMMU_STATUS_BIT_REPLAY_BUFFER_EMPTY = 1 << 4,
 140         IOMMU_STATUS_BIT_PAGE_FAULT_IS_WRITE = 1 << 5,
 141         IOMMU_STATUS_BIT_STALL_NOT_ACTIVE    = 1 << 31,
 142 };
 143
 144 /**
 145  * Size of an MMU page in bytes
 146  */
 147 #define IOMMU_PAGE_SIZE 0x1000
 148
 149 /*
 150  * Size of the address space referenced by a page table page
 151  */
 152 #define IOMMU_VIRTUAL_PAGE_SIZE 0x400000 /* 4 MiB */
 153
 154 /**
 155  * Page directory index from address
 156  * Calculates the page directory index from the given address
 157  */
 158 #define IOMMU_PDE_ENTRY(address) (((address)>>22) & 0x03FF)
 159
 160 /**
 161  * Page table index from address
 162  * Calculates the page table index from the given address
 163  */
 164 #define IOMMU_PTE_ENTRY(address) (((address)>>12) & 0x03FF)
 165
 166 /**
 167  * Extract the memory address from an PDE/PTE entry
 168  */
 169 #define IOMMU_ENTRY_ADDRESS(value) ((value) & 0xFFFFFC00)
 170
 171 #define INVALID_PAGE ((u32)(~0))
 172
 173 static struct kmem_cache *lv2table_kmem_cache;
 174
 175 static void rockchip_vcodec_select(const char *string)
 176 {
 177         if(strstr(string,"hevc"))
 178         {
 179                 writel_relaxed(readl_relaxed(RK_GRF_VIRT + RK3036_GRF_SOC_CON1) |
 180                               (BIT_VCODEC_SEL) | (BIT_VCODEC_SEL << 16),
 181                               RK_GRF_VIRT + RK3036_GRF_SOC_CON1);
 182         }
 183         else if(strstr(string,"vpu"))
 184         {
 185                 writel_relaxed((readl_relaxed(RK_GRF_VIRT + RK3036_GRF_SOC_CON1) &
 186                                (~BIT_VCODEC_SEL)) | (BIT_VCODEC_SEL << 16),
 187                                RK_GRF_VIRT + RK3036_GRF_SOC_CON1);
 188         }
 189 }
 190 static unsigned long *section_entry(unsigned long *pgtable, unsigned long iova)
 191 {
 192         return pgtable + lv1ent_offset(iova);
 193 }
 194
 195 static unsigned long *page_entry(unsigned long *sent, unsigned long iova)
 196 {
 197         return (unsigned long *)__va(lv2table_base(sent)) + lv2ent_offset(iova);
 198 }
 199
 200 static char *iommu_fault_name[IOMMU_FAULTS_NUM] = {
 201         "PAGE FAULT",
 202         "BUS ERROR",
 203         "UNKNOWN FAULT"
 204 };
 205
 206 struct rk_iommu_domain {
 207         struct list_head clients; /* list of iommu_drvdata.node */
 208         unsigned long *pgtable; /* lv1 page table, 4KB */
 209         short *lv2entcnt; /* free lv2 entry counter for each section */
 210         spinlock_t lock; /* lock for this structure */
 211         spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
 212 };
 213
 214 static bool set_iommu_active(struct iommu_drvdata *data)
 215 {
 216         /* return true if the IOMMU was not active previously
 217            and it needs to be initialized */
 218         return ++data->activations == 1;
 219 }
 220
 221 static bool set_iommu_inactive(struct iommu_drvdata *data)
 222 {
 223         /* return true if the IOMMU is needed to be disabled */
 224         BUG_ON(data->activations < 1);
 225         return --data->activations == 0;
 226 }
 227
 228 static bool is_iommu_active(struct iommu_drvdata *data)
 229 {
 230         return data->activations > 0;
 231 }
 232
 233 static void iommu_disable_stall(void __iomem *base)
 234 {
 235         int i;
 236         u32 mmu_status = __raw_readl(base + IOMMU_REGISTER_STATUS);
 237
 238         if (0 == (mmu_status & IOMMU_STATUS_BIT_PAGING_ENABLED))
 239                 return;
 240         if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE) {
 241                 pr_err("Aborting MMU disable stall request since it is in pagefault state.\n");
 242                 return;
 243         }
 244         __raw_writel(IOMMU_COMMAND_DISABLE_STALL,
 245                      base + IOMMU_REGISTER_COMMAND);
 246
 247         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 248                 u32 status = __raw_readl(base + IOMMU_REGISTER_STATUS);
 249
 250                 if (0 == (status & IOMMU_STATUS_BIT_STALL_ACTIVE))
 251                         break;
 252                 if (status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE)
 253                         break;
 254                 if (0 == (mmu_status & IOMMU_STATUS_BIT_PAGING_ENABLED))
 255                         break;
 256         }
 257         if (IOMMU_REG_POLL_COUNT_FAST == i)
 258                 pr_err("Disable stall request failed, MMU status is 0x%08X\n",
 259                        __raw_readl(base + IOMMU_REGISTER_STATUS));
 260 }
 261
 262 static bool iommu_enable_stall(void __iomem *base)
 263 {
 264         int i;
 265
 266         u32 mmu_status = __raw_readl(base + IOMMU_REGISTER_STATUS);
 267
 268         if (0 == (mmu_status & IOMMU_STATUS_BIT_PAGING_ENABLED))
 269                 return true;
 270         if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE) {
 271                 pr_err("Aborting MMU stall request since it is in pagefault state.\n");
 272                 return false;
 273         }
 274         __raw_writel(IOMMU_COMMAND_ENABLE_STALL,
 275                      base + IOMMU_REGISTER_COMMAND);
 276
 277         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 278                 mmu_status = __raw_readl(base + IOMMU_REGISTER_STATUS);
 279                 if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE)
 280                         break;
 281                 if ((mmu_status & IOMMU_STATUS_BIT_STALL_ACTIVE) &&
 282                     (0 == (mmu_status & IOMMU_STATUS_BIT_STALL_NOT_ACTIVE)))
 283                         break;
 284                 if (0 == (mmu_status & (IOMMU_STATUS_BIT_PAGING_ENABLED)))
 285                         break;
 286         }
 287         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 288                 pr_err("Enable stall request failed, MMU status is 0x%08X\n",
 289                        __raw_readl(base + IOMMU_REGISTER_STATUS));
 290                 return false;
 291         }
 292         if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE) {
 293                 pr_err("Aborting MMU stall request since it has a pagefault.\n");
 294                 return false;
 295         }
 296         return true;
 297 }
 298
 299 static bool iommu_enable_paging(void __iomem *base)
 300 {
 301         int i;
 302
 303         __raw_writel(IOMMU_COMMAND_ENABLE_PAGING,
 304                      base + IOMMU_REGISTER_COMMAND);
 305
 306         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 307                 if (__raw_readl(base + IOMMU_REGISTER_STATUS) &
 308                                 IOMMU_STATUS_BIT_PAGING_ENABLED)
 309                         break;
 310         }
 311         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 312                 pr_err("Enable paging request failed, MMU status is 0x%08X\n",
 313                        __raw_readl(base + IOMMU_REGISTER_STATUS));
 314                 return false;
 315         }
 316         return true;
 317 }
 318
 319 static bool iommu_disable_paging(void __iomem *base)
 320 {
 321         int i;
 322
 323         __raw_writel(IOMMU_COMMAND_DISABLE_PAGING,
 324                      base + IOMMU_REGISTER_COMMAND);
 325
 326         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 327                 if (!(__raw_readl(base + IOMMU_REGISTER_STATUS) &
 328                                   IOMMU_STATUS_BIT_PAGING_ENABLED))
 329                         break;
 330         }
 331         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 332                 pr_err("Disable paging request failed, MMU status is 0x%08X\n",
 333                        __raw_readl(base + IOMMU_REGISTER_STATUS));
 334                 return false;
 335         }
 336         return true;
 337 }
 338
 339 static void iommu_page_fault_done(void __iomem *base, const char *dbgname)
 340 {
 341         pr_info("MMU: %s: Leaving page fault mode\n",
 342                 dbgname);
 343         __raw_writel(IOMMU_COMMAND_PAGE_FAULT_DONE,
 344                      base + IOMMU_REGISTER_COMMAND);
 345 }
 346
 347 static bool iommu_zap_tlb(void __iomem *base)
 348 {
 349         bool stall_success = iommu_enable_stall(base);
 350
 351         __raw_writel(IOMMU_COMMAND_ZAP_CACHE,
 352                      base + IOMMU_REGISTER_COMMAND);
 353         if (!stall_success)
 354                 return false;
 355         iommu_disable_stall(base);
 356         return true;
 357 }
 358
 359 static inline bool iommu_raw_reset(void __iomem *base)
 360 {
 361         int i;
 362
 363         __raw_writel(0xCAFEBABE, base + IOMMU_REGISTER_DTE_ADDR);
 364
 365         if (!(0xCAFEB000 == __raw_readl(base + IOMMU_REGISTER_DTE_ADDR))) {
 366                 pr_err("error when %s.\n", __func__);
 367                 return false;
 368         }
 369         __raw_writel(IOMMU_COMMAND_HARD_RESET,
 370                      base + IOMMU_REGISTER_COMMAND);
 371
 372         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 373                 if (__raw_readl(base + IOMMU_REGISTER_DTE_ADDR) == 0)
 374                         break;
 375         }
 376         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 377                 pr_err("%s,Reset request failed, MMU status is 0x%08X\n",
 378                        __func__, __raw_readl(base + IOMMU_REGISTER_DTE_ADDR));
 379                 return false;
 380         }
 381         return true;
 382 }
 383
 384 static void __iommu_set_ptbase(void __iomem *base, unsigned long pgd)
 385 {
 386         __raw_writel(pgd, base + IOMMU_REGISTER_DTE_ADDR);
 387 }
 388
 389 static bool iommu_reset(void __iomem *base, const char *dbgname)
 390 {
 391         bool err = true;
 392
 393         err = iommu_enable_stall(base);
 394         if (!err) {
 395                 pr_err("%s:stall failed: %s\n", __func__, dbgname);
 396                 return err;
 397         }
 398         err = iommu_raw_reset(base);
 399         if (err)
 400                 __raw_writel(IOMMU_INTERRUPT_PAGE_FAULT |
 401                              IOMMU_INTERRUPT_READ_BUS_ERROR,
 402                              base+IOMMU_REGISTER_INT_MASK);
 403         iommu_disable_stall(base);
 404         if (!err)
 405                 pr_err("%s: failed: %s\n", __func__, dbgname);
 406         return err;
 407 }
 408
 409 static inline void pgtable_flush(void *vastart, void *vaend)
 410 {
 411         dmac_flush_range(vastart, vaend);
 412         outer_flush_range(virt_to_phys(vastart), virt_to_phys(vaend));
 413 }
 414
 415 static void set_fault_handler(struct iommu_drvdata *data,
 416                                 rockchip_iommu_fault_handler_t handler)
 417 {
 418         unsigned long flags;
 419
 420         write_lock_irqsave(&data->lock, flags);
 421         data->fault_handler = handler;
 422         write_unlock_irqrestore(&data->lock, flags);
 423 }
 424
 425 static int default_fault_handler(struct device *dev,
 426                                  enum rk_iommu_inttype itype,
 427                                  unsigned long pgtable_base,
 428                                  unsigned long fault_addr,
 429                                  unsigned int status)
 430 {
 431         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 432
 433         if (!data) {
 434                 pr_err("%s,iommu device not assigned yet\n", __func__);
 435                 return 0;
 436         }
 437         if ((itype >= IOMMU_FAULTS_NUM) || (itype < IOMMU_PAGEFAULT))
 438                 itype = IOMMU_FAULT_UNKNOWN;
 439
 440         if (itype == IOMMU_BUSERROR)
 441                 pr_err("%s occured at 0x%lx(Page table base: 0x%lx)\n",
 442                        iommu_fault_name[itype], fault_addr, pgtable_base);
 443
 444         if (itype == IOMMU_PAGEFAULT)
 445                 pr_err("IOMMU:Page fault detected at 0x%lx from bus id %d of type %s on %s\n",
 446                        fault_addr,
 447                        (status >> 6) & 0x1F,
 448                        (status & 32) ? "write" : "read",
 449                        data->dbgname);
 450
 451         pr_err("Generating Kernel OOPS... because it is unrecoverable.\n");
 452
 453         BUG();
 454
 455         return 0;
 456 }
 457
 458 static void dump_pagetbl(u32 fault_address, u32 addr_dte)
 459 {
 460         u32 lv1_offset;
 461         u32 lv2_offset;
 462
 463         u32 *lv1_entry_pa;
 464         u32 *lv1_entry_va;
 465         u32 *lv1_entry_value;
 466
 467         u32 *lv2_base;
 468         u32 *lv2_entry_pa;
 469         u32 *lv2_entry_va;
 470         u32 *lv2_entry_value;
 471
 472
 473         lv1_offset = lv1ent_offset(fault_address);
 474         lv2_offset = lv2ent_offset(fault_address);
 475
 476         lv1_entry_pa = (u32 *)addr_dte + lv1_offset;
 477         lv1_entry_va = (u32 *)(__va(addr_dte)) + lv1_offset;
 478         lv1_entry_value = (u32 *)(*lv1_entry_va);
 479
 480         lv2_base = (u32 *)((*lv1_entry_va) & 0xfffffffe);
 481         lv2_entry_pa = (u32 *)lv2_base + lv2_offset;
 482         lv2_entry_va = (u32 *)(__va(lv2_base)) + lv2_offset;
 483         lv2_entry_value = (u32 *)(*lv2_entry_va);
 484
 485         pr_info("fault address = 0x%08x,dte addr pa = 0x%08x,va = 0x%08x\n",
 486                 fault_address, addr_dte, (u32)__va(addr_dte));
 487         pr_info("lv1_offset = 0x%x,lv1_entry_pa = 0x%08x,lv1_entry_va = 0x%08x\n",
 488                 lv1_offset, (u32)lv1_entry_pa, (u32)lv1_entry_va);
 489         pr_info("lv1_entry_value(*lv1_entry_va) = 0x%08x,lv2_base = 0x%08x\n",
 490                 (u32)lv1_entry_value, (u32)lv2_base);
 491         pr_info("lv2_offset = 0x%x,lv2_entry_pa = 0x%08x,lv2_entry_va = 0x%08x\n",
 492                 lv2_offset, (u32)lv2_entry_pa, (u32)lv2_entry_va);
 493         pr_info("lv2_entry value(*lv2_entry_va) = 0x%08x\n",
 494                 (u32)lv2_entry_value);
 495 }
 496
 497 static irqreturn_t rockchip_iommu_irq(int irq, void *dev_id)
 498 {
 499         /* SYSMMU is in blocked when interrupt occurred. */
 500         struct iommu_drvdata *data = dev_id;
 501         struct resource *irqres;
 502         struct platform_device *pdev;
 503         enum rk_iommu_inttype itype = IOMMU_FAULT_UNKNOWN;
 504         u32 status;
 505         u32 rawstat;
 506         u32 int_status;
 507         u32 fault_address;
 508         int i, ret = 0;
 509
 510         read_lock(&data->lock);
 511
 512         if (!is_iommu_active(data)) {
 513                 read_unlock(&data->lock);
 514                 return IRQ_HANDLED;
 515         }
 516
 517         if(cpu_is_rk312x() || cpu_is_rk3036())
 518                 rockchip_vcodec_select(data->dbgname);
 519
 520         pdev = to_platform_device(data->iommu);
 521
 522         for (i = 0; i < data->num_res_irq; i++) {
 523                 irqres = platform_get_resource(pdev, IORESOURCE_IRQ, i);
 524                 if (irqres && ((int)irqres->start == irq))
 525                         break;
 526         }
 527
 528         if (i == data->num_res_irq) {
 529                 itype = IOMMU_FAULT_UNKNOWN;
 530         } else {
 531                 int_status = __raw_readl(data->res_bases[i] +
 532                                          IOMMU_REGISTER_INT_STATUS);
 533
 534                 if (int_status != 0) {
 535                         /*mask status*/
 536                         __raw_writel(0x00, data->res_bases[i] +
 537                                      IOMMU_REGISTER_INT_MASK);
 538
 539                         rawstat = __raw_readl(data->res_bases[i] +
 540                                               IOMMU_REGISTER_INT_RAWSTAT);
 541
 542                         if (rawstat & IOMMU_INTERRUPT_PAGE_FAULT) {
 543                                 fault_address = __raw_readl(data->res_bases[i] +
 544                                 IOMMU_REGISTER_PAGE_FAULT_ADDR);
 545                                 itype = IOMMU_PAGEFAULT;
 546                         } else if (rawstat & IOMMU_INTERRUPT_READ_BUS_ERROR) {
 547                                 itype = IOMMU_BUSERROR;
 548                         } else {
 549                                 goto out;
 550                         }
 551                         dump_pagetbl(fault_address,
 552                                      __raw_readl(data->res_bases[i] +
 553                                      IOMMU_REGISTER_DTE_ADDR));
 554                 } else {
 555                         goto out;
 556                 }
 557         }
 558
 559         if (data->fault_handler) {
 560                 unsigned long base = __raw_readl(data->res_bases[i] +
 561                                                  IOMMU_REGISTER_DTE_ADDR);
 562                 status = __raw_readl(data->res_bases[i] +
 563                                      IOMMU_REGISTER_STATUS);
 564                 ret = data->fault_handler(data->dev, itype, base,
 565                                           fault_address, status);
 566         }
 567
 568         if (!ret && (itype != IOMMU_FAULT_UNKNOWN)) {
 569                 if (IOMMU_PAGEFAULT == itype) {
 570                         iommu_zap_tlb(data->res_bases[i]);
 571                         iommu_page_fault_done(data->res_bases[i],
 572                                                data->dbgname);
 573                         __raw_writel(IOMMU_INTERRUPT_PAGE_FAULT |
 574                                      IOMMU_INTERRUPT_READ_BUS_ERROR,
 575                                      data->res_bases[i] +
 576                                      IOMMU_REGISTER_INT_MASK);
 577                 }
 578         } else {
 579                 pr_err("(%s) %s is not handled.\n",
 580                        data->dbgname, iommu_fault_name[itype]);
 581         }
 582
 583 out:
 584         read_unlock(&data->lock);
 585
 586         return IRQ_HANDLED;
 587 }
 588
 589 static bool __rockchip_iommu_disable(struct iommu_drvdata *data)
 590 {
 591         unsigned long flags;
 592         int i;
 593         bool disabled = false;
 594
 595         write_lock_irqsave(&data->lock, flags);
 596
 597         if (!set_iommu_inactive(data))
 598                 goto finish;
 599
 600         for (i = 0; i < data->num_res_mem; i++)
 601                 iommu_disable_paging(data->res_bases[i]);
 602
 603         disabled = true;
 604         data->pgtable = 0;
 605         data->domain = NULL;
 606 finish:
 607         write_unlock_irqrestore(&data->lock, flags);
 608
 609         if (disabled)
 610                 pr_info("(%s) Disabled\n", data->dbgname);
 611         else
 612                 pr_info("(%s) %d times left to be disabled\n",
 613                         data->dbgname, data->activations);
 614
 615         return disabled;
 616 }
 617
 618 /* __rk_sysmmu_enable: Enables System MMU
 619  *
 620  * returns -error if an error occurred and System MMU is not enabled,
 621  * 0 if the System MMU has been just enabled and 1 if System MMU was already
 622  * enabled before.
 623  */
 624 static int __rockchip_iommu_enable(struct iommu_drvdata *data,
 625                                     unsigned long pgtable,
 626                                     struct iommu_domain *domain)
 627 {
 628         int i, ret = 0;
 629         unsigned long flags;
 630
 631         write_lock_irqsave(&data->lock, flags);
 632
 633         if (!set_iommu_active(data)) {
 634                 if (WARN_ON(pgtable != data->pgtable)) {
 635                         ret = -EBUSY;
 636                         set_iommu_inactive(data);
 637                 } else {
 638                         ret = 1;
 639                 }
 640
 641                 pr_info("(%s) Already enabled\n", data->dbgname);
 642                 goto finish;
 643         }
 644
 645         data->pgtable = pgtable;
 646
 647         for (i = 0; i < data->num_res_mem; i++) {
 648                 bool status;
 649
 650                 status = iommu_enable_stall(data->res_bases[i]);
 651                 if (status) {
 652                         __iommu_set_ptbase(data->res_bases[i], pgtable);
 653                         __raw_writel(IOMMU_COMMAND_ZAP_CACHE,
 654                                      data->res_bases[i] +
 655                                      IOMMU_REGISTER_COMMAND);
 656                 }
 657                 __raw_writel(IOMMU_INTERRUPT_PAGE_FAULT |
 658                              IOMMU_INTERRUPT_READ_BUS_ERROR,
 659                              data->res_bases[i]+IOMMU_REGISTER_INT_MASK);
 660                 iommu_enable_paging(data->res_bases[i]);
 661                 iommu_disable_stall(data->res_bases[i]);
 662         }
 663
 664         data->domain = domain;
 665
 666         pr_info("(%s) Enabled\n", data->dbgname);
 667 finish:
 668         write_unlock_irqrestore(&data->lock, flags);
 669
 670         return ret;
 671 }
 672
 673 bool rockchip_iommu_disable(struct device *dev)
 674 {
 675         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 676         bool disabled;
 677
 678         disabled = __rockchip_iommu_disable(data);
 679
 680         return disabled;
 681 }
 682
 683 void rockchip_iommu_tlb_invalidate(struct device *dev)
 684 {
 685         unsigned long flags;
 686         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 687
 688         read_lock_irqsave(&data->lock, flags);
 689
 690         if(cpu_is_rk312x() || cpu_is_rk3036())
 691                 rockchip_vcodec_select(data->dbgname);
 692
 693         if (is_iommu_active(data)) {
 694                 int i;
 695
 696                 for (i = 0; i < data->num_res_mem; i++) {
 697                         if (!iommu_zap_tlb(data->res_bases[i]))
 698                                 pr_err("%s,invalidating TLB failed\n",
 699                                        data->dbgname);
 700                 }
 701         } else {
 702                 pr_info("(%s) Disabled. Skipping invalidating TLB.\n",
 703                         data->dbgname);
 704         }
 705
 706         read_unlock_irqrestore(&data->lock, flags);
 707 }
 708
 709 static phys_addr_t rockchip_iommu_iova_to_phys(struct iommu_domain *domain,
 710                                                dma_addr_t iova)
 711 {
 712         struct rk_iommu_domain *priv = domain->priv;
 713         unsigned long *entry;
 714         unsigned long flags;
 715         phys_addr_t phys = 0;
 716
 717         spin_lock_irqsave(&priv->pgtablelock, flags);
 718
 719         entry = section_entry(priv->pgtable, iova);
 720         entry = page_entry(entry, iova);
 721         phys = spage_phys(entry) + spage_offs(iova);
 722
 723         spin_unlock_irqrestore(&priv->pgtablelock, flags);
 724
 725         return phys;
 726 }
 727
 728 static int lv2set_page(unsigned long *pent, phys_addr_t paddr,
 729                        size_t size, short *pgcnt)
 730 {
 731         if (!lv2ent_fault(pent))
 732                 return -EADDRINUSE;
 733
 734         *pent = mk_lv2ent_spage(paddr);
 735         pgtable_flush(pent, pent + 1);
 736         *pgcnt -= 1;
 737         return 0;
 738 }
 739
 740 static unsigned long *alloc_lv2entry(unsigned long *sent,
 741                                      unsigned long iova, short *pgcounter)
 742 {
 743         if (lv1ent_fault(sent)) {
 744                 unsigned long *pent;
 745
 746                 pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
 747                 BUG_ON((unsigned long)pent & (LV2TABLE_SIZE - 1));
 748                 if (!pent)
 749                         return NULL;
 750
 751                 *sent = mk_lv1ent_page(__pa(pent));
 752                 kmemleak_ignore(pent);
 753                 *pgcounter = NUM_LV2ENTRIES;
 754                 pgtable_flush(pent, pent + NUM_LV2ENTRIES);
 755                 pgtable_flush(sent, sent + 1);
 756         }
 757         return page_entry(sent, iova);
 758 }
 759
 760 static size_t rockchip_iommu_unmap(struct iommu_domain *domain,
 761                                    unsigned long iova, size_t size)
 762 {
 763         struct rk_iommu_domain *priv = domain->priv;
 764         unsigned long flags;
 765         unsigned long *ent;
 766
 767         BUG_ON(priv->pgtable == NULL);
 768
 769         spin_lock_irqsave(&priv->pgtablelock, flags);
 770
 771         ent = section_entry(priv->pgtable, iova);
 772
 773         if (unlikely(lv1ent_fault(ent))) {
 774                 if (size > SPAGE_SIZE)
 775                         size = SPAGE_SIZE;
 776                 goto done;
 777         }
 778
 779         /* lv1ent_page(sent) == true here */
 780
 781         ent = page_entry(ent, iova);
 782
 783         if (unlikely(lv2ent_fault(ent))) {
 784                 size = SPAGE_SIZE;
 785                 goto done;
 786         }
 787
 788         *ent = 0;
 789         size = SPAGE_SIZE;
 790         priv->lv2entcnt[lv1ent_offset(iova)] += 1;
 791         goto done;
 792
 793 done:
 794         /*pr_info("%s:unmap iova 0x%lx/0x%x bytes\n",
 795                   __func__, iova,size);
 796         */
 797         spin_unlock_irqrestore(&priv->pgtablelock, flags);
 798
 799         return size;
 800 }
 801
 802 static int rockchip_iommu_map(struct iommu_domain *domain, unsigned long iova,
 803                               phys_addr_t paddr, size_t size, int prot)
 804 {
 805         struct rk_iommu_domain *priv = domain->priv;
 806         unsigned long *entry;
 807         unsigned long flags;
 808         int ret = -ENOMEM;
 809         unsigned long *pent;
 810
 811         BUG_ON(priv->pgtable == NULL);
 812
 813         spin_lock_irqsave(&priv->pgtablelock, flags);
 814
 815         entry = section_entry(priv->pgtable, iova);
 816
 817         pent = alloc_lv2entry(entry, iova,
 818                               &priv->lv2entcnt[lv1ent_offset(iova)]);
 819         if (!pent)
 820                 ret = -ENOMEM;
 821         else
 822                 ret = lv2set_page(pent, paddr, size,
 823                                   &priv->lv2entcnt[lv1ent_offset(iova)]);
 824
 825         if (ret) {
 826                 pr_err("%s: Failed to map iova 0x%lx/0x%x bytes\n", __func__,
 827                        iova, size);
 828         }
 829         spin_unlock_irqrestore(&priv->pgtablelock, flags);
 830
 831         return ret;
 832 }
 833
 834 static void rockchip_iommu_detach_device(struct iommu_domain *domain,
 835                                          struct device *dev)
 836 {
 837         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 838         struct rk_iommu_domain *priv = domain->priv;
 839         struct list_head *pos;
 840         unsigned long flags;
 841         bool found = false;
 842
 843         spin_lock_irqsave(&priv->lock, flags);
 844
 845         list_for_each(pos, &priv->clients)
 846         {
 847                 if (list_entry(pos, struct iommu_drvdata, node) == data) {
 848                         found = true;
 849                         break;
 850                 }
 851         }
 852         if (!found)
 853                 goto finish;
 854
 855         if(cpu_is_rk312x() || cpu_is_rk3036())
 856                 rockchip_vcodec_select(data->dbgname);
 857
 858         if (__rockchip_iommu_disable(data)) {
 859                 pr_info("%s: Detached IOMMU with pgtable %#lx\n",
 860                         __func__, __pa(priv->pgtable));
 861                 list_del(&data->node);
 862                 INIT_LIST_HEAD(&data->node);
 863
 864         } else
 865                 pr_info("%s: Detaching IOMMU with pgtable %#lx delayed",
 866                         __func__, __pa(priv->pgtable));
 867
 868 finish:
 869         spin_unlock_irqrestore(&priv->lock, flags);
 870 }
 871
 872 static int rockchip_iommu_attach_device(struct iommu_domain *domain,
 873                                         struct device *dev)
 874 {
 875         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 876         struct rk_iommu_domain *priv = domain->priv;
 877         unsigned long flags;
 878         int ret;
 879
 880         spin_lock_irqsave(&priv->lock, flags);
 881
 882         if(cpu_is_rk312x() || cpu_is_rk3036())
 883                 rockchip_vcodec_select(data->dbgname);
 884
 885         ret = __rockchip_iommu_enable(data, __pa(priv->pgtable), domain);
 886
 887         if (ret == 0) {
 888                 /* 'data->node' must not be appeared in priv->clients */
 889                 BUG_ON(!list_empty(&data->node));
 890                 data->dev = dev;
 891                 list_add_tail(&data->node, &priv->clients);
 892         }
 893
 894         spin_unlock_irqrestore(&priv->lock, flags);
 895
 896         if (ret < 0) {
 897                 pr_err("%s: Failed to attach IOMMU with pgtable %#lx\n",
 898                        __func__, __pa(priv->pgtable));
 899         } else if (ret > 0) {
 900                 pr_info("%s: IOMMU with pgtable 0x%lx already attached\n",
 901                         __func__, __pa(priv->pgtable));
 902         } else {
 903                 pr_info("%s: Attached new IOMMU with pgtable 0x%lx\n",
 904                         __func__, __pa(priv->pgtable));
 905         }
 906
 907         return ret;
 908 }
 909
 910 static void rockchip_iommu_domain_destroy(struct iommu_domain *domain)
 911 {
 912         struct rk_iommu_domain *priv = domain->priv;
 913         struct iommu_drvdata *data;
 914         unsigned long flags;
 915         int i;
 916
 917         WARN_ON(!list_empty(&priv->clients));
 918
 919         spin_lock_irqsave(&priv->lock, flags);
 920
 921         list_for_each_entry(data, &priv->clients, node) {
 922                 if(cpu_is_rk312x() || cpu_is_rk3036())
 923                         rockchip_vcodec_select(data->dbgname);
 924                 while (!rockchip_iommu_disable(data->dev))
 925                         ; /* until System MMU is actually disabled */
 926         }
 927         spin_unlock_irqrestore(&priv->lock, flags);
 928
 929         for (i = 0; i < NUM_LV1ENTRIES; i++)
 930                 if (lv1ent_page(priv->pgtable + i))
 931                         kmem_cache_free(lv2table_kmem_cache,
 932                                         __va(lv2table_base(priv->pgtable + i)));
 933
 934         free_pages((unsigned long)priv->pgtable, 0);
 935         free_pages((unsigned long)priv->lv2entcnt, 0);
 936         kfree(domain->priv);
 937         domain->priv = NULL;
 938 }
 939
 940 static int rockchip_iommu_domain_init(struct iommu_domain *domain)
 941 {
 942         struct rk_iommu_domain *priv;
 943
 944         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 945         if (!priv)
 946                 return -ENOMEM;
 947
 948 /*rk32xx iommu use 2 level pagetable,
 949    level1 and leve2 both have 1024 entries,each entry  occupy 4 bytes,
 950    so alloc a page size for each page table
 951 */
 952         priv->pgtable = (unsigned long *)__get_free_pages(GFP_KERNEL |
 953                                                           __GFP_ZERO, 0);
 954         if (!priv->pgtable)
 955                 goto err_pgtable;
 956
 957         priv->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL |
 958                                                     __GFP_ZERO, 0);
 959         if (!priv->lv2entcnt)
 960                 goto err_counter;
 961
 962         pgtable_flush(priv->pgtable, priv->pgtable + NUM_LV1ENTRIES);
 963
 964         spin_lock_init(&priv->lock);
 965         spin_lock_init(&priv->pgtablelock);
 966         INIT_LIST_HEAD(&priv->clients);
 967
 968         domain->priv = priv;
 969         return 0;
 970
 971 err_counter:
 972         free_pages((unsigned long)priv->pgtable, 0);
 973 err_pgtable:
 974         kfree(priv);
 975         return -ENOMEM;
 976 }
 977
 978 static struct iommu_ops rk_iommu_ops = {
 979         .domain_init = &rockchip_iommu_domain_init,
 980         .domain_destroy = &rockchip_iommu_domain_destroy,
 981         .attach_dev = &rockchip_iommu_attach_device,
 982         .detach_dev = &rockchip_iommu_detach_device,
 983         .map = &rockchip_iommu_map,
 984         .unmap = &rockchip_iommu_unmap,
 985         .iova_to_phys = &rockchip_iommu_iova_to_phys,
 986         .pgsize_bitmap = SPAGE_SIZE,
 987 };
 988
 989 static int rockchip_iommu_prepare(void)
 990 {
 991         int ret = 0;
 992         static int registed;
 993
 994         if (registed)
 995                 return 0;
 996
 997         lv2table_kmem_cache = kmem_cache_create("rk-iommu-lv2table",
 998                                                 LV2TABLE_SIZE,
 999                                                 LV2TABLE_SIZE,
1000                                                 0, NULL);
1001         if (!lv2table_kmem_cache) {
1002                 pr_err("%s: failed to create kmem cache\n", __func__);
1003                 return -ENOMEM;
1004         }
1005         ret = bus_set_iommu(&platform_bus_type, &rk_iommu_ops);
1006         if (!ret)
1007                 registed = 1;
1008         else
1009                 pr_err("%s:failed to set iommu to bus\r\n", __func__);
1010         return ret;
1011 }
1012
1013 static int  rockchip_get_iommu_resource_num(struct platform_device *pdev,
1014                                              unsigned int type)
1015 {
1016         struct resource *info = NULL;
1017         int num_resources = 0;
1018
1019         /*get resouce info*/
1020 again:
1021         info = platform_get_resource(pdev, type, num_resources);
1022         while (info) {
1023                 num_resources++;
1024                 goto again;
1025         }
1026         return num_resources;
1027 }
1028
1029 static struct kobject *dump_mmu_object;
1030
1031 static int dump_mmu_pagetbl(struct device *dev, struct device_attribute *attr,
1032                             const char *buf, u32 count)
1033 {
1034         u32 fault_address;
1035         u32 iommu_dte;
1036         u32 mmu_base;
1037         void __iomem *base;
1038         u32 ret;
1039
1040         ret = kstrtouint(buf, 0, &mmu_base);
1041         if (ret)
1042                 pr_info("%s is not in hexdecimal form.\n", buf);
1043         base = ioremap(mmu_base, 0x100);
1044         iommu_dte = __raw_readl(base + IOMMU_REGISTER_DTE_ADDR);
1045         fault_address = __raw_readl(base + IOMMU_REGISTER_PAGE_FAULT_ADDR);
1046         dump_pagetbl(fault_address, iommu_dte);
1047         return count;
1048 }
1049
1050 static DEVICE_ATTR(dump_mmu_pgtable, 0644, NULL, dump_mmu_pagetbl);
1051
1052 void dump_iommu_sysfs_init(void)
1053 {
1054         u32 ret;
1055
1056         dump_mmu_object = kobject_create_and_add("rk_iommu", NULL);
1057         if (dump_mmu_object == NULL)
1058                 return;
1059         ret = sysfs_create_file(dump_mmu_object,
1060                                 &dev_attr_dump_mmu_pgtable.attr);
1061 }
1062
1063 static int rockchip_iommu_probe(struct platform_device *pdev)
1064 {
1065         int i, ret;
1066         struct device *dev;
1067         struct iommu_drvdata *data;
1068
1069         dev = &pdev->dev;
1070
1071         ret = rockchip_iommu_prepare();
1072         if (ret) {
1073                 pr_err("%s,failed\r\n", __func__);
1074                 goto err_alloc;
1075         }
1076
1077         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
1078         if (!data) {
1079                 dev_dbg(dev, "Not enough memory\n");
1080                 ret = -ENOMEM;
1081                 goto err_alloc;
1082         }
1083         dev_set_drvdata(dev, data);
1084 /*
1085         ret = dev_set_drvdata(dev, data);
1086         if (ret)
1087         {
1088                 dev_dbg(dev, "Unabled to initialize driver data\n");
1089                 goto err_init;
1090         }
1091 */
1092         if (pdev->dev.of_node) {
1093                 of_property_read_string(pdev->dev.of_node,
1094                                         "dbgname", &(data->dbgname));
1095         } else {
1096                 pr_info("dbgname not assigned in device tree or device node not exist\r\n");
1097         }
1098
1099         pr_info("(%s) Enter\n", data->dbgname);
1100
1101         data->num_res_mem = rockchip_get_iommu_resource_num(pdev,
1102                                 IORESOURCE_MEM);
1103         if (0 == data->num_res_mem) {
1104                 pr_err("can't find iommu memory resource \r\n");
1105                 goto err_init;
1106         }
1107         pr_info("data->num_res_mem=%d\n", data->num_res_mem);
1108         data->num_res_irq = rockchip_get_iommu_resource_num(pdev,
1109                                 IORESOURCE_IRQ);
1110         if (0 == data->num_res_irq) {
1111                 pr_err("can't find iommu irq resource \r\n");
1112                 goto err_init;
1113         }
1114
1115         data->res_bases = kmalloc_array(data->num_res_mem,
1116                                 sizeof(*data->res_bases), GFP_KERNEL);
1117         if (data->res_bases == NULL) {
1118                 dev_dbg(dev, "Not enough memory\n");
1119                 ret = -ENOMEM;
1120                 goto err_init;
1121         }
1122
1123         for (i = 0; i < data->num_res_mem; i++) {
1124                 struct resource *res;
1125
1126                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1127                 if (!res) {
1128                         pr_err("Unable to find IOMEM region\n");
1129                         ret = -ENOENT;
1130                         goto err_res;
1131                 }
1132                 data->res_bases[i] = ioremap(res->start, resource_size(res));
1133                 pr_info("res->start = 0x%08x  ioremap to  data->res_bases[%d] = 0x%08x\n",
1134                         res->start, i, (unsigned int)data->res_bases[i]);
1135                 if (!data->res_bases[i]) {
1136                         pr_err("Unable to map IOMEM @ PA:%#x\n", res->start);
1137                         ret = -ENOENT;
1138                         goto err_res;
1139                 }
1140
1141                 if(cpu_is_rk312x() || cpu_is_rk3036())
1142                         rockchip_vcodec_select(data->dbgname);
1143
1144                 if (!strstr(data->dbgname, "isp")) {
1145                         if (!iommu_reset(data->res_bases[i], data->dbgname)) {
1146                                 ret = -ENOENT;
1147                                 goto err_res;
1148                         }
1149                 }
1150         }
1151
1152         for (i = 0; i < data->num_res_irq; i++) {
1153                 ret = platform_get_irq(pdev, i);
1154                 if (ret <= 0) {
1155                         pr_err("Unable to find IRQ resource\n");
1156                         goto err_irq;
1157                 }
1158                 ret = request_irq(ret, rockchip_iommu_irq,
1159                                   IRQF_SHARED, dev_name(dev), data);
1160                 if (ret) {
1161                         pr_err("Unabled to register interrupt handler\n");
1162                         goto err_irq;
1163                 }
1164         }
1165         ret = rockchip_init_iovmm(dev, &data->vmm);
1166         if (ret)
1167                 goto err_irq;
1168
1169         data->iommu = dev;
1170         rwlock_init(&data->lock);
1171         INIT_LIST_HEAD(&data->node);
1172
1173         set_fault_handler(data, &default_fault_handler);
1174
1175         pr_info("(%s) Initialized\n", data->dbgname);
1176         return 0;
1177
1178 err_irq:
1179         while (i-- > 0) {
1180                 int irq;
1181
1182                 irq = platform_get_irq(pdev, i);
1183                 free_irq(irq, data);
1184         }
1185 err_res:
1186         while (data->num_res_mem-- > 0)
1187                 iounmap(data->res_bases[data->num_res_mem]);
1188         kfree(data->res_bases);
1189 err_init:
1190         kfree(data);
1191 err_alloc:
1192         dev_err(dev, "Failed to initialize\n");
1193         return ret;
1194 }
1195
1196 #ifdef CONFIG_OF
1197 static const struct of_device_id iommu_dt_ids[] = {
1198         { .compatible = IEP_IOMMU_COMPATIBLE_NAME},
1199         { .compatible = VIP_IOMMU_COMPATIBLE_NAME},
1200         { .compatible = VOPB_IOMMU_COMPATIBLE_NAME},
1201         { .compatible = VOPL_IOMMU_COMPATIBLE_NAME},
1202         { .compatible = HEVC_IOMMU_COMPATIBLE_NAME},
1203         { .compatible = VPU_IOMMU_COMPATIBLE_NAME},
1204         { .compatible = ISP_IOMMU_COMPATIBLE_NAME},
1205         { .compatible = VOP_IOMMU_COMPATIBLE_NAME},
1206         { /* end */ }
1207 };
1208
1209 MODULE_DEVICE_TABLE(of, iommu_dt_ids);
1210 #endif
1211
1212 static struct platform_driver rk_iommu_driver = {
1213         .probe = rockchip_iommu_probe,
1214         .remove = NULL,
1215         .driver = {
1216                    .name = "rk_iommu",
1217                    .owner = THIS_MODULE,
1218                    .of_match_table = of_match_ptr(iommu_dt_ids),
1219         },
1220 };
1221
1222 static int __init rockchip_iommu_init_driver(void)
1223 {
1224         dump_iommu_sysfs_init();
1225
1226         return platform_driver_register(&rk_iommu_driver);
1227 }
1228
1229 core_initcall(rockchip_iommu_init_driver);