drivers/iommu/rockchip-iommu.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License version 2 as
   4  * published by the Free Software Foundation.
   5  */
   6
   7 #ifdef CONFIG_ROCKCHIP_IOMMU_DEBUG
   8 #define DEBUG
   9 #endif
  10
  11 #include <linux/io.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/slab.h>
  14 #include <linux/clk.h>
  15 #include <linux/err.h>
  16 #include <linux/mm.h>
  17 #include <linux/errno.h>
  18 #include <linux/memblock.h>
  19 #include <linux/export.h>
  20 #include <linux/module.h>
  21
  22 #include <asm/cacheflush.h>
  23 #include <asm/pgtable.h>
  24 #include <linux/of.h>
  25 #include <linux/rockchip-iovmm.h>
  26 #include <linux/rockchip/grf.h>
  27 #include <linux/rockchip/cpu.h>
  28 #include <linux/rockchip/iomap.h>
  29 #include <linux/device.h>
  30 #include "rockchip-iommu.h"
  31
  32 /* We does not consider super section mapping (16MB) */
  33 #define SPAGE_ORDER 12
  34 #define SPAGE_SIZE (1 << SPAGE_ORDER)
  35 #define SPAGE_MASK (~(SPAGE_SIZE - 1))
  36
  37 static void __iomem *rk312x_vop_mmu_base;
  38
  39 enum iommu_entry_flags {
  40         IOMMU_FLAGS_PRESENT = 0x01,
  41         IOMMU_FLAGS_READ_PERMISSION = 0x02,
  42         IOMMU_FLAGS_WRITE_PERMISSION = 0x04,
  43         IOMMU_FLAGS_OVERRIDE_CACHE = 0x8,
  44         IOMMU_FLAGS_WRITE_CACHEABLE = 0x10,
  45         IOMMU_FLAGS_WRITE_ALLOCATE = 0x20,
  46         IOMMU_FLAGS_WRITE_BUFFERABLE = 0x40,
  47         IOMMU_FLAGS_READ_CACHEABLE = 0x80,
  48         IOMMU_FLAGS_READ_ALLOCATE = 0x100,
  49         IOMMU_FLAGS_MASK = 0x1FF,
  50 };
  51
  52 #define rockchip_lv1ent_fault(sent) ((*(sent) & IOMMU_FLAGS_PRESENT) == 0)
  53 #define rockchip_lv1ent_page(sent) ((*(sent) & IOMMU_FLAGS_PRESENT) == 1)
  54 #define rockchip_lv2ent_fault(pent) ((*(pent) & IOMMU_FLAGS_PRESENT) == 0)
  55 #define rockchip_spage_phys(pent) (*(pent) & SPAGE_MASK)
  56 #define rockchip_spage_offs(iova) ((iova) & 0x0FFF)
  57
  58 #define rockchip_lv1ent_offset(iova) (((iova)>>22) & 0x03FF)
  59 #define rockchip_lv2ent_offset(iova) (((iova)>>12) & 0x03FF)
  60
  61 #define NUM_LV1ENTRIES 1024
  62 #define NUM_LV2ENTRIES 1024
  63
  64 #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(long))
  65
  66 #define rockchip_lv2table_base(sent) (*(sent) & 0xFFFFFFFE)
  67
  68 #define rockchip_mk_lv1ent_page(pa) ((pa) | IOMMU_FLAGS_PRESENT)
  69 /*write and read permission for level2 page default*/
  70 #define rockchip_mk_lv2ent_spage(pa) ((pa) | IOMMU_FLAGS_PRESENT | \
  71                              IOMMU_FLAGS_READ_PERMISSION | \
  72                              IOMMU_FLAGS_WRITE_PERMISSION)
  73
  74 #define IOMMU_REG_POLL_COUNT_FAST 1000
  75
  76 /**
  77  * MMU register numbers
  78  * Used in the register read/write routines.
  79  * See the hardware documentation for more information about each register
  80  */
  81 enum iommu_register {
  82         /**< Current Page Directory Pointer */
  83         IOMMU_REGISTER_DTE_ADDR = 0x0000,
  84         /**< Status of the MMU */
  85         IOMMU_REGISTER_STATUS = 0x0004,
  86         /**< Command register, used to control the MMU */
  87         IOMMU_REGISTER_COMMAND = 0x0008,
  88         /**< Logical address of the last page fault */
  89         IOMMU_REGISTER_PAGE_FAULT_ADDR = 0x000C,
  90         /**< Used to invalidate the mapping of a single page from the MMU */
  91         IOMMU_REGISTER_ZAP_ONE_LINE = 0x010,
  92         /**< Raw interrupt status, all interrupts visible */
  93         IOMMU_REGISTER_INT_RAWSTAT = 0x0014,
  94         /**< Indicate to the MMU that the interrupt has been received */
  95         IOMMU_REGISTER_INT_CLEAR = 0x0018,
  96         /**< Enable/disable types of interrupts */
  97         IOMMU_REGISTER_INT_MASK = 0x001C,
  98         /**< Interrupt status based on the mask */
  99         IOMMU_REGISTER_INT_STATUS = 0x0020,
 100         IOMMU_REGISTER_AUTO_GATING = 0x0024
 101 };
 102
 103 enum iommu_command {
 104         /**< Enable paging (memory translation) */
 105         IOMMU_COMMAND_ENABLE_PAGING = 0x00,
 106         /**< Disable paging (memory translation) */
 107         IOMMU_COMMAND_DISABLE_PAGING = 0x01,
 108         /**<  Enable stall on page fault */
 109         IOMMU_COMMAND_ENABLE_STALL = 0x02,
 110         /**< Disable stall on page fault */
 111         IOMMU_COMMAND_DISABLE_STALL = 0x03,
 112         /**< Zap the entire page table cache */
 113         IOMMU_COMMAND_ZAP_CACHE = 0x04,
 114         /**< Page fault processed */
 115         IOMMU_COMMAND_PAGE_FAULT_DONE = 0x05,
 116         /**< Reset the MMU back to power-on settings */
 117         IOMMU_COMMAND_HARD_RESET = 0x06
 118 };
 119
 120 /**
 121  * MMU interrupt register bits
 122  * Each cause of the interrupt is reported
 123  * through the (raw) interrupt status registers.
 124  * Multiple interrupts can be pending, so multiple bits
 125  * can be set at once.
 126  */
 127 enum iommu_interrupt {
 128         IOMMU_INTERRUPT_PAGE_FAULT = 0x01, /**< A page fault occured */
 129         IOMMU_INTERRUPT_READ_BUS_ERROR = 0x02 /**< A bus read error occured */
 130 };
 131
 132 enum iommu_status_bits {
 133         IOMMU_STATUS_BIT_PAGING_ENABLED      = 1 << 0,
 134         IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE   = 1 << 1,
 135         IOMMU_STATUS_BIT_STALL_ACTIVE        = 1 << 2,
 136         IOMMU_STATUS_BIT_IDLE                = 1 << 3,
 137         IOMMU_STATUS_BIT_REPLAY_BUFFER_EMPTY = 1 << 4,
 138         IOMMU_STATUS_BIT_PAGE_FAULT_IS_WRITE = 1 << 5,
 139         IOMMU_STATUS_BIT_STALL_NOT_ACTIVE    = 1 << 31,
 140 };
 141
 142 /**
 143  * Size of an MMU page in bytes
 144  */
 145 #define IOMMU_PAGE_SIZE 0x1000
 146
 147 /*
 148  * Size of the address space referenced by a page table page
 149  */
 150 #define IOMMU_VIRTUAL_PAGE_SIZE 0x400000 /* 4 MiB */
 151
 152 /**
 153  * Page directory index from address
 154  * Calculates the page directory index from the given address
 155  */
 156 #define IOMMU_PDE_ENTRY(address) (((address)>>22) & 0x03FF)
 157
 158 /**
 159  * Page table index from address
 160  * Calculates the page table index from the given address
 161  */
 162 #define IOMMU_PTE_ENTRY(address) (((address)>>12) & 0x03FF)
 163
 164 /**
 165  * Extract the memory address from an PDE/PTE entry
 166  */
 167 #define IOMMU_ENTRY_ADDRESS(value) ((value) & 0xFFFFFC00)
 168
 169 #define INVALID_PAGE ((u32)(~0))
 170
 171 static struct kmem_cache *lv2table_kmem_cache;
 172
 173 static unsigned long *rockchip_section_entry(unsigned long *pgtable, unsigned long iova)
 174 {
 175         return pgtable + rockchip_lv1ent_offset(iova);
 176 }
 177
 178 static unsigned long *rockchip_page_entry(unsigned long *sent, unsigned long iova)
 179 {
 180         return (unsigned long *)__va(rockchip_lv2table_base(sent)) +
 181                 rockchip_lv2ent_offset(iova);
 182 }
 183
 184 struct rk_iommu_domain {
 185         struct list_head clients; /* list of iommu_drvdata.node */
 186         unsigned long *pgtable; /* lv1 page table, 4KB */
 187         short *lv2entcnt; /* free lv2 entry counter for each section */
 188         spinlock_t lock; /* lock for this structure */
 189         spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
 190 };
 191
 192 static bool rockchip_set_iommu_active(struct iommu_drvdata *data)
 193 {
 194         /* return true if the IOMMU was not active previously
 195            and it needs to be initialized */
 196         return ++data->activations == 1;
 197 }
 198
 199 static bool rockchip_set_iommu_inactive(struct iommu_drvdata *data)
 200 {
 201         /* return true if the IOMMU is needed to be disabled */
 202         BUG_ON(data->activations < 1);
 203         return --data->activations == 0;
 204 }
 205
 206 static bool rockchip_is_iommu_active(struct iommu_drvdata *data)
 207 {
 208         return data->activations > 0;
 209 }
 210
 211 static void rockchip_iommu_disable_stall(void __iomem *base)
 212 {
 213         int i;
 214         u32 mmu_status;
 215
 216         if (base != rk312x_vop_mmu_base) {
 217                 mmu_status = __raw_readl(base + IOMMU_REGISTER_STATUS);
 218         } else {
 219                 goto skip_vop_mmu_disable;
 220         }
 221
 222         if (0 == (mmu_status & IOMMU_STATUS_BIT_PAGING_ENABLED)) {
 223                 return;
 224         }
 225
 226         if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE) {
 227                 pr_info("Aborting MMU disable stall request since it is in pagefault state.\n");
 228                 return;
 229         }
 230
 231         if (!(mmu_status & IOMMU_STATUS_BIT_STALL_ACTIVE)) {
 232                 return;
 233         }
 234
 235         skip_vop_mmu_disable:
 236         __raw_writel(IOMMU_COMMAND_DISABLE_STALL, base + IOMMU_REGISTER_COMMAND);
 237
 238         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 239                 u32 status;
 240
 241                 if (base != rk312x_vop_mmu_base) {
 242                         status = __raw_readl(base + IOMMU_REGISTER_STATUS);
 243                 } else {
 244                         int j;
 245                         while (j < 5)
 246                                 j++;
 247                         return;
 248                 }
 249
 250                 if (0 == (status & IOMMU_STATUS_BIT_STALL_ACTIVE))
 251                         break;
 252
 253                 if (status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE)
 254                         break;
 255
 256                 if (0 == (mmu_status & IOMMU_STATUS_BIT_PAGING_ENABLED))
 257                         break;
 258         }
 259
 260         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 261                 pr_info("Disable stall request failed, MMU status is 0x%08X\n",
 262                       __raw_readl(base + IOMMU_REGISTER_STATUS));
 263         }
 264 }
 265
 266 static bool rockchip_iommu_enable_stall(void __iomem *base)
 267 {
 268         int i;
 269
 270         u32 mmu_status;
 271
 272         if (base != rk312x_vop_mmu_base) {
 273                 mmu_status = __raw_readl(base + IOMMU_REGISTER_STATUS);
 274         } else {
 275                 goto skip_vop_mmu_enable;
 276         }
 277
 278         if (0 == (mmu_status & IOMMU_STATUS_BIT_PAGING_ENABLED)) {
 279                 return true;
 280         }
 281
 282         if (mmu_status & IOMMU_STATUS_BIT_STALL_ACTIVE){
 283                 pr_info("MMU stall already enabled\n");
 284                 return true;
 285         }
 286
 287         if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE) {
 288                 pr_info("Aborting MMU stall request since it is in pagefault state. mmu status is 0x%08x\n",
 289                         mmu_status);
 290                 return false;
 291         }
 292
 293         skip_vop_mmu_enable:
 294         __raw_writel(IOMMU_COMMAND_ENABLE_STALL, base + IOMMU_REGISTER_COMMAND);
 295
 296         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 297                 if (base != rk312x_vop_mmu_base) {
 298                         mmu_status = __raw_readl(base + IOMMU_REGISTER_STATUS);
 299                 } else {
 300                         int j;
 301                         while (j < 5)
 302                                 j++;
 303                         return true;
 304                 }
 305
 306                 if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE)
 307                         break;
 308
 309                 if ((mmu_status & IOMMU_STATUS_BIT_STALL_ACTIVE) &&
 310                     (0 == (mmu_status & IOMMU_STATUS_BIT_STALL_NOT_ACTIVE)))
 311                         break;
 312
 313                 if (0 == (mmu_status & (IOMMU_STATUS_BIT_PAGING_ENABLED)))
 314                         break;
 315         }
 316
 317         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 318                 pr_info("Enable stall request failed, MMU status is 0x%08X\n",
 319                        __raw_readl(base + IOMMU_REGISTER_STATUS));
 320                 return false;
 321         }
 322
 323         if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE) {
 324                 pr_info("Aborting MMU stall request since it has a pagefault.\n");
 325                 return false;
 326         }
 327
 328         return true;
 329 }
 330
 331 static bool rockchip_iommu_enable_paging(void __iomem *base)
 332 {
 333         int i;
 334
 335         __raw_writel(IOMMU_COMMAND_ENABLE_PAGING,
 336                      base + IOMMU_REGISTER_COMMAND);
 337
 338         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 339                 if (base != rk312x_vop_mmu_base) {
 340                         if (__raw_readl(base + IOMMU_REGISTER_STATUS) &
 341                                 IOMMU_STATUS_BIT_PAGING_ENABLED)
 342                         break;
 343                 } else {
 344                         int j;
 345                         while (j < 5)
 346                                 j++;
 347                         return true;
 348                 }
 349         }
 350
 351         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 352                 pr_info("Enable paging request failed, MMU status is 0x%08X\n",
 353                        __raw_readl(base + IOMMU_REGISTER_STATUS));
 354                 return false;
 355         }
 356
 357         return true;
 358 }
 359
 360 static bool rockchip_iommu_disable_paging(void __iomem *base)
 361 {
 362         int i;
 363
 364         __raw_writel(IOMMU_COMMAND_DISABLE_PAGING,
 365                      base + IOMMU_REGISTER_COMMAND);
 366
 367         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 368                 if (base != rk312x_vop_mmu_base) {
 369                         if (!(__raw_readl(base + IOMMU_REGISTER_STATUS) &
 370                                   IOMMU_STATUS_BIT_PAGING_ENABLED))
 371                                 break;
 372                 } else {
 373                         int j;
 374                         while (j < 5)
 375                                 j++;
 376                         return true;
 377                 }
 378         }
 379
 380         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 381                 pr_info("Disable paging request failed, MMU status is 0x%08X\n",
 382                        __raw_readl(base + IOMMU_REGISTER_STATUS));
 383                 return false;
 384         }
 385
 386         return true;
 387 }
 388
 389 static void rockchip_iommu_page_fault_done(void __iomem *base, const char *dbgname)
 390 {
 391         pr_info("MMU: %s: Leaving page fault mode\n",
 392                 dbgname);
 393         __raw_writel(IOMMU_COMMAND_PAGE_FAULT_DONE,
 394                      base + IOMMU_REGISTER_COMMAND);
 395 }
 396 #if 0
 397 static void rockchip_iommu_zap_tlb_without_stall (void __iomem *base)
 398 {
 399         __raw_writel(IOMMU_COMMAND_ZAP_CACHE, base + IOMMU_REGISTER_COMMAND);
 400 }
 401 #endif
 402 static int rockchip_iommu_zap_tlb(void __iomem *base)
 403 {
 404         if (!rockchip_iommu_enable_stall(base)) {
 405                 pr_err("%s failed\n", __func__);
 406                 return -1;
 407         }
 408
 409         __raw_writel(IOMMU_COMMAND_ZAP_CACHE, base + IOMMU_REGISTER_COMMAND);
 410
 411         rockchip_iommu_disable_stall(base);
 412
 413         return 0;
 414 }
 415
 416 static inline bool rockchip_iommu_raw_reset(void __iomem *base)
 417 {
 418         int i;
 419         unsigned int ret;
 420         unsigned int grf_value;
 421
 422         __raw_writel(0xCAFEBABE, base + IOMMU_REGISTER_DTE_ADDR);
 423
 424         if (base != rk312x_vop_mmu_base) {
 425                 ret = __raw_readl(base + IOMMU_REGISTER_DTE_ADDR);
 426                 if (!(0xCAFEB000 == ret)) {
 427                         grf_value = readl_relaxed(RK_GRF_VIRT + RK3036_GRF_SOC_CON1);
 428                         pr_info("error when %s. grf = 0x%08x\n", __func__, grf_value);
 429                         return false;
 430                 }
 431         }
 432         __raw_writel(IOMMU_COMMAND_HARD_RESET,
 433                      base + IOMMU_REGISTER_COMMAND);
 434
 435         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 436                 if (base != rk312x_vop_mmu_base) {
 437                         if (__raw_readl(base + IOMMU_REGISTER_DTE_ADDR) == 0)
 438                                 break;
 439                 } else {
 440                         int j;
 441                         while (j < 5)
 442                                 j++;
 443                         return true;
 444                 }
 445         }
 446
 447         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 448                 pr_info("%s,Reset request failed, MMU status is 0x%08X\n",
 449                        __func__, __raw_readl(base + IOMMU_REGISTER_DTE_ADDR));
 450                 return false;
 451         }
 452         return true;
 453 }
 454
 455 static void rockchip_iommu_set_ptbase(void __iomem *base, unsigned long pgd)
 456 {
 457         __raw_writel(pgd, base + IOMMU_REGISTER_DTE_ADDR);
 458 }
 459
 460 static bool rockchip_iommu_reset(void __iomem *base, const char *dbgname)
 461 {
 462         bool ret = true;
 463
 464         ret = rockchip_iommu_raw_reset(base);
 465         if (!ret) {
 466                 pr_info("(%s), %s failed\n", dbgname, __func__);
 467                 return ret;
 468         }
 469
 470         if (base != rk312x_vop_mmu_base)
 471                 __raw_writel(IOMMU_INTERRUPT_PAGE_FAULT |
 472                              IOMMU_INTERRUPT_READ_BUS_ERROR,
 473                              base + IOMMU_REGISTER_INT_MASK);
 474         else
 475                 __raw_writel(0x00, base + IOMMU_REGISTER_INT_MASK);
 476
 477         return ret;
 478 }
 479
 480 static inline void rockchip_pgtable_flush(void *vastart, void *vaend)
 481 {
 482         dmac_flush_range(vastart, vaend);
 483         outer_flush_range(virt_to_phys(vastart), virt_to_phys(vaend));
 484 }
 485
 486 static void dump_pagetbl(dma_addr_t fault_address, u32 addr_dte)
 487 {
 488         u32 dte_index, pte_index, page_offset;
 489         u32 mmu_dte_addr;
 490         phys_addr_t mmu_dte_addr_phys, dte_addr_phys;
 491         u32 *dte_addr;
 492         u32 dte;
 493         phys_addr_t pte_addr_phys = 0;
 494         u32 *pte_addr = NULL;
 495         u32 pte = 0;
 496         phys_addr_t page_addr_phys = 0;
 497         u32 page_flags = 0;
 498
 499         dte_index = rockchip_lv1ent_offset(fault_address);
 500         pte_index = rockchip_lv2ent_offset(fault_address);
 501         page_offset = (u32)(fault_address & 0x00000fff);
 502
 503         mmu_dte_addr = addr_dte;
 504         mmu_dte_addr_phys = (phys_addr_t)mmu_dte_addr;
 505
 506         dte_addr_phys = mmu_dte_addr_phys + (4 * dte_index);
 507         dte_addr = phys_to_virt(dte_addr_phys);
 508         dte = *dte_addr;
 509
 510         if (!(IOMMU_FLAGS_PRESENT & dte))
 511                 goto print_it;
 512
 513         pte_addr_phys = ((phys_addr_t)dte & 0xfffff000) + (pte_index * 4);
 514         pte_addr = phys_to_virt(pte_addr_phys);
 515         pte = *pte_addr;
 516
 517         if (!(IOMMU_FLAGS_PRESENT & pte))
 518                 goto print_it;
 519
 520         page_addr_phys = ((phys_addr_t)pte & 0xfffff000) + page_offset;
 521         page_flags = pte & 0x000001fe;
 522
 523 print_it:
 524         pr_err("iova = %pad: dte_index: 0x%03x pte_index: 0x%03x page_offset: 0x%03x\n",
 525                 &fault_address, dte_index, pte_index, page_offset);
 526         pr_err("mmu_dte_addr: %pa dte@%pa: %#08x valid: %u pte@%pa: %#08x valid: %u page@%pa flags: %#03x\n",
 527                 &mmu_dte_addr_phys, &dte_addr_phys, dte,
 528                 (dte & IOMMU_FLAGS_PRESENT), &pte_addr_phys, pte,
 529                 (pte & IOMMU_FLAGS_PRESENT), &page_addr_phys, page_flags);
 530 }
 531
 532 static irqreturn_t rockchip_iommu_irq(int irq, void *dev_id)
 533 {
 534         /* SYSMMU is in blocked when interrupt occurred. */
 535         struct iommu_drvdata *data = dev_id;
 536         u32 status;
 537         u32 rawstat;
 538         dma_addr_t fault_address;
 539         int i;
 540         unsigned long flags;
 541         int ret;
 542         u32 reg_status;
 543
 544         spin_lock_irqsave(&data->data_lock, flags);
 545
 546         if (!rockchip_is_iommu_active(data)) {
 547                 spin_unlock_irqrestore(&data->data_lock, flags);
 548                 return IRQ_HANDLED;
 549         }
 550
 551         for (i = 0; i < data->num_res_mem; i++) {
 552                 status = __raw_readl(data->res_bases[i] +
 553                                      IOMMU_REGISTER_INT_STATUS);
 554                 if (status == 0)
 555                         continue;
 556
 557                 rawstat = __raw_readl(data->res_bases[i] +
 558                                       IOMMU_REGISTER_INT_RAWSTAT);
 559
 560                 reg_status = __raw_readl(data->res_bases[i] +
 561                                          IOMMU_REGISTER_STATUS);
 562
 563                 dev_info(data->iommu, "1.rawstat = 0x%08x,status = 0x%08x,reg_status = 0x%08x\n",
 564                          rawstat, status, reg_status);
 565
 566                 if (rawstat & IOMMU_INTERRUPT_PAGE_FAULT) {
 567                         u32 dte;
 568                         int flags;
 569
 570                         fault_address = __raw_readl(data->res_bases[i] +
 571                                             IOMMU_REGISTER_PAGE_FAULT_ADDR);
 572
 573                         dte = __raw_readl(data->res_bases[i] +
 574                                           IOMMU_REGISTER_DTE_ADDR);
 575
 576                         flags = (status & 32) ? 1 : 0;
 577
 578                         dev_err(data->iommu, "Page fault detected at %pad from bus id %d of type %s on %s\n",
 579                                 &fault_address, (status >> 6) & 0x1F,
 580                                 (flags == 1) ? "write" : "read", data->dbgname);
 581
 582                         dump_pagetbl(fault_address, dte);
 583
 584                         if (data->domain)
 585                                 report_iommu_fault(data->domain, data->iommu,
 586                                                    fault_address, flags);
 587
 588                         rockchip_iommu_page_fault_done(data->res_bases[i],
 589                                                        data->dbgname);
 590                 }
 591
 592                 if (rawstat & IOMMU_INTERRUPT_READ_BUS_ERROR) {
 593                         dev_err(data->iommu, "bus error occured at %pad\n",
 594                                 &fault_address);
 595                 }
 596
 597                 if (rawstat & ~(IOMMU_INTERRUPT_READ_BUS_ERROR |
 598                     IOMMU_INTERRUPT_PAGE_FAULT)) {
 599                         dev_err(data->iommu, "unexpected int_status: %#08x\n\n",
 600                                 rawstat);
 601                 }
 602
 603                 __raw_writel(rawstat, data->res_bases[i] +
 604                              IOMMU_REGISTER_INT_CLEAR);
 605
 606                 status = __raw_readl(data->res_bases[i] +
 607                                      IOMMU_REGISTER_INT_STATUS);
 608
 609                 rawstat = __raw_readl(data->res_bases[i] +
 610                                       IOMMU_REGISTER_INT_RAWSTAT);
 611
 612                 reg_status = __raw_readl(data->res_bases[i] +
 613                                          IOMMU_REGISTER_STATUS);
 614
 615                 dev_info(data->iommu, "2.rawstat = 0x%08x,status = 0x%08x,reg_status = 0x%08x\n",
 616                          rawstat, status, reg_status);
 617
 618                 ret = rockchip_iommu_zap_tlb(data->res_bases[i]);
 619                 if (ret)
 620                         dev_err(data->iommu, "(%s) %s failed\n", data->dbgname,
 621                                 __func__);
 622         }
 623
 624         spin_unlock_irqrestore(&data->data_lock, flags);
 625         return IRQ_HANDLED;
 626 }
 627
 628 static bool rockchip_iommu_disable(struct iommu_drvdata *data)
 629 {
 630         unsigned long flags;
 631         int i;
 632         bool ret = false;
 633
 634         spin_lock_irqsave(&data->data_lock, flags);
 635
 636         if (!rockchip_set_iommu_inactive(data)) {
 637                 spin_unlock_irqrestore(&data->data_lock, flags);
 638                 dev_info(data->iommu,"(%s) %d times left to be disabled\n",
 639                          data->dbgname, data->activations);
 640                 return ret;
 641         }
 642
 643         for (i = 0; i < data->num_res_mem; i++) {
 644                 __raw_writel(0, data->res_bases[i] + IOMMU_REGISTER_INT_MASK);
 645                 ret = rockchip_iommu_disable_paging(data->res_bases[i]);
 646                 if (!ret) {
 647                         spin_unlock_irqrestore(&data->data_lock, flags);
 648                         dev_info(data->iommu, "%s error\n", __func__);
 649                         return ret;
 650                 }
 651         }
 652
 653         data->pgtable = 0;
 654
 655         spin_unlock_irqrestore(&data->data_lock, flags);
 656
 657         dev_info(data->iommu,"(%s) Disabled\n", data->dbgname);
 658
 659         return ret;
 660 }
 661
 662 /* __rk_sysmmu_enable: Enables System MMU
 663  *
 664  * returns -error if an error occurred and System MMU is not enabled,
 665  * 0 if the System MMU has been just enabled and 1 if System MMU was already
 666  * enabled before.
 667  */
 668 static int rockchip_iommu_enable(struct iommu_drvdata *data, unsigned long pgtable)
 669 {
 670         int i, ret = 0;
 671         unsigned long flags;
 672
 673         spin_lock_irqsave(&data->data_lock, flags);
 674
 675         if (!rockchip_set_iommu_active(data)) {
 676                 if (WARN_ON(pgtable != data->pgtable)) {
 677                         ret = -EBUSY;
 678                         rockchip_set_iommu_inactive(data);
 679                 } else {
 680                         ret = 1;
 681                 }
 682
 683                 spin_unlock_irqrestore(&data->data_lock, flags);
 684                 dev_info(data->iommu, "(%s) Already enabled\n", data->dbgname);
 685
 686                 return ret;
 687         }
 688
 689         for (i = 0; i < data->num_res_mem; i++) {
 690                 ret = rockchip_iommu_enable_stall(data->res_bases[i]);
 691                 if (!ret) {
 692                         dev_info(data->iommu, "(%s), %s failed\n",
 693                                  data->dbgname, __func__);
 694                         spin_unlock_irqrestore(&data->data_lock, flags);
 695                         return -EBUSY;
 696                 }
 697
 698                 if (!strstr(data->dbgname, "isp")) {
 699                         if (!rockchip_iommu_reset(data->res_bases[i],
 700                              data->dbgname)) {
 701                                 spin_unlock_irqrestore(&data->data_lock, flags);
 702                                 return -ENOENT;
 703                         }
 704                 }
 705
 706                 rockchip_iommu_set_ptbase(data->res_bases[i], pgtable);
 707
 708                 __raw_writel(IOMMU_COMMAND_ZAP_CACHE, data->res_bases[i] +
 709                              IOMMU_REGISTER_COMMAND);
 710
 711                 __raw_writel(IOMMU_INTERRUPT_PAGE_FAULT |
 712                              IOMMU_INTERRUPT_READ_BUS_ERROR,
 713                              data->res_bases[i] + IOMMU_REGISTER_INT_MASK);
 714
 715                 ret = rockchip_iommu_enable_paging(data->res_bases[i]);
 716                 if (!ret) {
 717                         spin_unlock_irqrestore(&data->data_lock, flags);
 718                         dev_info(data->iommu, "(%s), %s failed\n",
 719                                  data->dbgname, __func__);
 720                         return -EBUSY;
 721                 }
 722
 723                 rockchip_iommu_disable_stall(data->res_bases[i]);
 724         }
 725
 726         data->pgtable = pgtable;
 727
 728         dev_info(data->iommu,"(%s) Enabled\n", data->dbgname);
 729
 730         spin_unlock_irqrestore(&data->data_lock, flags);
 731
 732         return 0;
 733 }
 734
 735 int rockchip_iommu_tlb_invalidate(struct device *dev)
 736 {
 737         unsigned long flags;
 738         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 739
 740         spin_lock_irqsave(&data->data_lock, flags);
 741
 742         if (rockchip_is_iommu_active(data)) {
 743                 int i;
 744                 int ret;
 745
 746                 for (i = 0; i < data->num_res_mem; i++) {
 747                         ret = rockchip_iommu_zap_tlb(data->res_bases[i]);
 748                         if (ret) {
 749                                 dev_err(dev->archdata.iommu, "(%s) %s failed\n",
 750                                         data->dbgname, __func__);
 751                                 spin_unlock_irqrestore(&data->data_lock, flags);
 752                                 return ret;
 753                         }
 754
 755                 }
 756         } else {
 757                 dev_dbg(dev->archdata.iommu, "(%s) Disabled. Skipping invalidating TLB.\n",
 758                         data->dbgname);
 759         }
 760
 761         spin_unlock_irqrestore(&data->data_lock, flags);
 762
 763         return 0;
 764 }
 765
 766 static phys_addr_t rockchip_iommu_iova_to_phys(struct iommu_domain *domain,
 767                                                dma_addr_t iova)
 768 {
 769         struct rk_iommu_domain *priv = domain->priv;
 770         unsigned long *entry;
 771         unsigned long flags;
 772         phys_addr_t phys = 0;
 773
 774         spin_lock_irqsave(&priv->pgtablelock, flags);
 775
 776         entry = rockchip_section_entry(priv->pgtable, iova);
 777         entry = rockchip_page_entry(entry, iova);
 778         phys = rockchip_spage_phys(entry) + rockchip_spage_offs(iova);
 779
 780         spin_unlock_irqrestore(&priv->pgtablelock, flags);
 781
 782         return phys;
 783 }
 784
 785 static int rockchip_lv2set_page(unsigned long *pent, phys_addr_t paddr,
 786                        size_t size, short *pgcnt)
 787 {
 788         if (!rockchip_lv2ent_fault(pent))
 789                 return -EADDRINUSE;
 790
 791         *pent = rockchip_mk_lv2ent_spage(paddr);
 792         rockchip_pgtable_flush(pent, pent + 1);
 793         *pgcnt -= 1;
 794         return 0;
 795 }
 796
 797 static unsigned long *rockchip_alloc_lv2entry(unsigned long *sent,
 798                                      unsigned long iova, short *pgcounter)
 799 {
 800         if (rockchip_lv1ent_fault(sent)) {
 801                 unsigned long *pent;
 802
 803                 pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
 804                 BUG_ON((unsigned long)pent & (LV2TABLE_SIZE - 1));
 805                 if (!pent)
 806                         return NULL;
 807
 808                 *sent = rockchip_mk_lv1ent_page(__pa(pent));
 809                 kmemleak_ignore(pent);
 810                 *pgcounter = NUM_LV2ENTRIES;
 811                 rockchip_pgtable_flush(pent, pent + NUM_LV2ENTRIES);
 812                 rockchip_pgtable_flush(sent, sent + 1);
 813         }
 814         return rockchip_page_entry(sent, iova);
 815 }
 816
 817 static size_t rockchip_iommu_unmap(struct iommu_domain *domain,
 818                                    unsigned long iova, size_t size)
 819 {
 820         struct rk_iommu_domain *priv = domain->priv;
 821         unsigned long flags;
 822         unsigned long *ent;
 823
 824         BUG_ON(priv->pgtable == NULL);
 825
 826         spin_lock_irqsave(&priv->pgtablelock, flags);
 827
 828         ent = rockchip_section_entry(priv->pgtable, iova);
 829
 830         if (unlikely(rockchip_lv1ent_fault(ent))) {
 831                 if (size > SPAGE_SIZE)
 832                         size = SPAGE_SIZE;
 833                 goto done;
 834         }
 835
 836         /* lv1ent_page(sent) == true here */
 837
 838         ent = rockchip_page_entry(ent, iova);
 839
 840         if (unlikely(rockchip_lv2ent_fault(ent))) {
 841                 size = SPAGE_SIZE;
 842                 goto done;
 843         }
 844
 845         *ent = 0;
 846         size = SPAGE_SIZE;
 847         priv->lv2entcnt[rockchip_lv1ent_offset(iova)] += 1;
 848         goto done;
 849
 850 done:
 851         #if 0
 852         pr_info("%s:unmap iova 0x%lx/0x%x bytes\n",
 853                   __func__, iova,size);
 854         #endif
 855         spin_unlock_irqrestore(&priv->pgtablelock, flags);
 856
 857         return size;
 858 }
 859
 860 static int rockchip_iommu_map(struct iommu_domain *domain, unsigned long iova,
 861                               phys_addr_t paddr, size_t size, int prot)
 862 {
 863         struct rk_iommu_domain *priv = domain->priv;
 864         unsigned long *entry;
 865         unsigned long flags;
 866         int ret = -ENOMEM;
 867         unsigned long *pent;
 868
 869         BUG_ON(priv->pgtable == NULL);
 870
 871         spin_lock_irqsave(&priv->pgtablelock, flags);
 872
 873         entry = rockchip_section_entry(priv->pgtable, iova);
 874
 875         pent = rockchip_alloc_lv2entry(entry, iova,
 876                               &priv->lv2entcnt[rockchip_lv1ent_offset(iova)]);
 877         if (!pent)
 878                 ret = -ENOMEM;
 879         else
 880                 ret = rockchip_lv2set_page(pent, paddr, size,
 881                                 &priv->lv2entcnt[rockchip_lv1ent_offset(iova)]);
 882
 883         if (ret) {
 884                 pr_info("%s: Failed to map iova 0x%lx/0x%x bytes\n", __func__,
 885                        iova, size);
 886         }
 887         spin_unlock_irqrestore(&priv->pgtablelock, flags);
 888
 889         return ret;
 890 }
 891
 892 static void rockchip_iommu_detach_device(struct iommu_domain *domain, struct device *dev)
 893 {
 894         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 895         struct rk_iommu_domain *priv = domain->priv;
 896         struct list_head *pos;
 897         unsigned long flags;
 898         bool found = false;
 899
 900         spin_lock_irqsave(&priv->lock, flags);
 901
 902         list_for_each(pos, &priv->clients) {
 903                 if (list_entry(pos, struct iommu_drvdata, node) == data) {
 904                         found = true;
 905                         break;
 906                 }
 907         }
 908
 909         if (!found) {
 910                 spin_unlock_irqrestore(&priv->lock, flags);
 911                 return;
 912         }
 913
 914         if (rockchip_iommu_disable(data)) {
 915                 dev_dbg(dev->archdata.iommu,"%s: Detached IOMMU with pgtable %#lx\n",
 916                         __func__, __pa(priv->pgtable));
 917                 data->domain = NULL;
 918                 list_del_init(&data->node);
 919
 920         } else
 921                 dev_err(dev->archdata.iommu,"%s: Detaching IOMMU with pgtable %#lx delayed",
 922                         __func__, __pa(priv->pgtable));
 923
 924         spin_unlock_irqrestore(&priv->lock, flags);
 925 }
 926
 927 static int rockchip_iommu_attach_device(struct iommu_domain *domain, struct device *dev)
 928 {
 929         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 930         struct rk_iommu_domain *priv = domain->priv;
 931         unsigned long flags;
 932         int ret;
 933
 934         spin_lock_irqsave(&priv->lock, flags);
 935
 936         ret = rockchip_iommu_enable(data, __pa(priv->pgtable));
 937
 938         if (ret == 0) {
 939                 /* 'data->node' must not be appeared in priv->clients */
 940                 BUG_ON(!list_empty(&data->node));
 941                 list_add_tail(&data->node, &priv->clients);
 942                 data->domain = domain;
 943         }
 944
 945         spin_unlock_irqrestore(&priv->lock, flags);
 946
 947         if (ret < 0) {
 948                 dev_err(dev->archdata.iommu,"%s: Failed to attach IOMMU with pgtable %#lx\n",
 949                        __func__, __pa(priv->pgtable));
 950         } else if (ret > 0) {
 951                 dev_dbg(dev->archdata.iommu,"%s: IOMMU with pgtable 0x%lx already attached\n",
 952                         __func__, __pa(priv->pgtable));
 953         } else {
 954                 dev_dbg(dev->archdata.iommu,"%s: Attached new IOMMU with pgtable 0x%lx\n",
 955                         __func__, __pa(priv->pgtable));
 956         }
 957
 958         return ret;
 959 }
 960
 961 static void rockchip_iommu_domain_destroy(struct iommu_domain *domain)
 962 {
 963         struct rk_iommu_domain *priv = domain->priv;
 964         int i;
 965
 966         WARN_ON(!list_empty(&priv->clients));
 967
 968         for (i = 0; i < NUM_LV1ENTRIES; i++)
 969                 if (rockchip_lv1ent_page(priv->pgtable + i))
 970                         kmem_cache_free(lv2table_kmem_cache,
 971                                         __va(rockchip_lv2table_base(priv->pgtable + i)));
 972
 973         free_pages((unsigned long)priv->pgtable, 0);
 974         free_pages((unsigned long)priv->lv2entcnt, 0);
 975         kfree(domain->priv);
 976         domain->priv = NULL;
 977 }
 978
 979 static int rockchip_iommu_domain_init(struct iommu_domain *domain)
 980 {
 981         struct rk_iommu_domain *priv;
 982
 983         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 984         if (!priv)
 985                 return -ENOMEM;
 986
 987 /*rk32xx iommu use 2 level pagetable,
 988    level1 and leve2 both have 1024 entries,each entry  occupy 4 bytes,
 989    so alloc a page size for each page table
 990 */
 991         priv->pgtable = (unsigned long *)__get_free_pages(GFP_KERNEL |
 992                                                           __GFP_ZERO, 0);
 993         if (!priv->pgtable)
 994                 goto err_pgtable;
 995
 996         priv->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL |
 997                                                     __GFP_ZERO, 0);
 998         if (!priv->lv2entcnt)
 999                 goto err_counter;
1000
1001         rockchip_pgtable_flush(priv->pgtable, priv->pgtable + NUM_LV1ENTRIES);
1002
1003         spin_lock_init(&priv->lock);
1004         spin_lock_init(&priv->pgtablelock);
1005         INIT_LIST_HEAD(&priv->clients);
1006
1007         domain->priv = priv;
1008         return 0;
1009
1010 err_counter:
1011         free_pages((unsigned long)priv->pgtable, 0);
1012 err_pgtable:
1013         kfree(priv);
1014         return -ENOMEM;
1015 }
1016
1017 static struct iommu_ops rk_iommu_ops = {
1018         .domain_init = &rockchip_iommu_domain_init,
1019         .domain_destroy = &rockchip_iommu_domain_destroy,
1020         .attach_dev = &rockchip_iommu_attach_device,
1021         .detach_dev = &rockchip_iommu_detach_device,
1022         .map = &rockchip_iommu_map,
1023         .unmap = &rockchip_iommu_unmap,
1024         .iova_to_phys = &rockchip_iommu_iova_to_phys,
1025         .pgsize_bitmap = SPAGE_SIZE,
1026 };
1027
1028 static int  rockchip_get_iommu_resource_num(struct platform_device *pdev,
1029                                              unsigned int type)
1030 {
1031         int num = 0;
1032         int i;
1033
1034         for (i = 0; i < pdev->num_resources; i++) {
1035                 struct resource *r = &pdev->resource[i];
1036                 if (type == resource_type(r))
1037                         num++;
1038         }
1039
1040         return num;
1041 }
1042
1043 static int rockchip_iommu_probe(struct platform_device *pdev)
1044 {
1045         int i, ret;
1046         struct device *dev;
1047         struct iommu_drvdata *data;
1048
1049         dev = &pdev->dev;
1050
1051         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
1052         if (!data) {
1053                 dev_dbg(dev, "Not enough memory\n");
1054                 return -ENOMEM;
1055         }
1056
1057         dev_set_drvdata(dev, data);
1058
1059         if (pdev->dev.of_node)
1060                 of_property_read_string(pdev->dev.of_node, "dbgname",
1061                                         &(data->dbgname));
1062         else
1063                 dev_dbg(dev, "dbgname not assigned in device tree or device node not exist\r\n");
1064
1065         dev_info(dev,"(%s) Enter\n", data->dbgname);
1066
1067         data->num_res_mem = rockchip_get_iommu_resource_num(pdev,
1068                                 IORESOURCE_MEM);
1069         if (0 == data->num_res_mem) {
1070                 dev_err(dev,"can't find iommu memory resource \r\n");
1071                 return -ENOMEM;
1072         }
1073         dev_dbg(dev,"data->num_res_mem=%d\n", data->num_res_mem);
1074
1075         data->num_res_irq = rockchip_get_iommu_resource_num(pdev,
1076                                 IORESOURCE_IRQ);
1077         if (0 == data->num_res_irq) {
1078                 dev_err(dev,"can't find iommu irq resource \r\n");
1079                 return -ENOMEM;
1080         }
1081         dev_dbg(dev,"data->num_res_irq=%d\n", data->num_res_irq);
1082
1083         data->res_bases = devm_kmalloc_array(dev, data->num_res_mem,
1084                                 sizeof(*data->res_bases), GFP_KERNEL);
1085         if (data->res_bases == NULL) {
1086                 dev_err(dev, "Not enough memory\n");
1087                 return -ENOMEM;
1088         }
1089
1090         for (i = 0; i < data->num_res_mem; i++) {
1091                 struct resource *res;
1092
1093                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1094                 if (!res) {
1095                         dev_err(dev,"Unable to find IOMEM region\n");
1096                         return -ENOENT;
1097                 }
1098
1099                 data->res_bases[i] = devm_ioremap(dev,res->start,
1100                                                   resource_size(res));
1101                 if (!data->res_bases[i]) {
1102                         dev_err(dev, "Unable to map IOMEM @ PA:%#x\n",
1103                                 res->start);
1104                         return -ENOMEM;
1105                 }
1106
1107                 dev_dbg(dev,"res->start = 0x%08x ioremap to data->res_bases[%d] = 0x%08x\n",
1108                         res->start, i, (unsigned int)data->res_bases[i]);
1109
1110                 if (strstr(data->dbgname, "vop") && cpu_is_rk312x()) {
1111                         rk312x_vop_mmu_base = data->res_bases[0];
1112                         dev_dbg(dev, "rk312x_vop_mmu_base = 0x%08x\n",
1113                                 (unsigned int)rk312x_vop_mmu_base);
1114                 }
1115         }
1116
1117         for (i = 0; i < data->num_res_irq; i++) {
1118                 if (cpu_is_rk312x() && strstr(data->dbgname, "vop")) {
1119                         dev_info(dev, "skip request vop mmu irq\n");
1120                         continue;
1121                 }
1122
1123                 ret = platform_get_irq(pdev, i);
1124                 if (ret <= 0) {
1125                         dev_err(dev,"Unable to find IRQ resource\n");
1126                         return -ENOENT;
1127                 }
1128
1129                 ret = devm_request_irq(dev, ret, rockchip_iommu_irq,
1130                                   IRQF_SHARED, dev_name(dev), data);
1131                 if (ret) {
1132                         dev_err(dev, "Unabled to register interrupt handler\n");
1133                         return -ENOENT;
1134                 }
1135         }
1136
1137         ret = rockchip_init_iovmm(dev, &data->vmm);
1138         if (ret)
1139                 return ret;
1140
1141         data->iommu = dev;
1142         spin_lock_init(&data->data_lock);
1143         INIT_LIST_HEAD(&data->node);
1144
1145         dev_info(dev,"(%s) Initialized\n", data->dbgname);
1146
1147         return 0;
1148 }
1149
1150 #ifdef CONFIG_OF
1151 static const struct of_device_id iommu_dt_ids[] = {
1152         { .compatible = IEP_IOMMU_COMPATIBLE_NAME},
1153         { .compatible = VIP_IOMMU_COMPATIBLE_NAME},
1154         { .compatible = VOPB_IOMMU_COMPATIBLE_NAME},
1155         { .compatible = VOPL_IOMMU_COMPATIBLE_NAME},
1156         { .compatible = HEVC_IOMMU_COMPATIBLE_NAME},
1157         { .compatible = VPU_IOMMU_COMPATIBLE_NAME},
1158         { .compatible = ISP_IOMMU_COMPATIBLE_NAME},
1159         { .compatible = VOP_IOMMU_COMPATIBLE_NAME},
1160         { /* end */ }
1161 };
1162
1163 MODULE_DEVICE_TABLE(of, iommu_dt_ids);
1164 #endif
1165
1166 static struct platform_driver rk_iommu_driver = {
1167         .probe = rockchip_iommu_probe,
1168         .remove = NULL,
1169         .driver = {
1170                    .name = "rk_iommu",
1171                    .owner = THIS_MODULE,
1172                    .of_match_table = of_match_ptr(iommu_dt_ids),
1173         },
1174 };
1175
1176 static int __init rockchip_iommu_init_driver(void)
1177 {
1178         int ret;
1179
1180         lv2table_kmem_cache = kmem_cache_create("rk-iommu-lv2table",
1181                                                 LV2TABLE_SIZE, LV2TABLE_SIZE,
1182                                                 0, NULL);
1183         if (!lv2table_kmem_cache) {
1184                 pr_info("%s: failed to create kmem cache\n", __func__);
1185                 return -ENOMEM;
1186         }
1187
1188         ret = bus_set_iommu(&platform_bus_type, &rk_iommu_ops);
1189         if (ret)
1190                 return ret;
1191
1192         return platform_driver_register(&rk_iommu_driver);
1193 }
1194
1195 core_initcall(rockchip_iommu_init_driver);