drivers/iommu/rockchip-iommu.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License version 2 as
   4  * published by the Free Software Foundation.
   5  */
   6
   7 #ifdef CONFIG_ROCKCHIP_IOMMU_DEBUG
   8 #define DEBUG
   9 #endif
  10
  11 #include <linux/io.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/slab.h>
  14 #include <linux/clk.h>
  15 #include <linux/err.h>
  16 #include <linux/mm.h>
  17 #include <linux/errno.h>
  18 #include <linux/memblock.h>
  19 #include <linux/export.h>
  20 #include <linux/module.h>
  21
  22 #include <asm/cacheflush.h>
  23 #include <asm/pgtable.h>
  24 #include <linux/of.h>
  25 #include <linux/rockchip-iovmm.h>
  26 #include <linux/rockchip/grf.h>
  27 #include <linux/rockchip/cpu.h>
  28 #include <linux/rockchip/iomap.h>
  29 #include <linux/device.h>
  30 #include "rockchip-iommu.h"
  31
  32 /* We does not consider super section mapping (16MB) */
  33 #define SPAGE_ORDER 12
  34 #define SPAGE_SIZE (1 << SPAGE_ORDER)
  35 #define SPAGE_MASK (~(SPAGE_SIZE - 1))
  36
  37 static void __iomem *rk312x_vop_mmu_base;
  38
  39 enum iommu_entry_flags {
  40         IOMMU_FLAGS_PRESENT = 0x01,
  41         IOMMU_FLAGS_READ_PERMISSION = 0x02,
  42         IOMMU_FLAGS_WRITE_PERMISSION = 0x04,
  43         IOMMU_FLAGS_OVERRIDE_CACHE = 0x8,
  44         IOMMU_FLAGS_WRITE_CACHEABLE = 0x10,
  45         IOMMU_FLAGS_WRITE_ALLOCATE = 0x20,
  46         IOMMU_FLAGS_WRITE_BUFFERABLE = 0x40,
  47         IOMMU_FLAGS_READ_CACHEABLE = 0x80,
  48         IOMMU_FLAGS_READ_ALLOCATE = 0x100,
  49         IOMMU_FLAGS_MASK = 0x1FF,
  50 };
  51
  52 #define rockchip_lv1ent_fault(sent) ((*(sent) & IOMMU_FLAGS_PRESENT) == 0)
  53 #define rockchip_lv1ent_page(sent) ((*(sent) & IOMMU_FLAGS_PRESENT) == 1)
  54 #define rockchip_lv2ent_fault(pent) ((*(pent) & IOMMU_FLAGS_PRESENT) == 0)
  55 #define rockchip_spage_phys(pent) (*(pent) & SPAGE_MASK)
  56 #define rockchip_spage_offs(iova) ((iova) & 0x0FFF)
  57
  58 #define rockchip_lv1ent_offset(iova) (((iova)>>22) & 0x03FF)
  59 #define rockchip_lv2ent_offset(iova) (((iova)>>12) & 0x03FF)
  60
  61 #define NUM_LV1ENTRIES 1024
  62 #define NUM_LV2ENTRIES 1024
  63
  64 #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(long))
  65
  66 #define rockchip_lv2table_base(sent) (*(sent) & 0xFFFFFFFE)
  67
  68 #define rockchip_mk_lv1ent_page(pa) ((pa) | IOMMU_FLAGS_PRESENT)
  69 /*write and read permission for level2 page default*/
  70 #define rockchip_mk_lv2ent_spage(pa) ((pa) | IOMMU_FLAGS_PRESENT | \
  71                              IOMMU_FLAGS_READ_PERMISSION | \
  72                              IOMMU_FLAGS_WRITE_PERMISSION)
  73
  74 #define IOMMU_REG_POLL_COUNT_FAST 1000
  75
  76 /**
  77  * MMU register numbers
  78  * Used in the register read/write routines.
  79  * See the hardware documentation for more information about each register
  80  */
  81 enum iommu_register {
  82         /**< Current Page Directory Pointer */
  83         IOMMU_REGISTER_DTE_ADDR = 0x0000,
  84         /**< Status of the MMU */
  85         IOMMU_REGISTER_STATUS = 0x0004,
  86         /**< Command register, used to control the MMU */
  87         IOMMU_REGISTER_COMMAND = 0x0008,
  88         /**< Logical address of the last page fault */
  89         IOMMU_REGISTER_PAGE_FAULT_ADDR = 0x000C,
  90         /**< Used to invalidate the mapping of a single page from the MMU */
  91         IOMMU_REGISTER_ZAP_ONE_LINE = 0x010,
  92         /**< Raw interrupt status, all interrupts visible */
  93         IOMMU_REGISTER_INT_RAWSTAT = 0x0014,
  94         /**< Indicate to the MMU that the interrupt has been received */
  95         IOMMU_REGISTER_INT_CLEAR = 0x0018,
  96         /**< Enable/disable types of interrupts */
  97         IOMMU_REGISTER_INT_MASK = 0x001C,
  98         /**< Interrupt status based on the mask */
  99         IOMMU_REGISTER_INT_STATUS = 0x0020,
 100         IOMMU_REGISTER_AUTO_GATING = 0x0024
 101 };
 102
 103 enum iommu_command {
 104         /**< Enable paging (memory translation) */
 105         IOMMU_COMMAND_ENABLE_PAGING = 0x00,
 106         /**< Disable paging (memory translation) */
 107         IOMMU_COMMAND_DISABLE_PAGING = 0x01,
 108         /**<  Enable stall on page fault */
 109         IOMMU_COMMAND_ENABLE_STALL = 0x02,
 110         /**< Disable stall on page fault */
 111         IOMMU_COMMAND_DISABLE_STALL = 0x03,
 112         /**< Zap the entire page table cache */
 113         IOMMU_COMMAND_ZAP_CACHE = 0x04,
 114         /**< Page fault processed */
 115         IOMMU_COMMAND_PAGE_FAULT_DONE = 0x05,
 116         /**< Reset the MMU back to power-on settings */
 117         IOMMU_COMMAND_HARD_RESET = 0x06
 118 };
 119
 120 /**
 121  * MMU interrupt register bits
 122  * Each cause of the interrupt is reported
 123  * through the (raw) interrupt status registers.
 124  * Multiple interrupts can be pending, so multiple bits
 125  * can be set at once.
 126  */
 127 enum iommu_interrupt {
 128         IOMMU_INTERRUPT_PAGE_FAULT = 0x01, /**< A page fault occured */
 129         IOMMU_INTERRUPT_READ_BUS_ERROR = 0x02 /**< A bus read error occured */
 130 };
 131
 132 enum iommu_status_bits {
 133         IOMMU_STATUS_BIT_PAGING_ENABLED      = 1 << 0,
 134         IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE   = 1 << 1,
 135         IOMMU_STATUS_BIT_STALL_ACTIVE        = 1 << 2,
 136         IOMMU_STATUS_BIT_IDLE                = 1 << 3,
 137         IOMMU_STATUS_BIT_REPLAY_BUFFER_EMPTY = 1 << 4,
 138         IOMMU_STATUS_BIT_PAGE_FAULT_IS_WRITE = 1 << 5,
 139         IOMMU_STATUS_BIT_STALL_NOT_ACTIVE    = 1 << 31,
 140 };
 141
 142 /**
 143  * Size of an MMU page in bytes
 144  */
 145 #define IOMMU_PAGE_SIZE 0x1000
 146
 147 /*
 148  * Size of the address space referenced by a page table page
 149  */
 150 #define IOMMU_VIRTUAL_PAGE_SIZE 0x400000 /* 4 MiB */
 151
 152 /**
 153  * Page directory index from address
 154  * Calculates the page directory index from the given address
 155  */
 156 #define IOMMU_PDE_ENTRY(address) (((address)>>22) & 0x03FF)
 157
 158 /**
 159  * Page table index from address
 160  * Calculates the page table index from the given address
 161  */
 162 #define IOMMU_PTE_ENTRY(address) (((address)>>12) & 0x03FF)
 163
 164 /**
 165  * Extract the memory address from an PDE/PTE entry
 166  */
 167 #define IOMMU_ENTRY_ADDRESS(value) ((value) & 0xFFFFFC00)
 168
 169 #define INVALID_PAGE ((u32)(~0))
 170
 171 static struct kmem_cache *lv2table_kmem_cache;
 172
 173 static unsigned int *rockchip_section_entry(unsigned int *pgtable, unsigned long iova)
 174 {
 175         return pgtable + rockchip_lv1ent_offset(iova);
 176 }
 177
 178 static unsigned int *rockchip_page_entry(unsigned int *sent, unsigned long iova)
 179 {
 180         return (unsigned int *)phys_to_virt(rockchip_lv2table_base(sent)) +
 181                 rockchip_lv2ent_offset(iova);
 182 }
 183
 184 struct rk_iommu_domain {
 185         struct list_head clients; /* list of iommu_drvdata.node */
 186         unsigned int *pgtable; /* lv1 page table, 4KB */
 187         short *lv2entcnt; /* free lv2 entry counter for each section */
 188         spinlock_t lock; /* lock for this structure */
 189         spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
 190 };
 191
 192 static bool rockchip_set_iommu_active(struct iommu_drvdata *data)
 193 {
 194         /* return true if the IOMMU was not active previously
 195            and it needs to be initialized */
 196         return ++data->activations == 1;
 197 }
 198
 199 static bool rockchip_set_iommu_inactive(struct iommu_drvdata *data)
 200 {
 201         /* return true if the IOMMU is needed to be disabled */
 202         BUG_ON(data->activations < 1);
 203         return --data->activations == 0;
 204 }
 205
 206 static bool rockchip_is_iommu_active(struct iommu_drvdata *data)
 207 {
 208         return data->activations > 0;
 209 }
 210
 211 static void rockchip_iommu_disable_stall(void __iomem *base)
 212 {
 213         int i;
 214         u32 mmu_status;
 215
 216         if (base != rk312x_vop_mmu_base) {
 217                 mmu_status = __raw_readl(base + IOMMU_REGISTER_STATUS);
 218         } else {
 219                 goto skip_vop_mmu_disable;
 220         }
 221
 222         if (0 == (mmu_status & IOMMU_STATUS_BIT_PAGING_ENABLED)) {
 223                 return;
 224         }
 225
 226         if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE) {
 227                 pr_info("Aborting MMU disable stall request since it is in pagefault state.\n");
 228                 return;
 229         }
 230
 231         if (!(mmu_status & IOMMU_STATUS_BIT_STALL_ACTIVE)) {
 232                 return;
 233         }
 234
 235         __raw_writel(IOMMU_COMMAND_DISABLE_STALL, base + IOMMU_REGISTER_COMMAND);
 236
 237         skip_vop_mmu_disable:
 238
 239         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 240                 u32 status;
 241
 242                 if (base != rk312x_vop_mmu_base) {
 243                         status = __raw_readl(base + IOMMU_REGISTER_STATUS);
 244                 } else {
 245                         int j;
 246                         while (j < 5)
 247                                 j++;
 248                         return;
 249                 }
 250
 251                 if (0 == (status & IOMMU_STATUS_BIT_STALL_ACTIVE))
 252                         break;
 253
 254                 if (status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE)
 255                         break;
 256
 257                 if (0 == (mmu_status & IOMMU_STATUS_BIT_PAGING_ENABLED))
 258                         break;
 259         }
 260
 261         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 262                 pr_info("Disable stall request failed, MMU status is 0x%08X\n",
 263                       __raw_readl(base + IOMMU_REGISTER_STATUS));
 264         }
 265 }
 266
 267 static bool rockchip_iommu_enable_stall(void __iomem *base)
 268 {
 269         int i;
 270
 271         u32 mmu_status;
 272
 273         if (base != rk312x_vop_mmu_base) {
 274                 mmu_status = __raw_readl(base + IOMMU_REGISTER_STATUS);
 275         } else {
 276                 goto skip_vop_mmu_enable;
 277         }
 278
 279         if (0 == (mmu_status & IOMMU_STATUS_BIT_PAGING_ENABLED)) {
 280                 return true;
 281         }
 282
 283         if (mmu_status & IOMMU_STATUS_BIT_STALL_ACTIVE){
 284                 pr_info("MMU stall already enabled\n");
 285                 return true;
 286         }
 287
 288         if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE) {
 289                 pr_info("Aborting MMU stall request since it is in pagefault state. mmu status is 0x%08x\n",
 290                         mmu_status);
 291                 return false;
 292         }
 293
 294         __raw_writel(IOMMU_COMMAND_ENABLE_STALL, base + IOMMU_REGISTER_COMMAND);
 295
 296         skip_vop_mmu_enable:
 297
 298         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 299                 if (base != rk312x_vop_mmu_base) {
 300                         mmu_status = __raw_readl(base + IOMMU_REGISTER_STATUS);
 301                 } else {
 302                         int j;
 303                         while (j < 5)
 304                                 j++;
 305                         return true;
 306                 }
 307
 308                 if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE)
 309                         break;
 310
 311                 if ((mmu_status & IOMMU_STATUS_BIT_STALL_ACTIVE) &&
 312                     (0 == (mmu_status & IOMMU_STATUS_BIT_STALL_NOT_ACTIVE)))
 313                         break;
 314
 315                 if (0 == (mmu_status & (IOMMU_STATUS_BIT_PAGING_ENABLED)))
 316                         break;
 317         }
 318
 319         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 320                 pr_info("Enable stall request failed, MMU status is 0x%08X\n",
 321                        __raw_readl(base + IOMMU_REGISTER_STATUS));
 322                 return false;
 323         }
 324
 325         if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE) {
 326                 pr_info("Aborting MMU stall request since it has a pagefault.\n");
 327                 return false;
 328         }
 329
 330         return true;
 331 }
 332
 333 static bool rockchip_iommu_enable_paging(void __iomem *base)
 334 {
 335         int i;
 336
 337         __raw_writel(IOMMU_COMMAND_ENABLE_PAGING,
 338                      base + IOMMU_REGISTER_COMMAND);
 339
 340         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 341                 if (base != rk312x_vop_mmu_base) {
 342                         if (__raw_readl(base + IOMMU_REGISTER_STATUS) &
 343                                 IOMMU_STATUS_BIT_PAGING_ENABLED)
 344                         break;
 345                 } else {
 346                         int j;
 347                         while (j < 5)
 348                                 j++;
 349                         return true;
 350                 }
 351         }
 352
 353         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 354                 pr_info("Enable paging request failed, MMU status is 0x%08X\n",
 355                        __raw_readl(base + IOMMU_REGISTER_STATUS));
 356                 return false;
 357         }
 358
 359         return true;
 360 }
 361
 362 static bool rockchip_iommu_disable_paging(void __iomem *base)
 363 {
 364         int i;
 365
 366         __raw_writel(IOMMU_COMMAND_DISABLE_PAGING,
 367                      base + IOMMU_REGISTER_COMMAND);
 368
 369         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 370                 if (base != rk312x_vop_mmu_base) {
 371                         if (!(__raw_readl(base + IOMMU_REGISTER_STATUS) &
 372                                   IOMMU_STATUS_BIT_PAGING_ENABLED))
 373                                 break;
 374                 } else {
 375                         int j;
 376                         while (j < 5)
 377                                 j++;
 378                         return true;
 379                 }
 380         }
 381
 382         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 383                 pr_info("Disable paging request failed, MMU status is 0x%08X\n",
 384                        __raw_readl(base + IOMMU_REGISTER_STATUS));
 385                 return false;
 386         }
 387
 388         return true;
 389 }
 390
 391 static void rockchip_iommu_page_fault_done(void __iomem *base, const char *dbgname)
 392 {
 393         pr_info("MMU: %s: Leaving page fault mode\n",
 394                 dbgname);
 395         __raw_writel(IOMMU_COMMAND_PAGE_FAULT_DONE,
 396                      base + IOMMU_REGISTER_COMMAND);
 397 }
 398
 399 static int rockchip_iommu_zap_tlb_without_stall (void __iomem *base)
 400 {
 401         __raw_writel(IOMMU_COMMAND_ZAP_CACHE, base + IOMMU_REGISTER_COMMAND);
 402
 403         return 0;
 404 }
 405
 406 static int rockchip_iommu_zap_tlb(void __iomem *base)
 407 {
 408         if (!rockchip_iommu_enable_stall(base)) {
 409                 pr_err("%s failed\n", __func__);
 410                 return -1;
 411         }
 412
 413         __raw_writel(IOMMU_COMMAND_ZAP_CACHE, base + IOMMU_REGISTER_COMMAND);
 414
 415         rockchip_iommu_disable_stall(base);
 416
 417         return 0;
 418 }
 419
 420 static inline bool rockchip_iommu_raw_reset(void __iomem *base)
 421 {
 422         int i;
 423         unsigned int ret;
 424         unsigned int grf_value;
 425
 426         __raw_writel(0xCAFEBABE, base + IOMMU_REGISTER_DTE_ADDR);
 427
 428         if (base != rk312x_vop_mmu_base) {
 429                 ret = __raw_readl(base + IOMMU_REGISTER_DTE_ADDR);
 430                 if (!(0xCAFEB000 == ret)) {
 431                         grf_value = readl_relaxed(RK_GRF_VIRT + RK3036_GRF_SOC_CON1);
 432                         pr_info("error when %s. grf = 0x%08x\n", __func__, grf_value);
 433                         return false;
 434                 }
 435         }
 436         __raw_writel(IOMMU_COMMAND_HARD_RESET,
 437                      base + IOMMU_REGISTER_COMMAND);
 438
 439         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 440                 if (base != rk312x_vop_mmu_base) {
 441                         if (__raw_readl(base + IOMMU_REGISTER_DTE_ADDR) == 0)
 442                                 break;
 443                 } else {
 444                         int j;
 445                         while (j < 5)
 446                                 j++;
 447                         return true;
 448                 }
 449         }
 450
 451         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 452                 pr_info("%s,Reset request failed, MMU status is 0x%08X\n",
 453                        __func__, __raw_readl(base + IOMMU_REGISTER_DTE_ADDR));
 454                 return false;
 455         }
 456         return true;
 457 }
 458
 459 static void rockchip_iommu_set_ptbase(void __iomem *base, unsigned int pgd)
 460 {
 461         __raw_writel(pgd, base + IOMMU_REGISTER_DTE_ADDR);
 462 }
 463
 464 static bool rockchip_iommu_reset(void __iomem *base, const char *dbgname)
 465 {
 466         bool ret = true;
 467
 468         ret = rockchip_iommu_raw_reset(base);
 469         if (!ret) {
 470                 pr_info("(%s), %s failed\n", dbgname, __func__);
 471                 return ret;
 472         }
 473
 474         if (base != rk312x_vop_mmu_base)
 475                 __raw_writel(IOMMU_INTERRUPT_PAGE_FAULT |
 476                              IOMMU_INTERRUPT_READ_BUS_ERROR,
 477                              base + IOMMU_REGISTER_INT_MASK);
 478         else
 479                 __raw_writel(0x00, base + IOMMU_REGISTER_INT_MASK);
 480
 481         return ret;
 482 }
 483
 484 static inline void rockchip_pgtable_flush(void *vastart, void *vaend)
 485 {
 486 #ifdef CONFIG_ARM
 487         dmac_flush_range(vastart, vaend);
 488         outer_flush_range(virt_to_phys(vastart), virt_to_phys(vaend));
 489 #elif defined(CONFIG_ARM64)
 490         __dma_flush_range(vastart, vaend);
 491         //flush_cache_all();
 492 #endif
 493 }
 494
 495 static void dump_pagetbl(dma_addr_t fault_address, u32 addr_dte)
 496 {
 497         u32 dte_index, pte_index, page_offset;
 498         u32 mmu_dte_addr;
 499         phys_addr_t mmu_dte_addr_phys, dte_addr_phys;
 500         u32 *dte_addr;
 501         u32 dte;
 502         phys_addr_t pte_addr_phys = 0;
 503         u32 *pte_addr = NULL;
 504         u32 pte = 0;
 505         phys_addr_t page_addr_phys = 0;
 506         u32 page_flags = 0;
 507
 508         dte_index = rockchip_lv1ent_offset(fault_address);
 509         pte_index = rockchip_lv2ent_offset(fault_address);
 510         page_offset = (u32)(fault_address & 0x00000fff);
 511
 512         mmu_dte_addr = addr_dte;
 513         mmu_dte_addr_phys = (phys_addr_t)mmu_dte_addr;
 514
 515         dte_addr_phys = mmu_dte_addr_phys + (4 * dte_index);
 516         dte_addr = phys_to_virt(dte_addr_phys);
 517         dte = *dte_addr;
 518
 519         if (!(IOMMU_FLAGS_PRESENT & dte))
 520                 goto print_it;
 521
 522         pte_addr_phys = ((phys_addr_t)dte & 0xfffff000) + (pte_index * 4);
 523         pte_addr = phys_to_virt(pte_addr_phys);
 524         pte = *pte_addr;
 525
 526         if (!(IOMMU_FLAGS_PRESENT & pte))
 527                 goto print_it;
 528
 529         page_addr_phys = ((phys_addr_t)pte & 0xfffff000) + page_offset;
 530         page_flags = pte & 0x000001fe;
 531
 532 print_it:
 533         pr_err("iova = %pad: dte_index: 0x%03x pte_index: 0x%03x page_offset: 0x%03x\n",
 534                 &fault_address, dte_index, pte_index, page_offset);
 535         pr_err("mmu_dte_addr: %pa dte@%pa: %#08x valid: %u pte@%pa: %#08x valid: %u page@%pa flags: %#03x\n",
 536                 &mmu_dte_addr_phys, &dte_addr_phys, dte,
 537                 (dte & IOMMU_FLAGS_PRESENT), &pte_addr_phys, pte,
 538                 (pte & IOMMU_FLAGS_PRESENT), &page_addr_phys, page_flags);
 539 }
 540
 541 static irqreturn_t rockchip_iommu_irq(int irq, void *dev_id)
 542 {
 543         /* SYSMMU is in blocked when interrupt occurred. */
 544         struct iommu_drvdata *data = dev_id;
 545         u32 status;
 546         u32 rawstat;
 547         dma_addr_t fault_address;
 548         int i;
 549         unsigned long flags;
 550         int ret;
 551         u32 reg_status;
 552
 553         spin_lock_irqsave(&data->data_lock, flags);
 554
 555         if (!rockchip_is_iommu_active(data)) {
 556                 spin_unlock_irqrestore(&data->data_lock, flags);
 557                 return IRQ_HANDLED;
 558         }
 559
 560         for (i = 0; i < data->num_res_mem; i++) {
 561                 status = __raw_readl(data->res_bases[i] +
 562                                      IOMMU_REGISTER_INT_STATUS);
 563                 if (status == 0)
 564                         continue;
 565
 566                 rawstat = __raw_readl(data->res_bases[i] +
 567                                       IOMMU_REGISTER_INT_RAWSTAT);
 568
 569                 reg_status = __raw_readl(data->res_bases[i] +
 570                                          IOMMU_REGISTER_STATUS);
 571
 572                 dev_info(data->iommu, "1.rawstat = 0x%08x,status = 0x%08x,reg_status = 0x%08x\n",
 573                          rawstat, status, reg_status);
 574
 575                 if (rawstat & IOMMU_INTERRUPT_PAGE_FAULT) {
 576                         u32 dte;
 577                         int flags;
 578
 579                         fault_address = __raw_readl(data->res_bases[i] +
 580                                             IOMMU_REGISTER_PAGE_FAULT_ADDR);
 581
 582                         dte = __raw_readl(data->res_bases[i] +
 583                                           IOMMU_REGISTER_DTE_ADDR);
 584
 585                         flags = (status & 32) ? 1 : 0;
 586
 587                         dev_err(data->iommu, "Page fault detected at %pad from bus id %d of type %s on %s\n",
 588                                 &fault_address, (status >> 6) & 0x1F,
 589                                 (flags == 1) ? "write" : "read", data->dbgname);
 590
 591                         dump_pagetbl(fault_address, dte);
 592
 593                         if (data->domain)
 594                                 report_iommu_fault(data->domain, data->iommu,
 595                                                    fault_address, flags);
 596                         if (data->fault_handler)
 597                                 data->fault_handler(data->iommu, IOMMU_PAGEFAULT, dte, fault_address, 1);
 598
 599                         rockchip_iommu_page_fault_done(data->res_bases[i],
 600                                                        data->dbgname);
 601                 }
 602
 603                 if (rawstat & IOMMU_INTERRUPT_READ_BUS_ERROR) {
 604                         dev_err(data->iommu, "bus error occured at %pad\n",
 605                                 &fault_address);
 606                 }
 607
 608                 if (rawstat & ~(IOMMU_INTERRUPT_READ_BUS_ERROR |
 609                     IOMMU_INTERRUPT_PAGE_FAULT)) {
 610                         dev_err(data->iommu, "unexpected int_status: %#08x\n\n",
 611                                 rawstat);
 612                 }
 613
 614                 __raw_writel(rawstat, data->res_bases[i] +
 615                              IOMMU_REGISTER_INT_CLEAR);
 616
 617                 status = __raw_readl(data->res_bases[i] +
 618                                      IOMMU_REGISTER_INT_STATUS);
 619
 620                 rawstat = __raw_readl(data->res_bases[i] +
 621                                       IOMMU_REGISTER_INT_RAWSTAT);
 622
 623                 reg_status = __raw_readl(data->res_bases[i] +
 624                                          IOMMU_REGISTER_STATUS);
 625
 626                 dev_info(data->iommu, "2.rawstat = 0x%08x,status = 0x%08x,reg_status = 0x%08x\n",
 627                          rawstat, status, reg_status);
 628
 629                 ret = rockchip_iommu_zap_tlb_without_stall(data->res_bases[i]);
 630                 if (ret)
 631                         dev_err(data->iommu, "(%s) %s failed\n", data->dbgname,
 632                                 __func__);
 633         }
 634
 635         spin_unlock_irqrestore(&data->data_lock, flags);
 636         return IRQ_HANDLED;
 637 }
 638
 639 static bool rockchip_iommu_disable(struct iommu_drvdata *data)
 640 {
 641         unsigned long flags;
 642         int i;
 643         bool ret = false;
 644
 645         spin_lock_irqsave(&data->data_lock, flags);
 646
 647         if (!rockchip_set_iommu_inactive(data)) {
 648                 spin_unlock_irqrestore(&data->data_lock, flags);
 649                 dev_info(data->iommu,"(%s) %d times left to be disabled\n",
 650                          data->dbgname, data->activations);
 651                 return ret;
 652         }
 653
 654         for (i = 0; i < data->num_res_mem; i++) {
 655                 ret = rockchip_iommu_enable_stall(data->res_bases[i]);
 656                 if (!ret) {
 657                         dev_info(data->iommu, "(%s), %s failed\n",
 658                                  data->dbgname, __func__);
 659                         spin_unlock_irqrestore(&data->data_lock, flags);
 660                         return false;
 661                 }
 662
 663                 __raw_writel(0, data->res_bases[i] + IOMMU_REGISTER_INT_MASK);
 664
 665                 ret = rockchip_iommu_disable_paging(data->res_bases[i]);
 666                 if (!ret) {
 667                         rockchip_iommu_disable_stall(data->res_bases[i]);
 668                         spin_unlock_irqrestore(&data->data_lock, flags);
 669                         dev_info(data->iommu, "%s error\n", __func__);
 670                         return ret;
 671                 }
 672                 rockchip_iommu_disable_stall(data->res_bases[i]);
 673         }
 674
 675         data->pgtable = 0;
 676
 677         spin_unlock_irqrestore(&data->data_lock, flags);
 678
 679         dev_dbg(data->iommu,"(%s) Disabled\n", data->dbgname);
 680
 681         return ret;
 682 }
 683
 684 /* __rk_sysmmu_enable: Enables System MMU
 685  *
 686  * returns -error if an error occurred and System MMU is not enabled,
 687  * 0 if the System MMU has been just enabled and 1 if System MMU was already
 688  * enabled before.
 689  */
 690 static int rockchip_iommu_enable(struct iommu_drvdata *data, unsigned int pgtable)
 691 {
 692         int i, ret = 0;
 693         unsigned long flags;
 694
 695         spin_lock_irqsave(&data->data_lock, flags);
 696
 697         if (!rockchip_set_iommu_active(data)) {
 698                 if (WARN_ON(pgtable != data->pgtable)) {
 699                         ret = -EBUSY;
 700                         rockchip_set_iommu_inactive(data);
 701                 } else {
 702                         ret = 1;
 703                 }
 704
 705                 spin_unlock_irqrestore(&data->data_lock, flags);
 706                 dev_info(data->iommu, "(%s) Already enabled\n", data->dbgname);
 707
 708                 return ret;
 709         }
 710
 711         for (i = 0; i < data->num_res_mem; i++) {
 712                 ret = rockchip_iommu_enable_stall(data->res_bases[i]);
 713                 if (!ret) {
 714                         dev_info(data->iommu, "(%s), %s failed\n",
 715                                  data->dbgname, __func__);
 716                         spin_unlock_irqrestore(&data->data_lock, flags);
 717                         return -EBUSY;
 718                 }
 719
 720                 if (!strstr(data->dbgname, "isp")) {
 721                         if (!rockchip_iommu_reset(data->res_bases[i],
 722                              data->dbgname)) {
 723                                 spin_unlock_irqrestore(&data->data_lock, flags);
 724                                 return -ENOENT;
 725                         }
 726                 }
 727
 728                 rockchip_iommu_set_ptbase(data->res_bases[i], pgtable);
 729
 730                 __raw_writel(IOMMU_COMMAND_ZAP_CACHE, data->res_bases[i] +
 731                              IOMMU_REGISTER_COMMAND);
 732
 733                 if (strstr(data->dbgname, "isp")) {
 734                         __raw_writel(IOMMU_INTERRUPT_PAGE_FAULT |
 735                                 IOMMU_INTERRUPT_READ_BUS_ERROR,
 736                              data->res_bases[i] + IOMMU_REGISTER_INT_MASK);
 737                 }
 738
 739                 ret = rockchip_iommu_enable_paging(data->res_bases[i]);
 740                 if (!ret) {
 741                         spin_unlock_irqrestore(&data->data_lock, flags);
 742                         dev_info(data->iommu, "(%s), %s failed\n",
 743                                  data->dbgname, __func__);
 744                         return -EBUSY;
 745                 }
 746
 747                 rockchip_iommu_disable_stall(data->res_bases[i]);
 748         }
 749
 750         data->pgtable = pgtable;
 751
 752         dev_dbg(data->iommu,"(%s) Enabled\n", data->dbgname);
 753
 754         spin_unlock_irqrestore(&data->data_lock, flags);
 755
 756         return 0;
 757 }
 758
 759 int rockchip_iommu_tlb_invalidate_global(struct device *dev)
 760 {
 761         unsigned long flags;
 762         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 763         int ret;
 764
 765         spin_lock_irqsave(&data->data_lock, flags);
 766
 767         if (rockchip_is_iommu_active(data)) {
 768                 int i;
 769
 770                 for (i = 0; i < data->num_res_mem; i++) {
 771                         ret = rockchip_iommu_zap_tlb(data->res_bases[i]);
 772                         if (ret)
 773                                 dev_err(dev->archdata.iommu, "(%s) %s failed\n",
 774                                         data->dbgname, __func__);
 775                 }
 776         } else {
 777                 dev_dbg(dev->archdata.iommu, "(%s) Disabled. Skipping invalidating TLB.\n",
 778                         data->dbgname);
 779                 ret = -1;
 780         }
 781
 782         spin_unlock_irqrestore(&data->data_lock, flags);
 783
 784         return ret;
 785 }
 786
 787 int rockchip_iommu_tlb_invalidate(struct device *dev)
 788 {
 789         unsigned long flags;
 790         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 791
 792         if (strstr(data->dbgname, "vpu") || strstr(data->dbgname, "hevc"))
 793                         return 0;
 794
 795         spin_lock_irqsave(&data->data_lock, flags);
 796
 797         if (rockchip_is_iommu_active(data)) {
 798                 int i;
 799                 int ret;
 800
 801                 for (i = 0; i < data->num_res_mem; i++) {
 802                         ret = rockchip_iommu_zap_tlb(data->res_bases[i]);
 803                         if (ret) {
 804                                 dev_err(dev->archdata.iommu, "(%s) %s failed\n",
 805                                         data->dbgname, __func__);
 806                                 spin_unlock_irqrestore(&data->data_lock, flags);
 807                                 return ret;
 808                         }
 809
 810                 }
 811         } else {
 812                 dev_dbg(dev->archdata.iommu, "(%s) Disabled. Skipping invalidating TLB.\n",
 813                         data->dbgname);
 814         }
 815
 816         spin_unlock_irqrestore(&data->data_lock, flags);
 817
 818         return 0;
 819 }
 820
 821 static phys_addr_t rockchip_iommu_iova_to_phys(struct iommu_domain *domain,
 822                                                dma_addr_t iova)
 823 {
 824         struct rk_iommu_domain *priv = domain->priv;
 825         unsigned int *entry;
 826         unsigned long flags;
 827         phys_addr_t phys = 0;
 828
 829         spin_lock_irqsave(&priv->pgtablelock, flags);
 830
 831         entry = rockchip_section_entry(priv->pgtable, iova);
 832         entry = rockchip_page_entry(entry, iova);
 833         phys = rockchip_spage_phys(entry) + rockchip_spage_offs(iova);
 834
 835         spin_unlock_irqrestore(&priv->pgtablelock, flags);
 836
 837         return phys;
 838 }
 839
 840 static int rockchip_lv2set_page(unsigned int *pent, phys_addr_t paddr,
 841                        size_t size, short *pgcnt)
 842 {
 843         if (!rockchip_lv2ent_fault(pent))
 844                 return -EADDRINUSE;
 845
 846         *pent = rockchip_mk_lv2ent_spage(paddr);
 847         rockchip_pgtable_flush(pent, pent + 1);
 848         *pgcnt -= 1;
 849         return 0;
 850 }
 851
 852 static unsigned int *rockchip_alloc_lv2entry(unsigned int *sent,
 853                                      unsigned long iova, short *pgcounter)
 854 {
 855         if (rockchip_lv1ent_fault(sent)) {
 856                 unsigned int *pent;
 857
 858                 pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
 859                 BUG_ON((unsigned long)pent & (LV2TABLE_SIZE - 1));
 860                 if (!pent)
 861                         return NULL;
 862
 863                 *sent = rockchip_mk_lv1ent_page(virt_to_phys(pent));
 864                 kmemleak_ignore(pent);
 865                 *pgcounter = NUM_LV2ENTRIES;
 866                 rockchip_pgtable_flush(pent, pent + NUM_LV2ENTRIES);
 867                 rockchip_pgtable_flush(sent, sent + 1);
 868         }
 869         return rockchip_page_entry(sent, iova);
 870 }
 871
 872 static size_t rockchip_iommu_unmap(struct iommu_domain *domain,
 873                                    unsigned long iova, size_t size)
 874 {
 875         struct rk_iommu_domain *priv = domain->priv;
 876         unsigned long flags;
 877         unsigned int *ent;
 878
 879         BUG_ON(priv->pgtable == NULL);
 880
 881         spin_lock_irqsave(&priv->pgtablelock, flags);
 882
 883         ent = rockchip_section_entry(priv->pgtable, iova);
 884
 885         if (unlikely(rockchip_lv1ent_fault(ent))) {
 886                 if (size > SPAGE_SIZE)
 887                         size = SPAGE_SIZE;
 888                 goto done;
 889         }
 890
 891         /* lv1ent_page(sent) == true here */
 892
 893         ent = rockchip_page_entry(ent, iova);
 894
 895         if (unlikely(rockchip_lv2ent_fault(ent))) {
 896                 size = SPAGE_SIZE;
 897                 goto done;
 898         }
 899
 900         *ent = 0;
 901         size = SPAGE_SIZE;
 902         priv->lv2entcnt[rockchip_lv1ent_offset(iova)] += 1;
 903         goto done;
 904
 905 done:
 906         pr_debug("%s:unmap iova 0x%lx/%zx bytes\n",
 907                   __func__, iova,size);
 908         spin_unlock_irqrestore(&priv->pgtablelock, flags);
 909
 910         return size;
 911 }
 912
 913 static int rockchip_iommu_map(struct iommu_domain *domain, unsigned long iova,
 914                               phys_addr_t paddr, size_t size, int prot)
 915 {
 916         struct rk_iommu_domain *priv = domain->priv;
 917         unsigned int *entry;
 918         unsigned long flags;
 919         int ret = -ENOMEM;
 920         unsigned int *pent;
 921
 922         BUG_ON(priv->pgtable == NULL);
 923
 924         spin_lock_irqsave(&priv->pgtablelock, flags);
 925
 926         entry = rockchip_section_entry(priv->pgtable, iova);
 927
 928         pent = rockchip_alloc_lv2entry(entry, iova,
 929                               &priv->lv2entcnt[rockchip_lv1ent_offset(iova)]);
 930         if (!pent)
 931                 ret = -ENOMEM;
 932         else
 933                 ret = rockchip_lv2set_page(pent, paddr, size,
 934                                 &priv->lv2entcnt[rockchip_lv1ent_offset(iova)]);
 935
 936         if (ret) {
 937                 pr_info("%s: Failed to map iova 0x%lx/%zx bytes\n", __func__,
 938                        iova, size);
 939         }
 940         spin_unlock_irqrestore(&priv->pgtablelock, flags);
 941
 942         return ret;
 943 }
 944
 945 static void rockchip_iommu_detach_device(struct iommu_domain *domain, struct device *dev)
 946 {
 947         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 948         struct rk_iommu_domain *priv = domain->priv;
 949         struct list_head *pos;
 950         unsigned long flags;
 951         bool found = false;
 952
 953         spin_lock_irqsave(&priv->lock, flags);
 954
 955         list_for_each(pos, &priv->clients) {
 956                 if (list_entry(pos, struct iommu_drvdata, node) == data) {
 957                         found = true;
 958                         break;
 959                 }
 960         }
 961
 962         if (!found) {
 963                 spin_unlock_irqrestore(&priv->lock, flags);
 964                 return;
 965         }
 966
 967         if (rockchip_iommu_disable(data)) {
 968                 if (!(strstr(data->dbgname, "vpu") || strstr(data->dbgname, "hevc")))
 969                         dev_dbg(dev->archdata.iommu,"%s: Detached IOMMU with pgtable %08lx\n",
 970                                 __func__, (unsigned long)virt_to_phys(priv->pgtable));
 971                 data->domain = NULL;
 972                 list_del_init(&data->node);
 973
 974         } else
 975                 dev_err(dev->archdata.iommu,"%s: Detaching IOMMU with pgtable %08lx delayed",
 976                         __func__, (unsigned long)virt_to_phys(priv->pgtable));
 977
 978         spin_unlock_irqrestore(&priv->lock, flags);
 979 }
 980
 981 static int rockchip_iommu_attach_device(struct iommu_domain *domain, struct device *dev)
 982 {
 983         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 984         struct rk_iommu_domain *priv = domain->priv;
 985         unsigned long flags;
 986         int ret;
 987
 988         spin_lock_irqsave(&priv->lock, flags);
 989
 990         ret = rockchip_iommu_enable(data, virt_to_phys(priv->pgtable));
 991
 992         if (ret == 0) {
 993                 /* 'data->node' must not be appeared in priv->clients */
 994                 BUG_ON(!list_empty(&data->node));
 995                 list_add_tail(&data->node, &priv->clients);
 996                 data->domain = domain;
 997         }
 998
 999         spin_unlock_irqrestore(&priv->lock, flags);
1000
1001         if (ret < 0) {
1002                 dev_err(dev->archdata.iommu,"%s: Failed to attach IOMMU with pgtable %x\n",
1003                        __func__, (unsigned int)virt_to_phys(priv->pgtable));
1004         } else if (ret > 0) {
1005                 dev_dbg(dev->archdata.iommu,"%s: IOMMU with pgtable 0x%x already attached\n",
1006                         __func__, (unsigned int)virt_to_phys(priv->pgtable));
1007         } else {
1008                 if (!(strstr(data->dbgname, "vpu") || strstr(data->dbgname, "hevc")))
1009                         dev_info(dev->archdata.iommu,"%s: Attached new IOMMU with pgtable 0x%x\n",
1010                                 __func__, (unsigned int)virt_to_phys(priv->pgtable));
1011         }
1012
1013         return ret;
1014 }
1015
1016 static void rockchip_iommu_domain_destroy(struct iommu_domain *domain)
1017 {
1018         struct rk_iommu_domain *priv = domain->priv;
1019         int i;
1020
1021         WARN_ON(!list_empty(&priv->clients));
1022
1023         for (i = 0; i < NUM_LV1ENTRIES; i++)
1024                 if (rockchip_lv1ent_page(priv->pgtable + i))
1025                         kmem_cache_free(lv2table_kmem_cache,
1026                                         phys_to_virt(rockchip_lv2table_base(priv->pgtable + i)));
1027
1028         free_pages((unsigned long)priv->pgtable, 0);
1029         free_pages((unsigned long)priv->lv2entcnt, 0);
1030         kfree(domain->priv);
1031         domain->priv = NULL;
1032 }
1033
1034 static int rockchip_iommu_domain_init(struct iommu_domain *domain)
1035 {
1036         struct rk_iommu_domain *priv;
1037
1038         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1039         if (!priv)
1040                 return -ENOMEM;
1041
1042 /*rk32xx iommu use 2 level pagetable,
1043    level1 and leve2 both have 1024 entries,each entry  occupy 4 bytes,
1044    so alloc a page size for each page table
1045 */
1046         priv->pgtable = (unsigned int *)__get_free_pages(GFP_KERNEL |
1047                                                           __GFP_ZERO, 0);
1048         if (!priv->pgtable)
1049                 goto err_pgtable;
1050
1051         priv->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL |
1052                                                     __GFP_ZERO, 0);
1053         if (!priv->lv2entcnt)
1054                 goto err_counter;
1055
1056         rockchip_pgtable_flush(priv->pgtable, priv->pgtable + NUM_LV1ENTRIES);
1057
1058         spin_lock_init(&priv->lock);
1059         spin_lock_init(&priv->pgtablelock);
1060         INIT_LIST_HEAD(&priv->clients);
1061
1062         domain->priv = priv;
1063         return 0;
1064
1065 err_counter:
1066         free_pages((unsigned long)priv->pgtable, 0);
1067 err_pgtable:
1068         kfree(priv);
1069         return -ENOMEM;
1070 }
1071
1072 static struct iommu_ops rk_iommu_ops = {
1073         .domain_init = rockchip_iommu_domain_init,
1074         .domain_destroy = rockchip_iommu_domain_destroy,
1075         .attach_dev = rockchip_iommu_attach_device,
1076         .detach_dev = rockchip_iommu_detach_device,
1077         .map = rockchip_iommu_map,
1078         .unmap = rockchip_iommu_unmap,
1079         .iova_to_phys = rockchip_iommu_iova_to_phys,
1080         .pgsize_bitmap = SPAGE_SIZE,
1081 };
1082
1083 static int  rockchip_get_iommu_resource_num(struct platform_device *pdev,
1084                                              unsigned int type)
1085 {
1086         int num = 0;
1087         int i;
1088
1089         for (i = 0; i < pdev->num_resources; i++) {
1090                 struct resource *r = &pdev->resource[i];
1091                 if (type == resource_type(r))
1092                         num++;
1093         }
1094
1095         return num;
1096 }
1097
1098 static int rockchip_iommu_probe(struct platform_device *pdev)
1099 {
1100         int i, ret;
1101         struct device *dev;
1102         struct iommu_drvdata *data;
1103
1104         dev = &pdev->dev;
1105
1106         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
1107         if (!data) {
1108                 dev_dbg(dev, "Not enough memory\n");
1109                 return -ENOMEM;
1110         }
1111
1112         dev_set_drvdata(dev, data);
1113
1114         if (pdev->dev.of_node)
1115                 of_property_read_string(pdev->dev.of_node, "dbgname",
1116                                         &(data->dbgname));
1117         else
1118                 dev_dbg(dev, "dbgname not assigned in device tree or device node not exist\r\n");
1119
1120         dev_info(dev,"(%s) Enter\n", data->dbgname);
1121
1122         data->num_res_mem = rockchip_get_iommu_resource_num(pdev,
1123                                 IORESOURCE_MEM);
1124         if (0 == data->num_res_mem) {
1125                 dev_err(dev,"can't find iommu memory resource \r\n");
1126                 return -ENOMEM;
1127         }
1128         dev_dbg(dev,"data->num_res_mem=%d\n", data->num_res_mem);
1129
1130         data->num_res_irq = rockchip_get_iommu_resource_num(pdev,
1131                                 IORESOURCE_IRQ);
1132         if (0 == data->num_res_irq) {
1133                 dev_err(dev,"can't find iommu irq resource \r\n");
1134                 return -ENOMEM;
1135         }
1136         dev_dbg(dev,"data->num_res_irq=%d\n", data->num_res_irq);
1137
1138         data->res_bases = devm_kmalloc_array(dev, data->num_res_mem,
1139                                 sizeof(*data->res_bases), GFP_KERNEL);
1140         if (data->res_bases == NULL) {
1141                 dev_err(dev, "Not enough memory\n");
1142                 return -ENOMEM;
1143         }
1144
1145         for (i = 0; i < data->num_res_mem; i++) {
1146                 struct resource *res;
1147
1148                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1149                 if (!res) {
1150                         dev_err(dev,"Unable to find IOMEM region\n");
1151                         return -ENOENT;
1152                 }
1153
1154                 data->res_bases[i] = devm_ioremap(dev,res->start,
1155                                                   resource_size(res));
1156                 if (!data->res_bases[i]) {
1157                         dev_err(dev, "Unable to map IOMEM @ PA:%pa\n",
1158                                 &res->start);
1159                         return -ENOMEM;
1160                 }
1161
1162                 dev_dbg(dev,"res->start = 0x%pa ioremap to data->res_bases[%d] = %p\n",
1163                         &res->start, i, data->res_bases[i]);
1164
1165                 if (strstr(data->dbgname, "vop") &&
1166                     (soc_is_rk3128() || soc_is_rk3126())) {
1167                         rk312x_vop_mmu_base = data->res_bases[0];
1168                         dev_dbg(dev, "rk312x_vop_mmu_base = %p\n",
1169                                 rk312x_vop_mmu_base);
1170                 }
1171         }
1172
1173         for (i = 0; i < data->num_res_irq; i++) {
1174                 if ((soc_is_rk3128() || soc_is_rk3126()) &&
1175                     strstr(data->dbgname, "vop")) {
1176                         dev_info(dev, "skip request vop mmu irq\n");
1177                         continue;
1178                 }
1179
1180                 ret = platform_get_irq(pdev, i);
1181                 if (ret <= 0) {
1182                         dev_err(dev,"Unable to find IRQ resource\n");
1183                         return -ENOENT;
1184                 }
1185
1186                 ret = devm_request_irq(dev, ret, rockchip_iommu_irq,
1187                                   IRQF_SHARED, dev_name(dev), data);
1188                 if (ret) {
1189                         dev_err(dev, "Unabled to register interrupt handler\n");
1190                         return -ENOENT;
1191                 }
1192         }
1193
1194         ret = rockchip_init_iovmm(dev, &data->vmm);
1195         if (ret)
1196                 return ret;
1197
1198         data->iommu = dev;
1199         spin_lock_init(&data->data_lock);
1200         INIT_LIST_HEAD(&data->node);
1201
1202         dev_info(dev,"(%s) Initialized\n", data->dbgname);
1203
1204         return 0;
1205 }
1206
1207 #ifdef CONFIG_OF
1208 static const struct of_device_id iommu_dt_ids[] = {
1209         { .compatible = IEP_IOMMU_COMPATIBLE_NAME},
1210         { .compatible = VIP_IOMMU_COMPATIBLE_NAME},
1211         { .compatible = VOPB_IOMMU_COMPATIBLE_NAME},
1212         { .compatible = VOPL_IOMMU_COMPATIBLE_NAME},
1213         { .compatible = HEVC_IOMMU_COMPATIBLE_NAME},
1214         { .compatible = VPU_IOMMU_COMPATIBLE_NAME},
1215         { .compatible = ISP_IOMMU_COMPATIBLE_NAME},
1216         { .compatible = VOP_IOMMU_COMPATIBLE_NAME},
1217         { /* end */ }
1218 };
1219
1220 MODULE_DEVICE_TABLE(of, iommu_dt_ids);
1221 #endif
1222
1223 static struct platform_driver rk_iommu_driver = {
1224         .probe = rockchip_iommu_probe,
1225         .remove = NULL,
1226         .driver = {
1227                    .name = "rk_iommu",
1228                    .owner = THIS_MODULE,
1229                    .of_match_table = of_match_ptr(iommu_dt_ids),
1230         },
1231 };
1232
1233 static int __init rockchip_iommu_init_driver(void)
1234 {
1235         int ret;
1236
1237         lv2table_kmem_cache = kmem_cache_create("rk-iommu-lv2table",
1238                                                 LV2TABLE_SIZE, LV2TABLE_SIZE,
1239                                                 0, NULL);
1240         if (!lv2table_kmem_cache) {
1241                 pr_info("%s: failed to create kmem cache\n", __func__);
1242                 return -ENOMEM;
1243         }
1244
1245         ret = bus_set_iommu(&platform_bus_type, &rk_iommu_ops);
1246         if (ret)
1247                 return ret;
1248
1249         return platform_driver_register(&rk_iommu_driver);
1250 }
1251
1252 core_initcall(rockchip_iommu_init_driver);