2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
7 #ifdef CONFIG_ROCKCHIP_IOMMU_DEBUG
12 #include <linux/interrupt.h>
13 #include <linux/slab.h>
14 #include <linux/clk.h>
15 #include <linux/err.h>
17 #include <linux/errno.h>
18 #include <linux/memblock.h>
19 #include <linux/export.h>
21 #include <asm/cacheflush.h>
22 #include <asm/pgtable.h>
24 #include <linux/rockchip/sysmmu.h>
26 #include "rockchip-iommu.h"
28 /* We does not consider super section mapping (16MB) */
29 #define SPAGE_ORDER 12
30 #define SPAGE_SIZE (1 << SPAGE_ORDER)
31 #define SPAGE_MASK (~(SPAGE_SIZE - 1))
33 typedef enum sysmmu_entry_flags
35 SYSMMU_FLAGS_PRESENT = 0x01,
36 SYSMMU_FLAGS_READ_PERMISSION = 0x02,
37 SYSMMU_FLAGS_WRITE_PERMISSION = 0x04,
38 SYSMMU_FLAGS_OVERRIDE_CACHE = 0x8,
39 SYSMMU_FLAGS_WRITE_CACHEABLE = 0x10,
40 SYSMMU_FLAGS_WRITE_ALLOCATE = 0x20,
41 SYSMMU_FLAGS_WRITE_BUFFERABLE = 0x40,
42 SYSMMU_FLAGS_READ_CACHEABLE = 0x80,
43 SYSMMU_FLAGS_READ_ALLOCATE = 0x100,
44 SYSMMU_FLAGS_MASK = 0x1FF,
47 #define lv1ent_fault(sent) ((*(sent) & SYSMMU_FLAGS_PRESENT) == 0)
48 #define lv1ent_page(sent) ((*(sent) & SYSMMU_FLAGS_PRESENT) == 1)
49 #define lv2ent_fault(pent) ((*(pent) & SYSMMU_FLAGS_PRESENT) == 0)
50 #define spage_phys(pent) (*(pent) & SPAGE_MASK)
51 #define spage_offs(iova) ((iova) & 0x0FFF)
53 #define lv1ent_offset(iova) (((iova)>>22) & 0x03FF)
54 #define lv2ent_offset(iova) (((iova)>>12) & 0x03FF)
56 #define NUM_LV1ENTRIES 1024
57 #define NUM_LV2ENTRIES 1024
59 #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(long))
61 #define lv2table_base(sent) (*(sent) & 0xFFFFFFFE)
63 #define mk_lv1ent_page(pa) ((pa) | SYSMMU_FLAGS_PRESENT)
64 /*write and read permission for level2 page default*/
65 #define mk_lv2ent_spage(pa) ((pa) | SYSMMU_FLAGS_PRESENT |SYSMMU_FLAGS_READ_PERMISSION |SYSMMU_FLAGS_WRITE_PERMISSION)
67 #define SYSMMU_REG_POLL_COUNT_FAST 1000
70 * MMU register numbers
71 * Used in the register read/write routines.
72 * See the hardware documentation for more information about each register
74 typedef enum sysmmu_register
76 SYSMMU_REGISTER_DTE_ADDR = 0x0000, /**< Current Page Directory Pointer */
77 SYSMMU_REGISTER_STATUS = 0x0004, /**< Status of the MMU */
78 SYSMMU_REGISTER_COMMAND = 0x0008, /**< Command register, used to control the MMU */
79 SYSMMU_REGISTER_PAGE_FAULT_ADDR = 0x000C, /**< Logical address of the last page fault */
80 SYSMMU_REGISTER_ZAP_ONE_LINE = 0x010, /**< Used to invalidate the mapping of a single page from the MMU */
81 SYSMMU_REGISTER_INT_RAWSTAT = 0x0014, /**< Raw interrupt status, all interrupts visible */
82 SYSMMU_REGISTER_INT_CLEAR = 0x0018, /**< Indicate to the MMU that the interrupt has been received */
83 SYSMMU_REGISTER_INT_MASK = 0x001C, /**< Enable/disable types of interrupts */
84 SYSMMU_REGISTER_INT_STATUS = 0x0020, /**< Interrupt status based on the mask */
85 SYSMMU_REGISTER_AUTO_GATING = 0x0024
88 typedef enum sysmmu_command
90 SYSMMU_COMMAND_ENABLE_PAGING = 0x00, /**< Enable paging (memory translation) */
91 SYSMMU_COMMAND_DISABLE_PAGING = 0x01, /**< Disable paging (memory translation) */
92 SYSMMU_COMMAND_ENABLE_STALL = 0x02, /**< Enable stall on page fault */
93 SYSMMU_COMMAND_DISABLE_STALL = 0x03, /**< Disable stall on page fault */
94 SYSMMU_COMMAND_ZAP_CACHE = 0x04, /**< Zap the entire page table cache */
95 SYSMMU_COMMAND_PAGE_FAULT_DONE = 0x05, /**< Page fault processed */
96 SYSMMU_COMMAND_HARD_RESET = 0x06 /**< Reset the MMU back to power-on settings */
100 * MMU interrupt register bits
101 * Each cause of the interrupt is reported
102 * through the (raw) interrupt status registers.
103 * Multiple interrupts can be pending, so multiple bits
104 * can be set at once.
106 typedef enum sysmmu_interrupt
108 SYSMMU_INTERRUPT_PAGE_FAULT = 0x01, /**< A page fault occured */
109 SYSMMU_INTERRUPT_READ_BUS_ERROR = 0x02 /**< A bus read error occured */
112 typedef enum sysmmu_status_bits
114 SYSMMU_STATUS_BIT_PAGING_ENABLED = 1 << 0,
115 SYSMMU_STATUS_BIT_PAGE_FAULT_ACTIVE = 1 << 1,
116 SYSMMU_STATUS_BIT_STALL_ACTIVE = 1 << 2,
117 SYSMMU_STATUS_BIT_IDLE = 1 << 3,
118 SYSMMU_STATUS_BIT_REPLAY_BUFFER_EMPTY = 1 << 4,
119 SYSMMU_STATUS_BIT_PAGE_FAULT_IS_WRITE = 1 << 5,
120 SYSMMU_STATUS_BIT_STALL_NOT_ACTIVE = 1 << 31,
121 } sys_mmu_status_bits;
124 * Size of an MMU page in bytes
126 #define SYSMMU_PAGE_SIZE 0x1000
129 * Size of the address space referenced by a page table page
131 #define SYSMMU_VIRTUAL_PAGE_SIZE 0x400000 /* 4 MiB */
134 * Page directory index from address
135 * Calculates the page directory index from the given address
137 #define SYSMMU_PDE_ENTRY(address) (((address)>>22) & 0x03FF)
140 * Page table index from address
141 * Calculates the page table index from the given address
143 #define SYSMMU_PTE_ENTRY(address) (((address)>>12) & 0x03FF)
146 * Extract the memory address from an PDE/PTE entry
148 #define SYSMMU_ENTRY_ADDRESS(value) ((value) & 0xFFFFFC00)
150 #define INVALID_PAGE ((u32)(~0))
152 static struct kmem_cache *lv2table_kmem_cache;
154 static unsigned long *section_entry(unsigned long *pgtable, unsigned long iova)
156 return pgtable + lv1ent_offset(iova);
159 static unsigned long *page_entry(unsigned long *sent, unsigned long iova)
161 return (unsigned long *)__va(lv2table_base(sent)) + lv2ent_offset(iova);
164 static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = {
170 struct rk_iommu_domain {
171 struct list_head clients; /* list of sysmmu_drvdata.node */
172 unsigned long *pgtable; /* lv1 page table, 4KB */
173 short *lv2entcnt; /* free lv2 entry counter for each section */
174 spinlock_t lock; /* lock for this structure */
175 spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
178 static bool set_sysmmu_active(struct sysmmu_drvdata *data)
180 /* return true if the System MMU was not active previously
181 and it needs to be initialized */
182 return ++data->activations == 1;
185 static bool set_sysmmu_inactive(struct sysmmu_drvdata *data)
187 /* return true if the System MMU is needed to be disabled */
188 BUG_ON(data->activations < 1);
189 return --data->activations == 0;
192 static bool is_sysmmu_active(struct sysmmu_drvdata *data)
194 return data->activations > 0;
196 static void sysmmu_disable_stall(void __iomem *sfrbase)
199 u32 mmu_status = __raw_readl(sfrbase+SYSMMU_REGISTER_STATUS);
200 if ( 0 == (mmu_status & SYSMMU_STATUS_BIT_PAGING_ENABLED ))
202 pr_err("MMU disable skipped since it was not enabled.\n");
205 if (mmu_status & SYSMMU_STATUS_BIT_PAGE_FAULT_ACTIVE)
207 pr_err("Aborting MMU disable stall request since it is in pagefault state.\n");
211 __raw_writel(SYSMMU_COMMAND_DISABLE_STALL, sfrbase + SYSMMU_REGISTER_COMMAND);
213 for (i = 0; i < SYSMMU_REG_POLL_COUNT_FAST; ++i)
215 u32 status = __raw_readl(sfrbase + SYSMMU_REGISTER_STATUS);
216 if ( 0 == (status & SYSMMU_STATUS_BIT_STALL_ACTIVE) )
220 if ( status & SYSMMU_STATUS_BIT_PAGE_FAULT_ACTIVE )
224 if ( 0 == (mmu_status & SYSMMU_STATUS_BIT_PAGING_ENABLED ))
229 if (SYSMMU_REG_POLL_COUNT_FAST == i)
230 pr_err("Disable stall request failed, MMU status is 0x%08X\n", __raw_readl(sfrbase + SYSMMU_REGISTER_STATUS));
232 static bool sysmmu_enable_stall(void __iomem *sfrbase)
235 u32 mmu_status = __raw_readl(sfrbase + SYSMMU_REGISTER_STATUS);
237 if ( 0 == (mmu_status & SYSMMU_STATUS_BIT_PAGING_ENABLED) )
239 pr_info("MMU stall is implicit when Paging is not enabled.\n");
242 if ( mmu_status & SYSMMU_STATUS_BIT_PAGE_FAULT_ACTIVE )
244 pr_err("Aborting MMU stall request since it is in pagefault state.\n");
248 __raw_writel(SYSMMU_COMMAND_ENABLE_STALL, sfrbase + SYSMMU_REGISTER_COMMAND);
250 for (i = 0; i < SYSMMU_REG_POLL_COUNT_FAST; ++i)
252 mmu_status = __raw_readl(sfrbase + SYSMMU_REGISTER_STATUS);
253 if (mmu_status & SYSMMU_STATUS_BIT_PAGE_FAULT_ACTIVE)
257 if ((mmu_status & SYSMMU_STATUS_BIT_STALL_ACTIVE)&&(0==(mmu_status & SYSMMU_STATUS_BIT_STALL_NOT_ACTIVE)))
261 if (0 == (mmu_status & ( SYSMMU_STATUS_BIT_PAGING_ENABLED )))
266 if (SYSMMU_REG_POLL_COUNT_FAST == i)
268 pr_info("Enable stall request failed, MMU status is 0x%08X\n", __raw_readl(sfrbase + SYSMMU_REGISTER_STATUS));
271 if ( mmu_status & SYSMMU_STATUS_BIT_PAGE_FAULT_ACTIVE )
273 pr_info("Aborting MMU stall request since it has a pagefault.\n");
279 static bool sysmmu_enable_paging(void __iomem *sfrbase)
282 __raw_writel(SYSMMU_COMMAND_ENABLE_PAGING, sfrbase + SYSMMU_REGISTER_COMMAND);
284 for (i = 0; i < SYSMMU_REG_POLL_COUNT_FAST; ++i)
286 if (__raw_readl(sfrbase + SYSMMU_REGISTER_STATUS) & SYSMMU_STATUS_BIT_PAGING_ENABLED)
288 pr_info("Enable paging request success.\n");
292 if (SYSMMU_REG_POLL_COUNT_FAST == i)
294 pr_err("Enable paging request failed, MMU status is 0x%08X\n", __raw_readl(sfrbase + SYSMMU_REGISTER_STATUS));
299 void sysmmu_page_fault_done(void __iomem *sfrbase,const char *dbgname)
301 pr_info("MMU: %s: Leaving page fault mode\n", dbgname);
302 __raw_writel(SYSMMU_COMMAND_PAGE_FAULT_DONE, sfrbase + SYSMMU_REGISTER_COMMAND);
304 bool sysmmu_zap_tlb(void __iomem *sfrbase)
306 bool stall_success = sysmmu_enable_stall(sfrbase);
308 __raw_writel(SYSMMU_COMMAND_ZAP_CACHE, sfrbase + SYSMMU_REGISTER_COMMAND);
309 if (false == stall_success)
311 /* False means that it is in Pagefault state. Not possible to disable_stall then */
314 sysmmu_disable_stall(sfrbase);
317 static inline int sysmmu_raw_reset(void __iomem *sfrbase)
320 __raw_writel(0xCAFEBABE, sfrbase + SYSMMU_REGISTER_DTE_ADDR);
322 if(!(0xCAFEB000 == __raw_readl(sfrbase+SYSMMU_REGISTER_DTE_ADDR)))
324 pr_err("error when %s.\n",__func__);
327 __raw_writel(SYSMMU_COMMAND_HARD_RESET, sfrbase + SYSMMU_REGISTER_COMMAND);
329 for (i = 0; i < SYSMMU_REG_POLL_COUNT_FAST; ++i)
331 if(__raw_readl(sfrbase + SYSMMU_REGISTER_DTE_ADDR) == 0)
336 if (SYSMMU_REG_POLL_COUNT_FAST == i) {
337 pr_err("Reset request failed, MMU status is 0x%08X\n", __raw_readl(sfrbase + SYSMMU_REGISTER_DTE_ADDR));
343 static bool sysmmu_reset(void __iomem *sfrbase,const char *dbgname)
348 stall_success = sysmmu_enable_stall(sfrbase);
351 pr_info("sysmmu reset:stall failed: %s\n",dbgname);
354 if(0 == sysmmu_raw_reset(sfrbase))
356 __raw_writel(SYSMMU_INTERRUPT_PAGE_FAULT|SYSMMU_INTERRUPT_READ_BUS_ERROR, sfrbase+SYSMMU_REGISTER_INT_MASK);
357 err = sysmmu_enable_paging(sfrbase);
359 sysmmu_disable_stall(sfrbase);
361 pr_info("SYSMMU: reset successed: %s\n",dbgname);
363 pr_info("SYSMMU: reset failed: %s\n", dbgname);
367 static void __sysmmu_set_ptbase(void __iomem *sfrbase,unsigned long pgd)
369 __raw_writel(pgd, sfrbase + SYSMMU_REGISTER_DTE_ADDR);
372 static inline void pgtable_flush(void *vastart, void *vaend)
374 dmac_flush_range(vastart, vaend);
375 outer_flush_range(virt_to_phys(vastart),virt_to_phys(vaend));
377 static void __set_fault_handler(struct sysmmu_drvdata *data,
378 sysmmu_fault_handler_t handler)
382 write_lock_irqsave(&data->lock, flags);
383 data->fault_handler = handler;
384 write_unlock_irqrestore(&data->lock, flags);
387 void rockchip_sysmmu_set_fault_handler(struct device *dev,sysmmu_fault_handler_t handler)
389 struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
391 __set_fault_handler(data, handler);
394 static int default_fault_handler(struct device *dev,
395 enum rk_sysmmu_inttype itype,
396 unsigned long pgtable_base,
397 unsigned long fault_addr,
401 struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
403 if ((itype >= SYSMMU_FAULTS_NUM) || (itype < SYSMMU_PAGEFAULT))
404 itype = SYSMMU_FAULT_UNKNOWN;
406 if(itype == SYSMMU_BUSERROR)
407 pr_err("%s occured at 0x%lx(Page table base: 0x%lx)\n",sysmmu_fault_name[itype], fault_addr, pgtable_base);
409 if(itype == SYSMMU_PAGEFAULT)
410 pr_err("SYSMMU:Page fault detected at 0x%lx from bus id %d of type %s on %s\n",
412 (status >> 6) & 0x1F,
413 (status & 32) ? "write" : "read",
417 pr_err("Generating Kernel OOPS... because it is unrecoverable.\n");
424 static irqreturn_t rockchip_sysmmu_irq(int irq, void *dev_id)
426 /* SYSMMU is in blocked when interrupt occurred. */
427 struct sysmmu_drvdata *data = dev_id;
428 struct resource *irqres;
429 struct platform_device *pdev;
430 enum rk_sysmmu_inttype itype = SYSMMU_FAULT_UNKNOWN;
434 int i, ret = -ENOSYS;
436 read_lock(&data->lock);
438 WARN_ON(!is_sysmmu_active(data));
440 pdev = to_platform_device(data->sysmmu);
441 for (i = 0; i < data->num_res_irq; i++)
443 irqres = platform_get_resource(pdev, IORESOURCE_IRQ, i);
444 if (irqres && ((int)irqres->start == irq))
448 if (i == data->num_res_irq)
450 itype = SYSMMU_FAULT_UNKNOWN;
454 status = __raw_readl(data->res_bases[i] + SYSMMU_REGISTER_STATUS);
457 rawstat = __raw_readl(data->res_bases[i] + SYSMMU_REGISTER_INT_RAWSTAT);
458 if(rawstat & SYSMMU_INTERRUPT_PAGE_FAULT)
460 fault_address = __raw_readl(data->res_bases[i] + SYSMMU_REGISTER_PAGE_FAULT_ADDR);
461 itype = SYSMMU_PAGEFAULT;
463 else if(rawstat & SYSMMU_INTERRUPT_READ_BUS_ERROR)
465 itype = SYSMMU_BUSERROR;
475 ret = report_iommu_fault(data->domain, data->dev,fault_address, itype);
477 if ((ret == -ENOSYS) && data->fault_handler)
479 unsigned long base = data->pgtable;
480 if (itype != SYSMMU_FAULT_UNKNOWN)
481 base = __raw_readl(data->res_bases[i] + SYSMMU_REGISTER_DTE_ADDR);
482 ret = data->fault_handler(data->dev, itype, base, fault_address,status);
485 if (!ret && (itype != SYSMMU_FAULT_UNKNOWN))
487 if(SYSMMU_PAGEFAULT == itype)
488 sysmmu_page_fault_done(data->res_bases[i],data->dbgname);
489 sysmmu_reset(data->res_bases[i],data->dbgname);
492 pr_err("(%s) %s is not handled.\n",data->dbgname, sysmmu_fault_name[itype]);
495 read_unlock(&data->lock);
500 static bool __rockchip_sysmmu_disable(struct sysmmu_drvdata *data)
503 bool disabled = false;
505 write_lock_irqsave(&data->lock, flags);
507 if (!set_sysmmu_inactive(data))
510 for(i=0;i<data->num_res_mem;i++)
512 if(!sysmmu_reset(data->res_bases[i],data->dbgname))
519 write_unlock_irqrestore(&data->lock, flags);
522 pr_info("(%s) Disabled\n", data->dbgname);
524 pr_info("(%s) %d times left to be disabled\n",data->dbgname, data->activations);
529 /* __rk_sysmmu_enable: Enables System MMU
531 * returns -error if an error occurred and System MMU is not enabled,
532 * 0 if the System MMU has been just enabled and 1 if System MMU was already
535 static int __rockchip_sysmmu_enable(struct sysmmu_drvdata *data,unsigned long pgtable, struct iommu_domain *domain)
540 write_lock_irqsave(&data->lock, flags);
542 if (!set_sysmmu_active(data))
544 if (WARN_ON(pgtable != data->pgtable))
547 set_sysmmu_inactive(data);
552 pr_info("(%s) Already enabled\n", data->dbgname);
556 data->pgtable = pgtable;
558 for (i = 0; i < data->num_res_mem; i++)
561 status = sysmmu_enable_stall(data->res_bases[i]);
564 __sysmmu_set_ptbase(data->res_bases[i], pgtable);
565 __raw_writel(SYSMMU_COMMAND_ZAP_CACHE, data->res_bases[i] + SYSMMU_REGISTER_COMMAND);
567 sysmmu_disable_stall(data->res_bases[i]);
570 data->domain = domain;
572 pr_info("(%s) Enabled\n", data->dbgname);
574 write_unlock_irqrestore(&data->lock, flags);
578 bool rockchip_sysmmu_disable(struct device *dev)
580 struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
583 disabled = __rockchip_sysmmu_disable(data);
587 void rockchip_sysmmu_tlb_invalidate(struct device *dev)
590 struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
592 read_lock_irqsave(&data->lock, flags);
594 if (is_sysmmu_active(data))
597 for (i = 0; i < data->num_res_mem; i++)
599 if(!sysmmu_zap_tlb(data->res_bases[i]))
600 pr_err("%s,invalidating TLB failed\n",data->dbgname);
604 pr_info("(%s) Disabled. Skipping invalidating TLB.\n",data->dbgname);
606 read_unlock_irqrestore(&data->lock, flags);
608 static phys_addr_t rockchip_iommu_iova_to_phys(struct iommu_domain *domain,dma_addr_t iova)
610 struct rk_iommu_domain *priv = domain->priv;
611 unsigned long *entry;
613 phys_addr_t phys = 0;
615 spin_lock_irqsave(&priv->pgtablelock, flags);
617 entry = section_entry(priv->pgtable, iova);
618 entry = page_entry(entry, iova);
619 phys = spage_phys(entry) + spage_offs(iova);
621 spin_unlock_irqrestore(&priv->pgtablelock, flags);
625 static int lv2set_page(unsigned long *pent, phys_addr_t paddr, size_t size,
628 if (!lv2ent_fault(pent))
631 *pent = mk_lv2ent_spage(paddr);
632 pgtable_flush(pent, pent + 1);
637 static unsigned long *alloc_lv2entry(unsigned long *sent, unsigned long iova,short *pgcounter)
639 if (lv1ent_fault(sent))
643 pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
644 BUG_ON((unsigned long)pent & (LV2TABLE_SIZE - 1));
648 *sent = mk_lv1ent_page(__pa(pent));
649 kmemleak_ignore(pent);
650 *pgcounter = NUM_LV2ENTRIES;
651 pgtable_flush(pent, pent + NUM_LV2ENTRIES);
652 pgtable_flush(sent, sent + 1);
654 return page_entry(sent, iova);
657 static size_t rockchip_iommu_unmap(struct iommu_domain *domain,unsigned long iova, size_t size)
659 struct rk_iommu_domain *priv = domain->priv;
663 BUG_ON(priv->pgtable == NULL);
665 spin_lock_irqsave(&priv->pgtablelock, flags);
667 ent = section_entry(priv->pgtable, iova);
669 if (unlikely(lv1ent_fault(ent)))
671 if (size > SPAGE_SIZE)
676 /* lv1ent_page(sent) == true here */
678 ent = page_entry(ent, iova);
680 if (unlikely(lv2ent_fault(ent)))
688 priv->lv2entcnt[lv1ent_offset(iova)] += 1;
692 pr_info("%s:unmap iova 0x%lx/0x%x bytes\n",__func__, iova,size);
693 spin_unlock_irqrestore(&priv->pgtablelock, flags);
697 static int rockchip_iommu_map(struct iommu_domain *domain, unsigned long iova,
698 phys_addr_t paddr, size_t size, int prot)
700 struct rk_iommu_domain *priv = domain->priv;
701 unsigned long *entry;
706 BUG_ON(priv->pgtable == NULL);
708 spin_lock_irqsave(&priv->pgtablelock, flags);
710 entry = section_entry(priv->pgtable, iova);
712 pent = alloc_lv2entry(entry, iova,&priv->lv2entcnt[lv1ent_offset(iova)]);
716 ret = lv2set_page(pent, paddr, size,&priv->lv2entcnt[lv1ent_offset(iova)]);
720 pr_debug("%s: Failed to map iova 0x%lx/0x%x bytes\n",__func__, iova, size);
722 spin_unlock_irqrestore(&priv->pgtablelock, flags);
727 static void rockchip_iommu_detach_device(struct iommu_domain *domain,
730 struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
731 struct rk_iommu_domain *priv = domain->priv;
732 struct list_head *pos;
736 spin_lock_irqsave(&priv->lock, flags);
738 list_for_each(pos, &priv->clients)
740 if (list_entry(pos, struct sysmmu_drvdata, node) == data)
749 if (__rockchip_sysmmu_disable(data))
751 pr_info("%s: Detached IOMMU with pgtable %#lx\n",__func__, __pa(priv->pgtable));
752 list_del(&data->node);
753 INIT_LIST_HEAD(&data->node);
757 pr_info("%s: Detaching IOMMU with pgtable %#lx delayed",__func__, __pa(priv->pgtable));
760 spin_unlock_irqrestore(&priv->lock, flags);
762 static int rockchip_iommu_attach_device(struct iommu_domain *domain,struct device *dev)
764 struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
765 struct rk_iommu_domain *priv = domain->priv;
769 spin_lock_irqsave(&priv->lock, flags);
771 ret = __rockchip_sysmmu_enable(data, __pa(priv->pgtable), domain);
775 /* 'data->node' must not be appeared in priv->clients */
776 BUG_ON(!list_empty(&data->node));
778 list_add_tail(&data->node, &priv->clients);
781 spin_unlock_irqrestore(&priv->lock, flags);
785 pr_err("%s: Failed to attach IOMMU with pgtable %#lx\n",__func__, __pa(priv->pgtable));
789 pr_info("%s: IOMMU with pgtable 0x%lx already attached\n",__func__, __pa(priv->pgtable));
793 pr_info("%s: Attached new IOMMU with pgtable 0x%lx\n",__func__, __pa(priv->pgtable));
798 static void rockchip_iommu_domain_destroy(struct iommu_domain *domain)
800 struct rk_iommu_domain *priv = domain->priv;
801 struct sysmmu_drvdata *data;
805 WARN_ON(!list_empty(&priv->clients));
807 spin_lock_irqsave(&priv->lock, flags);
809 list_for_each_entry(data, &priv->clients, node)
811 while (!rockchip_sysmmu_disable(data->dev))
812 ; /* until System MMU is actually disabled */
814 spin_unlock_irqrestore(&priv->lock, flags);
816 for (i = 0; i < NUM_LV1ENTRIES; i++)
817 if (lv1ent_page(priv->pgtable + i))
818 kmem_cache_free(lv2table_kmem_cache,__va(lv2table_base(priv->pgtable + i)));
820 free_pages((unsigned long)priv->pgtable, 0);
821 free_pages((unsigned long)priv->lv2entcnt, 0);
826 static int rockchip_iommu_domain_init(struct iommu_domain *domain)
828 struct rk_iommu_domain *priv;
830 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
834 /*rk32xx sysmmu use 2 level pagetable,
835 level1 and leve2 both have 1024 entries,each entry occupy 4 bytes,
836 so alloc a page size for each page table
838 priv->pgtable = (unsigned long *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 0);
842 priv->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 0);
843 if (!priv->lv2entcnt)
846 pgtable_flush(priv->pgtable, priv->pgtable + NUM_LV1ENTRIES);
848 spin_lock_init(&priv->lock);
849 spin_lock_init(&priv->pgtablelock);
850 INIT_LIST_HEAD(&priv->clients);
856 free_pages((unsigned long)priv->pgtable, 2);
862 static struct iommu_ops rk_iommu_ops =
864 .domain_init = &rockchip_iommu_domain_init,
865 .domain_destroy = &rockchip_iommu_domain_destroy,
866 .attach_dev = &rockchip_iommu_attach_device,
867 .detach_dev = &rockchip_iommu_detach_device,
868 .map = &rockchip_iommu_map,
869 .unmap = &rockchip_iommu_unmap,
870 .iova_to_phys = &rockchip_iommu_iova_to_phys,
871 .pgsize_bitmap = SPAGE_SIZE,
874 static int rockchip_sysmmu_prepare(void)
877 static int registed = 0;
882 lv2table_kmem_cache = kmem_cache_create("rk-iommu-lv2table",LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL);
883 if (!lv2table_kmem_cache)
885 pr_err("%s: failed to create kmem cache\n", __func__);
888 ret = bus_set_iommu(&platform_bus_type, &rk_iommu_ops);
892 pr_err("%s:failed to set iommu to bus\r\n",__func__);
895 static int rockchip_get_sysmmu_resource_num(struct platform_device *pdev,unsigned int type)
897 struct resource *info = NULL;
898 int num_resources = 0;
902 info = platform_get_resource(pdev, type, num_resources);
909 if(IORESOURCE_MEM == type)
910 pr_info("have memory resource %d\r\n",num_resources);
911 if(IORESOURCE_IRQ == type)
912 pr_info("have IRQ resource %d\r\n",num_resources);
913 return num_resources;
916 static int rockchip_sysmmu_probe(struct platform_device *pdev)
920 struct sysmmu_drvdata *data;
924 ret = rockchip_sysmmu_prepare();
927 pr_err("%s,failed\r\n",__func__);
931 data = devm_kzalloc(dev,sizeof(*data), GFP_KERNEL);
934 dev_dbg(dev, "Not enough memory\n");
939 ret = dev_set_drvdata(dev, data);
942 dev_dbg(dev, "Unabled to initialize driver data\n");
946 /*rk32xx sysmmu need both irq and memory */
947 data->num_res_mem = rockchip_get_sysmmu_resource_num(pdev,IORESOURCE_MEM);
948 if(0 == data->num_res_mem)
950 pr_err("can't find sysmmu memory resource \r\n");
953 data->num_res_irq = rockchip_get_sysmmu_resource_num(pdev,IORESOURCE_IRQ);
954 if(0 == data->num_res_irq)
956 pr_err("can't find sysmmu irq resource \r\n");
960 data->res_bases = kmalloc(sizeof(*data->res_bases) * data->num_res_mem,GFP_KERNEL);
961 if (data->res_bases == NULL)
963 dev_dbg(dev, "Not enough memory\n");
968 for (i = 0; i < data->num_res_mem; i++)
970 struct resource *res;
971 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
974 pr_err("Unable to find IOMEM region\n");
978 data->res_bases[i] = ioremap(res->start, resource_size(res));
979 if (!data->res_bases[i])
981 pr_err("Unable to map IOMEM @ PA:%#x\n",res->start);
986 if(!sysmmu_reset(data->res_bases[i],data->dbgname))
993 for (i = 0; i < data->num_res_irq; i++)
995 ret = platform_get_irq(pdev, i);
998 pr_err("Unable to find IRQ resource\n");
1001 ret = request_irq(ret, rockchip_sysmmu_irq, IRQF_SHARED ,dev_name(dev), data);
1004 pr_err("Unabled to register interrupt handler\n");
1009 if(pdev->dev.of_node)
1011 of_property_read_string(pdev->dev.of_node,"dbgname",&(data->dbgname));
1012 pr_info("dbgname : %s\n",data->dbgname);
1016 pr_info("dbgname not assigned in device tree or device node not exist\r\n");
1018 ret = rockchip_init_iovmm(dev, &data->vmm);
1023 rwlock_init(&data->lock);
1024 INIT_LIST_HEAD(&data->node);
1026 __set_fault_handler(data, &default_fault_handler);
1028 pr_info("(%s) Initialized\n", data->dbgname);
1036 irq = platform_get_irq(pdev, i);
1037 free_irq(irq, data);
1040 while (data->num_res_mem-- > 0)
1041 iounmap(data->res_bases[data->num_res_mem]);
1042 kfree(data->res_bases);
1046 dev_err(dev, "Failed to initialize\n");
1051 static const struct of_device_id sysmmu_dt_ids[] =
1053 { .compatible = IEP_SYSMMU_COMPATIBLE_NAME},
1054 { .compatible = VIP_SYSMMU_COMPATIBLE_NAME},
1055 { .compatible = ISP0_SYSMMU_COMPATIBLE_NAME},
1056 { .compatible = ISP1_SYSMMU_COMPATIBLE_NAME},
1057 { .compatible = VOPB_SYSMMU_COMPATIBLE_NAME},
1058 { .compatible = VOPL_SYSMMU_COMPATIBLE_NAME},
1061 MODULE_DEVICE_TABLE(of, sysmmu_dt_ids);
1064 static struct platform_driver rk_sysmmu_driver =
1066 .probe = rockchip_sysmmu_probe,
1070 .name = "rk_sysmmu",
1071 .owner = THIS_MODULE,
1072 .of_match_table = of_match_ptr(sysmmu_dt_ids),
1077 /*I don't know why this can't work*/
1079 module_platform_driver(rk_sysmmu_driver);
1082 static int __init rockchip_sysmmu_init_driver(void)
1084 return platform_driver_register(&rk_sysmmu_driver);
1087 core_initcall(rockchip_sysmmu_init_driver);