drivers/iommu/rockchip-iommu.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License version 2 as
   4  * published by the Free Software Foundation.
   5  */
   6
   7 #ifdef CONFIG_ROCKCHIP_IOMMU_DEBUG
   8 #define DEBUG
   9 #endif
  10
  11 #include <linux/io.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/slab.h>
  14 #include <linux/clk.h>
  15 #include <linux/err.h>
  16 #include <linux/mm.h>
  17 #include <linux/errno.h>
  18 #include <linux/memblock.h>
  19 #include <linux/export.h>
  20 #include <linux/module.h>
  21
  22 #include <asm/cacheflush.h>
  23 #include <asm/pgtable.h>
  24 #include <linux/of.h>
  25 #include <linux/rockchip-iovmm.h>
  26 #include <linux/rockchip/grf.h>
  27 #include <linux/rockchip/cpu.h>
  28 #include <linux/rockchip/iomap.h>
  29 #include <linux/device.h>
  30 #include "rockchip-iommu.h"
  31
  32 /* We does not consider super section mapping (16MB) */
  33 #define SPAGE_ORDER 12
  34 #define SPAGE_SIZE (1 << SPAGE_ORDER)
  35 #define SPAGE_MASK (~(SPAGE_SIZE - 1))
  36
  37 static void __iomem *rk312x_vop_mmu_base;
  38
  39 enum iommu_entry_flags {
  40         IOMMU_FLAGS_PRESENT = 0x01,
  41         IOMMU_FLAGS_READ_PERMISSION = 0x02,
  42         IOMMU_FLAGS_WRITE_PERMISSION = 0x04,
  43         IOMMU_FLAGS_OVERRIDE_CACHE = 0x8,
  44         IOMMU_FLAGS_WRITE_CACHEABLE = 0x10,
  45         IOMMU_FLAGS_WRITE_ALLOCATE = 0x20,
  46         IOMMU_FLAGS_WRITE_BUFFERABLE = 0x40,
  47         IOMMU_FLAGS_READ_CACHEABLE = 0x80,
  48         IOMMU_FLAGS_READ_ALLOCATE = 0x100,
  49         IOMMU_FLAGS_MASK = 0x1FF,
  50 };
  51
  52 #define rockchip_lv1ent_fault(sent) ((*(sent) & IOMMU_FLAGS_PRESENT) == 0)
  53 #define rockchip_lv1ent_page(sent) ((*(sent) & IOMMU_FLAGS_PRESENT) == 1)
  54 #define rockchip_lv2ent_fault(pent) ((*(pent) & IOMMU_FLAGS_PRESENT) == 0)
  55 #define rockchip_spage_phys(pent) (*(pent) & SPAGE_MASK)
  56 #define rockchip_spage_offs(iova) ((iova) & 0x0FFF)
  57
  58 #define rockchip_lv1ent_offset(iova) (((iova)>>22) & 0x03FF)
  59 #define rockchip_lv2ent_offset(iova) (((iova)>>12) & 0x03FF)
  60
  61 #define NUM_LV1ENTRIES 1024
  62 #define NUM_LV2ENTRIES 1024
  63
  64 #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(long))
  65
  66 #define rockchip_lv2table_base(sent) (*(sent) & 0xFFFFFFFE)
  67
  68 #define rockchip_mk_lv1ent_page(pa) ((pa) | IOMMU_FLAGS_PRESENT)
  69 /*write and read permission for level2 page default*/
  70 #define rockchip_mk_lv2ent_spage(pa) ((pa) | IOMMU_FLAGS_PRESENT | \
  71                              IOMMU_FLAGS_READ_PERMISSION | \
  72                              IOMMU_FLAGS_WRITE_PERMISSION)
  73
  74 #define IOMMU_REG_POLL_COUNT_FAST 1000
  75
  76 /**
  77  * MMU register numbers
  78  * Used in the register read/write routines.
  79  * See the hardware documentation for more information about each register
  80  */
  81 enum iommu_register {
  82         /**< Current Page Directory Pointer */
  83         IOMMU_REGISTER_DTE_ADDR = 0x0000,
  84         /**< Status of the MMU */
  85         IOMMU_REGISTER_STATUS = 0x0004,
  86         /**< Command register, used to control the MMU */
  87         IOMMU_REGISTER_COMMAND = 0x0008,
  88         /**< Logical address of the last page fault */
  89         IOMMU_REGISTER_PAGE_FAULT_ADDR = 0x000C,
  90         /**< Used to invalidate the mapping of a single page from the MMU */
  91         IOMMU_REGISTER_ZAP_ONE_LINE = 0x010,
  92         /**< Raw interrupt status, all interrupts visible */
  93         IOMMU_REGISTER_INT_RAWSTAT = 0x0014,
  94         /**< Indicate to the MMU that the interrupt has been received */
  95         IOMMU_REGISTER_INT_CLEAR = 0x0018,
  96         /**< Enable/disable types of interrupts */
  97         IOMMU_REGISTER_INT_MASK = 0x001C,
  98         /**< Interrupt status based on the mask */
  99         IOMMU_REGISTER_INT_STATUS = 0x0020,
 100         IOMMU_REGISTER_AUTO_GATING = 0x0024
 101 };
 102
 103 enum iommu_command {
 104         /**< Enable paging (memory translation) */
 105         IOMMU_COMMAND_ENABLE_PAGING = 0x00,
 106         /**< Disable paging (memory translation) */
 107         IOMMU_COMMAND_DISABLE_PAGING = 0x01,
 108         /**<  Enable stall on page fault */
 109         IOMMU_COMMAND_ENABLE_STALL = 0x02,
 110         /**< Disable stall on page fault */
 111         IOMMU_COMMAND_DISABLE_STALL = 0x03,
 112         /**< Zap the entire page table cache */
 113         IOMMU_COMMAND_ZAP_CACHE = 0x04,
 114         /**< Page fault processed */
 115         IOMMU_COMMAND_PAGE_FAULT_DONE = 0x05,
 116         /**< Reset the MMU back to power-on settings */
 117         IOMMU_COMMAND_HARD_RESET = 0x06
 118 };
 119
 120 /**
 121  * MMU interrupt register bits
 122  * Each cause of the interrupt is reported
 123  * through the (raw) interrupt status registers.
 124  * Multiple interrupts can be pending, so multiple bits
 125  * can be set at once.
 126  */
 127 enum iommu_interrupt {
 128         IOMMU_INTERRUPT_PAGE_FAULT = 0x01, /**< A page fault occured */
 129         IOMMU_INTERRUPT_READ_BUS_ERROR = 0x02 /**< A bus read error occured */
 130 };
 131
 132 enum iommu_status_bits {
 133         IOMMU_STATUS_BIT_PAGING_ENABLED      = 1 << 0,
 134         IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE   = 1 << 1,
 135         IOMMU_STATUS_BIT_STALL_ACTIVE        = 1 << 2,
 136         IOMMU_STATUS_BIT_IDLE                = 1 << 3,
 137         IOMMU_STATUS_BIT_REPLAY_BUFFER_EMPTY = 1 << 4,
 138         IOMMU_STATUS_BIT_PAGE_FAULT_IS_WRITE = 1 << 5,
 139         IOMMU_STATUS_BIT_STALL_NOT_ACTIVE    = 1 << 31,
 140 };
 141
 142 /**
 143  * Size of an MMU page in bytes
 144  */
 145 #define IOMMU_PAGE_SIZE 0x1000
 146
 147 /*
 148  * Size of the address space referenced by a page table page
 149  */
 150 #define IOMMU_VIRTUAL_PAGE_SIZE 0x400000 /* 4 MiB */
 151
 152 /**
 153  * Page directory index from address
 154  * Calculates the page directory index from the given address
 155  */
 156 #define IOMMU_PDE_ENTRY(address) (((address)>>22) & 0x03FF)
 157
 158 /**
 159  * Page table index from address
 160  * Calculates the page table index from the given address
 161  */
 162 #define IOMMU_PTE_ENTRY(address) (((address)>>12) & 0x03FF)
 163
 164 /**
 165  * Extract the memory address from an PDE/PTE entry
 166  */
 167 #define IOMMU_ENTRY_ADDRESS(value) ((value) & 0xFFFFFC00)
 168
 169 #define INVALID_PAGE ((u32)(~0))
 170
 171 static struct kmem_cache *lv2table_kmem_cache;
 172
 173 static unsigned long *rockchip_section_entry(unsigned long *pgtable, unsigned long iova)
 174 {
 175         return pgtable + rockchip_lv1ent_offset(iova);
 176 }
 177
 178 static unsigned long *rockchip_page_entry(unsigned long *sent, unsigned long iova)
 179 {
 180         return (unsigned long *)__va(rockchip_lv2table_base(sent)) +
 181                 rockchip_lv2ent_offset(iova);
 182 }
 183
 184 struct rk_iommu_domain {
 185         struct list_head clients; /* list of iommu_drvdata.node */
 186         unsigned long *pgtable; /* lv1 page table, 4KB */
 187         short *lv2entcnt; /* free lv2 entry counter for each section */
 188         spinlock_t lock; /* lock for this structure */
 189         spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
 190 };
 191
 192 static bool rockchip_set_iommu_active(struct iommu_drvdata *data)
 193 {
 194         /* return true if the IOMMU was not active previously
 195            and it needs to be initialized */
 196         return ++data->activations == 1;
 197 }
 198
 199 static bool rockchip_set_iommu_inactive(struct iommu_drvdata *data)
 200 {
 201         /* return true if the IOMMU is needed to be disabled */
 202         BUG_ON(data->activations < 1);
 203         return --data->activations == 0;
 204 }
 205
 206 static bool rockchip_is_iommu_active(struct iommu_drvdata *data)
 207 {
 208         return data->activations > 0;
 209 }
 210
 211 static void rockchip_iommu_disable_stall(void __iomem *base)
 212 {
 213         int i;
 214         u32 mmu_status;
 215
 216         if (base != rk312x_vop_mmu_base) {
 217                 mmu_status = __raw_readl(base + IOMMU_REGISTER_STATUS);
 218         } else {
 219                 goto skip_vop_mmu_disable;
 220         }
 221
 222         if (0 == (mmu_status & IOMMU_STATUS_BIT_PAGING_ENABLED)) {
 223                 return;
 224         }
 225
 226         if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE) {
 227                 pr_info("Aborting MMU disable stall request since it is in pagefault state.\n");
 228                 return;
 229         }
 230
 231         if (!(mmu_status & IOMMU_STATUS_BIT_STALL_ACTIVE)) {
 232                 return;
 233         }
 234
 235         skip_vop_mmu_disable:
 236         __raw_writel(IOMMU_COMMAND_DISABLE_STALL, base + IOMMU_REGISTER_COMMAND);
 237
 238         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 239                 u32 status;
 240
 241                 if (base != rk312x_vop_mmu_base) {
 242                         status = __raw_readl(base + IOMMU_REGISTER_STATUS);
 243                 } else {
 244                         int j;
 245                         while (j < 5)
 246                                 j++;
 247                         return;
 248                 }
 249
 250                 if (0 == (status & IOMMU_STATUS_BIT_STALL_ACTIVE))
 251                         break;
 252
 253                 if (status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE)
 254                         break;
 255
 256                 if (0 == (mmu_status & IOMMU_STATUS_BIT_PAGING_ENABLED))
 257                         break;
 258         }
 259
 260         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 261                 pr_info("Disable stall request failed, MMU status is 0x%08X\n",
 262                       __raw_readl(base + IOMMU_REGISTER_STATUS));
 263         }
 264 }
 265
 266 static bool rockchip_iommu_enable_stall(void __iomem *base)
 267 {
 268         int i;
 269
 270         u32 mmu_status;
 271
 272         if (base != rk312x_vop_mmu_base) {
 273                 mmu_status = __raw_readl(base + IOMMU_REGISTER_STATUS);
 274         } else {
 275                 goto skip_vop_mmu_enable;
 276         }
 277
 278         if (0 == (mmu_status & IOMMU_STATUS_BIT_PAGING_ENABLED)) {
 279                 return true;
 280         }
 281
 282         if (mmu_status & IOMMU_STATUS_BIT_STALL_ACTIVE){
 283                 pr_info("MMU stall already enabled\n");
 284                 return true;
 285         }
 286
 287         if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE) {
 288                 pr_info("Aborting MMU stall request since it is in pagefault state. mmu status is 0x%08x\n",
 289                         mmu_status);
 290                 return false;
 291         }
 292
 293         skip_vop_mmu_enable:
 294         __raw_writel(IOMMU_COMMAND_ENABLE_STALL, base + IOMMU_REGISTER_COMMAND);
 295
 296         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 297                 if (base != rk312x_vop_mmu_base) {
 298                         mmu_status = __raw_readl(base + IOMMU_REGISTER_STATUS);
 299                 } else {
 300                         int j;
 301                         while (j < 5)
 302                                 j++;
 303                         return true;
 304                 }
 305
 306                 if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE)
 307                         break;
 308
 309                 if ((mmu_status & IOMMU_STATUS_BIT_STALL_ACTIVE) &&
 310                     (0 == (mmu_status & IOMMU_STATUS_BIT_STALL_NOT_ACTIVE)))
 311                         break;
 312
 313                 if (0 == (mmu_status & (IOMMU_STATUS_BIT_PAGING_ENABLED)))
 314                         break;
 315         }
 316
 317         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 318                 pr_info("Enable stall request failed, MMU status is 0x%08X\n",
 319                        __raw_readl(base + IOMMU_REGISTER_STATUS));
 320                 return false;
 321         }
 322
 323         if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE) {
 324                 pr_info("Aborting MMU stall request since it has a pagefault.\n");
 325                 return false;
 326         }
 327
 328         return true;
 329 }
 330
 331 static bool rockchip_iommu_enable_paging(void __iomem *base)
 332 {
 333         int i;
 334
 335         __raw_writel(IOMMU_COMMAND_ENABLE_PAGING,
 336                      base + IOMMU_REGISTER_COMMAND);
 337
 338         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 339                 if (base != rk312x_vop_mmu_base) {
 340                         if (__raw_readl(base + IOMMU_REGISTER_STATUS) &
 341                                 IOMMU_STATUS_BIT_PAGING_ENABLED)
 342                         break;
 343                 } else {
 344                         int j;
 345                         while (j < 5)
 346                                 j++;
 347                         return true;
 348                 }
 349         }
 350
 351         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 352                 pr_info("Enable paging request failed, MMU status is 0x%08X\n",
 353                        __raw_readl(base + IOMMU_REGISTER_STATUS));
 354                 return false;
 355         }
 356
 357         return true;
 358 }
 359
 360 static bool rockchip_iommu_disable_paging(void __iomem *base)
 361 {
 362         int i;
 363
 364         __raw_writel(IOMMU_COMMAND_DISABLE_PAGING,
 365                      base + IOMMU_REGISTER_COMMAND);
 366
 367         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 368                 if (base != rk312x_vop_mmu_base) {
 369                         if (!(__raw_readl(base + IOMMU_REGISTER_STATUS) &
 370                                   IOMMU_STATUS_BIT_PAGING_ENABLED))
 371                                 break;
 372                 } else {
 373                         int j;
 374                         while (j < 5)
 375                                 j++;
 376                         return true;
 377                 }
 378         }
 379
 380         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 381                 pr_info("Disable paging request failed, MMU status is 0x%08X\n",
 382                        __raw_readl(base + IOMMU_REGISTER_STATUS));
 383                 return false;
 384         }
 385
 386         return true;
 387 }
 388
 389 static void rockchip_iommu_page_fault_done(void __iomem *base, const char *dbgname)
 390 {
 391         pr_info("MMU: %s: Leaving page fault mode\n",
 392                 dbgname);
 393         __raw_writel(IOMMU_COMMAND_PAGE_FAULT_DONE,
 394                      base + IOMMU_REGISTER_COMMAND);
 395 }
 396 #if 1
 397 static int rockchip_iommu_zap_tlb_without_stall (void __iomem *base)
 398 {
 399         __raw_writel(IOMMU_COMMAND_ZAP_CACHE, base + IOMMU_REGISTER_COMMAND);
 400
 401         return 0;
 402 }
 403 #endif
 404
 405 #if 0
 406 static int rockchip_iommu_zap_tlb(void __iomem *base)
 407 {
 408         if (!rockchip_iommu_enable_stall(base)) {
 409                 pr_err("%s failed\n", __func__);
 410                 return -1;
 411         }
 412
 413         __raw_writel(IOMMU_COMMAND_ZAP_CACHE, base + IOMMU_REGISTER_COMMAND);
 414
 415         rockchip_iommu_disable_stall(base);
 416
 417         return 0;
 418 }
 419 #endif
 420
 421 static inline bool rockchip_iommu_raw_reset(void __iomem *base)
 422 {
 423         int i;
 424         unsigned int ret;
 425         unsigned int grf_value;
 426
 427         __raw_writel(0xCAFEBABE, base + IOMMU_REGISTER_DTE_ADDR);
 428
 429         if (base != rk312x_vop_mmu_base) {
 430                 ret = __raw_readl(base + IOMMU_REGISTER_DTE_ADDR);
 431                 if (!(0xCAFEB000 == ret)) {
 432                         grf_value = readl_relaxed(RK_GRF_VIRT + RK3036_GRF_SOC_CON1);
 433                         pr_info("error when %s. grf = 0x%08x\n", __func__, grf_value);
 434                         return false;
 435                 }
 436         }
 437         __raw_writel(IOMMU_COMMAND_HARD_RESET,
 438                      base + IOMMU_REGISTER_COMMAND);
 439
 440         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
 441                 if (base != rk312x_vop_mmu_base) {
 442                         if (__raw_readl(base + IOMMU_REGISTER_DTE_ADDR) == 0)
 443                                 break;
 444                 } else {
 445                         int j;
 446                         while (j < 5)
 447                                 j++;
 448                         return true;
 449                 }
 450         }
 451
 452         if (IOMMU_REG_POLL_COUNT_FAST == i) {
 453                 pr_info("%s,Reset request failed, MMU status is 0x%08X\n",
 454                        __func__, __raw_readl(base + IOMMU_REGISTER_DTE_ADDR));
 455                 return false;
 456         }
 457         return true;
 458 }
 459
 460 static void rockchip_iommu_set_ptbase(void __iomem *base, unsigned long pgd)
 461 {
 462         __raw_writel(pgd, base + IOMMU_REGISTER_DTE_ADDR);
 463 }
 464
 465 static bool rockchip_iommu_reset(void __iomem *base, const char *dbgname)
 466 {
 467         bool ret = true;
 468
 469         ret = rockchip_iommu_raw_reset(base);
 470         if (!ret) {
 471                 pr_info("(%s), %s failed\n", dbgname, __func__);
 472                 return ret;
 473         }
 474
 475         if (base != rk312x_vop_mmu_base)
 476                 __raw_writel(IOMMU_INTERRUPT_PAGE_FAULT |
 477                              IOMMU_INTERRUPT_READ_BUS_ERROR,
 478                              base + IOMMU_REGISTER_INT_MASK);
 479         else
 480                 __raw_writel(0x00, base + IOMMU_REGISTER_INT_MASK);
 481
 482         return ret;
 483 }
 484
 485 static inline void rockchip_pgtable_flush(void *vastart, void *vaend)
 486 {
 487 #ifdef CONFIG_ARM
 488         dmac_flush_range(vastart, vaend);
 489         outer_flush_range(virt_to_phys(vastart), virt_to_phys(vaend));
 490 #elif defined(CONFIG_ARM64)
 491         __dma_flush_range(vastart, vaend);
 492 #endif
 493 }
 494
 495 static void dump_pagetbl(dma_addr_t fault_address, u32 addr_dte)
 496 {
 497         u32 dte_index, pte_index, page_offset;
 498         u32 mmu_dte_addr;
 499         phys_addr_t mmu_dte_addr_phys, dte_addr_phys;
 500         u32 *dte_addr;
 501         u32 dte;
 502         phys_addr_t pte_addr_phys = 0;
 503         u32 *pte_addr = NULL;
 504         u32 pte = 0;
 505         phys_addr_t page_addr_phys = 0;
 506         u32 page_flags = 0;
 507
 508         dte_index = rockchip_lv1ent_offset(fault_address);
 509         pte_index = rockchip_lv2ent_offset(fault_address);
 510         page_offset = (u32)(fault_address & 0x00000fff);
 511
 512         mmu_dte_addr = addr_dte;
 513         mmu_dte_addr_phys = (phys_addr_t)mmu_dte_addr;
 514
 515         dte_addr_phys = mmu_dte_addr_phys + (4 * dte_index);
 516         dte_addr = phys_to_virt(dte_addr_phys);
 517         dte = *dte_addr;
 518
 519         if (!(IOMMU_FLAGS_PRESENT & dte))
 520                 goto print_it;
 521
 522         pte_addr_phys = ((phys_addr_t)dte & 0xfffff000) + (pte_index * 4);
 523         pte_addr = phys_to_virt(pte_addr_phys);
 524         pte = *pte_addr;
 525
 526         if (!(IOMMU_FLAGS_PRESENT & pte))
 527                 goto print_it;
 528
 529         page_addr_phys = ((phys_addr_t)pte & 0xfffff000) + page_offset;
 530         page_flags = pte & 0x000001fe;
 531
 532 print_it:
 533         pr_err("iova = %pad: dte_index: 0x%03x pte_index: 0x%03x page_offset: 0x%03x\n",
 534                 &fault_address, dte_index, pte_index, page_offset);
 535         pr_err("mmu_dte_addr: %pa dte@%pa: %#08x valid: %u pte@%pa: %#08x valid: %u page@%pa flags: %#03x\n",
 536                 &mmu_dte_addr_phys, &dte_addr_phys, dte,
 537                 (dte & IOMMU_FLAGS_PRESENT), &pte_addr_phys, pte,
 538                 (pte & IOMMU_FLAGS_PRESENT), &page_addr_phys, page_flags);
 539 }
 540
 541 static irqreturn_t rockchip_iommu_irq(int irq, void *dev_id)
 542 {
 543         /* SYSMMU is in blocked when interrupt occurred. */
 544         struct iommu_drvdata *data = dev_id;
 545         u32 status;
 546         u32 rawstat;
 547         dma_addr_t fault_address;
 548         int i;
 549         unsigned long flags;
 550         int ret;
 551         u32 reg_status;
 552
 553         spin_lock_irqsave(&data->data_lock, flags);
 554
 555         if (!rockchip_is_iommu_active(data)) {
 556                 spin_unlock_irqrestore(&data->data_lock, flags);
 557                 return IRQ_HANDLED;
 558         }
 559
 560         for (i = 0; i < data->num_res_mem; i++) {
 561                 status = __raw_readl(data->res_bases[i] +
 562                                      IOMMU_REGISTER_INT_STATUS);
 563                 if (status == 0)
 564                         continue;
 565
 566                 rawstat = __raw_readl(data->res_bases[i] +
 567                                       IOMMU_REGISTER_INT_RAWSTAT);
 568
 569                 reg_status = __raw_readl(data->res_bases[i] +
 570                                          IOMMU_REGISTER_STATUS);
 571
 572                 dev_info(data->iommu, "1.rawstat = 0x%08x,status = 0x%08x,reg_status = 0x%08x\n",
 573                          rawstat, status, reg_status);
 574
 575                 if (rawstat & IOMMU_INTERRUPT_PAGE_FAULT) {
 576                         u32 dte;
 577                         int flags;
 578
 579                         fault_address = __raw_readl(data->res_bases[i] +
 580                                             IOMMU_REGISTER_PAGE_FAULT_ADDR);
 581
 582                         dte = __raw_readl(data->res_bases[i] +
 583                                           IOMMU_REGISTER_DTE_ADDR);
 584
 585                         flags = (status & 32) ? 1 : 0;
 586
 587                         dev_err(data->iommu, "Page fault detected at %pad from bus id %d of type %s on %s\n",
 588                                 &fault_address, (status >> 6) & 0x1F,
 589                                 (flags == 1) ? "write" : "read", data->dbgname);
 590
 591                         dump_pagetbl(fault_address, dte);
 592
 593                         if (data->domain)
 594                                 report_iommu_fault(data->domain, data->iommu,
 595                                                    fault_address, flags);
 596
 597                         rockchip_iommu_page_fault_done(data->res_bases[i],
 598                                                        data->dbgname);
 599                 }
 600
 601                 if (rawstat & IOMMU_INTERRUPT_READ_BUS_ERROR) {
 602                         dev_err(data->iommu, "bus error occured at %pad\n",
 603                                 &fault_address);
 604                 }
 605
 606                 if (rawstat & ~(IOMMU_INTERRUPT_READ_BUS_ERROR |
 607                     IOMMU_INTERRUPT_PAGE_FAULT)) {
 608                         dev_err(data->iommu, "unexpected int_status: %#08x\n\n",
 609                                 rawstat);
 610                 }
 611
 612                 __raw_writel(rawstat, data->res_bases[i] +
 613                              IOMMU_REGISTER_INT_CLEAR);
 614
 615                 status = __raw_readl(data->res_bases[i] +
 616                                      IOMMU_REGISTER_INT_STATUS);
 617
 618                 rawstat = __raw_readl(data->res_bases[i] +
 619                                       IOMMU_REGISTER_INT_RAWSTAT);
 620
 621                 reg_status = __raw_readl(data->res_bases[i] +
 622                                          IOMMU_REGISTER_STATUS);
 623
 624                 dev_info(data->iommu, "2.rawstat = 0x%08x,status = 0x%08x,reg_status = 0x%08x\n",
 625                          rawstat, status, reg_status);
 626
 627                 ret = rockchip_iommu_zap_tlb_without_stall(data->res_bases[i]);
 628                 if (ret)
 629                         dev_err(data->iommu, "(%s) %s failed\n", data->dbgname,
 630                                 __func__);
 631         }
 632
 633         spin_unlock_irqrestore(&data->data_lock, flags);
 634         return IRQ_HANDLED;
 635 }
 636
 637 static bool rockchip_iommu_disable(struct iommu_drvdata *data)
 638 {
 639         unsigned long flags;
 640         int i;
 641         bool ret = false;
 642
 643         spin_lock_irqsave(&data->data_lock, flags);
 644
 645         if (!rockchip_set_iommu_inactive(data)) {
 646                 spin_unlock_irqrestore(&data->data_lock, flags);
 647                 dev_info(data->iommu,"(%s) %d times left to be disabled\n",
 648                          data->dbgname, data->activations);
 649                 return ret;
 650         }
 651
 652         for (i = 0; i < data->num_res_mem; i++) {
 653                 ret = rockchip_iommu_enable_stall(data->res_bases[i]);
 654                 if (!ret) {
 655                         dev_info(data->iommu, "(%s), %s failed\n",
 656                                  data->dbgname, __func__);
 657                         spin_unlock_irqrestore(&data->data_lock, flags);
 658                         return false;
 659                 }
 660
 661                 __raw_writel(0, data->res_bases[i] + IOMMU_REGISTER_INT_MASK);
 662
 663                 ret = rockchip_iommu_disable_paging(data->res_bases[i]);
 664                 if (!ret) {
 665                         rockchip_iommu_disable_stall(data->res_bases[i]);
 666                         spin_unlock_irqrestore(&data->data_lock, flags);
 667                         dev_info(data->iommu, "%s error\n", __func__);
 668                         return ret;
 669                 }
 670                 rockchip_iommu_disable_stall(data->res_bases[i]);
 671         }
 672
 673         data->pgtable = 0;
 674
 675         spin_unlock_irqrestore(&data->data_lock, flags);
 676
 677         dev_dbg(data->iommu,"(%s) Disabled\n", data->dbgname);
 678
 679         return ret;
 680 }
 681
 682 /* __rk_sysmmu_enable: Enables System MMU
 683  *
 684  * returns -error if an error occurred and System MMU is not enabled,
 685  * 0 if the System MMU has been just enabled and 1 if System MMU was already
 686  * enabled before.
 687  */
 688 static int rockchip_iommu_enable(struct iommu_drvdata *data, unsigned long pgtable)
 689 {
 690         int i, ret = 0;
 691         unsigned long flags;
 692
 693         spin_lock_irqsave(&data->data_lock, flags);
 694
 695         if (!rockchip_set_iommu_active(data)) {
 696                 if (WARN_ON(pgtable != data->pgtable)) {
 697                         ret = -EBUSY;
 698                         rockchip_set_iommu_inactive(data);
 699                 } else {
 700                         ret = 1;
 701                 }
 702
 703                 spin_unlock_irqrestore(&data->data_lock, flags);
 704                 dev_info(data->iommu, "(%s) Already enabled\n", data->dbgname);
 705
 706                 return ret;
 707         }
 708
 709         for (i = 0; i < data->num_res_mem; i++) {
 710                 ret = rockchip_iommu_enable_stall(data->res_bases[i]);
 711                 if (!ret) {
 712                         dev_info(data->iommu, "(%s), %s failed\n",
 713                                  data->dbgname, __func__);
 714                         spin_unlock_irqrestore(&data->data_lock, flags);
 715                         return -EBUSY;
 716                 }
 717
 718                 if (!strstr(data->dbgname, "isp")) {
 719                         if (!rockchip_iommu_reset(data->res_bases[i],
 720                              data->dbgname)) {
 721                                 spin_unlock_irqrestore(&data->data_lock, flags);
 722                                 return -ENOENT;
 723                         }
 724                 }
 725
 726                 rockchip_iommu_set_ptbase(data->res_bases[i], pgtable);
 727
 728                 __raw_writel(IOMMU_COMMAND_ZAP_CACHE, data->res_bases[i] +
 729                              IOMMU_REGISTER_COMMAND);
 730
 731                 __raw_writel(IOMMU_INTERRUPT_PAGE_FAULT |
 732                              IOMMU_INTERRUPT_READ_BUS_ERROR,
 733                              data->res_bases[i] + IOMMU_REGISTER_INT_MASK);
 734
 735                 ret = rockchip_iommu_enable_paging(data->res_bases[i]);
 736                 if (!ret) {
 737                         spin_unlock_irqrestore(&data->data_lock, flags);
 738                         dev_info(data->iommu, "(%s), %s failed\n",
 739                                  data->dbgname, __func__);
 740                         return -EBUSY;
 741                 }
 742
 743                 rockchip_iommu_disable_stall(data->res_bases[i]);
 744         }
 745
 746         data->pgtable = pgtable;
 747
 748         dev_dbg(data->iommu,"(%s) Enabled\n", data->dbgname);
 749
 750         spin_unlock_irqrestore(&data->data_lock, flags);
 751
 752         return 0;
 753 }
 754
 755 int rockchip_iommu_tlb_invalidate(struct device *dev)
 756 {
 757         unsigned long flags;
 758         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 759
 760         spin_lock_irqsave(&data->data_lock, flags);
 761
 762         if (rockchip_is_iommu_active(data)) {
 763                 int i;
 764                 int ret;
 765
 766                 for (i = 0; i < data->num_res_mem; i++) {
 767                         ret = rockchip_iommu_zap_tlb_without_stall(data->res_bases[i]);
 768                         if (ret) {
 769                                 dev_err(dev->archdata.iommu, "(%s) %s failed\n",
 770                                         data->dbgname, __func__);
 771                                 spin_unlock_irqrestore(&data->data_lock, flags);
 772                                 return ret;
 773                         }
 774
 775                 }
 776         } else {
 777                 dev_dbg(dev->archdata.iommu, "(%s) Disabled. Skipping invalidating TLB.\n",
 778                         data->dbgname);
 779         }
 780
 781         spin_unlock_irqrestore(&data->data_lock, flags);
 782
 783         return 0;
 784 }
 785
 786 static phys_addr_t rockchip_iommu_iova_to_phys(struct iommu_domain *domain,
 787                                                dma_addr_t iova)
 788 {
 789         struct rk_iommu_domain *priv = domain->priv;
 790         unsigned long *entry;
 791         unsigned long flags;
 792         phys_addr_t phys = 0;
 793
 794         spin_lock_irqsave(&priv->pgtablelock, flags);
 795
 796         entry = rockchip_section_entry(priv->pgtable, iova);
 797         entry = rockchip_page_entry(entry, iova);
 798         phys = rockchip_spage_phys(entry) + rockchip_spage_offs(iova);
 799
 800         spin_unlock_irqrestore(&priv->pgtablelock, flags);
 801
 802         return phys;
 803 }
 804
 805 static int rockchip_lv2set_page(unsigned long *pent, phys_addr_t paddr,
 806                        size_t size, short *pgcnt)
 807 {
 808         if (!rockchip_lv2ent_fault(pent))
 809                 return -EADDRINUSE;
 810
 811         *pent = rockchip_mk_lv2ent_spage(paddr);
 812         rockchip_pgtable_flush(pent, pent + 1);
 813         *pgcnt -= 1;
 814         return 0;
 815 }
 816
 817 static unsigned long *rockchip_alloc_lv2entry(unsigned long *sent,
 818                                      unsigned long iova, short *pgcounter)
 819 {
 820         if (rockchip_lv1ent_fault(sent)) {
 821                 unsigned long *pent;
 822
 823                 pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
 824                 BUG_ON((unsigned long)pent & (LV2TABLE_SIZE - 1));
 825                 if (!pent)
 826                         return NULL;
 827
 828                 *sent = rockchip_mk_lv1ent_page(__pa(pent));
 829                 kmemleak_ignore(pent);
 830                 *pgcounter = NUM_LV2ENTRIES;
 831                 rockchip_pgtable_flush(pent, pent + NUM_LV2ENTRIES);
 832                 rockchip_pgtable_flush(sent, sent + 1);
 833         }
 834         return rockchip_page_entry(sent, iova);
 835 }
 836
 837 static size_t rockchip_iommu_unmap(struct iommu_domain *domain,
 838                                    unsigned long iova, size_t size)
 839 {
 840         struct rk_iommu_domain *priv = domain->priv;
 841         unsigned long flags;
 842         unsigned long *ent;
 843
 844         BUG_ON(priv->pgtable == NULL);
 845
 846         spin_lock_irqsave(&priv->pgtablelock, flags);
 847
 848         ent = rockchip_section_entry(priv->pgtable, iova);
 849
 850         if (unlikely(rockchip_lv1ent_fault(ent))) {
 851                 if (size > SPAGE_SIZE)
 852                         size = SPAGE_SIZE;
 853                 goto done;
 854         }
 855
 856         /* lv1ent_page(sent) == true here */
 857
 858         ent = rockchip_page_entry(ent, iova);
 859
 860         if (unlikely(rockchip_lv2ent_fault(ent))) {
 861                 size = SPAGE_SIZE;
 862                 goto done;
 863         }
 864
 865         *ent = 0;
 866         size = SPAGE_SIZE;
 867         priv->lv2entcnt[rockchip_lv1ent_offset(iova)] += 1;
 868         goto done;
 869
 870 done:
 871         #if 0
 872         pr_info("%s:unmap iova 0x%lx/0x%x bytes\n",
 873                   __func__, iova,size);
 874         #endif
 875         spin_unlock_irqrestore(&priv->pgtablelock, flags);
 876
 877         return size;
 878 }
 879
 880 static int rockchip_iommu_map(struct iommu_domain *domain, unsigned long iova,
 881                               phys_addr_t paddr, size_t size, int prot)
 882 {
 883         struct rk_iommu_domain *priv = domain->priv;
 884         unsigned long *entry;
 885         unsigned long flags;
 886         int ret = -ENOMEM;
 887         unsigned long *pent;
 888
 889         BUG_ON(priv->pgtable == NULL);
 890
 891         spin_lock_irqsave(&priv->pgtablelock, flags);
 892
 893         entry = rockchip_section_entry(priv->pgtable, iova);
 894
 895         pent = rockchip_alloc_lv2entry(entry, iova,
 896                               &priv->lv2entcnt[rockchip_lv1ent_offset(iova)]);
 897         if (!pent)
 898                 ret = -ENOMEM;
 899         else
 900                 ret = rockchip_lv2set_page(pent, paddr, size,
 901                                 &priv->lv2entcnt[rockchip_lv1ent_offset(iova)]);
 902
 903         if (ret) {
 904                 pr_info("%s: Failed to map iova 0x%lx/0x%x bytes\n", __func__,
 905                        iova, size);
 906         }
 907         spin_unlock_irqrestore(&priv->pgtablelock, flags);
 908
 909         return ret;
 910 }
 911
 912 static void rockchip_iommu_detach_device(struct iommu_domain *domain, struct device *dev)
 913 {
 914         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 915         struct rk_iommu_domain *priv = domain->priv;
 916         struct list_head *pos;
 917         unsigned long flags;
 918         bool found = false;
 919
 920         spin_lock_irqsave(&priv->lock, flags);
 921
 922         list_for_each(pos, &priv->clients) {
 923                 if (list_entry(pos, struct iommu_drvdata, node) == data) {
 924                         found = true;
 925                         break;
 926                 }
 927         }
 928
 929         if (!found) {
 930                 spin_unlock_irqrestore(&priv->lock, flags);
 931                 return;
 932         }
 933
 934         if (rockchip_iommu_disable(data)) {
 935                 dev_dbg(dev->archdata.iommu,"%s: Detached IOMMU with pgtable %#lx\n",
 936                         __func__, __pa(priv->pgtable));
 937                 data->domain = NULL;
 938                 list_del_init(&data->node);
 939
 940         } else
 941                 dev_err(dev->archdata.iommu,"%s: Detaching IOMMU with pgtable %#lx delayed",
 942                         __func__, __pa(priv->pgtable));
 943
 944         spin_unlock_irqrestore(&priv->lock, flags);
 945 }
 946
 947 static int rockchip_iommu_attach_device(struct iommu_domain *domain, struct device *dev)
 948 {
 949         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 950         struct rk_iommu_domain *priv = domain->priv;
 951         unsigned long flags;
 952         int ret;
 953
 954         spin_lock_irqsave(&priv->lock, flags);
 955
 956         ret = rockchip_iommu_enable(data, __pa(priv->pgtable));
 957
 958         if (ret == 0) {
 959                 /* 'data->node' must not be appeared in priv->clients */
 960                 BUG_ON(!list_empty(&data->node));
 961                 list_add_tail(&data->node, &priv->clients);
 962                 data->domain = domain;
 963         }
 964
 965         spin_unlock_irqrestore(&priv->lock, flags);
 966
 967         if (ret < 0) {
 968                 dev_err(dev->archdata.iommu,"%s: Failed to attach IOMMU with pgtable %#lx\n",
 969                        __func__, __pa(priv->pgtable));
 970         } else if (ret > 0) {
 971                 dev_dbg(dev->archdata.iommu,"%s: IOMMU with pgtable 0x%lx already attached\n",
 972                         __func__, __pa(priv->pgtable));
 973         } else {
 974                 dev_dbg(dev->archdata.iommu,"%s: Attached new IOMMU with pgtable 0x%lx\n",
 975                         __func__, __pa(priv->pgtable));
 976         }
 977
 978         return ret;
 979 }
 980
 981 static void rockchip_iommu_domain_destroy(struct iommu_domain *domain)
 982 {
 983         struct rk_iommu_domain *priv = domain->priv;
 984         int i;
 985
 986         WARN_ON(!list_empty(&priv->clients));
 987
 988         for (i = 0; i < NUM_LV1ENTRIES; i++)
 989                 if (rockchip_lv1ent_page(priv->pgtable + i))
 990                         kmem_cache_free(lv2table_kmem_cache,
 991                                         __va(rockchip_lv2table_base(priv->pgtable + i)));
 992
 993         free_pages((unsigned long)priv->pgtable, 0);
 994         free_pages((unsigned long)priv->lv2entcnt, 0);
 995         kfree(domain->priv);
 996         domain->priv = NULL;
 997 }
 998
 999 static int rockchip_iommu_domain_init(struct iommu_domain *domain)
1000 {
1001         struct rk_iommu_domain *priv;
1002
1003         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1004         if (!priv)
1005                 return -ENOMEM;
1006
1007 /*rk32xx iommu use 2 level pagetable,
1008    level1 and leve2 both have 1024 entries,each entry  occupy 4 bytes,
1009    so alloc a page size for each page table
1010 */
1011         priv->pgtable = (unsigned long *)__get_free_pages(GFP_KERNEL |
1012                                                           __GFP_ZERO, 0);
1013         if (!priv->pgtable)
1014                 goto err_pgtable;
1015
1016         priv->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL |
1017                                                     __GFP_ZERO, 0);
1018         if (!priv->lv2entcnt)
1019                 goto err_counter;
1020
1021         rockchip_pgtable_flush(priv->pgtable, priv->pgtable + NUM_LV1ENTRIES);
1022
1023         spin_lock_init(&priv->lock);
1024         spin_lock_init(&priv->pgtablelock);
1025         INIT_LIST_HEAD(&priv->clients);
1026
1027         domain->priv = priv;
1028         return 0;
1029
1030 err_counter:
1031         free_pages((unsigned long)priv->pgtable, 0);
1032 err_pgtable:
1033         kfree(priv);
1034         return -ENOMEM;
1035 }
1036
1037 static struct iommu_ops rk_iommu_ops = {
1038         .domain_init = &rockchip_iommu_domain_init,
1039         .domain_destroy = &rockchip_iommu_domain_destroy,
1040         .attach_dev = &rockchip_iommu_attach_device,
1041         .detach_dev = &rockchip_iommu_detach_device,
1042         .map = &rockchip_iommu_map,
1043         .unmap = &rockchip_iommu_unmap,
1044         .iova_to_phys = &rockchip_iommu_iova_to_phys,
1045         .pgsize_bitmap = SPAGE_SIZE,
1046 };
1047
1048 static int  rockchip_get_iommu_resource_num(struct platform_device *pdev,
1049                                              unsigned int type)
1050 {
1051         int num = 0;
1052         int i;
1053
1054         for (i = 0; i < pdev->num_resources; i++) {
1055                 struct resource *r = &pdev->resource[i];
1056                 if (type == resource_type(r))
1057                         num++;
1058         }
1059
1060         return num;
1061 }
1062
1063 static int rockchip_iommu_probe(struct platform_device *pdev)
1064 {
1065         int i, ret;
1066         struct device *dev;
1067         struct iommu_drvdata *data;
1068
1069         dev = &pdev->dev;
1070
1071         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
1072         if (!data) {
1073                 dev_dbg(dev, "Not enough memory\n");
1074                 return -ENOMEM;
1075         }
1076
1077         dev_set_drvdata(dev, data);
1078
1079         if (pdev->dev.of_node)
1080                 of_property_read_string(pdev->dev.of_node, "dbgname",
1081                                         &(data->dbgname));
1082         else
1083                 dev_dbg(dev, "dbgname not assigned in device tree or device node not exist\r\n");
1084
1085         dev_info(dev,"(%s) Enter\n", data->dbgname);
1086
1087         data->num_res_mem = rockchip_get_iommu_resource_num(pdev,
1088                                 IORESOURCE_MEM);
1089         if (0 == data->num_res_mem) {
1090                 dev_err(dev,"can't find iommu memory resource \r\n");
1091                 return -ENOMEM;
1092         }
1093         dev_dbg(dev,"data->num_res_mem=%d\n", data->num_res_mem);
1094
1095         data->num_res_irq = rockchip_get_iommu_resource_num(pdev,
1096                                 IORESOURCE_IRQ);
1097         if (0 == data->num_res_irq) {
1098                 dev_err(dev,"can't find iommu irq resource \r\n");
1099                 return -ENOMEM;
1100         }
1101         dev_dbg(dev,"data->num_res_irq=%d\n", data->num_res_irq);
1102
1103         data->res_bases = devm_kmalloc_array(dev, data->num_res_mem,
1104                                 sizeof(*data->res_bases), GFP_KERNEL);
1105         if (data->res_bases == NULL) {
1106                 dev_err(dev, "Not enough memory\n");
1107                 return -ENOMEM;
1108         }
1109
1110         for (i = 0; i < data->num_res_mem; i++) {
1111                 struct resource *res;
1112
1113                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1114                 if (!res) {
1115                         dev_err(dev,"Unable to find IOMEM region\n");
1116                         return -ENOENT;
1117                 }
1118
1119                 data->res_bases[i] = devm_ioremap(dev,res->start,
1120                                                   resource_size(res));
1121                 if (!data->res_bases[i]) {
1122                         dev_err(dev, "Unable to map IOMEM @ PA:%#x\n",
1123                                 res->start);
1124                         return -ENOMEM;
1125                 }
1126
1127                 dev_dbg(dev,"res->start = 0x%08x ioremap to data->res_bases[%d] = 0x%08x\n",
1128                         res->start, i, (unsigned int)data->res_bases[i]);
1129
1130                 if (strstr(data->dbgname, "vop") &&
1131                     (soc_is_rk3128() || soc_is_rk3126())) {
1132                         rk312x_vop_mmu_base = data->res_bases[0];
1133                         dev_dbg(dev, "rk312x_vop_mmu_base = 0x%08x\n",
1134                                 (unsigned int)rk312x_vop_mmu_base);
1135                 }
1136         }
1137
1138         for (i = 0; i < data->num_res_irq; i++) {
1139                 if ((soc_is_rk3128() || soc_is_rk3126()) &&
1140                     strstr(data->dbgname, "vop")) {
1141                         dev_info(dev, "skip request vop mmu irq\n");
1142                         continue;
1143                 }
1144
1145                 ret = platform_get_irq(pdev, i);
1146                 if (ret <= 0) {
1147                         dev_err(dev,"Unable to find IRQ resource\n");
1148                         return -ENOENT;
1149                 }
1150
1151                 ret = devm_request_irq(dev, ret, rockchip_iommu_irq,
1152                                   IRQF_SHARED, dev_name(dev), data);
1153                 if (ret) {
1154                         dev_err(dev, "Unabled to register interrupt handler\n");
1155                         return -ENOENT;
1156                 }
1157         }
1158
1159         ret = rockchip_init_iovmm(dev, &data->vmm);
1160         if (ret)
1161                 return ret;
1162
1163         data->iommu = dev;
1164         spin_lock_init(&data->data_lock);
1165         INIT_LIST_HEAD(&data->node);
1166
1167         dev_info(dev,"(%s) Initialized\n", data->dbgname);
1168
1169         return 0;
1170 }
1171
1172 #ifdef CONFIG_OF
1173 static const struct of_device_id iommu_dt_ids[] = {
1174         { .compatible = IEP_IOMMU_COMPATIBLE_NAME},
1175         { .compatible = VIP_IOMMU_COMPATIBLE_NAME},
1176         { .compatible = VOPB_IOMMU_COMPATIBLE_NAME},
1177         { .compatible = VOPL_IOMMU_COMPATIBLE_NAME},
1178         { .compatible = HEVC_IOMMU_COMPATIBLE_NAME},
1179         { .compatible = VPU_IOMMU_COMPATIBLE_NAME},
1180         { .compatible = ISP_IOMMU_COMPATIBLE_NAME},
1181         { .compatible = VOP_IOMMU_COMPATIBLE_NAME},
1182         { /* end */ }
1183 };
1184
1185 MODULE_DEVICE_TABLE(of, iommu_dt_ids);
1186 #endif
1187
1188 static struct platform_driver rk_iommu_driver = {
1189         .probe = rockchip_iommu_probe,
1190         .remove = NULL,
1191         .driver = {
1192                    .name = "rk_iommu",
1193                    .owner = THIS_MODULE,
1194                    .of_match_table = of_match_ptr(iommu_dt_ids),
1195         },
1196 };
1197
1198 static int __init rockchip_iommu_init_driver(void)
1199 {
1200         int ret;
1201
1202         lv2table_kmem_cache = kmem_cache_create("rk-iommu-lv2table",
1203                                                 LV2TABLE_SIZE, LV2TABLE_SIZE,
1204                                                 0, NULL);
1205         if (!lv2table_kmem_cache) {
1206                 pr_info("%s: failed to create kmem cache\n", __func__);
1207                 return -ENOMEM;
1208         }
1209
1210         ret = bus_set_iommu(&platform_bus_type, &rk_iommu_ops);
1211         if (ret)
1212                 return ret;
1213
1214         return platform_driver_register(&rk_iommu_driver);
1215 }
1216
1217 core_initcall(rockchip_iommu_init_driver);