2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
8 #include <linux/compiler.h>
9 #include <linux/delay.h>
10 #include <linux/device.h>
11 #include <linux/dma-iommu.h>
12 #include <linux/errno.h>
13 #include <linux/interrupt.h>
15 #include <linux/iommu.h>
16 #include <linux/jiffies.h>
17 #include <linux/list.h>
19 #include <linux/module.h>
21 #include <linux/of_platform.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
27 /** MMU register offsets */
28 #define RK_MMU_DTE_ADDR 0x00 /* Directory table address */
29 #define RK_MMU_STATUS 0x04
30 #define RK_MMU_COMMAND 0x08
31 #define RK_MMU_PAGE_FAULT_ADDR 0x0C /* IOVA of last page fault */
32 #define RK_MMU_ZAP_ONE_LINE 0x10 /* Shootdown one IOTLB entry */
33 #define RK_MMU_INT_RAWSTAT 0x14 /* IRQ status ignoring mask */
34 #define RK_MMU_INT_CLEAR 0x18 /* Acknowledge and re-arm irq */
35 #define RK_MMU_INT_MASK 0x1C /* IRQ enable */
36 #define RK_MMU_INT_STATUS 0x20 /* IRQ status after masking */
37 #define RK_MMU_AUTO_GATING 0x24
39 #define DTE_ADDR_DUMMY 0xCAFEBABE
40 #define FORCE_RESET_TIMEOUT 100 /* ms */
42 /* RK_MMU_STATUS fields */
43 #define RK_MMU_STATUS_PAGING_ENABLED BIT(0)
44 #define RK_MMU_STATUS_PAGE_FAULT_ACTIVE BIT(1)
45 #define RK_MMU_STATUS_STALL_ACTIVE BIT(2)
46 #define RK_MMU_STATUS_IDLE BIT(3)
47 #define RK_MMU_STATUS_REPLAY_BUFFER_EMPTY BIT(4)
48 #define RK_MMU_STATUS_PAGE_FAULT_IS_WRITE BIT(5)
49 #define RK_MMU_STATUS_STALL_NOT_ACTIVE BIT(31)
51 /* RK_MMU_COMMAND command values */
52 #define RK_MMU_CMD_ENABLE_PAGING 0 /* Enable memory translation */
53 #define RK_MMU_CMD_DISABLE_PAGING 1 /* Disable memory translation */
54 #define RK_MMU_CMD_ENABLE_STALL 2 /* Stall paging to allow other cmds */
55 #define RK_MMU_CMD_DISABLE_STALL 3 /* Stop stall re-enables paging */
56 #define RK_MMU_CMD_ZAP_CACHE 4 /* Shoot down entire IOTLB */
57 #define RK_MMU_CMD_PAGE_FAULT_DONE 5 /* Clear page fault */
58 #define RK_MMU_CMD_FORCE_RESET 6 /* Reset all registers */
60 /* RK_MMU_INT_* register fields */
61 #define RK_MMU_IRQ_PAGE_FAULT 0x01 /* page fault */
62 #define RK_MMU_IRQ_BUS_ERROR 0x02 /* bus read error */
63 #define RK_MMU_IRQ_MASK (RK_MMU_IRQ_PAGE_FAULT | RK_MMU_IRQ_BUS_ERROR)
65 #define NUM_DT_ENTRIES 1024
66 #define NUM_PT_ENTRIES 1024
68 #define SPAGE_ORDER 12
69 #define SPAGE_SIZE (1 << SPAGE_ORDER)
72 * Support mapping any size that fits in one page table:
75 #define RK_IOMMU_PGSIZE_BITMAP 0x007ff000
77 #define IOMMU_REG_POLL_COUNT_FAST 1000
79 struct rk_iommu_domain {
80 struct list_head iommus;
81 struct platform_device *pdev;
82 u32 *dt; /* page directory table */
84 struct mutex iommus_lock; /* lock for iommus list */
85 struct mutex dt_lock; /* lock for modifying page directory table */
87 struct iommu_domain domain;
95 bool reset_disabled; /* isp iommu reset operation would failed */
96 struct list_head node; /* entry in rk_iommu_domain.iommus */
97 struct iommu_domain *domain; /* domain to which iommu is attached */
98 struct clk *aclk; /* aclock belong to master */
99 struct clk *hclk; /* hclock belong to master */
102 static inline void rk_table_flush(struct rk_iommu_domain *dom, dma_addr_t dma,
105 size_t size = count * sizeof(u32); /* count of u32 entry */
107 dma_sync_single_for_device(&dom->pdev->dev, dma, size, DMA_TO_DEVICE);
110 static struct rk_iommu_domain *to_rk_domain(struct iommu_domain *dom)
112 return container_of(dom, struct rk_iommu_domain, domain);
116 * Inspired by _wait_for in intel_drv.h
117 * This is NOT safe for use in interrupt context.
119 * Note that it's important that we check the condition again after having
120 * timed out, since the timeout could be due to preemption or similar and
121 * we've never had a chance to check the condition before the timeout.
123 #define rk_wait_for(COND, MS) ({ \
124 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
127 if (time_after(jiffies, timeout__)) { \
128 ret__ = (COND) ? 0 : -ETIMEDOUT; \
131 usleep_range(50, 100); \
137 * The Rockchip rk3288 iommu uses a 2-level page table.
138 * The first level is the "Directory Table" (DT).
139 * The DT consists of 1024 4-byte Directory Table Entries (DTEs), each pointing
141 * The second level is the 1024 Page Tables (PT).
142 * Each PT consists of 1024 4-byte Page Table Entries (PTEs), each pointing to
143 * a 4 KB page of physical memory.
145 * The DT and each PT fits in a single 4 KB page (4-bytes * 1024 entries).
146 * Each iommu device has a MMU_DTE_ADDR register that contains the physical
147 * address of the start of the DT page.
149 * The structure of the page table is as follows:
152 * MMU_DTE_ADDR -> +-----+
158 * | | | PTE | -> +-----+
159 * +-----+ +-----+ | |
169 * Each DTE has a PT address and a valid bit:
170 * +---------------------+-----------+-+
171 * | PT address | Reserved |V|
172 * +---------------------+-----------+-+
173 * 31:12 - PT address (PTs always starts on a 4 KB boundary)
175 * 0 - 1 if PT @ PT address is valid
177 #define RK_DTE_PT_ADDRESS_MASK 0xfffff000
178 #define RK_DTE_PT_VALID BIT(0)
180 static inline phys_addr_t rk_dte_pt_address(u32 dte)
182 return (phys_addr_t)dte & RK_DTE_PT_ADDRESS_MASK;
185 static inline bool rk_dte_is_pt_valid(u32 dte)
187 return dte & RK_DTE_PT_VALID;
190 static inline u32 rk_mk_dte(dma_addr_t pt_dma)
192 return (pt_dma & RK_DTE_PT_ADDRESS_MASK) | RK_DTE_PT_VALID;
196 * Each PTE has a Page address, some flags and a valid bit:
197 * +---------------------+---+-------+-+
198 * | Page address |Rsv| Flags |V|
199 * +---------------------+---+-------+-+
200 * 31:12 - Page address (Pages always start on a 4 KB boundary)
203 * 8 - Read allocate - allocate cache space on read misses
204 * 7 - Read cache - enable cache & prefetch of data
205 * 6 - Write buffer - enable delaying writes on their way to memory
206 * 5 - Write allocate - allocate cache space on write misses
207 * 4 - Write cache - different writes can be merged together
208 * 3 - Override cache attributes
209 * if 1, bits 4-8 control cache attributes
210 * if 0, the system bus defaults are used
213 * 0 - 1 if Page @ Page address is valid
215 #define RK_PTE_PAGE_ADDRESS_MASK 0xfffff000
216 #define RK_PTE_PAGE_FLAGS_MASK 0x000001fe
217 #define RK_PTE_PAGE_WRITABLE BIT(2)
218 #define RK_PTE_PAGE_READABLE BIT(1)
219 #define RK_PTE_PAGE_VALID BIT(0)
221 static inline phys_addr_t rk_pte_page_address(u32 pte)
223 return (phys_addr_t)pte & RK_PTE_PAGE_ADDRESS_MASK;
226 static inline bool rk_pte_is_page_valid(u32 pte)
228 return pte & RK_PTE_PAGE_VALID;
231 /* TODO: set cache flags per prot IOMMU_CACHE */
232 static u32 rk_mk_pte(phys_addr_t page, int prot)
235 flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE : 0;
236 flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE : 0;
237 page &= RK_PTE_PAGE_ADDRESS_MASK;
238 return page | flags | RK_PTE_PAGE_VALID;
241 static u32 rk_mk_pte_invalid(u32 pte)
243 return pte & ~RK_PTE_PAGE_VALID;
247 * rk3288 iova (IOMMU Virtual Address) format
249 * +-----------+-----------+-------------+
250 * | DTE index | PTE index | Page offset |
251 * +-----------+-----------+-------------+
252 * 31:22 - DTE index - index of DTE in DT
253 * 21:12 - PTE index - index of PTE in PT @ DTE.pt_address
254 * 11: 0 - Page offset - offset into page @ PTE.page_address
256 #define RK_IOVA_DTE_MASK 0xffc00000
257 #define RK_IOVA_DTE_SHIFT 22
258 #define RK_IOVA_PTE_MASK 0x003ff000
259 #define RK_IOVA_PTE_SHIFT 12
260 #define RK_IOVA_PAGE_MASK 0x00000fff
261 #define RK_IOVA_PAGE_SHIFT 0
263 static void rk_iommu_power_on(struct rk_iommu *iommu)
265 if (iommu->aclk && iommu->hclk) {
266 clk_enable(iommu->aclk);
267 clk_enable(iommu->hclk);
270 pm_runtime_enable(iommu->dev);
271 pm_runtime_get_sync(iommu->dev);
274 static void rk_iommu_power_off(struct rk_iommu *iommu)
276 pm_runtime_put_sync(iommu->dev);
277 pm_runtime_disable(iommu->dev);
279 if (iommu->aclk && iommu->hclk) {
280 clk_disable(iommu->aclk);
281 clk_disable(iommu->hclk);
285 static u32 rk_iova_dte_index(dma_addr_t iova)
287 return (u32)(iova & RK_IOVA_DTE_MASK) >> RK_IOVA_DTE_SHIFT;
290 static u32 rk_iova_pte_index(dma_addr_t iova)
292 return (u32)(iova & RK_IOVA_PTE_MASK) >> RK_IOVA_PTE_SHIFT;
295 static u32 rk_iova_page_offset(dma_addr_t iova)
297 return (u32)(iova & RK_IOVA_PAGE_MASK) >> RK_IOVA_PAGE_SHIFT;
300 static u32 rk_iommu_read(void __iomem *base, u32 offset)
302 return readl(base + offset);
305 static void rk_iommu_write(void __iomem *base, u32 offset, u32 value)
307 writel(value, base + offset);
310 static void rk_iommu_command(struct rk_iommu *iommu, u32 command)
314 for (i = 0; i < iommu->num_mmu; i++)
315 writel(command, iommu->bases[i] + RK_MMU_COMMAND);
318 static void rk_iommu_base_command(void __iomem *base, u32 command)
320 writel(command, base + RK_MMU_COMMAND);
322 static void rk_iommu_zap_lines(struct rk_iommu *iommu, dma_addr_t iova_start,
326 dma_addr_t iova_end = iova_start + size;
328 * TODO(djkurtz): Figure out when it is more efficient to shootdown the
329 * entire iotlb rather than iterate over individual iovas.
332 rk_iommu_power_on(iommu);
334 for (i = 0; i < iommu->num_mmu; i++) {
337 for (iova = iova_start; iova < iova_end; iova += SPAGE_SIZE)
338 rk_iommu_write(iommu->bases[i], RK_MMU_ZAP_ONE_LINE, iova);
341 rk_iommu_power_off(iommu);
344 static bool rk_iommu_is_stall_active(struct rk_iommu *iommu)
349 for (i = 0; i < iommu->num_mmu; i++)
350 active &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) &
351 RK_MMU_STATUS_STALL_ACTIVE);
356 static bool rk_iommu_is_paging_enabled(struct rk_iommu *iommu)
361 for (i = 0; i < iommu->num_mmu; i++)
362 enable &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) &
363 RK_MMU_STATUS_PAGING_ENABLED);
368 static int rk_iommu_enable_stall(struct rk_iommu *iommu)
372 if (rk_iommu_is_stall_active(iommu))
375 /* Stall can only be enabled if paging is enabled */
376 if (!rk_iommu_is_paging_enabled(iommu))
379 rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_STALL);
381 ret = rk_wait_for(rk_iommu_is_stall_active(iommu), 1);
383 for (i = 0; i < iommu->num_mmu; i++)
384 dev_err(iommu->dev, "Enable stall request timed out, status: %#08x\n",
385 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
390 static int rk_iommu_disable_stall(struct rk_iommu *iommu)
394 if (!rk_iommu_is_stall_active(iommu))
397 rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_STALL);
399 ret = rk_wait_for(!rk_iommu_is_stall_active(iommu), 1);
401 for (i = 0; i < iommu->num_mmu; i++)
402 dev_err(iommu->dev, "Disable stall request timed out, status: %#08x\n",
403 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
408 static int rk_iommu_enable_paging(struct rk_iommu *iommu)
412 if (rk_iommu_is_paging_enabled(iommu))
415 rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_PAGING);
417 ret = rk_wait_for(rk_iommu_is_paging_enabled(iommu), 1);
419 for (i = 0; i < iommu->num_mmu; i++)
420 dev_err(iommu->dev, "Enable paging request timed out, status: %#08x\n",
421 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
426 static int rk_iommu_disable_paging(struct rk_iommu *iommu)
430 if (!rk_iommu_is_paging_enabled(iommu))
433 rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_PAGING);
435 ret = rk_wait_for(!rk_iommu_is_paging_enabled(iommu), 1);
437 for (i = 0; i < iommu->num_mmu; i++)
438 dev_err(iommu->dev, "Disable paging request timed out, status: %#08x\n",
439 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
444 static int rk_iommu_force_reset(struct rk_iommu *iommu)
449 /* Workaround for isp mmus */
450 if (iommu->reset_disabled)
454 * Check if register DTE_ADDR is working by writing DTE_ADDR_DUMMY
455 * and verifying that upper 5 nybbles are read back.
457 for (i = 0; i < iommu->num_mmu; i++) {
458 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, DTE_ADDR_DUMMY);
460 dte_addr = rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR);
461 if (dte_addr != (DTE_ADDR_DUMMY & RK_DTE_PT_ADDRESS_MASK)) {
462 dev_err(iommu->dev, "Error during raw reset. MMU_DTE_ADDR is not functioning\n");
467 rk_iommu_command(iommu, RK_MMU_CMD_FORCE_RESET);
469 for (i = 0; i < iommu->num_mmu; i++) {
470 ret = rk_wait_for(rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR) == 0x00000000,
471 FORCE_RESET_TIMEOUT);
473 dev_err(iommu->dev, "FORCE_RESET command timed out\n");
481 static void log_iova(struct rk_iommu *iommu, int index, dma_addr_t iova)
483 void __iomem *base = iommu->bases[index];
484 u32 dte_index, pte_index, page_offset;
486 phys_addr_t mmu_dte_addr_phys, dte_addr_phys;
489 phys_addr_t pte_addr_phys = 0;
490 u32 *pte_addr = NULL;
492 phys_addr_t page_addr_phys = 0;
495 dte_index = rk_iova_dte_index(iova);
496 pte_index = rk_iova_pte_index(iova);
497 page_offset = rk_iova_page_offset(iova);
499 mmu_dte_addr = rk_iommu_read(base, RK_MMU_DTE_ADDR);
500 mmu_dte_addr_phys = (phys_addr_t)mmu_dte_addr;
502 dte_addr_phys = mmu_dte_addr_phys + (4 * dte_index);
503 dte_addr = phys_to_virt(dte_addr_phys);
506 if (!rk_dte_is_pt_valid(dte))
509 pte_addr_phys = rk_dte_pt_address(dte) + (pte_index * 4);
510 pte_addr = phys_to_virt(pte_addr_phys);
513 if (!rk_pte_is_page_valid(pte))
516 page_addr_phys = rk_pte_page_address(pte) + page_offset;
517 page_flags = pte & RK_PTE_PAGE_FLAGS_MASK;
520 dev_err(iommu->dev, "iova = %pad: dte_index: %#03x pte_index: %#03x page_offset: %#03x\n",
521 &iova, dte_index, pte_index, page_offset);
522 dev_err(iommu->dev, "mmu_dte_addr: %pa dte@%pa: %#08x valid: %u pte@%pa: %#08x valid: %u page@%pa flags: %#03x\n",
523 &mmu_dte_addr_phys, &dte_addr_phys, dte,
524 rk_dte_is_pt_valid(dte), &pte_addr_phys, pte,
525 rk_pte_is_page_valid(pte), &page_addr_phys, page_flags);
528 static irqreturn_t rk_iommu_irq(int irq, void *dev_id)
530 struct rk_iommu *iommu = dev_id;
534 irqreturn_t ret = IRQ_NONE;
537 for (i = 0; i < iommu->num_mmu; i++) {
538 int_status = rk_iommu_read(iommu->bases[i], RK_MMU_INT_STATUS);
543 iova = rk_iommu_read(iommu->bases[i], RK_MMU_PAGE_FAULT_ADDR);
545 if (int_status & RK_MMU_IRQ_PAGE_FAULT) {
548 status = rk_iommu_read(iommu->bases[i], RK_MMU_STATUS);
549 flags = (status & RK_MMU_STATUS_PAGE_FAULT_IS_WRITE) ?
550 IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
552 dev_err(iommu->dev, "Page fault at %pad of type %s\n",
554 (flags == IOMMU_FAULT_WRITE) ? "write" : "read");
556 log_iova(iommu, i, iova);
559 * Report page fault to any installed handlers.
560 * Ignore the return code, though, since we always zap cache
561 * and clear the page fault anyway.
564 report_iommu_fault(iommu->domain, iommu->dev, iova,
567 dev_err(iommu->dev, "Page fault while iommu not attached to domain?\n");
569 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE);
570 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_PAGE_FAULT_DONE);
573 if (int_status & RK_MMU_IRQ_BUS_ERROR)
574 dev_err(iommu->dev, "BUS_ERROR occurred at %pad\n", &iova);
576 if (int_status & ~RK_MMU_IRQ_MASK)
577 dev_err(iommu->dev, "unexpected int_status: %#08x\n",
580 rk_iommu_write(iommu->bases[i], RK_MMU_INT_CLEAR, int_status);
586 static phys_addr_t rk_iommu_iova_to_phys(struct iommu_domain *domain,
589 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
590 phys_addr_t pt_phys, phys = 0;
594 mutex_lock(&rk_domain->dt_lock);
596 dte = rk_domain->dt[rk_iova_dte_index(iova)];
597 if (!rk_dte_is_pt_valid(dte))
600 pt_phys = rk_dte_pt_address(dte);
601 page_table = (u32 *)phys_to_virt(pt_phys);
602 pte = page_table[rk_iova_pte_index(iova)];
603 if (!rk_pte_is_page_valid(pte))
606 phys = rk_pte_page_address(pte) + rk_iova_page_offset(iova);
608 mutex_unlock(&rk_domain->dt_lock);
613 static void rk_iommu_zap_iova(struct rk_iommu_domain *rk_domain,
614 dma_addr_t iova, size_t size)
616 struct list_head *pos;
618 /* shootdown these iova from all iommus using this domain */
619 mutex_lock(&rk_domain->iommus_lock);
620 list_for_each(pos, &rk_domain->iommus) {
621 struct rk_iommu *iommu;
622 iommu = list_entry(pos, struct rk_iommu, node);
623 rk_iommu_zap_lines(iommu, iova, size);
625 mutex_unlock(&rk_domain->iommus_lock);
628 static void rk_iommu_zap_iova_first_last(struct rk_iommu_domain *rk_domain,
629 dma_addr_t iova, size_t size)
631 rk_iommu_zap_iova(rk_domain, iova, SPAGE_SIZE);
632 if (size > SPAGE_SIZE)
633 rk_iommu_zap_iova(rk_domain, iova + size - SPAGE_SIZE,
637 static u32 *rk_dte_get_page_table(struct rk_iommu_domain *rk_domain,
640 struct device *dev = &rk_domain->pdev->dev;
641 u32 *page_table, *dte_addr;
646 WARN_ON(!mutex_is_locked(&rk_domain->dt_lock));
648 dte_index = rk_iova_dte_index(iova);
649 dte_addr = &rk_domain->dt[dte_index];
651 if (rk_dte_is_pt_valid(dte))
654 page_table = (u32 *)get_zeroed_page(GFP_ATOMIC | GFP_DMA32);
656 return ERR_PTR(-ENOMEM);
658 pt_dma = dma_map_single(dev, page_table, SPAGE_SIZE, DMA_TO_DEVICE);
659 if (dma_mapping_error(dev, pt_dma)) {
660 dev_err(dev, "DMA mapping error while allocating page table\n");
661 free_page((unsigned long)page_table);
662 return ERR_PTR(-ENOMEM);
665 dte = rk_mk_dte(pt_dma);
668 rk_table_flush(rk_domain, pt_dma, NUM_PT_ENTRIES);
669 rk_table_flush(rk_domain,
670 rk_domain->dt_dma + dte_index * sizeof(u32), 1);
672 pt_phys = rk_dte_pt_address(dte);
673 return (u32 *)phys_to_virt(pt_phys);
676 static size_t rk_iommu_unmap_iova(struct rk_iommu_domain *rk_domain,
677 u32 *pte_addr, dma_addr_t pte_dma,
680 unsigned int pte_count;
681 unsigned int pte_total = size / SPAGE_SIZE;
683 WARN_ON(!mutex_is_locked(&rk_domain->dt_lock));
685 for (pte_count = 0; pte_count < pte_total; pte_count++) {
686 u32 pte = pte_addr[pte_count];
687 if (!rk_pte_is_page_valid(pte))
690 pte_addr[pte_count] = rk_mk_pte_invalid(pte);
693 rk_table_flush(rk_domain, pte_dma, pte_count);
695 return pte_count * SPAGE_SIZE;
698 static int rk_iommu_map_iova(struct rk_iommu_domain *rk_domain, u32 *pte_addr,
699 dma_addr_t pte_dma, dma_addr_t iova,
700 phys_addr_t paddr, size_t size, int prot)
702 unsigned int pte_count;
703 unsigned int pte_total = size / SPAGE_SIZE;
704 phys_addr_t page_phys;
706 WARN_ON(!mutex_is_locked(&rk_domain->dt_lock));
708 for (pte_count = 0; pte_count < pte_total; pte_count++) {
709 u32 pte = pte_addr[pte_count];
711 if (rk_pte_is_page_valid(pte))
714 pte_addr[pte_count] = rk_mk_pte(paddr, prot);
719 rk_table_flush(rk_domain, pte_dma, pte_total);
722 * Zap the first and last iova to evict from iotlb any previously
723 * mapped cachelines holding stale values for its dte and pte.
724 * We only zap the first and last iova, since only they could have
725 * dte or pte shared with an existing mapping.
727 rk_iommu_zap_iova_first_last(rk_domain, iova, size);
731 /* Unmap the range of iovas that we just mapped */
732 rk_iommu_unmap_iova(rk_domain, pte_addr, pte_dma,
733 pte_count * SPAGE_SIZE);
735 iova += pte_count * SPAGE_SIZE;
736 page_phys = rk_pte_page_address(pte_addr[pte_count]);
737 pr_err("iova: %pad already mapped to %pa cannot remap to phys: %pa prot: %#x\n",
738 &iova, &page_phys, &paddr, prot);
743 static int rk_iommu_map(struct iommu_domain *domain, unsigned long _iova,
744 phys_addr_t paddr, size_t size, int prot)
746 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
747 dma_addr_t pte_dma, iova = (dma_addr_t)_iova;
748 u32 *page_table, *pte_addr;
749 u32 dte_index, pte_index;
752 mutex_lock(&rk_domain->dt_lock);
755 * pgsize_bitmap specifies iova sizes that fit in one page table
756 * (1024 4-KiB pages = 4 MiB).
757 * So, size will always be 4096 <= size <= 4194304.
758 * Since iommu_map() guarantees that both iova and size will be
759 * aligned, we will always only be mapping from a single dte here.
761 page_table = rk_dte_get_page_table(rk_domain, iova);
762 if (IS_ERR(page_table)) {
763 mutex_unlock(&rk_domain->dt_lock);
764 return PTR_ERR(page_table);
767 dte_index = rk_domain->dt[rk_iova_dte_index(iova)];
768 pte_index = rk_iova_pte_index(iova);
769 pte_addr = &page_table[pte_index];
770 pte_dma = rk_dte_pt_address(dte_index) + pte_index * sizeof(u32);
771 ret = rk_iommu_map_iova(rk_domain, pte_addr, pte_dma, iova,
774 mutex_unlock(&rk_domain->dt_lock);
779 static size_t rk_iommu_unmap(struct iommu_domain *domain, unsigned long _iova,
782 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
783 dma_addr_t pte_dma, iova = (dma_addr_t)_iova;
789 mutex_lock(&rk_domain->dt_lock);
792 * pgsize_bitmap specifies iova sizes that fit in one page table
793 * (1024 4-KiB pages = 4 MiB).
794 * So, size will always be 4096 <= size <= 4194304.
795 * Since iommu_unmap() guarantees that both iova and size will be
796 * aligned, we will always only be unmapping from a single dte here.
798 dte = rk_domain->dt[rk_iova_dte_index(iova)];
799 /* Just return 0 if iova is unmapped */
800 if (!rk_dte_is_pt_valid(dte)) {
801 mutex_unlock(&rk_domain->dt_lock);
805 pt_phys = rk_dte_pt_address(dte);
806 pte_addr = (u32 *)phys_to_virt(pt_phys) + rk_iova_pte_index(iova);
807 pte_dma = pt_phys + rk_iova_pte_index(iova) * sizeof(u32);
808 unmap_size = rk_iommu_unmap_iova(rk_domain, pte_addr, pte_dma, size);
810 mutex_unlock(&rk_domain->dt_lock);
812 /* Shootdown iotlb entries for iova range that was just unmapped */
813 rk_iommu_zap_iova(rk_domain, iova, unmap_size);
818 static struct rk_iommu *rk_iommu_from_dev(struct device *dev)
820 struct iommu_group *group;
821 struct device *iommu_dev;
822 struct rk_iommu *rk_iommu;
824 group = iommu_group_get(dev);
827 iommu_dev = iommu_group_get_iommudata(group);
829 dev_info(dev, "Possibly a virtual device\n");
833 rk_iommu = dev_get_drvdata(iommu_dev);
834 iommu_group_put(group);
839 static int rk_iommu_attach_device(struct iommu_domain *domain,
842 struct rk_iommu *iommu;
843 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
847 * Allow 'virtual devices' (e.g., drm) to attach to domain.
848 * Such a device does not belong to an iommu group.
850 iommu = rk_iommu_from_dev(dev);
854 rk_iommu_power_on(iommu);
856 ret = rk_iommu_enable_stall(iommu);
860 ret = rk_iommu_force_reset(iommu);
864 iommu->domain = domain;
866 ret = devm_request_irq(iommu->dev, iommu->irq, rk_iommu_irq,
867 IRQF_SHARED, dev_name(dev), iommu);
871 for (i = 0; i < iommu->num_mmu; i++) {
872 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR,
874 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE);
875 rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, RK_MMU_IRQ_MASK);
878 ret = rk_iommu_enable_paging(iommu);
882 mutex_lock(&rk_domain->iommus_lock);
883 list_add_tail(&iommu->node, &rk_domain->iommus);
884 mutex_unlock(&rk_domain->iommus_lock);
886 dev_dbg(dev, "Attached to iommu domain\n");
888 rk_iommu_disable_stall(iommu);
893 static void rk_iommu_detach_device(struct iommu_domain *domain,
896 struct rk_iommu *iommu;
897 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
900 /* Allow 'virtual devices' (eg drm) to detach from domain */
901 iommu = rk_iommu_from_dev(dev);
905 mutex_lock(&rk_domain->iommus_lock);
906 list_del_init(&iommu->node);
907 mutex_unlock(&rk_domain->iommus_lock);
909 /* Ignore error while disabling, just keep going */
910 rk_iommu_enable_stall(iommu);
911 rk_iommu_disable_paging(iommu);
912 for (i = 0; i < iommu->num_mmu; i++) {
913 rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, 0);
914 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, 0);
916 rk_iommu_disable_stall(iommu);
918 devm_free_irq(iommu->dev, iommu->irq, iommu);
920 iommu->domain = NULL;
922 rk_iommu_power_off(iommu);
924 dev_dbg(dev, "Detached from iommu domain\n");
927 static struct iommu_domain *rk_iommu_domain_alloc(unsigned type)
929 struct rk_iommu_domain *rk_domain;
930 struct platform_device *pdev;
931 struct device *iommu_dev;
933 if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA)
936 /* Register a pdev per domain, so DMA API can base on this *dev
937 * even some virtual master doesn't have an iommu slave
939 pdev = platform_device_register_simple("rk_iommu_domain",
940 PLATFORM_DEVID_AUTO, NULL, 0);
944 rk_domain = devm_kzalloc(&pdev->dev, sizeof(*rk_domain), GFP_KERNEL);
948 rk_domain->pdev = pdev;
950 if (type == IOMMU_DOMAIN_DMA &&
951 iommu_get_dma_cookie(&rk_domain->domain))
955 * rk32xx iommus use a 2 level pagetable.
956 * Each level1 (dt) and level2 (pt) table has 1024 4-byte entries.
957 * Allocate one 4 KiB page for each table.
959 rk_domain->dt = (u32 *)get_zeroed_page(GFP_KERNEL | GFP_DMA32);
963 iommu_dev = &pdev->dev;
964 rk_domain->dt_dma = dma_map_single(iommu_dev, rk_domain->dt,
965 SPAGE_SIZE, DMA_TO_DEVICE);
966 if (dma_mapping_error(iommu_dev, rk_domain->dt_dma)) {
967 dev_err(iommu_dev, "DMA map error for DT\n");
971 rk_table_flush(rk_domain, rk_domain->dt_dma, NUM_DT_ENTRIES);
973 mutex_init(&rk_domain->iommus_lock);
974 mutex_init(&rk_domain->dt_lock);
975 INIT_LIST_HEAD(&rk_domain->iommus);
977 rk_domain->domain.geometry.aperture_start = 0;
978 rk_domain->domain.geometry.aperture_end = DMA_BIT_MASK(32);
979 rk_domain->domain.geometry.force_aperture = true;
981 return &rk_domain->domain;
984 free_page((unsigned long)rk_domain->dt);
986 if (type == IOMMU_DOMAIN_DMA)
987 iommu_put_dma_cookie(&rk_domain->domain);
989 platform_device_unregister(pdev);
994 static void rk_iommu_domain_free(struct iommu_domain *domain)
996 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
999 WARN_ON(!list_empty(&rk_domain->iommus));
1001 for (i = 0; i < NUM_DT_ENTRIES; i++) {
1002 u32 dte = rk_domain->dt[i];
1003 if (rk_dte_is_pt_valid(dte)) {
1004 phys_addr_t pt_phys = rk_dte_pt_address(dte);
1005 u32 *page_table = phys_to_virt(pt_phys);
1006 dma_unmap_single(&rk_domain->pdev->dev, pt_phys,
1007 SPAGE_SIZE, DMA_TO_DEVICE);
1008 free_page((unsigned long)page_table);
1012 dma_unmap_single(&rk_domain->pdev->dev, rk_domain->dt_dma,
1013 SPAGE_SIZE, DMA_TO_DEVICE);
1014 free_page((unsigned long)rk_domain->dt);
1016 if (domain->type == IOMMU_DOMAIN_DMA)
1017 iommu_put_dma_cookie(&rk_domain->domain);
1019 platform_device_unregister(rk_domain->pdev);
1022 static bool rk_iommu_is_dev_iommu_master(struct device *dev)
1024 struct device_node *np = dev->of_node;
1028 * An iommu master has an iommus property containing a list of phandles
1029 * to iommu nodes, each with an #iommu-cells property with value 0.
1031 ret = of_count_phandle_with_args(np, "iommus", "#iommu-cells");
1035 static int rk_iommu_group_set_iommudata(struct iommu_group *group,
1038 struct device_node *np = dev->of_node;
1039 struct platform_device *pd;
1041 struct of_phandle_args args;
1044 * An iommu master has an iommus property containing a list of phandles
1045 * to iommu nodes, each with an #iommu-cells property with value 0.
1047 ret = of_parse_phandle_with_args(np, "iommus", "#iommu-cells", 0,
1050 dev_err(dev, "of_parse_phandle_with_args(%s) => %d\n",
1051 np->full_name, ret);
1054 if (args.args_count != 0) {
1055 dev_err(dev, "incorrect number of iommu params found for %s (found %d, expected 0)\n",
1056 args.np->full_name, args.args_count);
1060 pd = of_find_device_by_node(args.np);
1061 of_node_put(args.np);
1063 dev_err(dev, "iommu %s not found\n", args.np->full_name);
1064 return -EPROBE_DEFER;
1067 /* TODO(djkurtz): handle multiple slave iommus for a single master */
1068 iommu_group_set_iommudata(group, &pd->dev, NULL);
1073 static int rk_iommu_add_device(struct device *dev)
1075 struct iommu_group *group;
1078 if (!rk_iommu_is_dev_iommu_master(dev))
1081 group = iommu_group_get(dev);
1083 group = iommu_group_alloc();
1084 if (IS_ERR(group)) {
1085 dev_err(dev, "Failed to allocate IOMMU group\n");
1086 return PTR_ERR(group);
1090 ret = iommu_group_add_device(group, dev);
1094 ret = rk_iommu_group_set_iommudata(group, dev);
1096 goto err_remove_device;
1098 iommu_group_put(group);
1103 iommu_group_remove_device(dev);
1105 iommu_group_put(group);
1109 static void rk_iommu_remove_device(struct device *dev)
1111 if (!rk_iommu_is_dev_iommu_master(dev))
1114 iommu_group_remove_device(dev);
1117 static const struct iommu_ops rk_iommu_ops = {
1118 .domain_alloc = rk_iommu_domain_alloc,
1119 .domain_free = rk_iommu_domain_free,
1120 .attach_dev = rk_iommu_attach_device,
1121 .detach_dev = rk_iommu_detach_device,
1122 .map = rk_iommu_map,
1123 .unmap = rk_iommu_unmap,
1124 .map_sg = default_iommu_map_sg,
1125 .add_device = rk_iommu_add_device,
1126 .remove_device = rk_iommu_remove_device,
1127 .iova_to_phys = rk_iommu_iova_to_phys,
1128 .pgsize_bitmap = RK_IOMMU_PGSIZE_BITMAP,
1131 static int rk_iommu_domain_probe(struct platform_device *pdev)
1133 struct device *dev = &pdev->dev;
1135 dev->dma_parms = devm_kzalloc(dev, sizeof(*dev->dma_parms), GFP_KERNEL);
1136 if (!dev->dma_parms)
1139 /* Set dma_ops for dev, otherwise it would be dummy_dma_ops */
1140 arch_setup_dma_ops(dev, 0, DMA_BIT_MASK(32), NULL, false);
1142 dma_set_max_seg_size(dev, DMA_BIT_MASK(32));
1143 dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
1148 static struct platform_driver rk_iommu_domain_driver = {
1149 .probe = rk_iommu_domain_probe,
1151 .name = "rk_iommu_domain",
1155 static int rk_iommu_probe(struct platform_device *pdev)
1157 struct device *dev = &pdev->dev;
1158 struct rk_iommu *iommu;
1159 struct resource *res;
1160 int num_res = pdev->num_resources;
1163 iommu = devm_kzalloc(dev, sizeof(*iommu), GFP_KERNEL);
1167 platform_set_drvdata(pdev, iommu);
1171 iommu->bases = devm_kzalloc(dev, sizeof(*iommu->bases) * num_res,
1176 for (i = 0; i < num_res; i++) {
1177 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1180 iommu->bases[i] = devm_ioremap_resource(&pdev->dev, res);
1181 if (IS_ERR(iommu->bases[i]))
1185 if (iommu->num_mmu == 0)
1186 return PTR_ERR(iommu->bases[0]);
1188 iommu->irq = platform_get_irq(pdev, 0);
1189 if (iommu->irq < 0) {
1190 dev_err(dev, "Failed to get IRQ, %d\n", iommu->irq);
1194 iommu->reset_disabled = device_property_read_bool(dev,
1195 "rk_iommu,disable_reset_quirk");
1197 iommu->aclk = devm_clk_get(dev, "aclk");
1198 if (IS_ERR(iommu->aclk)) {
1199 dev_info(dev, "can't get aclk\n");
1203 iommu->hclk = devm_clk_get(dev, "hclk");
1204 if (IS_ERR(iommu->hclk)) {
1205 dev_info(dev, "can't get hclk\n");
1209 if (iommu->aclk && iommu->hclk) {
1210 clk_prepare(iommu->aclk);
1211 clk_prepare(iommu->hclk);
1217 static int rk_iommu_remove(struct platform_device *pdev)
1222 static const struct of_device_id rk_iommu_dt_ids[] = {
1223 { .compatible = "rockchip,iommu" },
1226 MODULE_DEVICE_TABLE(of, rk_iommu_dt_ids);
1228 static struct platform_driver rk_iommu_driver = {
1229 .probe = rk_iommu_probe,
1230 .remove = rk_iommu_remove,
1233 .of_match_table = rk_iommu_dt_ids,
1237 static int __init rk_iommu_init(void)
1239 struct device_node *np;
1242 np = of_find_matching_node(NULL, rk_iommu_dt_ids);
1248 ret = bus_set_iommu(&platform_bus_type, &rk_iommu_ops);
1252 ret = platform_driver_register(&rk_iommu_domain_driver);
1256 ret = platform_driver_register(&rk_iommu_driver);
1258 platform_driver_unregister(&rk_iommu_domain_driver);
1261 static void __exit rk_iommu_exit(void)
1263 platform_driver_unregister(&rk_iommu_driver);
1264 platform_driver_unregister(&rk_iommu_domain_driver);
1267 subsys_initcall(rk_iommu_init);
1268 module_exit(rk_iommu_exit);
1270 MODULE_DESCRIPTION("IOMMU API for Rockchip");
1271 MODULE_AUTHOR("Simon Xue <xxm@rock-chips.com> and Daniel Kurtz <djkurtz@chromium.org>");
1272 MODULE_ALIAS("platform:rockchip-iommu");
1273 MODULE_LICENSE("GPL v2");