2 * Copyright © 2015 Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * Authors: David Woodhouse <dwmw2@infradead.org>
16 #include <linux/intel-iommu.h>
17 #include <linux/mmu_notifier.h>
18 #include <linux/sched.h>
19 #include <linux/slab.h>
20 #include <linux/intel-svm.h>
21 #include <linux/rculist.h>
22 #include <linux/pci.h>
23 #include <linux/pci-ats.h>
24 #include <linux/dmar.h>
25 #include <linux/interrupt.h>
27 static irqreturn_t prq_event_thread(int irq, void *d);
33 struct pasid_state_entry {
37 int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu)
42 order = ecap_pss(iommu->ecap) + 7 - PAGE_SHIFT;
46 pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, order);
48 pr_warn("IOMMU: %s: Failed to allocate PASID table\n",
52 iommu->pasid_table = page_address(pages);
53 pr_info("%s: Allocated order %d PASID table.\n", iommu->name, order);
55 if (ecap_dis(iommu->ecap)) {
56 pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, order);
58 iommu->pasid_state_table = page_address(pages);
60 pr_warn("IOMMU: %s: Failed to allocate PASID state table\n",
64 idr_init(&iommu->pasid_idr);
69 int intel_svm_free_pasid_tables(struct intel_iommu *iommu)
73 order = ecap_pss(iommu->ecap) + 7 - PAGE_SHIFT;
77 if (iommu->pasid_table) {
78 free_pages((unsigned long)iommu->pasid_table, order);
79 iommu->pasid_table = NULL;
81 if (iommu->pasid_state_table) {
82 free_pages((unsigned long)iommu->pasid_state_table, order);
83 iommu->pasid_state_table = NULL;
85 idr_destroy(&iommu->pasid_idr);
91 int intel_svm_enable_prq(struct intel_iommu *iommu)
96 pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, PRQ_ORDER);
98 pr_warn("IOMMU: %s: Failed to allocate page request queue\n",
102 iommu->prq = page_address(pages);
104 irq = dmar_alloc_hwirq(DMAR_UNITS_SUPPORTED + iommu->seq_id, iommu->node, iommu);
106 pr_err("IOMMU: %s: Failed to create IRQ vector for page request queue\n",
110 free_pages((unsigned long)iommu->prq, PRQ_ORDER);
116 snprintf(iommu->prq_name, sizeof(iommu->prq_name), "dmar%d-prq", iommu->seq_id);
118 ret = request_threaded_irq(irq, NULL, prq_event_thread, IRQF_ONESHOT,
119 iommu->prq_name, iommu);
121 pr_err("IOMMU: %s: Failed to request IRQ for page request queue\n",
123 dmar_free_hwirq(irq);
126 dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
127 dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
128 dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORDER);
133 int intel_svm_finish_prq(struct intel_iommu *iommu)
135 dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
136 dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
137 dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL);
139 free_irq(iommu->pr_irq, iommu);
140 dmar_free_hwirq(iommu->pr_irq);
143 free_pages((unsigned long)iommu->prq, PRQ_ORDER);
149 static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_dev *sdev,
150 unsigned long address, int pages, int ih)
153 int mask = ilog2(__roundup_pow_of_two(pages));
155 if (pages == -1 || !cap_pgsel_inv(svm->iommu->cap) ||
156 mask > cap_max_amask_val(svm->iommu->cap)) {
157 desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
158 QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | QI_EIOTLB_TYPE;
161 desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
162 QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) | QI_EIOTLB_TYPE;
163 desc.high = QI_EIOTLB_ADDR(address) | QI_EIOTLB_GL(1) |
164 QI_EIOTLB_IH(ih) | QI_EIOTLB_AM(mask);
167 qi_submit_sync(&desc, svm->iommu);
169 if (sdev->dev_iotlb) {
170 desc.low = QI_DEV_EIOTLB_PASID(svm->pasid) | QI_DEV_EIOTLB_SID(sdev->sid) |
171 QI_DEV_EIOTLB_QDEP(sdev->qdep) | QI_DEIOTLB_TYPE;
173 unsigned long adr, delta;
175 /* Least significant zero bits in the address indicate the
176 * range of the request. So mask them out according to the
178 adr = address & ((1<<(VTD_PAGE_SHIFT + mask)) - 1);
180 /* Now ensure that we round down further if the original
181 * request was not aligned w.r.t. its size */
182 delta = address - adr;
183 if (delta + (pages << VTD_PAGE_SHIFT) >= (1 << (VTD_PAGE_SHIFT + mask)))
184 adr &= ~(1 << (VTD_PAGE_SHIFT + mask));
185 desc.high = QI_DEV_EIOTLB_ADDR(adr) | QI_DEV_EIOTLB_SIZE;
187 desc.high = QI_DEV_EIOTLB_ADDR(address);
189 qi_submit_sync(&desc, svm->iommu);
193 static void intel_flush_svm_range(struct intel_svm *svm, unsigned long address,
196 struct intel_svm_dev *sdev;
198 /* Try deferred invalidate if available */
199 if (svm->iommu->pasid_state_table &&
200 !cmpxchg64(&svm->iommu->pasid_state_table[svm->pasid].val, 0, 1ULL << 63))
204 list_for_each_entry_rcu(sdev, &svm->devs, list)
205 intel_flush_svm_range_dev(svm, sdev, address, pages, ih);
209 static void intel_change_pte(struct mmu_notifier *mn, struct mm_struct *mm,
210 unsigned long address, pte_t pte)
212 struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
214 intel_flush_svm_range(svm, address, 1, 1);
217 static void intel_invalidate_page(struct mmu_notifier *mn, struct mm_struct *mm,
218 unsigned long address)
220 struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
222 intel_flush_svm_range(svm, address, 1, 1);
225 /* Pages have been freed at this point */
226 static void intel_invalidate_range(struct mmu_notifier *mn,
227 struct mm_struct *mm,
228 unsigned long start, unsigned long end)
230 struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
232 intel_flush_svm_range(svm, start,
233 (end - start + PAGE_SIZE - 1) >> VTD_PAGE_SHIFT , 0);
237 static void intel_flush_pasid_dev(struct intel_svm *svm, struct intel_svm_dev *sdev)
242 desc.low = QI_PC_TYPE | QI_PC_DID(sdev->did) | QI_PC_PASID_SEL | QI_PC_PASID(svm->pasid);
244 qi_submit_sync(&desc, svm->iommu);
247 static void intel_mm_release(struct mmu_notifier *mn, struct mm_struct *mm)
249 struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
251 svm->iommu->pasid_table[svm->pasid].val = 0;
253 /* There's no need to do any flush because we can't get here if there
254 * are any devices left anyway. */
255 WARN_ON(!list_empty(&svm->devs));
258 static const struct mmu_notifier_ops intel_mmuops = {
259 .release = intel_mm_release,
260 .change_pte = intel_change_pte,
261 .invalidate_page = intel_invalidate_page,
262 .invalidate_range = intel_invalidate_range,
265 static DEFINE_MUTEX(pasid_mutex);
267 int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_ops *ops)
269 struct intel_iommu *iommu = intel_svm_device_to_iommu(dev);
270 struct intel_svm_dev *sdev;
271 struct intel_svm *svm = NULL;
272 struct mm_struct *mm = NULL;
279 if (dev_is_pci(dev)) {
280 pasid_max = pci_max_pasids(to_pci_dev(dev));
286 if ((flags & SVM_FLAG_SUPERVISOR_MODE)) {
287 if (!ecap_srs(iommu->ecap))
290 mm = get_task_mm(current);
294 mutex_lock(&pasid_mutex);
295 if (pasid && !(flags & SVM_FLAG_PRIVATE_PASID)) {
298 idr_for_each_entry(&iommu->pasid_idr, svm, i) {
300 (svm->flags & SVM_FLAG_PRIVATE_PASID))
303 if (svm->pasid >= pasid_max) {
305 "Limited PASID width. Cannot use existing PASID %d\n",
311 list_for_each_entry(sdev, &svm->devs, list) {
312 if (dev == sdev->dev) {
313 if (sdev->ops != ops) {
326 sdev = kzalloc(sizeof(*sdev), GFP_KERNEL);
333 ret = intel_iommu_enable_pasid(iommu, sdev);
335 /* If they don't actually want to assign a PASID, this is
336 * just an enabling check/preparation. */
340 /* Finish the setup now we know we're keeping it */
343 init_rcu_head(&sdev->rcu);
346 svm = kzalloc(sizeof(*svm), GFP_KERNEL);
354 if (pasid_max > 2 << ecap_pss(iommu->ecap))
355 pasid_max = 2 << ecap_pss(iommu->ecap);
357 ret = idr_alloc(&iommu->pasid_idr, svm, 0, pasid_max - 1,
364 svm->notifier.ops = &intel_mmuops;
367 INIT_LIST_HEAD_RCU(&svm->devs);
370 ret = mmu_notifier_register(&svm->notifier, mm);
372 idr_remove(&svm->iommu->pasid_idr, svm->pasid);
377 iommu->pasid_table[svm->pasid].val = (u64)__pa(mm->pgd) | 1;
380 iommu->pasid_table[svm->pasid].val = (u64)__pa(init_mm.pgd) | 1 | (1ULL << 11);
383 list_add_rcu(&sdev->list, &svm->devs);
389 mutex_unlock(&pasid_mutex);
394 EXPORT_SYMBOL_GPL(intel_svm_bind_mm);
396 int intel_svm_unbind_mm(struct device *dev, int pasid)
398 struct intel_svm_dev *sdev;
399 struct intel_iommu *iommu;
400 struct intel_svm *svm;
403 mutex_lock(&pasid_mutex);
404 iommu = intel_svm_device_to_iommu(dev);
405 if (!iommu || !iommu->pasid_table)
408 svm = idr_find(&iommu->pasid_idr, pasid);
412 list_for_each_entry(sdev, &svm->devs, list) {
413 if (dev == sdev->dev) {
417 list_del_rcu(&sdev->list);
418 /* Flush the PASID cache and IOTLB for this device.
419 * Note that we do depend on the hardware *not* using
420 * the PASID any more. Just as we depend on other
421 * devices never using PASIDs that they have no right
422 * to use. We have a *shared* PASID table, because it's
423 * large and has to be physically contiguous. So it's
424 * hard to be as defensive as we might like. */
425 intel_flush_pasid_dev(svm, sdev);
426 intel_flush_svm_range_dev(svm, sdev, 0, -1, 0);
427 kfree_rcu(sdev, rcu);
429 if (list_empty(&svm->devs)) {
430 mmu_notifier_unregister(&svm->notifier, svm->mm);
432 idr_remove(&svm->iommu->pasid_idr, svm->pasid);
435 /* We mandate that no page faults may be outstanding
436 * for the PASID when intel_svm_unbind_mm() is called.
437 * If that is not obeyed, subtle errors will happen.
438 * Let's make them less subtle... */
439 memset(svm, 0x6b, sizeof(*svm));
447 mutex_unlock(&pasid_mutex);
451 EXPORT_SYMBOL_GPL(intel_svm_unbind_mm);
453 /* Page request queue descriptor */
454 struct page_req_dsc {
471 #define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x10)
472 static irqreturn_t prq_event_thread(int irq, void *d)
474 struct intel_iommu *iommu = d;
475 struct intel_svm *svm = NULL;
476 int head, tail, handled = 0;
478 tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
479 head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
480 while (head != tail) {
481 struct intel_svm_dev *sdev;
482 struct vm_area_struct *vma;
483 struct page_req_dsc *req;
490 req = &iommu->prq[head / sizeof(*req)];
492 result = QI_RESP_FAILURE;
493 address = (u64)req->addr << PAGE_SHIFT;
494 if (!req->pasid_present) {
495 pr_err("%s: Page request without PASID: %08llx %08llx\n",
496 iommu->name, ((unsigned long long *)req)[0],
497 ((unsigned long long *)req)[1]);
501 if (!svm || svm->pasid != req->pasid) {
503 svm = idr_find(&iommu->pasid_idr, req->pasid);
504 /* It *can't* go away, because the driver is not permitted
505 * to unbind the mm while any page faults are outstanding.
506 * So we only need RCU to protect the internal idr code. */
510 pr_err("%s: Page request for invalid PASID %d: %08llx %08llx\n",
511 iommu->name, req->pasid, ((unsigned long long *)req)[0],
512 ((unsigned long long *)req)[1]);
517 result = QI_RESP_INVALID;
518 /* Since we're using init_mm.pgd directly, we should never take
519 * any faults on kernel addresses. */
522 down_read(&svm->mm->mmap_sem);
523 vma = find_extend_vma(svm->mm, address);
524 if (!vma || address < vma->vm_start)
527 ret = handle_mm_fault(svm->mm, vma, address,
528 req->wr_req ? FAULT_FLAG_WRITE : 0);
529 if (ret & VM_FAULT_ERROR)
532 result = QI_RESP_SUCCESS;
534 up_read(&svm->mm->mmap_sem);
536 /* Accounting for major/minor faults? */
538 list_for_each_entry_rcu(sdev, &svm->devs, list) {
539 if (sdev->sid == PCI_DEVID(req->bus, req->devfn));
542 /* Other devices can go away, but the drivers are not permitted
543 * to unbind while any page faults might be in flight. So it's
544 * OK to drop the 'lock' here now we have it. */
547 if (WARN_ON(&sdev->list == &svm->devs))
550 if (sdev && sdev->ops && sdev->ops->fault_cb) {
551 int rwxp = (req->rd_req << 3) | (req->wr_req << 2) |
552 (req->wr_req << 1) | (req->exe_req);
553 sdev->ops->fault_cb(sdev->dev, req->pasid, req->addr, req->private, rwxp, result);
555 /* We get here in the error case where the PASID lookup failed,
556 and these can be NULL. Do not use them below this point! */
561 /* Page Group Response */
562 resp.low = QI_PGRP_PASID(req->pasid) |
563 QI_PGRP_DID((req->bus << 8) | req->devfn) |
564 QI_PGRP_PASID_P(req->pasid_present) |
566 resp.high = QI_PGRP_IDX(req->prg_index) |
567 QI_PGRP_PRIV(req->private) | QI_PGRP_RESP_CODE(result);
569 qi_submit_sync(&resp, iommu);
570 } else if (req->srr) {
571 /* Page Stream Response */
572 resp.low = QI_PSTRM_IDX(req->prg_index) |
573 QI_PSTRM_PRIV(req->private) | QI_PSTRM_BUS(req->bus) |
574 QI_PSTRM_PASID(req->pasid) | QI_PSTRM_RESP_TYPE;
575 resp.high = QI_PSTRM_ADDR(address) | QI_PSTRM_DEVFN(req->devfn) |
576 QI_PSTRM_RESP_CODE(result);
578 qi_submit_sync(&resp, iommu);
581 head = (head + sizeof(*req)) & PRQ_RING_MASK;
584 dmar_writeq(iommu->reg + DMAR_PQH_REG, tail);
586 return IRQ_RETVAL(handled);