drivers/iommu/amd_iommu_v2.c

   1 /*
   2  * Copyright (C) 2010-2012 Advanced Micro Devices, Inc.
   3  * Author: Joerg Roedel <jroedel@suse.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published
   7  * by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  17  */
  18
  19 #include <linux/mmu_notifier.h>
  20 #include <linux/amd-iommu.h>
  21 #include <linux/mm_types.h>
  22 #include <linux/profile.h>
  23 #include <linux/module.h>
  24 #include <linux/sched.h>
  25 #include <linux/iommu.h>
  26 #include <linux/wait.h>
  27 #include <linux/pci.h>
  28 #include <linux/gfp.h>
  29
  30 #include "amd_iommu_types.h"
  31 #include "amd_iommu_proto.h"
  32
  33 MODULE_LICENSE("GPL v2");
  34 MODULE_AUTHOR("Joerg Roedel <jroedel@suse.de>");
  35
  36 #define MAX_DEVICES             0x10000
  37 #define PRI_QUEUE_SIZE          512
  38
  39 struct pri_queue {
  40         atomic_t inflight;
  41         bool finish;
  42         int status;
  43 };
  44
  45 struct pasid_state {
  46         struct list_head list;                  /* For global state-list */
  47         atomic_t count;                         /* Reference count */
  48         unsigned mmu_notifier_count;            /* Counting nested mmu_notifier
  49                                                    calls */
  50         struct mm_struct *mm;                   /* mm_struct for the faults */
  51         struct mmu_notifier mn;                 /* mmu_notifier handle */
  52         struct pri_queue pri[PRI_QUEUE_SIZE];   /* PRI tag states */
  53         struct device_state *device_state;      /* Link to our device_state */
  54         int pasid;                              /* PASID index */
  55         bool invalid;                           /* Used during setup and
  56                                                    teardown of the pasid */
  57         spinlock_t lock;                        /* Protect pri_queues and
  58                                                    mmu_notifer_count */
  59         wait_queue_head_t wq;                   /* To wait for count == 0 */
  60 };
  61
  62 struct device_state {
  63         struct list_head list;
  64         u16 devid;
  65         atomic_t count;
  66         struct pci_dev *pdev;
  67         struct pasid_state **states;
  68         struct iommu_domain *domain;
  69         int pasid_levels;
  70         int max_pasids;
  71         amd_iommu_invalid_ppr_cb inv_ppr_cb;
  72         amd_iommu_invalidate_ctx inv_ctx_cb;
  73         spinlock_t lock;
  74         wait_queue_head_t wq;
  75 };
  76
  77 struct fault {
  78         struct work_struct work;
  79         struct device_state *dev_state;
  80         struct pasid_state *state;
  81         struct mm_struct *mm;
  82         u64 address;
  83         u16 devid;
  84         u16 pasid;
  85         u16 tag;
  86         u16 finish;
  87         u16 flags;
  88 };
  89
  90 static LIST_HEAD(state_list);
  91 static spinlock_t state_lock;
  92
  93 static struct workqueue_struct *iommu_wq;
  94
  95 static void free_pasid_states(struct device_state *dev_state);
  96
  97 static u16 device_id(struct pci_dev *pdev)
  98 {
  99         u16 devid;
 100
 101         devid = pdev->bus->number;
 102         devid = (devid << 8) | pdev->devfn;
 103
 104         return devid;
 105 }
 106
 107 static struct device_state *__get_device_state(u16 devid)
 108 {
 109         struct device_state *dev_state;
 110
 111         list_for_each_entry(dev_state, &state_list, list) {
 112                 if (dev_state->devid == devid)
 113                         return dev_state;
 114         }
 115
 116         return NULL;
 117 }
 118
 119 static struct device_state *get_device_state(u16 devid)
 120 {
 121         struct device_state *dev_state;
 122         unsigned long flags;
 123
 124         spin_lock_irqsave(&state_lock, flags);
 125         dev_state = __get_device_state(devid);
 126         if (dev_state != NULL)
 127                 atomic_inc(&dev_state->count);
 128         spin_unlock_irqrestore(&state_lock, flags);
 129
 130         return dev_state;
 131 }
 132
 133 static void free_device_state(struct device_state *dev_state)
 134 {
 135         /*
 136          * First detach device from domain - No more PRI requests will arrive
 137          * from that device after it is unbound from the IOMMUv2 domain.
 138          */
 139         iommu_detach_device(dev_state->domain, &dev_state->pdev->dev);
 140
 141         /* Everything is down now, free the IOMMUv2 domain */
 142         iommu_domain_free(dev_state->domain);
 143
 144         /* Finally get rid of the device-state */
 145         kfree(dev_state);
 146 }
 147
 148 static void put_device_state(struct device_state *dev_state)
 149 {
 150         if (atomic_dec_and_test(&dev_state->count))
 151                 wake_up(&dev_state->wq);
 152 }
 153
 154 /* Must be called under dev_state->lock */
 155 static struct pasid_state **__get_pasid_state_ptr(struct device_state *dev_state,
 156                                                   int pasid, bool alloc)
 157 {
 158         struct pasid_state **root, **ptr;
 159         int level, index;
 160
 161         level = dev_state->pasid_levels;
 162         root  = dev_state->states;
 163
 164         while (true) {
 165
 166                 index = (pasid >> (9 * level)) & 0x1ff;
 167                 ptr   = &root[index];
 168
 169                 if (level == 0)
 170                         break;
 171
 172                 if (*ptr == NULL) {
 173                         if (!alloc)
 174                                 return NULL;
 175
 176                         *ptr = (void *)get_zeroed_page(GFP_ATOMIC);
 177                         if (*ptr == NULL)
 178                                 return NULL;
 179                 }
 180
 181                 root   = (struct pasid_state **)*ptr;
 182                 level -= 1;
 183         }
 184
 185         return ptr;
 186 }
 187
 188 static int set_pasid_state(struct device_state *dev_state,
 189                            struct pasid_state *pasid_state,
 190                            int pasid)
 191 {
 192         struct pasid_state **ptr;
 193         unsigned long flags;
 194         int ret;
 195
 196         spin_lock_irqsave(&dev_state->lock, flags);
 197         ptr = __get_pasid_state_ptr(dev_state, pasid, true);
 198
 199         ret = -ENOMEM;
 200         if (ptr == NULL)
 201                 goto out_unlock;
 202
 203         ret = -ENOMEM;
 204         if (*ptr != NULL)
 205                 goto out_unlock;
 206
 207         *ptr = pasid_state;
 208
 209         ret = 0;
 210
 211 out_unlock:
 212         spin_unlock_irqrestore(&dev_state->lock, flags);
 213
 214         return ret;
 215 }
 216
 217 static void clear_pasid_state(struct device_state *dev_state, int pasid)
 218 {
 219         struct pasid_state **ptr;
 220         unsigned long flags;
 221
 222         spin_lock_irqsave(&dev_state->lock, flags);
 223         ptr = __get_pasid_state_ptr(dev_state, pasid, true);
 224
 225         if (ptr == NULL)
 226                 goto out_unlock;
 227
 228         *ptr = NULL;
 229
 230 out_unlock:
 231         spin_unlock_irqrestore(&dev_state->lock, flags);
 232 }
 233
 234 static struct pasid_state *get_pasid_state(struct device_state *dev_state,
 235                                            int pasid)
 236 {
 237         struct pasid_state **ptr, *ret = NULL;
 238         unsigned long flags;
 239
 240         spin_lock_irqsave(&dev_state->lock, flags);
 241         ptr = __get_pasid_state_ptr(dev_state, pasid, false);
 242
 243         if (ptr == NULL)
 244                 goto out_unlock;
 245
 246         ret = *ptr;
 247         if (ret)
 248                 atomic_inc(&ret->count);
 249
 250 out_unlock:
 251         spin_unlock_irqrestore(&dev_state->lock, flags);
 252
 253         return ret;
 254 }
 255
 256 static void free_pasid_state(struct pasid_state *pasid_state)
 257 {
 258         kfree(pasid_state);
 259 }
 260
 261 static void put_pasid_state(struct pasid_state *pasid_state)
 262 {
 263         if (atomic_dec_and_test(&pasid_state->count))
 264                 wake_up(&pasid_state->wq);
 265 }
 266
 267 static void put_pasid_state_wait(struct pasid_state *pasid_state)
 268 {
 269         wait_event(pasid_state->wq, !atomic_read(&pasid_state->count));
 270         free_pasid_state(pasid_state);
 271 }
 272
 273 static void unbind_pasid(struct pasid_state *pasid_state)
 274 {
 275         struct iommu_domain *domain;
 276
 277         domain = pasid_state->device_state->domain;
 278
 279         /*
 280          * Mark pasid_state as invalid, no more faults will we added to the
 281          * work queue after this is visible everywhere.
 282          */
 283         pasid_state->invalid = true;
 284
 285         /* Make sure this is visible */
 286         smp_wmb();
 287
 288         /* After this the device/pasid can't access the mm anymore */
 289         amd_iommu_domain_clear_gcr3(domain, pasid_state->pasid);
 290
 291         /* Make sure no more pending faults are in the queue */
 292         flush_workqueue(iommu_wq);
 293 }
 294
 295 static void free_pasid_states_level1(struct pasid_state **tbl)
 296 {
 297         int i;
 298
 299         for (i = 0; i < 512; ++i) {
 300                 if (tbl[i] == NULL)
 301                         continue;
 302
 303                 free_page((unsigned long)tbl[i]);
 304         }
 305 }
 306
 307 static void free_pasid_states_level2(struct pasid_state **tbl)
 308 {
 309         struct pasid_state **ptr;
 310         int i;
 311
 312         for (i = 0; i < 512; ++i) {
 313                 if (tbl[i] == NULL)
 314                         continue;
 315
 316                 ptr = (struct pasid_state **)tbl[i];
 317                 free_pasid_states_level1(ptr);
 318         }
 319 }
 320
 321 static void free_pasid_states(struct device_state *dev_state)
 322 {
 323         struct pasid_state *pasid_state;
 324         int i;
 325
 326         for (i = 0; i < dev_state->max_pasids; ++i) {
 327                 pasid_state = get_pasid_state(dev_state, i);
 328                 if (pasid_state == NULL)
 329                         continue;
 330
 331                 put_pasid_state(pasid_state);
 332
 333                 /*
 334                  * This will call the mn_release function and
 335                  * unbind the PASID
 336                  */
 337                 mmu_notifier_unregister(&pasid_state->mn, pasid_state->mm);
 338
 339                 put_pasid_state_wait(pasid_state); /* Reference taken in
 340                                                       amd_iommu_bind_pasid */
 341
 342                 /* Drop reference taken in amd_iommu_bind_pasid */
 343                 put_device_state(dev_state);
 344         }
 345
 346         if (dev_state->pasid_levels == 2)
 347                 free_pasid_states_level2(dev_state->states);
 348         else if (dev_state->pasid_levels == 1)
 349                 free_pasid_states_level1(dev_state->states);
 350         else if (dev_state->pasid_levels != 0)
 351                 BUG();
 352
 353         free_page((unsigned long)dev_state->states);
 354 }
 355
 356 static struct pasid_state *mn_to_state(struct mmu_notifier *mn)
 357 {
 358         return container_of(mn, struct pasid_state, mn);
 359 }
 360
 361 static void __mn_flush_page(struct mmu_notifier *mn,
 362                             unsigned long address)
 363 {
 364         struct pasid_state *pasid_state;
 365         struct device_state *dev_state;
 366
 367         pasid_state = mn_to_state(mn);
 368         dev_state   = pasid_state->device_state;
 369
 370         amd_iommu_flush_page(dev_state->domain, pasid_state->pasid, address);
 371 }
 372
 373 static int mn_clear_flush_young(struct mmu_notifier *mn,
 374                                 struct mm_struct *mm,
 375                                 unsigned long start,
 376                                 unsigned long end)
 377 {
 378         for (; start < end; start += PAGE_SIZE)
 379                 __mn_flush_page(mn, start);
 380
 381         return 0;
 382 }
 383
 384 static void mn_invalidate_page(struct mmu_notifier *mn,
 385                                struct mm_struct *mm,
 386                                unsigned long address)
 387 {
 388         __mn_flush_page(mn, address);
 389 }
 390
 391 static void mn_invalidate_range(struct mmu_notifier *mn,
 392                                 struct mm_struct *mm,
 393                                 unsigned long start, unsigned long end)
 394 {
 395         struct pasid_state *pasid_state;
 396         struct device_state *dev_state;
 397
 398         pasid_state = mn_to_state(mn);
 399         dev_state   = pasid_state->device_state;
 400
 401         if ((start ^ (end - 1)) < PAGE_SIZE)
 402                 amd_iommu_flush_page(dev_state->domain, pasid_state->pasid,
 403                                      start);
 404         else
 405                 amd_iommu_flush_tlb(dev_state->domain, pasid_state->pasid);
 406 }
 407
 408 static void mn_release(struct mmu_notifier *mn, struct mm_struct *mm)
 409 {
 410         struct pasid_state *pasid_state;
 411         struct device_state *dev_state;
 412         bool run_inv_ctx_cb;
 413
 414         might_sleep();
 415
 416         pasid_state    = mn_to_state(mn);
 417         dev_state      = pasid_state->device_state;
 418         run_inv_ctx_cb = !pasid_state->invalid;
 419
 420         if (run_inv_ctx_cb && dev_state->inv_ctx_cb)
 421                 dev_state->inv_ctx_cb(dev_state->pdev, pasid_state->pasid);
 422
 423         unbind_pasid(pasid_state);
 424 }
 425
 426 static struct mmu_notifier_ops iommu_mn = {
 427         .release                = mn_release,
 428         .clear_flush_young      = mn_clear_flush_young,
 429         .invalidate_page        = mn_invalidate_page,
 430         .invalidate_range       = mn_invalidate_range,
 431 };
 432
 433 static void set_pri_tag_status(struct pasid_state *pasid_state,
 434                                u16 tag, int status)
 435 {
 436         unsigned long flags;
 437
 438         spin_lock_irqsave(&pasid_state->lock, flags);
 439         pasid_state->pri[tag].status = status;
 440         spin_unlock_irqrestore(&pasid_state->lock, flags);
 441 }
 442
 443 static void finish_pri_tag(struct device_state *dev_state,
 444                            struct pasid_state *pasid_state,
 445                            u16 tag)
 446 {
 447         unsigned long flags;
 448
 449         spin_lock_irqsave(&pasid_state->lock, flags);
 450         if (atomic_dec_and_test(&pasid_state->pri[tag].inflight) &&
 451             pasid_state->pri[tag].finish) {
 452                 amd_iommu_complete_ppr(dev_state->pdev, pasid_state->pasid,
 453                                        pasid_state->pri[tag].status, tag);
 454                 pasid_state->pri[tag].finish = false;
 455                 pasid_state->pri[tag].status = PPR_SUCCESS;
 456         }
 457         spin_unlock_irqrestore(&pasid_state->lock, flags);
 458 }
 459
 460 static void handle_fault_error(struct fault *fault)
 461 {
 462         int status;
 463
 464         if (!fault->dev_state->inv_ppr_cb) {
 465                 set_pri_tag_status(fault->state, fault->tag, PPR_INVALID);
 466                 return;
 467         }
 468
 469         status = fault->dev_state->inv_ppr_cb(fault->dev_state->pdev,
 470                                               fault->pasid,
 471                                               fault->address,
 472                                               fault->flags);
 473         switch (status) {
 474         case AMD_IOMMU_INV_PRI_RSP_SUCCESS:
 475                 set_pri_tag_status(fault->state, fault->tag, PPR_SUCCESS);
 476                 break;
 477         case AMD_IOMMU_INV_PRI_RSP_INVALID:
 478                 set_pri_tag_status(fault->state, fault->tag, PPR_INVALID);
 479                 break;
 480         case AMD_IOMMU_INV_PRI_RSP_FAIL:
 481                 set_pri_tag_status(fault->state, fault->tag, PPR_FAILURE);
 482                 break;
 483         default:
 484                 BUG();
 485         }
 486 }
 487
 488 static void do_fault(struct work_struct *work)
 489 {
 490         struct fault *fault = container_of(work, struct fault, work);
 491         struct mm_struct *mm;
 492         struct vm_area_struct *vma;
 493         u64 address;
 494         int ret, write;
 495
 496         write = !!(fault->flags & PPR_FAULT_WRITE);
 497
 498         mm = fault->state->mm;
 499         address = fault->address;
 500
 501         down_read(&mm->mmap_sem);
 502         vma = find_extend_vma(mm, address);
 503         if (!vma || address < vma->vm_start) {
 504                 /* failed to get a vma in the right range */
 505                 up_read(&mm->mmap_sem);
 506                 handle_fault_error(fault);
 507                 goto out;
 508         }
 509
 510         ret = handle_mm_fault(mm, vma, address, write);
 511         if (ret & VM_FAULT_ERROR) {
 512                 /* failed to service fault */
 513                 up_read(&mm->mmap_sem);
 514                 handle_fault_error(fault);
 515                 goto out;
 516         }
 517
 518         up_read(&mm->mmap_sem);
 519
 520 out:
 521         finish_pri_tag(fault->dev_state, fault->state, fault->tag);
 522
 523         put_pasid_state(fault->state);
 524
 525         kfree(fault);
 526 }
 527
 528 static int ppr_notifier(struct notifier_block *nb, unsigned long e, void *data)
 529 {
 530         struct amd_iommu_fault *iommu_fault;
 531         struct pasid_state *pasid_state;
 532         struct device_state *dev_state;
 533         unsigned long flags;
 534         struct fault *fault;
 535         bool finish;
 536         u16 tag;
 537         int ret;
 538
 539         iommu_fault = data;
 540         tag         = iommu_fault->tag & 0x1ff;
 541         finish      = (iommu_fault->tag >> 9) & 1;
 542
 543         ret = NOTIFY_DONE;
 544         dev_state = get_device_state(iommu_fault->device_id);
 545         if (dev_state == NULL)
 546                 goto out;
 547
 548         pasid_state = get_pasid_state(dev_state, iommu_fault->pasid);
 549         if (pasid_state == NULL || pasid_state->invalid) {
 550                 /* We know the device but not the PASID -> send INVALID */
 551                 amd_iommu_complete_ppr(dev_state->pdev, iommu_fault->pasid,
 552                                        PPR_INVALID, tag);
 553                 goto out_drop_state;
 554         }
 555
 556         spin_lock_irqsave(&pasid_state->lock, flags);
 557         atomic_inc(&pasid_state->pri[tag].inflight);
 558         if (finish)
 559                 pasid_state->pri[tag].finish = true;
 560         spin_unlock_irqrestore(&pasid_state->lock, flags);
 561
 562         fault = kzalloc(sizeof(*fault), GFP_ATOMIC);
 563         if (fault == NULL) {
 564                 /* We are OOM - send success and let the device re-fault */
 565                 finish_pri_tag(dev_state, pasid_state, tag);
 566                 goto out_drop_state;
 567         }
 568
 569         fault->dev_state = dev_state;
 570         fault->address   = iommu_fault->address;
 571         fault->state     = pasid_state;
 572         fault->tag       = tag;
 573         fault->finish    = finish;
 574         fault->pasid     = iommu_fault->pasid;
 575         fault->flags     = iommu_fault->flags;
 576         INIT_WORK(&fault->work, do_fault);
 577
 578         queue_work(iommu_wq, &fault->work);
 579
 580         ret = NOTIFY_OK;
 581
 582 out_drop_state:
 583
 584         if (ret != NOTIFY_OK && pasid_state)
 585                 put_pasid_state(pasid_state);
 586
 587         put_device_state(dev_state);
 588
 589 out:
 590         return ret;
 591 }
 592
 593 static struct notifier_block ppr_nb = {
 594         .notifier_call = ppr_notifier,
 595 };
 596
 597 int amd_iommu_bind_pasid(struct pci_dev *pdev, int pasid,
 598                          struct task_struct *task)
 599 {
 600         struct pasid_state *pasid_state;
 601         struct device_state *dev_state;
 602         struct mm_struct *mm;
 603         u16 devid;
 604         int ret;
 605
 606         might_sleep();
 607
 608         if (!amd_iommu_v2_supported())
 609                 return -ENODEV;
 610
 611         devid     = device_id(pdev);
 612         dev_state = get_device_state(devid);
 613
 614         if (dev_state == NULL)
 615                 return -EINVAL;
 616
 617         ret = -EINVAL;
 618         if (pasid < 0 || pasid >= dev_state->max_pasids)
 619                 goto out;
 620
 621         ret = -ENOMEM;
 622         pasid_state = kzalloc(sizeof(*pasid_state), GFP_KERNEL);
 623         if (pasid_state == NULL)
 624                 goto out;
 625
 626
 627         atomic_set(&pasid_state->count, 1);
 628         init_waitqueue_head(&pasid_state->wq);
 629         spin_lock_init(&pasid_state->lock);
 630
 631         mm                        = get_task_mm(task);
 632         pasid_state->mm           = mm;
 633         pasid_state->device_state = dev_state;
 634         pasid_state->pasid        = pasid;
 635         pasid_state->invalid      = true; /* Mark as valid only if we are
 636                                              done with setting up the pasid */
 637         pasid_state->mn.ops       = &iommu_mn;
 638
 639         if (pasid_state->mm == NULL)
 640                 goto out_free;
 641
 642         mmu_notifier_register(&pasid_state->mn, mm);
 643
 644         ret = set_pasid_state(dev_state, pasid_state, pasid);
 645         if (ret)
 646                 goto out_unregister;
 647
 648         ret = amd_iommu_domain_set_gcr3(dev_state->domain, pasid,
 649                                         __pa(pasid_state->mm->pgd));
 650         if (ret)
 651                 goto out_clear_state;
 652
 653         /* Now we are ready to handle faults */
 654         pasid_state->invalid = false;
 655
 656         /*
 657          * Drop the reference to the mm_struct here. We rely on the
 658          * mmu_notifier release call-back to inform us when the mm
 659          * is going away.
 660          */
 661         mmput(mm);
 662
 663         return 0;
 664
 665 out_clear_state:
 666         clear_pasid_state(dev_state, pasid);
 667
 668 out_unregister:
 669         mmu_notifier_unregister(&pasid_state->mn, mm);
 670
 671 out_free:
 672         mmput(mm);
 673         free_pasid_state(pasid_state);
 674
 675 out:
 676         put_device_state(dev_state);
 677
 678         return ret;
 679 }
 680 EXPORT_SYMBOL(amd_iommu_bind_pasid);
 681
 682 void amd_iommu_unbind_pasid(struct pci_dev *pdev, int pasid)
 683 {
 684         struct pasid_state *pasid_state;
 685         struct device_state *dev_state;
 686         u16 devid;
 687
 688         might_sleep();
 689
 690         if (!amd_iommu_v2_supported())
 691                 return;
 692
 693         devid = device_id(pdev);
 694         dev_state = get_device_state(devid);
 695         if (dev_state == NULL)
 696                 return;
 697
 698         if (pasid < 0 || pasid >= dev_state->max_pasids)
 699                 goto out;
 700
 701         pasid_state = get_pasid_state(dev_state, pasid);
 702         if (pasid_state == NULL)
 703                 goto out;
 704         /*
 705          * Drop reference taken here. We are safe because we still hold
 706          * the reference taken in the amd_iommu_bind_pasid function.
 707          */
 708         put_pasid_state(pasid_state);
 709
 710         /* Clear the pasid state so that the pasid can be re-used */
 711         clear_pasid_state(dev_state, pasid_state->pasid);
 712
 713         /*
 714          * Call mmu_notifier_unregister to drop our reference
 715          * to pasid_state->mm
 716          */
 717         mmu_notifier_unregister(&pasid_state->mn, pasid_state->mm);
 718
 719         put_pasid_state_wait(pasid_state); /* Reference taken in
 720                                               amd_iommu_bind_pasid */
 721 out:
 722         /* Drop reference taken in this function */
 723         put_device_state(dev_state);
 724
 725         /* Drop reference taken in amd_iommu_bind_pasid */
 726         put_device_state(dev_state);
 727 }
 728 EXPORT_SYMBOL(amd_iommu_unbind_pasid);
 729
 730 int amd_iommu_init_device(struct pci_dev *pdev, int pasids)
 731 {
 732         struct device_state *dev_state;
 733         unsigned long flags;
 734         int ret, tmp;
 735         u16 devid;
 736
 737         might_sleep();
 738
 739         if (!amd_iommu_v2_supported())
 740                 return -ENODEV;
 741
 742         if (pasids <= 0 || pasids > (PASID_MASK + 1))
 743                 return -EINVAL;
 744
 745         devid = device_id(pdev);
 746
 747         dev_state = kzalloc(sizeof(*dev_state), GFP_KERNEL);
 748         if (dev_state == NULL)
 749                 return -ENOMEM;
 750
 751         spin_lock_init(&dev_state->lock);
 752         init_waitqueue_head(&dev_state->wq);
 753         dev_state->pdev  = pdev;
 754         dev_state->devid = devid;
 755
 756         tmp = pasids;
 757         for (dev_state->pasid_levels = 0; (tmp - 1) & ~0x1ff; tmp >>= 9)
 758                 dev_state->pasid_levels += 1;
 759
 760         atomic_set(&dev_state->count, 1);
 761         dev_state->max_pasids = pasids;
 762
 763         ret = -ENOMEM;
 764         dev_state->states = (void *)get_zeroed_page(GFP_KERNEL);
 765         if (dev_state->states == NULL)
 766                 goto out_free_dev_state;
 767
 768         dev_state->domain = iommu_domain_alloc(&pci_bus_type);
 769         if (dev_state->domain == NULL)
 770                 goto out_free_states;
 771
 772         amd_iommu_domain_direct_map(dev_state->domain);
 773
 774         ret = amd_iommu_domain_enable_v2(dev_state->domain, pasids);
 775         if (ret)
 776                 goto out_free_domain;
 777
 778         ret = iommu_attach_device(dev_state->domain, &pdev->dev);
 779         if (ret != 0)
 780                 goto out_free_domain;
 781
 782         spin_lock_irqsave(&state_lock, flags);
 783
 784         if (__get_device_state(devid) != NULL) {
 785                 spin_unlock_irqrestore(&state_lock, flags);
 786                 ret = -EBUSY;
 787                 goto out_free_domain;
 788         }
 789
 790         list_add_tail(&dev_state->list, &state_list);
 791
 792         spin_unlock_irqrestore(&state_lock, flags);
 793
 794         return 0;
 795
 796 out_free_domain:
 797         iommu_domain_free(dev_state->domain);
 798
 799 out_free_states:
 800         free_page((unsigned long)dev_state->states);
 801
 802 out_free_dev_state:
 803         kfree(dev_state);
 804
 805         return ret;
 806 }
 807 EXPORT_SYMBOL(amd_iommu_init_device);
 808
 809 void amd_iommu_free_device(struct pci_dev *pdev)
 810 {
 811         struct device_state *dev_state;
 812         unsigned long flags;
 813         u16 devid;
 814
 815         if (!amd_iommu_v2_supported())
 816                 return;
 817
 818         devid = device_id(pdev);
 819
 820         spin_lock_irqsave(&state_lock, flags);
 821
 822         dev_state = __get_device_state(devid);
 823         if (dev_state == NULL) {
 824                 spin_unlock_irqrestore(&state_lock, flags);
 825                 return;
 826         }
 827
 828         list_del(&dev_state->list);
 829
 830         spin_unlock_irqrestore(&state_lock, flags);
 831
 832         /* Get rid of any remaining pasid states */
 833         free_pasid_states(dev_state);
 834
 835         put_device_state(dev_state);
 836         /*
 837          * Wait until the last reference is dropped before freeing
 838          * the device state.
 839          */
 840         wait_event(dev_state->wq, !atomic_read(&dev_state->count));
 841         free_device_state(dev_state);
 842 }
 843 EXPORT_SYMBOL(amd_iommu_free_device);
 844
 845 int amd_iommu_set_invalid_ppr_cb(struct pci_dev *pdev,
 846                                  amd_iommu_invalid_ppr_cb cb)
 847 {
 848         struct device_state *dev_state;
 849         unsigned long flags;
 850         u16 devid;
 851         int ret;
 852
 853         if (!amd_iommu_v2_supported())
 854                 return -ENODEV;
 855
 856         devid = device_id(pdev);
 857
 858         spin_lock_irqsave(&state_lock, flags);
 859
 860         ret = -EINVAL;
 861         dev_state = __get_device_state(devid);
 862         if (dev_state == NULL)
 863                 goto out_unlock;
 864
 865         dev_state->inv_ppr_cb = cb;
 866
 867         ret = 0;
 868
 869 out_unlock:
 870         spin_unlock_irqrestore(&state_lock, flags);
 871
 872         return ret;
 873 }
 874 EXPORT_SYMBOL(amd_iommu_set_invalid_ppr_cb);
 875
 876 int amd_iommu_set_invalidate_ctx_cb(struct pci_dev *pdev,
 877                                     amd_iommu_invalidate_ctx cb)
 878 {
 879         struct device_state *dev_state;
 880         unsigned long flags;
 881         u16 devid;
 882         int ret;
 883
 884         if (!amd_iommu_v2_supported())
 885                 return -ENODEV;
 886
 887         devid = device_id(pdev);
 888
 889         spin_lock_irqsave(&state_lock, flags);
 890
 891         ret = -EINVAL;
 892         dev_state = __get_device_state(devid);
 893         if (dev_state == NULL)
 894                 goto out_unlock;
 895
 896         dev_state->inv_ctx_cb = cb;
 897
 898         ret = 0;
 899
 900 out_unlock:
 901         spin_unlock_irqrestore(&state_lock, flags);
 902
 903         return ret;
 904 }
 905 EXPORT_SYMBOL(amd_iommu_set_invalidate_ctx_cb);
 906
 907 static int __init amd_iommu_v2_init(void)
 908 {
 909         int ret;
 910
 911         pr_info("AMD IOMMUv2 driver by Joerg Roedel <jroedel@suse.de>\n");
 912
 913         if (!amd_iommu_v2_supported()) {
 914                 pr_info("AMD IOMMUv2 functionality not available on this system\n");
 915                 /*
 916                  * Load anyway to provide the symbols to other modules
 917                  * which may use AMD IOMMUv2 optionally.
 918                  */
 919                 return 0;
 920         }
 921
 922         spin_lock_init(&state_lock);
 923
 924         ret = -ENOMEM;
 925         iommu_wq = create_workqueue("amd_iommu_v2");
 926         if (iommu_wq == NULL)
 927                 goto out;
 928
 929         amd_iommu_register_ppr_notifier(&ppr_nb);
 930
 931         return 0;
 932
 933 out:
 934         return ret;
 935 }
 936
 937 static void __exit amd_iommu_v2_exit(void)
 938 {
 939         struct device_state *dev_state;
 940         int i;
 941
 942         if (!amd_iommu_v2_supported())
 943                 return;
 944
 945         amd_iommu_unregister_ppr_notifier(&ppr_nb);
 946
 947         flush_workqueue(iommu_wq);
 948
 949         /*
 950          * The loop below might call flush_workqueue(), so call
 951          * destroy_workqueue() after it
 952          */
 953         for (i = 0; i < MAX_DEVICES; ++i) {
 954                 dev_state = get_device_state(i);
 955
 956                 if (dev_state == NULL)
 957                         continue;
 958
 959                 WARN_ON_ONCE(1);
 960
 961                 put_device_state(dev_state);
 962                 amd_iommu_free_device(dev_state->pdev);
 963         }
 964
 965         destroy_workqueue(iommu_wq);
 966 }
 967
 968 module_init(amd_iommu_v2_init);
 969 module_exit(amd_iommu_v2_exit);