2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/pci-ats.h>
23 #include <linux/bitmap.h>
24 #include <linux/slab.h>
25 #include <linux/debugfs.h>
26 #include <linux/scatterlist.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/iommu-helper.h>
29 #include <linux/iommu.h>
30 #include <linux/delay.h>
31 #include <linux/amd-iommu.h>
32 #include <linux/notifier.h>
33 #include <linux/export.h>
34 #include <asm/msidef.h>
35 #include <asm/proto.h>
36 #include <asm/iommu.h>
40 #include "amd_iommu_proto.h"
41 #include "amd_iommu_types.h"
43 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
45 #define LOOP_TIMEOUT 100000
47 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
49 /* A list of preallocated protection domains */
50 static LIST_HEAD(iommu_pd_list);
51 static DEFINE_SPINLOCK(iommu_pd_list_lock);
53 /* List of all available dev_data structures */
54 static LIST_HEAD(dev_data_list);
55 static DEFINE_SPINLOCK(dev_data_list_lock);
58 * Domain for untranslated devices - only allocated
59 * if iommu=pt passed on kernel cmd line.
61 static struct protection_domain *pt_domain;
63 static struct iommu_ops amd_iommu_ops;
65 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
66 int amd_iommu_max_glx_val = -1;
69 * general struct to manage commands send to an IOMMU
75 static void update_domain(struct protection_domain *domain);
76 static int __init alloc_passthrough_domain(void);
78 /****************************************************************************
82 ****************************************************************************/
84 static struct iommu_dev_data *alloc_dev_data(u16 devid)
86 struct iommu_dev_data *dev_data;
89 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
93 dev_data->devid = devid;
94 atomic_set(&dev_data->bind, 0);
96 spin_lock_irqsave(&dev_data_list_lock, flags);
97 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
98 spin_unlock_irqrestore(&dev_data_list_lock, flags);
103 static void free_dev_data(struct iommu_dev_data *dev_data)
107 spin_lock_irqsave(&dev_data_list_lock, flags);
108 list_del(&dev_data->dev_data_list);
109 spin_unlock_irqrestore(&dev_data_list_lock, flags);
114 static struct iommu_dev_data *search_dev_data(u16 devid)
116 struct iommu_dev_data *dev_data;
119 spin_lock_irqsave(&dev_data_list_lock, flags);
120 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
121 if (dev_data->devid == devid)
128 spin_unlock_irqrestore(&dev_data_list_lock, flags);
133 static struct iommu_dev_data *find_dev_data(u16 devid)
135 struct iommu_dev_data *dev_data;
137 dev_data = search_dev_data(devid);
139 if (dev_data == NULL)
140 dev_data = alloc_dev_data(devid);
145 static inline u16 get_device_id(struct device *dev)
147 struct pci_dev *pdev = to_pci_dev(dev);
149 return calc_devid(pdev->bus->number, pdev->devfn);
152 static struct iommu_dev_data *get_dev_data(struct device *dev)
154 return dev->archdata.iommu;
157 static bool pci_iommuv2_capable(struct pci_dev *pdev)
159 static const int caps[] = {
166 for (i = 0; i < 3; ++i) {
167 pos = pci_find_ext_capability(pdev, caps[i]);
175 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
177 struct iommu_dev_data *dev_data;
179 dev_data = get_dev_data(&pdev->dev);
181 return dev_data->errata & (1 << erratum) ? true : false;
185 * In this function the list of preallocated protection domains is traversed to
186 * find the domain for a specific device
188 static struct dma_ops_domain *find_protection_domain(u16 devid)
190 struct dma_ops_domain *entry, *ret = NULL;
192 u16 alias = amd_iommu_alias_table[devid];
194 if (list_empty(&iommu_pd_list))
197 spin_lock_irqsave(&iommu_pd_list_lock, flags);
199 list_for_each_entry(entry, &iommu_pd_list, list) {
200 if (entry->target_dev == devid ||
201 entry->target_dev == alias) {
207 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
213 * This function checks if the driver got a valid device from the caller to
214 * avoid dereferencing invalid pointers.
216 static bool check_device(struct device *dev)
220 if (!dev || !dev->dma_mask)
223 /* No device or no PCI device */
224 if (dev->bus != &pci_bus_type)
227 devid = get_device_id(dev);
229 /* Out of our scope? */
230 if (devid > amd_iommu_last_bdf)
233 if (amd_iommu_rlookup_table[devid] == NULL)
239 static int iommu_init_device(struct device *dev)
241 struct pci_dev *pdev = to_pci_dev(dev);
242 struct iommu_dev_data *dev_data;
245 if (dev->archdata.iommu)
248 dev_data = find_dev_data(get_device_id(dev));
252 alias = amd_iommu_alias_table[dev_data->devid];
253 if (alias != dev_data->devid) {
254 struct iommu_dev_data *alias_data;
256 alias_data = find_dev_data(alias);
257 if (alias_data == NULL) {
258 pr_err("AMD-Vi: Warning: Unhandled device %s\n",
260 free_dev_data(dev_data);
263 dev_data->alias_data = alias_data;
266 if (pci_iommuv2_capable(pdev)) {
267 struct amd_iommu *iommu;
269 iommu = amd_iommu_rlookup_table[dev_data->devid];
270 dev_data->iommu_v2 = iommu->is_iommu_v2;
273 dev->archdata.iommu = dev_data;
278 static void iommu_ignore_device(struct device *dev)
282 devid = get_device_id(dev);
283 alias = amd_iommu_alias_table[devid];
285 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
286 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
288 amd_iommu_rlookup_table[devid] = NULL;
289 amd_iommu_rlookup_table[alias] = NULL;
292 static void iommu_uninit_device(struct device *dev)
295 * Nothing to do here - we keep dev_data around for unplugged devices
296 * and reuse it when the device is re-plugged - not doing so would
297 * introduce a ton of races.
301 void __init amd_iommu_uninit_devices(void)
303 struct iommu_dev_data *dev_data, *n;
304 struct pci_dev *pdev = NULL;
306 for_each_pci_dev(pdev) {
308 if (!check_device(&pdev->dev))
311 iommu_uninit_device(&pdev->dev);
314 /* Free all of our dev_data structures */
315 list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list)
316 free_dev_data(dev_data);
319 int __init amd_iommu_init_devices(void)
321 struct pci_dev *pdev = NULL;
324 for_each_pci_dev(pdev) {
326 if (!check_device(&pdev->dev))
329 ret = iommu_init_device(&pdev->dev);
330 if (ret == -ENOTSUPP)
331 iommu_ignore_device(&pdev->dev);
340 amd_iommu_uninit_devices();
344 #ifdef CONFIG_AMD_IOMMU_STATS
347 * Initialization code for statistics collection
350 DECLARE_STATS_COUNTER(compl_wait);
351 DECLARE_STATS_COUNTER(cnt_map_single);
352 DECLARE_STATS_COUNTER(cnt_unmap_single);
353 DECLARE_STATS_COUNTER(cnt_map_sg);
354 DECLARE_STATS_COUNTER(cnt_unmap_sg);
355 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
356 DECLARE_STATS_COUNTER(cnt_free_coherent);
357 DECLARE_STATS_COUNTER(cross_page);
358 DECLARE_STATS_COUNTER(domain_flush_single);
359 DECLARE_STATS_COUNTER(domain_flush_all);
360 DECLARE_STATS_COUNTER(alloced_io_mem);
361 DECLARE_STATS_COUNTER(total_map_requests);
362 DECLARE_STATS_COUNTER(complete_ppr);
363 DECLARE_STATS_COUNTER(invalidate_iotlb);
364 DECLARE_STATS_COUNTER(invalidate_iotlb_all);
365 DECLARE_STATS_COUNTER(pri_requests);
368 static struct dentry *stats_dir;
369 static struct dentry *de_fflush;
371 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
373 if (stats_dir == NULL)
376 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
380 static void amd_iommu_stats_init(void)
382 stats_dir = debugfs_create_dir("amd-iommu", NULL);
383 if (stats_dir == NULL)
386 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
387 (u32 *)&amd_iommu_unmap_flush);
389 amd_iommu_stats_add(&compl_wait);
390 amd_iommu_stats_add(&cnt_map_single);
391 amd_iommu_stats_add(&cnt_unmap_single);
392 amd_iommu_stats_add(&cnt_map_sg);
393 amd_iommu_stats_add(&cnt_unmap_sg);
394 amd_iommu_stats_add(&cnt_alloc_coherent);
395 amd_iommu_stats_add(&cnt_free_coherent);
396 amd_iommu_stats_add(&cross_page);
397 amd_iommu_stats_add(&domain_flush_single);
398 amd_iommu_stats_add(&domain_flush_all);
399 amd_iommu_stats_add(&alloced_io_mem);
400 amd_iommu_stats_add(&total_map_requests);
401 amd_iommu_stats_add(&complete_ppr);
402 amd_iommu_stats_add(&invalidate_iotlb);
403 amd_iommu_stats_add(&invalidate_iotlb_all);
404 amd_iommu_stats_add(&pri_requests);
409 /****************************************************************************
411 * Interrupt handling functions
413 ****************************************************************************/
415 static void dump_dte_entry(u16 devid)
419 for (i = 0; i < 4; ++i)
420 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
421 amd_iommu_dev_table[devid].data[i]);
424 static void dump_command(unsigned long phys_addr)
426 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
429 for (i = 0; i < 4; ++i)
430 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
433 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
436 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
437 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
438 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
439 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
440 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
442 printk(KERN_ERR "AMD-Vi: Event logged [");
445 case EVENT_TYPE_ILL_DEV:
446 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
447 "address=0x%016llx flags=0x%04x]\n",
448 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
450 dump_dte_entry(devid);
452 case EVENT_TYPE_IO_FAULT:
453 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
454 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
455 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
456 domid, address, flags);
458 case EVENT_TYPE_DEV_TAB_ERR:
459 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
460 "address=0x%016llx flags=0x%04x]\n",
461 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
464 case EVENT_TYPE_PAGE_TAB_ERR:
465 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
466 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
467 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
468 domid, address, flags);
470 case EVENT_TYPE_ILL_CMD:
471 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
472 dump_command(address);
474 case EVENT_TYPE_CMD_HARD_ERR:
475 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
476 "flags=0x%04x]\n", address, flags);
478 case EVENT_TYPE_IOTLB_INV_TO:
479 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
480 "address=0x%016llx]\n",
481 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
484 case EVENT_TYPE_INV_DEV_REQ:
485 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
486 "address=0x%016llx flags=0x%04x]\n",
487 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
491 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
495 static void iommu_poll_events(struct amd_iommu *iommu)
500 spin_lock_irqsave(&iommu->lock, flags);
502 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
503 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
505 while (head != tail) {
506 iommu_print_event(iommu, iommu->evt_buf + head);
507 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
510 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
512 spin_unlock_irqrestore(&iommu->lock, flags);
515 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u32 head)
517 struct amd_iommu_fault fault;
521 INC_STATS_COUNTER(pri_requests);
523 raw = (u64 *)(iommu->ppr_log + head);
526 * Hardware bug: Interrupt may arrive before the entry is written to
527 * memory. If this happens we need to wait for the entry to arrive.
529 for (i = 0; i < LOOP_TIMEOUT; ++i) {
530 if (PPR_REQ_TYPE(raw[0]) != 0)
535 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
536 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
540 fault.address = raw[1];
541 fault.pasid = PPR_PASID(raw[0]);
542 fault.device_id = PPR_DEVID(raw[0]);
543 fault.tag = PPR_TAG(raw[0]);
544 fault.flags = PPR_FLAGS(raw[0]);
547 * To detect the hardware bug we need to clear the entry
552 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
555 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
560 if (iommu->ppr_log == NULL)
563 spin_lock_irqsave(&iommu->lock, flags);
565 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
566 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
568 while (head != tail) {
570 /* Handle PPR entry */
571 iommu_handle_ppr_entry(iommu, head);
573 /* Update and refresh ring-buffer state*/
574 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
575 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
576 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
579 /* enable ppr interrupts again */
580 writel(MMIO_STATUS_PPR_INT_MASK, iommu->mmio_base + MMIO_STATUS_OFFSET);
582 spin_unlock_irqrestore(&iommu->lock, flags);
585 irqreturn_t amd_iommu_int_thread(int irq, void *data)
587 struct amd_iommu *iommu;
589 for_each_iommu(iommu) {
590 iommu_poll_events(iommu);
591 iommu_poll_ppr_log(iommu);
597 irqreturn_t amd_iommu_int_handler(int irq, void *data)
599 return IRQ_WAKE_THREAD;
602 /****************************************************************************
604 * IOMMU command queuing functions
606 ****************************************************************************/
608 static int wait_on_sem(volatile u64 *sem)
612 while (*sem == 0 && i < LOOP_TIMEOUT) {
617 if (i == LOOP_TIMEOUT) {
618 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
625 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
626 struct iommu_cmd *cmd,
631 target = iommu->cmd_buf + tail;
632 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
634 /* Copy command to buffer */
635 memcpy(target, cmd, sizeof(*cmd));
637 /* Tell the IOMMU about it */
638 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
641 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
643 WARN_ON(address & 0x7ULL);
645 memset(cmd, 0, sizeof(*cmd));
646 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
647 cmd->data[1] = upper_32_bits(__pa(address));
649 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
652 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
654 memset(cmd, 0, sizeof(*cmd));
655 cmd->data[0] = devid;
656 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
659 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
660 size_t size, u16 domid, int pde)
665 pages = iommu_num_pages(address, size, PAGE_SIZE);
670 * If we have to flush more than one page, flush all
671 * TLB entries for this domain
673 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
677 address &= PAGE_MASK;
679 memset(cmd, 0, sizeof(*cmd));
680 cmd->data[1] |= domid;
681 cmd->data[2] = lower_32_bits(address);
682 cmd->data[3] = upper_32_bits(address);
683 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
684 if (s) /* size bit - we flush more than one 4kb page */
685 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
686 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
687 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
690 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
691 u64 address, size_t size)
696 pages = iommu_num_pages(address, size, PAGE_SIZE);
701 * If we have to flush more than one page, flush all
702 * TLB entries for this domain
704 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
708 address &= PAGE_MASK;
710 memset(cmd, 0, sizeof(*cmd));
711 cmd->data[0] = devid;
712 cmd->data[0] |= (qdep & 0xff) << 24;
713 cmd->data[1] = devid;
714 cmd->data[2] = lower_32_bits(address);
715 cmd->data[3] = upper_32_bits(address);
716 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
718 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
721 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
722 u64 address, bool size)
724 memset(cmd, 0, sizeof(*cmd));
726 address &= ~(0xfffULL);
728 cmd->data[0] = pasid & PASID_MASK;
729 cmd->data[1] = domid;
730 cmd->data[2] = lower_32_bits(address);
731 cmd->data[3] = upper_32_bits(address);
732 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
733 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
735 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
736 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
739 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
740 int qdep, u64 address, bool size)
742 memset(cmd, 0, sizeof(*cmd));
744 address &= ~(0xfffULL);
746 cmd->data[0] = devid;
747 cmd->data[0] |= (pasid & 0xff) << 16;
748 cmd->data[0] |= (qdep & 0xff) << 24;
749 cmd->data[1] = devid;
750 cmd->data[1] |= ((pasid >> 8) & 0xfff) << 16;
751 cmd->data[2] = lower_32_bits(address);
752 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
753 cmd->data[3] = upper_32_bits(address);
755 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
756 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
759 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
760 int status, int tag, bool gn)
762 memset(cmd, 0, sizeof(*cmd));
764 cmd->data[0] = devid;
766 cmd->data[1] = pasid & PASID_MASK;
767 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
769 cmd->data[3] = tag & 0x1ff;
770 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
772 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
775 static void build_inv_all(struct iommu_cmd *cmd)
777 memset(cmd, 0, sizeof(*cmd));
778 CMD_SET_TYPE(cmd, CMD_INV_ALL);
782 * Writes the command to the IOMMUs command buffer and informs the
783 * hardware about the new command.
785 static int iommu_queue_command_sync(struct amd_iommu *iommu,
786 struct iommu_cmd *cmd,
789 u32 left, tail, head, next_tail;
792 WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
795 spin_lock_irqsave(&iommu->lock, flags);
797 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
798 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
799 next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
800 left = (head - next_tail) % iommu->cmd_buf_size;
803 struct iommu_cmd sync_cmd;
804 volatile u64 sem = 0;
807 build_completion_wait(&sync_cmd, (u64)&sem);
808 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
810 spin_unlock_irqrestore(&iommu->lock, flags);
812 if ((ret = wait_on_sem(&sem)) != 0)
818 copy_cmd_to_buffer(iommu, cmd, tail);
820 /* We need to sync now to make sure all commands are processed */
821 iommu->need_sync = sync;
823 spin_unlock_irqrestore(&iommu->lock, flags);
828 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
830 return iommu_queue_command_sync(iommu, cmd, true);
834 * This function queues a completion wait command into the command
837 static int iommu_completion_wait(struct amd_iommu *iommu)
839 struct iommu_cmd cmd;
840 volatile u64 sem = 0;
843 if (!iommu->need_sync)
846 build_completion_wait(&cmd, (u64)&sem);
848 ret = iommu_queue_command_sync(iommu, &cmd, false);
852 return wait_on_sem(&sem);
855 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
857 struct iommu_cmd cmd;
859 build_inv_dte(&cmd, devid);
861 return iommu_queue_command(iommu, &cmd);
864 static void iommu_flush_dte_all(struct amd_iommu *iommu)
868 for (devid = 0; devid <= 0xffff; ++devid)
869 iommu_flush_dte(iommu, devid);
871 iommu_completion_wait(iommu);
875 * This function uses heavy locking and may disable irqs for some time. But
876 * this is no issue because it is only called during resume.
878 static void iommu_flush_tlb_all(struct amd_iommu *iommu)
882 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
883 struct iommu_cmd cmd;
884 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
886 iommu_queue_command(iommu, &cmd);
889 iommu_completion_wait(iommu);
892 static void iommu_flush_all(struct amd_iommu *iommu)
894 struct iommu_cmd cmd;
898 iommu_queue_command(iommu, &cmd);
899 iommu_completion_wait(iommu);
902 void iommu_flush_all_caches(struct amd_iommu *iommu)
904 if (iommu_feature(iommu, FEATURE_IA)) {
905 iommu_flush_all(iommu);
907 iommu_flush_dte_all(iommu);
908 iommu_flush_tlb_all(iommu);
913 * Command send function for flushing on-device TLB
915 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
916 u64 address, size_t size)
918 struct amd_iommu *iommu;
919 struct iommu_cmd cmd;
922 qdep = dev_data->ats.qdep;
923 iommu = amd_iommu_rlookup_table[dev_data->devid];
925 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
927 return iommu_queue_command(iommu, &cmd);
931 * Command send function for invalidating a device table entry
933 static int device_flush_dte(struct iommu_dev_data *dev_data)
935 struct amd_iommu *iommu;
938 iommu = amd_iommu_rlookup_table[dev_data->devid];
940 ret = iommu_flush_dte(iommu, dev_data->devid);
944 if (dev_data->ats.enabled)
945 ret = device_flush_iotlb(dev_data, 0, ~0UL);
951 * TLB invalidation function which is called from the mapping functions.
952 * It invalidates a single PTE if the range to flush is within a single
953 * page. Otherwise it flushes the whole TLB of the IOMMU.
955 static void __domain_flush_pages(struct protection_domain *domain,
956 u64 address, size_t size, int pde)
958 struct iommu_dev_data *dev_data;
959 struct iommu_cmd cmd;
962 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
964 for (i = 0; i < amd_iommus_present; ++i) {
965 if (!domain->dev_iommu[i])
969 * Devices of this domain are behind this IOMMU
970 * We need a TLB flush
972 ret |= iommu_queue_command(amd_iommus[i], &cmd);
975 list_for_each_entry(dev_data, &domain->dev_list, list) {
977 if (!dev_data->ats.enabled)
980 ret |= device_flush_iotlb(dev_data, address, size);
986 static void domain_flush_pages(struct protection_domain *domain,
987 u64 address, size_t size)
989 __domain_flush_pages(domain, address, size, 0);
992 /* Flush the whole IO/TLB for a given protection domain */
993 static void domain_flush_tlb(struct protection_domain *domain)
995 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
998 /* Flush the whole IO/TLB for a given protection domain - including PDE */
999 static void domain_flush_tlb_pde(struct protection_domain *domain)
1001 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1004 static void domain_flush_complete(struct protection_domain *domain)
1008 for (i = 0; i < amd_iommus_present; ++i) {
1009 if (!domain->dev_iommu[i])
1013 * Devices of this domain are behind this IOMMU
1014 * We need to wait for completion of all commands.
1016 iommu_completion_wait(amd_iommus[i]);
1022 * This function flushes the DTEs for all devices in domain
1024 static void domain_flush_devices(struct protection_domain *domain)
1026 struct iommu_dev_data *dev_data;
1028 list_for_each_entry(dev_data, &domain->dev_list, list)
1029 device_flush_dte(dev_data);
1032 /****************************************************************************
1034 * The functions below are used the create the page table mappings for
1035 * unity mapped regions.
1037 ****************************************************************************/
1040 * This function is used to add another level to an IO page table. Adding
1041 * another level increases the size of the address space by 9 bits to a size up
1044 static bool increase_address_space(struct protection_domain *domain,
1049 if (domain->mode == PAGE_MODE_6_LEVEL)
1050 /* address space already 64 bit large */
1053 pte = (void *)get_zeroed_page(gfp);
1057 *pte = PM_LEVEL_PDE(domain->mode,
1058 virt_to_phys(domain->pt_root));
1059 domain->pt_root = pte;
1061 domain->updated = true;
1066 static u64 *alloc_pte(struct protection_domain *domain,
1067 unsigned long address,
1068 unsigned long page_size,
1075 BUG_ON(!is_power_of_2(page_size));
1077 while (address > PM_LEVEL_SIZE(domain->mode))
1078 increase_address_space(domain, gfp);
1080 level = domain->mode - 1;
1081 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1082 address = PAGE_SIZE_ALIGN(address, page_size);
1083 end_lvl = PAGE_SIZE_LEVEL(page_size);
1085 while (level > end_lvl) {
1086 if (!IOMMU_PTE_PRESENT(*pte)) {
1087 page = (u64 *)get_zeroed_page(gfp);
1090 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
1093 /* No level skipping support yet */
1094 if (PM_PTE_LEVEL(*pte) != level)
1099 pte = IOMMU_PTE_PAGE(*pte);
1101 if (pte_page && level == end_lvl)
1104 pte = &pte[PM_LEVEL_INDEX(level, address)];
1111 * This function checks if there is a PTE for a given dma address. If
1112 * there is one, it returns the pointer to it.
1114 static u64 *fetch_pte(struct protection_domain *domain, unsigned long address)
1119 if (address > PM_LEVEL_SIZE(domain->mode))
1122 level = domain->mode - 1;
1123 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1128 if (!IOMMU_PTE_PRESENT(*pte))
1132 if (PM_PTE_LEVEL(*pte) == 0x07) {
1133 unsigned long pte_mask, __pte;
1136 * If we have a series of large PTEs, make
1137 * sure to return a pointer to the first one.
1139 pte_mask = PTE_PAGE_SIZE(*pte);
1140 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1141 __pte = ((unsigned long)pte) & pte_mask;
1143 return (u64 *)__pte;
1146 /* No level skipping support yet */
1147 if (PM_PTE_LEVEL(*pte) != level)
1152 /* Walk to the next level */
1153 pte = IOMMU_PTE_PAGE(*pte);
1154 pte = &pte[PM_LEVEL_INDEX(level, address)];
1161 * Generic mapping functions. It maps a physical address into a DMA
1162 * address space. It allocates the page table pages if necessary.
1163 * In the future it can be extended to a generic mapping function
1164 * supporting all features of AMD IOMMU page tables like level skipping
1165 * and full 64 bit address spaces.
1167 static int iommu_map_page(struct protection_domain *dom,
1168 unsigned long bus_addr,
1169 unsigned long phys_addr,
1171 unsigned long page_size)
1176 if (!(prot & IOMMU_PROT_MASK))
1179 bus_addr = PAGE_ALIGN(bus_addr);
1180 phys_addr = PAGE_ALIGN(phys_addr);
1181 count = PAGE_SIZE_PTE_COUNT(page_size);
1182 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
1184 for (i = 0; i < count; ++i)
1185 if (IOMMU_PTE_PRESENT(pte[i]))
1188 if (page_size > PAGE_SIZE) {
1189 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1190 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1192 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
1194 if (prot & IOMMU_PROT_IR)
1195 __pte |= IOMMU_PTE_IR;
1196 if (prot & IOMMU_PROT_IW)
1197 __pte |= IOMMU_PTE_IW;
1199 for (i = 0; i < count; ++i)
1207 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1208 unsigned long bus_addr,
1209 unsigned long page_size)
1211 unsigned long long unmap_size, unmapped;
1214 BUG_ON(!is_power_of_2(page_size));
1218 while (unmapped < page_size) {
1220 pte = fetch_pte(dom, bus_addr);
1224 * No PTE for this address
1225 * move forward in 4kb steps
1227 unmap_size = PAGE_SIZE;
1228 } else if (PM_PTE_LEVEL(*pte) == 0) {
1229 /* 4kb PTE found for this address */
1230 unmap_size = PAGE_SIZE;
1235 /* Large PTE found which maps this address */
1236 unmap_size = PTE_PAGE_SIZE(*pte);
1237 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1238 for (i = 0; i < count; i++)
1242 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1243 unmapped += unmap_size;
1246 BUG_ON(!is_power_of_2(unmapped));
1252 * This function checks if a specific unity mapping entry is needed for
1253 * this specific IOMMU.
1255 static int iommu_for_unity_map(struct amd_iommu *iommu,
1256 struct unity_map_entry *entry)
1260 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
1261 bdf = amd_iommu_alias_table[i];
1262 if (amd_iommu_rlookup_table[bdf] == iommu)
1270 * This function actually applies the mapping to the page table of the
1273 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
1274 struct unity_map_entry *e)
1279 for (addr = e->address_start; addr < e->address_end;
1280 addr += PAGE_SIZE) {
1281 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
1286 * if unity mapping is in aperture range mark the page
1287 * as allocated in the aperture
1289 if (addr < dma_dom->aperture_size)
1290 __set_bit(addr >> PAGE_SHIFT,
1291 dma_dom->aperture[0]->bitmap);
1298 * Init the unity mappings for a specific IOMMU in the system
1300 * Basically iterates over all unity mapping entries and applies them to
1301 * the default domain DMA of that IOMMU if necessary.
1303 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
1305 struct unity_map_entry *entry;
1308 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
1309 if (!iommu_for_unity_map(iommu, entry))
1311 ret = dma_ops_unity_map(iommu->default_dom, entry);
1320 * Inits the unity mappings required for a specific device
1322 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
1325 struct unity_map_entry *e;
1328 list_for_each_entry(e, &amd_iommu_unity_map, list) {
1329 if (!(devid >= e->devid_start && devid <= e->devid_end))
1331 ret = dma_ops_unity_map(dma_dom, e);
1339 /****************************************************************************
1341 * The next functions belong to the address allocator for the dma_ops
1342 * interface functions. They work like the allocators in the other IOMMU
1343 * drivers. Its basically a bitmap which marks the allocated pages in
1344 * the aperture. Maybe it could be enhanced in the future to a more
1345 * efficient allocator.
1347 ****************************************************************************/
1350 * The address allocator core functions.
1352 * called with domain->lock held
1356 * Used to reserve address ranges in the aperture (e.g. for exclusion
1359 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1360 unsigned long start_page,
1363 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1365 if (start_page + pages > last_page)
1366 pages = last_page - start_page;
1368 for (i = start_page; i < start_page + pages; ++i) {
1369 int index = i / APERTURE_RANGE_PAGES;
1370 int page = i % APERTURE_RANGE_PAGES;
1371 __set_bit(page, dom->aperture[index]->bitmap);
1376 * This function is used to add a new aperture range to an existing
1377 * aperture in case of dma_ops domain allocation or address allocation
1380 static int alloc_new_range(struct dma_ops_domain *dma_dom,
1381 bool populate, gfp_t gfp)
1383 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
1384 struct amd_iommu *iommu;
1385 unsigned long i, old_size;
1387 #ifdef CONFIG_IOMMU_STRESS
1391 if (index >= APERTURE_MAX_RANGES)
1394 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
1395 if (!dma_dom->aperture[index])
1398 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
1399 if (!dma_dom->aperture[index]->bitmap)
1402 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1405 unsigned long address = dma_dom->aperture_size;
1406 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1407 u64 *pte, *pte_page;
1409 for (i = 0; i < num_ptes; ++i) {
1410 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
1415 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1417 address += APERTURE_RANGE_SIZE / 64;
1421 old_size = dma_dom->aperture_size;
1422 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1424 /* Reserve address range used for MSI messages */
1425 if (old_size < MSI_ADDR_BASE_LO &&
1426 dma_dom->aperture_size > MSI_ADDR_BASE_LO) {
1427 unsigned long spage;
1430 pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE);
1431 spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT;
1433 dma_ops_reserve_addresses(dma_dom, spage, pages);
1436 /* Initialize the exclusion range if necessary */
1437 for_each_iommu(iommu) {
1438 if (iommu->exclusion_start &&
1439 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1440 && iommu->exclusion_start < dma_dom->aperture_size) {
1441 unsigned long startpage;
1442 int pages = iommu_num_pages(iommu->exclusion_start,
1443 iommu->exclusion_length,
1445 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1446 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1451 * Check for areas already mapped as present in the new aperture
1452 * range and mark those pages as reserved in the allocator. Such
1453 * mappings may already exist as a result of requested unity
1454 * mappings for devices.
1456 for (i = dma_dom->aperture[index]->offset;
1457 i < dma_dom->aperture_size;
1459 u64 *pte = fetch_pte(&dma_dom->domain, i);
1460 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1463 dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, 1);
1466 update_domain(&dma_dom->domain);
1471 update_domain(&dma_dom->domain);
1473 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1475 kfree(dma_dom->aperture[index]);
1476 dma_dom->aperture[index] = NULL;
1481 static unsigned long dma_ops_area_alloc(struct device *dev,
1482 struct dma_ops_domain *dom,
1484 unsigned long align_mask,
1486 unsigned long start)
1488 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
1489 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1490 int i = start >> APERTURE_RANGE_SHIFT;
1491 unsigned long boundary_size;
1492 unsigned long address = -1;
1493 unsigned long limit;
1495 next_bit >>= PAGE_SHIFT;
1497 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
1498 PAGE_SIZE) >> PAGE_SHIFT;
1500 for (;i < max_index; ++i) {
1501 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1503 if (dom->aperture[i]->offset >= dma_mask)
1506 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1507 dma_mask >> PAGE_SHIFT);
1509 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1510 limit, next_bit, pages, 0,
1511 boundary_size, align_mask);
1512 if (address != -1) {
1513 address = dom->aperture[i]->offset +
1514 (address << PAGE_SHIFT);
1515 dom->next_address = address + (pages << PAGE_SHIFT);
1525 static unsigned long dma_ops_alloc_addresses(struct device *dev,
1526 struct dma_ops_domain *dom,
1528 unsigned long align_mask,
1531 unsigned long address;
1533 #ifdef CONFIG_IOMMU_STRESS
1534 dom->next_address = 0;
1535 dom->need_flush = true;
1538 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1539 dma_mask, dom->next_address);
1541 if (address == -1) {
1542 dom->next_address = 0;
1543 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1545 dom->need_flush = true;
1548 if (unlikely(address == -1))
1549 address = DMA_ERROR_CODE;
1551 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1557 * The address free function.
1559 * called with domain->lock held
1561 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1562 unsigned long address,
1565 unsigned i = address >> APERTURE_RANGE_SHIFT;
1566 struct aperture_range *range = dom->aperture[i];
1568 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1570 #ifdef CONFIG_IOMMU_STRESS
1575 if (address >= dom->next_address)
1576 dom->need_flush = true;
1578 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1580 bitmap_clear(range->bitmap, address, pages);
1584 /****************************************************************************
1586 * The next functions belong to the domain allocation. A domain is
1587 * allocated for every IOMMU as the default domain. If device isolation
1588 * is enabled, every device get its own domain. The most important thing
1589 * about domains is the page table mapping the DMA address space they
1592 ****************************************************************************/
1595 * This function adds a protection domain to the global protection domain list
1597 static void add_domain_to_list(struct protection_domain *domain)
1599 unsigned long flags;
1601 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1602 list_add(&domain->list, &amd_iommu_pd_list);
1603 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1607 * This function removes a protection domain to the global
1608 * protection domain list
1610 static void del_domain_from_list(struct protection_domain *domain)
1612 unsigned long flags;
1614 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1615 list_del(&domain->list);
1616 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1619 static u16 domain_id_alloc(void)
1621 unsigned long flags;
1624 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1625 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1627 if (id > 0 && id < MAX_DOMAIN_ID)
1628 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1631 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1636 static void domain_id_free(int id)
1638 unsigned long flags;
1640 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1641 if (id > 0 && id < MAX_DOMAIN_ID)
1642 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1643 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1646 static void free_pagetable(struct protection_domain *domain)
1651 p1 = domain->pt_root;
1656 for (i = 0; i < 512; ++i) {
1657 if (!IOMMU_PTE_PRESENT(p1[i]))
1660 p2 = IOMMU_PTE_PAGE(p1[i]);
1661 for (j = 0; j < 512; ++j) {
1662 if (!IOMMU_PTE_PRESENT(p2[j]))
1664 p3 = IOMMU_PTE_PAGE(p2[j]);
1665 free_page((unsigned long)p3);
1668 free_page((unsigned long)p2);
1671 free_page((unsigned long)p1);
1673 domain->pt_root = NULL;
1676 static void free_gcr3_tbl_level1(u64 *tbl)
1681 for (i = 0; i < 512; ++i) {
1682 if (!(tbl[i] & GCR3_VALID))
1685 ptr = __va(tbl[i] & PAGE_MASK);
1687 free_page((unsigned long)ptr);
1691 static void free_gcr3_tbl_level2(u64 *tbl)
1696 for (i = 0; i < 512; ++i) {
1697 if (!(tbl[i] & GCR3_VALID))
1700 ptr = __va(tbl[i] & PAGE_MASK);
1702 free_gcr3_tbl_level1(ptr);
1706 static void free_gcr3_table(struct protection_domain *domain)
1708 if (domain->glx == 2)
1709 free_gcr3_tbl_level2(domain->gcr3_tbl);
1710 else if (domain->glx == 1)
1711 free_gcr3_tbl_level1(domain->gcr3_tbl);
1712 else if (domain->glx != 0)
1715 free_page((unsigned long)domain->gcr3_tbl);
1719 * Free a domain, only used if something went wrong in the
1720 * allocation path and we need to free an already allocated page table
1722 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1729 del_domain_from_list(&dom->domain);
1731 free_pagetable(&dom->domain);
1733 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1734 if (!dom->aperture[i])
1736 free_page((unsigned long)dom->aperture[i]->bitmap);
1737 kfree(dom->aperture[i]);
1744 * Allocates a new protection domain usable for the dma_ops functions.
1745 * It also initializes the page table and the address allocator data
1746 * structures required for the dma_ops interface
1748 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1750 struct dma_ops_domain *dma_dom;
1752 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1756 spin_lock_init(&dma_dom->domain.lock);
1758 dma_dom->domain.id = domain_id_alloc();
1759 if (dma_dom->domain.id == 0)
1761 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
1762 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
1763 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1764 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1765 dma_dom->domain.priv = dma_dom;
1766 if (!dma_dom->domain.pt_root)
1769 dma_dom->need_flush = false;
1770 dma_dom->target_dev = 0xffff;
1772 add_domain_to_list(&dma_dom->domain);
1774 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
1778 * mark the first page as allocated so we never return 0 as
1779 * a valid dma-address. So we can use 0 as error value
1781 dma_dom->aperture[0]->bitmap[0] = 1;
1782 dma_dom->next_address = 0;
1788 dma_ops_domain_free(dma_dom);
1794 * little helper function to check whether a given protection domain is a
1797 static bool dma_ops_domain(struct protection_domain *domain)
1799 return domain->flags & PD_DMA_OPS_MASK;
1802 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
1807 if (domain->mode != PAGE_MODE_NONE)
1808 pte_root = virt_to_phys(domain->pt_root);
1810 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1811 << DEV_ENTRY_MODE_SHIFT;
1812 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1814 flags = amd_iommu_dev_table[devid].data[1];
1817 flags |= DTE_FLAG_IOTLB;
1819 if (domain->flags & PD_IOMMUV2_MASK) {
1820 u64 gcr3 = __pa(domain->gcr3_tbl);
1821 u64 glx = domain->glx;
1824 pte_root |= DTE_FLAG_GV;
1825 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1827 /* First mask out possible old values for GCR3 table */
1828 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1831 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1834 /* Encode GCR3 table into DTE */
1835 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1838 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1841 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1845 flags &= ~(0xffffUL);
1846 flags |= domain->id;
1848 amd_iommu_dev_table[devid].data[1] = flags;
1849 amd_iommu_dev_table[devid].data[0] = pte_root;
1852 static void clear_dte_entry(u16 devid)
1854 /* remove entry from the device table seen by the hardware */
1855 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1856 amd_iommu_dev_table[devid].data[1] = 0;
1858 amd_iommu_apply_erratum_63(devid);
1861 static void do_attach(struct iommu_dev_data *dev_data,
1862 struct protection_domain *domain)
1864 struct amd_iommu *iommu;
1867 iommu = amd_iommu_rlookup_table[dev_data->devid];
1868 ats = dev_data->ats.enabled;
1870 /* Update data structures */
1871 dev_data->domain = domain;
1872 list_add(&dev_data->list, &domain->dev_list);
1873 set_dte_entry(dev_data->devid, domain, ats);
1875 /* Do reference counting */
1876 domain->dev_iommu[iommu->index] += 1;
1877 domain->dev_cnt += 1;
1879 /* Flush the DTE entry */
1880 device_flush_dte(dev_data);
1883 static void do_detach(struct iommu_dev_data *dev_data)
1885 struct amd_iommu *iommu;
1887 iommu = amd_iommu_rlookup_table[dev_data->devid];
1889 /* decrease reference counters */
1890 dev_data->domain->dev_iommu[iommu->index] -= 1;
1891 dev_data->domain->dev_cnt -= 1;
1893 /* Update data structures */
1894 dev_data->domain = NULL;
1895 list_del(&dev_data->list);
1896 clear_dte_entry(dev_data->devid);
1898 /* Flush the DTE entry */
1899 device_flush_dte(dev_data);
1903 * If a device is not yet associated with a domain, this function does
1904 * assigns it visible for the hardware
1906 static int __attach_device(struct iommu_dev_data *dev_data,
1907 struct protection_domain *domain)
1912 spin_lock(&domain->lock);
1914 if (dev_data->alias_data != NULL) {
1915 struct iommu_dev_data *alias_data = dev_data->alias_data;
1917 /* Some sanity checks */
1919 if (alias_data->domain != NULL &&
1920 alias_data->domain != domain)
1923 if (dev_data->domain != NULL &&
1924 dev_data->domain != domain)
1927 /* Do real assignment */
1928 if (alias_data->domain == NULL)
1929 do_attach(alias_data, domain);
1931 atomic_inc(&alias_data->bind);
1934 if (dev_data->domain == NULL)
1935 do_attach(dev_data, domain);
1937 atomic_inc(&dev_data->bind);
1944 spin_unlock(&domain->lock);
1950 static void pdev_iommuv2_disable(struct pci_dev *pdev)
1952 pci_disable_ats(pdev);
1953 pci_disable_pri(pdev);
1954 pci_disable_pasid(pdev);
1957 /* FIXME: Change generic reset-function to do the same */
1958 static int pri_reset_while_enabled(struct pci_dev *pdev)
1963 pos = pci_find_ext_capability(pdev, PCI_PRI_CAP);
1967 pci_read_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, &control);
1968 control |= PCI_PRI_RESET;
1969 pci_write_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, control);
1974 static int pdev_iommuv2_enable(struct pci_dev *pdev)
1979 /* FIXME: Hardcode number of outstanding requests for now */
1981 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
1983 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
1985 /* Only allow access to user-accessible pages */
1986 ret = pci_enable_pasid(pdev, 0);
1990 /* First reset the PRI state of the device */
1991 ret = pci_reset_pri(pdev);
1996 ret = pci_enable_pri(pdev, reqs);
2001 ret = pri_reset_while_enabled(pdev);
2006 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2013 pci_disable_pri(pdev);
2014 pci_disable_pasid(pdev);
2019 /* FIXME: Move this to PCI code */
2020 #define PCI_PRI_TLP_OFF (1 << 2)
2022 bool pci_pri_tlp_required(struct pci_dev *pdev)
2027 pos = pci_find_ext_capability(pdev, PCI_PRI_CAP);
2031 pci_read_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, &control);
2033 return (control & PCI_PRI_TLP_OFF) ? true : false;
2037 * If a device is not yet associated with a domain, this function does
2038 * assigns it visible for the hardware
2040 static int attach_device(struct device *dev,
2041 struct protection_domain *domain)
2043 struct pci_dev *pdev = to_pci_dev(dev);
2044 struct iommu_dev_data *dev_data;
2045 unsigned long flags;
2048 dev_data = get_dev_data(dev);
2050 if (domain->flags & PD_IOMMUV2_MASK) {
2051 if (!dev_data->iommu_v2 || !dev_data->passthrough)
2054 if (pdev_iommuv2_enable(pdev) != 0)
2057 dev_data->ats.enabled = true;
2058 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2059 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2060 } else if (amd_iommu_iotlb_sup &&
2061 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2062 dev_data->ats.enabled = true;
2063 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2066 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2067 ret = __attach_device(dev_data, domain);
2068 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2071 * We might boot into a crash-kernel here. The crashed kernel
2072 * left the caches in the IOMMU dirty. So we have to flush
2073 * here to evict all dirty stuff.
2075 domain_flush_tlb_pde(domain);
2081 * Removes a device from a protection domain (unlocked)
2083 static void __detach_device(struct iommu_dev_data *dev_data)
2085 struct protection_domain *domain;
2086 unsigned long flags;
2088 BUG_ON(!dev_data->domain);
2090 domain = dev_data->domain;
2092 spin_lock_irqsave(&domain->lock, flags);
2094 if (dev_data->alias_data != NULL) {
2095 struct iommu_dev_data *alias_data = dev_data->alias_data;
2097 if (atomic_dec_and_test(&alias_data->bind))
2098 do_detach(alias_data);
2101 if (atomic_dec_and_test(&dev_data->bind))
2102 do_detach(dev_data);
2104 spin_unlock_irqrestore(&domain->lock, flags);
2107 * If we run in passthrough mode the device must be assigned to the
2108 * passthrough domain if it is detached from any other domain.
2109 * Make sure we can deassign from the pt_domain itself.
2111 if (dev_data->passthrough &&
2112 (dev_data->domain == NULL && domain != pt_domain))
2113 __attach_device(dev_data, pt_domain);
2117 * Removes a device from a protection domain (with devtable_lock held)
2119 static void detach_device(struct device *dev)
2121 struct protection_domain *domain;
2122 struct iommu_dev_data *dev_data;
2123 unsigned long flags;
2125 dev_data = get_dev_data(dev);
2126 domain = dev_data->domain;
2128 /* lock device table */
2129 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2130 __detach_device(dev_data);
2131 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2133 if (domain->flags & PD_IOMMUV2_MASK)
2134 pdev_iommuv2_disable(to_pci_dev(dev));
2135 else if (dev_data->ats.enabled)
2136 pci_disable_ats(to_pci_dev(dev));
2138 dev_data->ats.enabled = false;
2142 * Find out the protection domain structure for a given PCI device. This
2143 * will give us the pointer to the page table root for example.
2145 static struct protection_domain *domain_for_device(struct device *dev)
2147 struct iommu_dev_data *dev_data;
2148 struct protection_domain *dom = NULL;
2149 unsigned long flags;
2151 dev_data = get_dev_data(dev);
2153 if (dev_data->domain)
2154 return dev_data->domain;
2156 if (dev_data->alias_data != NULL) {
2157 struct iommu_dev_data *alias_data = dev_data->alias_data;
2159 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
2160 if (alias_data->domain != NULL) {
2161 __attach_device(dev_data, alias_data->domain);
2162 dom = alias_data->domain;
2164 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2170 static int device_change_notifier(struct notifier_block *nb,
2171 unsigned long action, void *data)
2173 struct dma_ops_domain *dma_domain;
2174 struct protection_domain *domain;
2175 struct iommu_dev_data *dev_data;
2176 struct device *dev = data;
2177 struct amd_iommu *iommu;
2178 unsigned long flags;
2181 if (!check_device(dev))
2184 devid = get_device_id(dev);
2185 iommu = amd_iommu_rlookup_table[devid];
2186 dev_data = get_dev_data(dev);
2189 case BUS_NOTIFY_UNBOUND_DRIVER:
2191 domain = domain_for_device(dev);
2195 if (dev_data->passthrough)
2199 case BUS_NOTIFY_ADD_DEVICE:
2201 iommu_init_device(dev);
2203 domain = domain_for_device(dev);
2205 /* allocate a protection domain if a device is added */
2206 dma_domain = find_protection_domain(devid);
2209 dma_domain = dma_ops_domain_alloc();
2212 dma_domain->target_dev = devid;
2214 spin_lock_irqsave(&iommu_pd_list_lock, flags);
2215 list_add_tail(&dma_domain->list, &iommu_pd_list);
2216 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
2219 case BUS_NOTIFY_DEL_DEVICE:
2221 iommu_uninit_device(dev);
2227 iommu_completion_wait(iommu);
2233 static struct notifier_block device_nb = {
2234 .notifier_call = device_change_notifier,
2237 void amd_iommu_init_notifier(void)
2239 bus_register_notifier(&pci_bus_type, &device_nb);
2242 /*****************************************************************************
2244 * The next functions belong to the dma_ops mapping/unmapping code.
2246 *****************************************************************************/
2249 * In the dma_ops path we only have the struct device. This function
2250 * finds the corresponding IOMMU, the protection domain and the
2251 * requestor id for a given device.
2252 * If the device is not yet associated with a domain this is also done
2255 static struct protection_domain *get_domain(struct device *dev)
2257 struct protection_domain *domain;
2258 struct dma_ops_domain *dma_dom;
2259 u16 devid = get_device_id(dev);
2261 if (!check_device(dev))
2262 return ERR_PTR(-EINVAL);
2264 domain = domain_for_device(dev);
2265 if (domain != NULL && !dma_ops_domain(domain))
2266 return ERR_PTR(-EBUSY);
2271 /* Device not bount yet - bind it */
2272 dma_dom = find_protection_domain(devid);
2274 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
2275 attach_device(dev, &dma_dom->domain);
2276 DUMP_printk("Using protection domain %d for device %s\n",
2277 dma_dom->domain.id, dev_name(dev));
2279 return &dma_dom->domain;
2282 static void update_device_table(struct protection_domain *domain)
2284 struct iommu_dev_data *dev_data;
2286 list_for_each_entry(dev_data, &domain->dev_list, list)
2287 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
2290 static void update_domain(struct protection_domain *domain)
2292 if (!domain->updated)
2295 update_device_table(domain);
2297 domain_flush_devices(domain);
2298 domain_flush_tlb_pde(domain);
2300 domain->updated = false;
2304 * This function fetches the PTE for a given address in the aperture
2306 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
2307 unsigned long address)
2309 struct aperture_range *aperture;
2310 u64 *pte, *pte_page;
2312 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2316 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2318 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
2320 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
2322 pte += PM_LEVEL_INDEX(0, address);
2324 update_domain(&dom->domain);
2330 * This is the generic map function. It maps one 4kb page at paddr to
2331 * the given address in the DMA address space for the domain.
2333 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
2334 unsigned long address,
2340 WARN_ON(address > dom->aperture_size);
2344 pte = dma_ops_get_pte(dom, address);
2346 return DMA_ERROR_CODE;
2348 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
2350 if (direction == DMA_TO_DEVICE)
2351 __pte |= IOMMU_PTE_IR;
2352 else if (direction == DMA_FROM_DEVICE)
2353 __pte |= IOMMU_PTE_IW;
2354 else if (direction == DMA_BIDIRECTIONAL)
2355 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
2361 return (dma_addr_t)address;
2365 * The generic unmapping function for on page in the DMA address space.
2367 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
2368 unsigned long address)
2370 struct aperture_range *aperture;
2373 if (address >= dom->aperture_size)
2376 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2380 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2384 pte += PM_LEVEL_INDEX(0, address);
2392 * This function contains common code for mapping of a physically
2393 * contiguous memory region into DMA address space. It is used by all
2394 * mapping functions provided with this IOMMU driver.
2395 * Must be called with the domain lock held.
2397 static dma_addr_t __map_single(struct device *dev,
2398 struct dma_ops_domain *dma_dom,
2405 dma_addr_t offset = paddr & ~PAGE_MASK;
2406 dma_addr_t address, start, ret;
2408 unsigned long align_mask = 0;
2411 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2414 INC_STATS_COUNTER(total_map_requests);
2417 INC_STATS_COUNTER(cross_page);
2420 align_mask = (1UL << get_order(size)) - 1;
2423 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
2425 if (unlikely(address == DMA_ERROR_CODE)) {
2427 * setting next_address here will let the address
2428 * allocator only scan the new allocated range in the
2429 * first run. This is a small optimization.
2431 dma_dom->next_address = dma_dom->aperture_size;
2433 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
2437 * aperture was successfully enlarged by 128 MB, try
2444 for (i = 0; i < pages; ++i) {
2445 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
2446 if (ret == DMA_ERROR_CODE)
2454 ADD_STATS_COUNTER(alloced_io_mem, size);
2456 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
2457 domain_flush_tlb(&dma_dom->domain);
2458 dma_dom->need_flush = false;
2459 } else if (unlikely(amd_iommu_np_cache))
2460 domain_flush_pages(&dma_dom->domain, address, size);
2467 for (--i; i >= 0; --i) {
2469 dma_ops_domain_unmap(dma_dom, start);
2472 dma_ops_free_addresses(dma_dom, address, pages);
2474 return DMA_ERROR_CODE;
2478 * Does the reverse of the __map_single function. Must be called with
2479 * the domain lock held too
2481 static void __unmap_single(struct dma_ops_domain *dma_dom,
2482 dma_addr_t dma_addr,
2486 dma_addr_t flush_addr;
2487 dma_addr_t i, start;
2490 if ((dma_addr == DMA_ERROR_CODE) ||
2491 (dma_addr + size > dma_dom->aperture_size))
2494 flush_addr = dma_addr;
2495 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2496 dma_addr &= PAGE_MASK;
2499 for (i = 0; i < pages; ++i) {
2500 dma_ops_domain_unmap(dma_dom, start);
2504 SUB_STATS_COUNTER(alloced_io_mem, size);
2506 dma_ops_free_addresses(dma_dom, dma_addr, pages);
2508 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
2509 domain_flush_pages(&dma_dom->domain, flush_addr, size);
2510 dma_dom->need_flush = false;
2515 * The exported map_single function for dma_ops.
2517 static dma_addr_t map_page(struct device *dev, struct page *page,
2518 unsigned long offset, size_t size,
2519 enum dma_data_direction dir,
2520 struct dma_attrs *attrs)
2522 unsigned long flags;
2523 struct protection_domain *domain;
2526 phys_addr_t paddr = page_to_phys(page) + offset;
2528 INC_STATS_COUNTER(cnt_map_single);
2530 domain = get_domain(dev);
2531 if (PTR_ERR(domain) == -EINVAL)
2532 return (dma_addr_t)paddr;
2533 else if (IS_ERR(domain))
2534 return DMA_ERROR_CODE;
2536 dma_mask = *dev->dma_mask;
2538 spin_lock_irqsave(&domain->lock, flags);
2540 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
2542 if (addr == DMA_ERROR_CODE)
2545 domain_flush_complete(domain);
2548 spin_unlock_irqrestore(&domain->lock, flags);
2554 * The exported unmap_single function for dma_ops.
2556 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2557 enum dma_data_direction dir, struct dma_attrs *attrs)
2559 unsigned long flags;
2560 struct protection_domain *domain;
2562 INC_STATS_COUNTER(cnt_unmap_single);
2564 domain = get_domain(dev);
2568 spin_lock_irqsave(&domain->lock, flags);
2570 __unmap_single(domain->priv, dma_addr, size, dir);
2572 domain_flush_complete(domain);
2574 spin_unlock_irqrestore(&domain->lock, flags);
2578 * This is a special map_sg function which is used if we should map a
2579 * device which is not handled by an AMD IOMMU in the system.
2581 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
2582 int nelems, int dir)
2584 struct scatterlist *s;
2587 for_each_sg(sglist, s, nelems, i) {
2588 s->dma_address = (dma_addr_t)sg_phys(s);
2589 s->dma_length = s->length;
2596 * The exported map_sg function for dma_ops (handles scatter-gather
2599 static int map_sg(struct device *dev, struct scatterlist *sglist,
2600 int nelems, enum dma_data_direction dir,
2601 struct dma_attrs *attrs)
2603 unsigned long flags;
2604 struct protection_domain *domain;
2606 struct scatterlist *s;
2608 int mapped_elems = 0;
2611 INC_STATS_COUNTER(cnt_map_sg);
2613 domain = get_domain(dev);
2614 if (PTR_ERR(domain) == -EINVAL)
2615 return map_sg_no_iommu(dev, sglist, nelems, dir);
2616 else if (IS_ERR(domain))
2619 dma_mask = *dev->dma_mask;
2621 spin_lock_irqsave(&domain->lock, flags);
2623 for_each_sg(sglist, s, nelems, i) {
2626 s->dma_address = __map_single(dev, domain->priv,
2627 paddr, s->length, dir, false,
2630 if (s->dma_address) {
2631 s->dma_length = s->length;
2637 domain_flush_complete(domain);
2640 spin_unlock_irqrestore(&domain->lock, flags);
2642 return mapped_elems;
2644 for_each_sg(sglist, s, mapped_elems, i) {
2646 __unmap_single(domain->priv, s->dma_address,
2647 s->dma_length, dir);
2648 s->dma_address = s->dma_length = 0;
2657 * The exported map_sg function for dma_ops (handles scatter-gather
2660 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2661 int nelems, enum dma_data_direction dir,
2662 struct dma_attrs *attrs)
2664 unsigned long flags;
2665 struct protection_domain *domain;
2666 struct scatterlist *s;
2669 INC_STATS_COUNTER(cnt_unmap_sg);
2671 domain = get_domain(dev);
2675 spin_lock_irqsave(&domain->lock, flags);
2677 for_each_sg(sglist, s, nelems, i) {
2678 __unmap_single(domain->priv, s->dma_address,
2679 s->dma_length, dir);
2680 s->dma_address = s->dma_length = 0;
2683 domain_flush_complete(domain);
2685 spin_unlock_irqrestore(&domain->lock, flags);
2689 * The exported alloc_coherent function for dma_ops.
2691 static void *alloc_coherent(struct device *dev, size_t size,
2692 dma_addr_t *dma_addr, gfp_t flag)
2694 unsigned long flags;
2696 struct protection_domain *domain;
2698 u64 dma_mask = dev->coherent_dma_mask;
2700 INC_STATS_COUNTER(cnt_alloc_coherent);
2702 domain = get_domain(dev);
2703 if (PTR_ERR(domain) == -EINVAL) {
2704 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2705 *dma_addr = __pa(virt_addr);
2707 } else if (IS_ERR(domain))
2710 dma_mask = dev->coherent_dma_mask;
2711 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2714 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2718 paddr = virt_to_phys(virt_addr);
2721 dma_mask = *dev->dma_mask;
2723 spin_lock_irqsave(&domain->lock, flags);
2725 *dma_addr = __map_single(dev, domain->priv, paddr,
2726 size, DMA_BIDIRECTIONAL, true, dma_mask);
2728 if (*dma_addr == DMA_ERROR_CODE) {
2729 spin_unlock_irqrestore(&domain->lock, flags);
2733 domain_flush_complete(domain);
2735 spin_unlock_irqrestore(&domain->lock, flags);
2741 free_pages((unsigned long)virt_addr, get_order(size));
2747 * The exported free_coherent function for dma_ops.
2749 static void free_coherent(struct device *dev, size_t size,
2750 void *virt_addr, dma_addr_t dma_addr)
2752 unsigned long flags;
2753 struct protection_domain *domain;
2755 INC_STATS_COUNTER(cnt_free_coherent);
2757 domain = get_domain(dev);
2761 spin_lock_irqsave(&domain->lock, flags);
2763 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2765 domain_flush_complete(domain);
2767 spin_unlock_irqrestore(&domain->lock, flags);
2770 free_pages((unsigned long)virt_addr, get_order(size));
2774 * This function is called by the DMA layer to find out if we can handle a
2775 * particular device. It is part of the dma_ops.
2777 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2779 return check_device(dev);
2783 * The function for pre-allocating protection domains.
2785 * If the driver core informs the DMA layer if a driver grabs a device
2786 * we don't need to preallocate the protection domains anymore.
2787 * For now we have to.
2789 static void prealloc_protection_domains(void)
2791 struct iommu_dev_data *dev_data;
2792 struct dma_ops_domain *dma_dom;
2793 struct pci_dev *dev = NULL;
2796 for_each_pci_dev(dev) {
2798 /* Do we handle this device? */
2799 if (!check_device(&dev->dev))
2802 dev_data = get_dev_data(&dev->dev);
2803 if (!amd_iommu_force_isolation && dev_data->iommu_v2) {
2804 /* Make sure passthrough domain is allocated */
2805 alloc_passthrough_domain();
2806 dev_data->passthrough = true;
2807 attach_device(&dev->dev, pt_domain);
2808 pr_info("AMD-Vi: Using passthough domain for device %s\n",
2809 dev_name(&dev->dev));
2812 /* Is there already any domain for it? */
2813 if (domain_for_device(&dev->dev))
2816 devid = get_device_id(&dev->dev);
2818 dma_dom = dma_ops_domain_alloc();
2821 init_unity_mappings_for_device(dma_dom, devid);
2822 dma_dom->target_dev = devid;
2824 attach_device(&dev->dev, &dma_dom->domain);
2826 list_add_tail(&dma_dom->list, &iommu_pd_list);
2830 static struct dma_map_ops amd_iommu_dma_ops = {
2831 .alloc_coherent = alloc_coherent,
2832 .free_coherent = free_coherent,
2833 .map_page = map_page,
2834 .unmap_page = unmap_page,
2836 .unmap_sg = unmap_sg,
2837 .dma_supported = amd_iommu_dma_supported,
2840 static unsigned device_dma_ops_init(void)
2842 struct iommu_dev_data *dev_data;
2843 struct pci_dev *pdev = NULL;
2844 unsigned unhandled = 0;
2846 for_each_pci_dev(pdev) {
2847 if (!check_device(&pdev->dev)) {
2852 dev_data = get_dev_data(&pdev->dev);
2854 if (!dev_data->passthrough)
2855 pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops;
2857 pdev->dev.archdata.dma_ops = &nommu_dma_ops;
2864 * The function which clues the AMD IOMMU driver into dma_ops.
2867 void __init amd_iommu_init_api(void)
2869 bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2872 int __init amd_iommu_init_dma_ops(void)
2874 struct amd_iommu *iommu;
2878 * first allocate a default protection domain for every IOMMU we
2879 * found in the system. Devices not assigned to any other
2880 * protection domain will be assigned to the default one.
2882 for_each_iommu(iommu) {
2883 iommu->default_dom = dma_ops_domain_alloc();
2884 if (iommu->default_dom == NULL)
2886 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
2887 ret = iommu_init_unity_mappings(iommu);
2893 * Pre-allocate the protection domains for each device.
2895 prealloc_protection_domains();
2900 /* Make the driver finally visible to the drivers */
2901 unhandled = device_dma_ops_init();
2902 if (unhandled && max_pfn > MAX_DMA32_PFN) {
2903 /* There are unhandled devices - initialize swiotlb for them */
2907 amd_iommu_stats_init();
2913 for_each_iommu(iommu) {
2914 if (iommu->default_dom)
2915 dma_ops_domain_free(iommu->default_dom);
2921 /*****************************************************************************
2923 * The following functions belong to the exported interface of AMD IOMMU
2925 * This interface allows access to lower level functions of the IOMMU
2926 * like protection domain handling and assignement of devices to domains
2927 * which is not possible with the dma_ops interface.
2929 *****************************************************************************/
2931 static void cleanup_domain(struct protection_domain *domain)
2933 struct iommu_dev_data *dev_data, *next;
2934 unsigned long flags;
2936 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2938 list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) {
2939 __detach_device(dev_data);
2940 atomic_set(&dev_data->bind, 0);
2943 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2946 static void protection_domain_free(struct protection_domain *domain)
2951 del_domain_from_list(domain);
2954 domain_id_free(domain->id);
2959 static struct protection_domain *protection_domain_alloc(void)
2961 struct protection_domain *domain;
2963 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2967 spin_lock_init(&domain->lock);
2968 mutex_init(&domain->api_lock);
2969 domain->id = domain_id_alloc();
2972 INIT_LIST_HEAD(&domain->dev_list);
2974 add_domain_to_list(domain);
2984 static int __init alloc_passthrough_domain(void)
2986 if (pt_domain != NULL)
2989 /* allocate passthrough domain */
2990 pt_domain = protection_domain_alloc();
2994 pt_domain->mode = PAGE_MODE_NONE;
2998 static int amd_iommu_domain_init(struct iommu_domain *dom)
3000 struct protection_domain *domain;
3002 domain = protection_domain_alloc();
3006 domain->mode = PAGE_MODE_3_LEVEL;
3007 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
3008 if (!domain->pt_root)
3011 domain->iommu_domain = dom;
3018 protection_domain_free(domain);
3023 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
3025 struct protection_domain *domain = dom->priv;
3030 if (domain->dev_cnt > 0)
3031 cleanup_domain(domain);
3033 BUG_ON(domain->dev_cnt != 0);
3035 if (domain->mode != PAGE_MODE_NONE)
3036 free_pagetable(domain);
3038 if (domain->flags & PD_IOMMUV2_MASK)
3039 free_gcr3_table(domain);
3041 protection_domain_free(domain);
3046 static void amd_iommu_detach_device(struct iommu_domain *dom,
3049 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3050 struct amd_iommu *iommu;
3053 if (!check_device(dev))
3056 devid = get_device_id(dev);
3058 if (dev_data->domain != NULL)
3061 iommu = amd_iommu_rlookup_table[devid];
3065 iommu_completion_wait(iommu);
3068 static int amd_iommu_attach_device(struct iommu_domain *dom,
3071 struct protection_domain *domain = dom->priv;
3072 struct iommu_dev_data *dev_data;
3073 struct amd_iommu *iommu;
3076 if (!check_device(dev))
3079 dev_data = dev->archdata.iommu;
3081 iommu = amd_iommu_rlookup_table[dev_data->devid];
3085 if (dev_data->domain)
3088 ret = attach_device(dev, domain);
3090 iommu_completion_wait(iommu);
3095 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3096 phys_addr_t paddr, int gfp_order, int iommu_prot)
3098 unsigned long page_size = 0x1000UL << gfp_order;
3099 struct protection_domain *domain = dom->priv;
3103 if (domain->mode == PAGE_MODE_NONE)
3106 if (iommu_prot & IOMMU_READ)
3107 prot |= IOMMU_PROT_IR;
3108 if (iommu_prot & IOMMU_WRITE)
3109 prot |= IOMMU_PROT_IW;
3111 mutex_lock(&domain->api_lock);
3112 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
3113 mutex_unlock(&domain->api_lock);
3118 static int amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3121 struct protection_domain *domain = dom->priv;
3122 unsigned long page_size, unmap_size;
3124 if (domain->mode == PAGE_MODE_NONE)
3127 page_size = 0x1000UL << gfp_order;
3129 mutex_lock(&domain->api_lock);
3130 unmap_size = iommu_unmap_page(domain, iova, page_size);
3131 mutex_unlock(&domain->api_lock);
3133 domain_flush_tlb_pde(domain);
3135 return get_order(unmap_size);
3138 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3141 struct protection_domain *domain = dom->priv;
3142 unsigned long offset_mask;
3146 if (domain->mode == PAGE_MODE_NONE)
3149 pte = fetch_pte(domain, iova);
3151 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3154 if (PM_PTE_LEVEL(*pte) == 0)
3155 offset_mask = PAGE_SIZE - 1;
3157 offset_mask = PTE_PAGE_SIZE(*pte) - 1;
3159 __pte = *pte & PM_ADDR_MASK;
3160 paddr = (__pte & ~offset_mask) | (iova & offset_mask);
3165 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
3169 case IOMMU_CAP_CACHE_COHERENCY:
3176 static struct iommu_ops amd_iommu_ops = {
3177 .domain_init = amd_iommu_domain_init,
3178 .domain_destroy = amd_iommu_domain_destroy,
3179 .attach_dev = amd_iommu_attach_device,
3180 .detach_dev = amd_iommu_detach_device,
3181 .map = amd_iommu_map,
3182 .unmap = amd_iommu_unmap,
3183 .iova_to_phys = amd_iommu_iova_to_phys,
3184 .domain_has_cap = amd_iommu_domain_has_cap,
3187 /*****************************************************************************
3189 * The next functions do a basic initialization of IOMMU for pass through
3192 * In passthrough mode the IOMMU is initialized and enabled but not used for
3193 * DMA-API translation.
3195 *****************************************************************************/
3197 int __init amd_iommu_init_passthrough(void)
3199 struct iommu_dev_data *dev_data;
3200 struct pci_dev *dev = NULL;
3201 struct amd_iommu *iommu;
3205 ret = alloc_passthrough_domain();
3209 for_each_pci_dev(dev) {
3210 if (!check_device(&dev->dev))
3213 dev_data = get_dev_data(&dev->dev);
3214 dev_data->passthrough = true;
3216 devid = get_device_id(&dev->dev);
3218 iommu = amd_iommu_rlookup_table[devid];
3222 attach_device(&dev->dev, pt_domain);
3225 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
3230 /* IOMMUv2 specific functions */
3231 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3233 return atomic_notifier_chain_register(&ppr_notifier, nb);
3235 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3237 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3239 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3241 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3243 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3245 struct protection_domain *domain = dom->priv;
3246 unsigned long flags;
3248 spin_lock_irqsave(&domain->lock, flags);
3250 /* Update data structure */
3251 domain->mode = PAGE_MODE_NONE;
3252 domain->updated = true;
3254 /* Make changes visible to IOMMUs */
3255 update_domain(domain);
3257 /* Page-table is not visible to IOMMU anymore, so free it */
3258 free_pagetable(domain);
3260 spin_unlock_irqrestore(&domain->lock, flags);
3262 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3264 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3266 struct protection_domain *domain = dom->priv;
3267 unsigned long flags;
3270 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3273 /* Number of GCR3 table levels required */
3274 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3277 if (levels > amd_iommu_max_glx_val)
3280 spin_lock_irqsave(&domain->lock, flags);
3283 * Save us all sanity checks whether devices already in the
3284 * domain support IOMMUv2. Just force that the domain has no
3285 * devices attached when it is switched into IOMMUv2 mode.
3288 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3292 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3293 if (domain->gcr3_tbl == NULL)
3296 domain->glx = levels;
3297 domain->flags |= PD_IOMMUV2_MASK;
3298 domain->updated = true;
3300 update_domain(domain);
3305 spin_unlock_irqrestore(&domain->lock, flags);
3309 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3311 static int __flush_pasid(struct protection_domain *domain, int pasid,
3312 u64 address, bool size)
3314 struct iommu_dev_data *dev_data;
3315 struct iommu_cmd cmd;
3318 if (!(domain->flags & PD_IOMMUV2_MASK))
3321 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3324 * IOMMU TLB needs to be flushed before Device TLB to
3325 * prevent device TLB refill from IOMMU TLB
3327 for (i = 0; i < amd_iommus_present; ++i) {
3328 if (domain->dev_iommu[i] == 0)
3331 ret = iommu_queue_command(amd_iommus[i], &cmd);
3336 /* Wait until IOMMU TLB flushes are complete */
3337 domain_flush_complete(domain);
3339 /* Now flush device TLBs */
3340 list_for_each_entry(dev_data, &domain->dev_list, list) {
3341 struct amd_iommu *iommu;
3344 BUG_ON(!dev_data->ats.enabled);
3346 qdep = dev_data->ats.qdep;
3347 iommu = amd_iommu_rlookup_table[dev_data->devid];
3349 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3350 qdep, address, size);
3352 ret = iommu_queue_command(iommu, &cmd);
3357 /* Wait until all device TLBs are flushed */
3358 domain_flush_complete(domain);
3367 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3370 INC_STATS_COUNTER(invalidate_iotlb);
3372 return __flush_pasid(domain, pasid, address, false);
3375 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3378 struct protection_domain *domain = dom->priv;
3379 unsigned long flags;
3382 spin_lock_irqsave(&domain->lock, flags);
3383 ret = __amd_iommu_flush_page(domain, pasid, address);
3384 spin_unlock_irqrestore(&domain->lock, flags);
3388 EXPORT_SYMBOL(amd_iommu_flush_page);
3390 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3392 INC_STATS_COUNTER(invalidate_iotlb_all);
3394 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3398 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3400 struct protection_domain *domain = dom->priv;
3401 unsigned long flags;
3404 spin_lock_irqsave(&domain->lock, flags);
3405 ret = __amd_iommu_flush_tlb(domain, pasid);
3406 spin_unlock_irqrestore(&domain->lock, flags);
3410 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3412 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3419 index = (pasid >> (9 * level)) & 0x1ff;
3425 if (!(*pte & GCR3_VALID)) {
3429 root = (void *)get_zeroed_page(GFP_ATOMIC);
3433 *pte = __pa(root) | GCR3_VALID;
3436 root = __va(*pte & PAGE_MASK);
3444 static int __set_gcr3(struct protection_domain *domain, int pasid,
3449 if (domain->mode != PAGE_MODE_NONE)
3452 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3456 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3458 return __amd_iommu_flush_tlb(domain, pasid);
3461 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3465 if (domain->mode != PAGE_MODE_NONE)
3468 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3474 return __amd_iommu_flush_tlb(domain, pasid);
3477 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3480 struct protection_domain *domain = dom->priv;
3481 unsigned long flags;
3484 spin_lock_irqsave(&domain->lock, flags);
3485 ret = __set_gcr3(domain, pasid, cr3);
3486 spin_unlock_irqrestore(&domain->lock, flags);
3490 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3492 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3494 struct protection_domain *domain = dom->priv;
3495 unsigned long flags;
3498 spin_lock_irqsave(&domain->lock, flags);
3499 ret = __clear_gcr3(domain, pasid);
3500 spin_unlock_irqrestore(&domain->lock, flags);
3504 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3506 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3507 int status, int tag)
3509 struct iommu_dev_data *dev_data;
3510 struct amd_iommu *iommu;
3511 struct iommu_cmd cmd;
3513 INC_STATS_COUNTER(complete_ppr);
3515 dev_data = get_dev_data(&pdev->dev);
3516 iommu = amd_iommu_rlookup_table[dev_data->devid];
3518 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3519 tag, dev_data->pri_tlp);
3521 return iommu_queue_command(iommu, &cmd);
3523 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3525 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3527 struct protection_domain *domain;
3529 domain = get_domain(&pdev->dev);
3533 /* Only return IOMMUv2 domains */
3534 if (!(domain->flags & PD_IOMMUV2_MASK))
3537 return domain->iommu_domain;
3539 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3541 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3543 struct iommu_dev_data *dev_data;
3545 if (!amd_iommu_v2_supported())
3548 dev_data = get_dev_data(&pdev->dev);
3549 dev_data->errata |= (1 << erratum);
3551 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);