2 * Copyright (c) 2012 Intel Corporation. All rights reserved.
3 * Copyright (c) 2008 - 2012 QLogic Corporation. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 * This file contains all of the code that is specific to the
36 * InfiniPath 7322 chip
39 #include <linux/interrupt.h>
40 #include <linux/pci.h>
41 #include <linux/delay.h>
43 #include <linux/jiffies.h>
44 #include <linux/module.h>
45 #include <rdma/ib_verbs.h>
46 #include <rdma/ib_smi.h>
47 #ifdef CONFIG_INFINIBAND_QIB_DCA
48 #include <linux/dca.h>
52 #include "qib_7322_regs.h"
56 #include "qib_verbs.h"
59 #define pr_fmt(fmt) QIB_DRV_NAME " " fmt
61 static void qib_setup_7322_setextled(struct qib_pportdata *, u32);
62 static void qib_7322_handle_hwerrors(struct qib_devdata *, char *, size_t);
63 static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op);
64 static irqreturn_t qib_7322intr(int irq, void *data);
65 static irqreturn_t qib_7322bufavail(int irq, void *data);
66 static irqreturn_t sdma_intr(int irq, void *data);
67 static irqreturn_t sdma_idle_intr(int irq, void *data);
68 static irqreturn_t sdma_progress_intr(int irq, void *data);
69 static irqreturn_t sdma_cleanup_intr(int irq, void *data);
70 static void qib_7322_txchk_change(struct qib_devdata *, u32, u32, u32,
71 struct qib_ctxtdata *rcd);
72 static u8 qib_7322_phys_portstate(u64);
73 static u32 qib_7322_iblink_state(u64);
74 static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd,
76 static void force_h1(struct qib_pportdata *);
77 static void adj_tx_serdes(struct qib_pportdata *);
78 static u32 qib_7322_setpbc_control(struct qib_pportdata *, u32, u8, u8);
79 static void qib_7322_mini_pcs_reset(struct qib_pportdata *);
81 static u32 ahb_mod(struct qib_devdata *, int, int, int, u32, u32);
82 static void ibsd_wr_allchans(struct qib_pportdata *, int, unsigned, unsigned);
83 static void serdes_7322_los_enable(struct qib_pportdata *, int);
84 static int serdes_7322_init_old(struct qib_pportdata *);
85 static int serdes_7322_init_new(struct qib_pportdata *);
86 static void dump_sdma_7322_state(struct qib_pportdata *);
88 #define BMASK(msb, lsb) (((1 << ((msb) + 1 - (lsb))) - 1) << (lsb))
90 /* LE2 serdes values for different cases */
95 /* Below is special-purpose, so only really works for the IB SerDes blocks. */
96 #define IBSD(hw_pidx) (hw_pidx + 2)
98 /* these are variables for documentation and experimentation purposes */
99 static const unsigned rcv_int_timeout = 375;
100 static const unsigned rcv_int_count = 16;
101 static const unsigned sdma_idle_cnt = 64;
103 /* Time to stop altering Rx Equalization parameters, after link up. */
104 #define RXEQ_DISABLE_MSECS 2500
107 * Number of VLs we are configured to use (to allow for more
108 * credits per vl, etc.)
110 ushort qib_num_cfg_vls = 2;
111 module_param_named(num_vls, qib_num_cfg_vls, ushort, S_IRUGO);
112 MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");
114 static ushort qib_chase = 1;
115 module_param_named(chase, qib_chase, ushort, S_IRUGO);
116 MODULE_PARM_DESC(chase, "Enable state chase handling");
118 static ushort qib_long_atten = 10; /* 10 dB ~= 5m length */
119 module_param_named(long_attenuation, qib_long_atten, ushort, S_IRUGO);
120 MODULE_PARM_DESC(long_attenuation, \
121 "attenuation cutoff (dB) for long copper cable setup");
123 static ushort qib_singleport;
124 module_param_named(singleport, qib_singleport, ushort, S_IRUGO);
125 MODULE_PARM_DESC(singleport, "Use only IB port 1; more per-port buffer space");
127 static ushort qib_krcvq01_no_msi;
128 module_param_named(krcvq01_no_msi, qib_krcvq01_no_msi, ushort, S_IRUGO);
129 MODULE_PARM_DESC(krcvq01_no_msi, "No MSI for kctx < 2");
132 * Receive header queue sizes
134 static unsigned qib_rcvhdrcnt;
135 module_param_named(rcvhdrcnt, qib_rcvhdrcnt, uint, S_IRUGO);
136 MODULE_PARM_DESC(rcvhdrcnt, "receive header count");
138 static unsigned qib_rcvhdrsize;
139 module_param_named(rcvhdrsize, qib_rcvhdrsize, uint, S_IRUGO);
140 MODULE_PARM_DESC(rcvhdrsize, "receive header size in 32-bit words");
142 static unsigned qib_rcvhdrentsize;
143 module_param_named(rcvhdrentsize, qib_rcvhdrentsize, uint, S_IRUGO);
144 MODULE_PARM_DESC(rcvhdrentsize, "receive header entry size in 32-bit words");
146 #define MAX_ATTEN_LEN 64 /* plenty for any real system */
147 /* for read back, default index is ~5m copper cable */
148 static char txselect_list[MAX_ATTEN_LEN] = "10";
149 static struct kparam_string kp_txselect = {
150 .string = txselect_list,
151 .maxlen = MAX_ATTEN_LEN
153 static int setup_txselect(const char *, struct kernel_param *);
154 module_param_call(txselect, setup_txselect, param_get_string,
155 &kp_txselect, S_IWUSR | S_IRUGO);
156 MODULE_PARM_DESC(txselect, \
157 "Tx serdes indices (for no QSFP or invalid QSFP data)");
159 #define BOARD_QME7342 5
160 #define BOARD_QMH7342 6
161 #define IS_QMH(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
163 #define IS_QME(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
166 #define KREG_IDX(regname) (QIB_7322_##regname##_OFFS / sizeof(u64))
168 #define KREG_IBPORT_IDX(regname) ((QIB_7322_##regname##_0_OFFS / sizeof(u64)))
170 #define MASK_ACROSS(lsb, msb) \
171 (((1ULL << ((msb) + 1 - (lsb))) - 1) << (lsb))
173 #define SYM_RMASK(regname, fldname) ((u64) \
174 QIB_7322_##regname##_##fldname##_RMASK)
176 #define SYM_MASK(regname, fldname) ((u64) \
177 QIB_7322_##regname##_##fldname##_RMASK << \
178 QIB_7322_##regname##_##fldname##_LSB)
180 #define SYM_FIELD(value, regname, fldname) ((u64) \
181 (((value) >> SYM_LSB(regname, fldname)) & \
182 SYM_RMASK(regname, fldname)))
184 /* useful for things like LaFifoEmpty_0...7, TxCreditOK_0...7, etc. */
185 #define SYM_FIELD_ACROSS(value, regname, fldname, nbits) \
186 (((value) >> SYM_LSB(regname, fldname)) & MASK_ACROSS(0, nbits))
188 #define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask)
189 #define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask)
190 #define ERR_MASK_N(fldname) SYM_MASK(ErrMask_0, fldname##Mask)
191 #define INT_MASK(fldname) SYM_MASK(IntMask, fldname##IntMask)
192 #define INT_MASK_P(fldname, port) SYM_MASK(IntMask, fldname##IntMask##_##port)
193 /* Below because most, but not all, fields of IntMask have that full suffix */
194 #define INT_MASK_PM(fldname, port) SYM_MASK(IntMask, fldname##Mask##_##port)
197 #define SYM_LSB(regname, fldname) (QIB_7322_##regname##_##fldname##_LSB)
200 * the size bits give us 2^N, in KB units. 0 marks as invalid,
201 * and 7 is reserved. We currently use only 2KB and 4KB
203 #define IBA7322_TID_SZ_SHIFT QIB_7322_RcvTIDArray0_RT_BufSize_LSB
204 #define IBA7322_TID_SZ_2K (1UL<<IBA7322_TID_SZ_SHIFT) /* 2KB */
205 #define IBA7322_TID_SZ_4K (2UL<<IBA7322_TID_SZ_SHIFT) /* 4KB */
206 #define IBA7322_TID_PA_SHIFT 11U /* TID addr in chip stored w/o low bits */
208 #define SendIBSLIDAssignMask \
209 QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_RMASK
210 #define SendIBSLMCMask \
211 QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_RMASK
213 #define ExtLED_IB1_YEL SYM_MASK(EXTCtrl, LEDPort0YellowOn)
214 #define ExtLED_IB1_GRN SYM_MASK(EXTCtrl, LEDPort0GreenOn)
215 #define ExtLED_IB2_YEL SYM_MASK(EXTCtrl, LEDPort1YellowOn)
216 #define ExtLED_IB2_GRN SYM_MASK(EXTCtrl, LEDPort1GreenOn)
217 #define ExtLED_IB1_MASK (ExtLED_IB1_YEL | ExtLED_IB1_GRN)
218 #define ExtLED_IB2_MASK (ExtLED_IB2_YEL | ExtLED_IB2_GRN)
220 #define _QIB_GPIO_SDA_NUM 1
221 #define _QIB_GPIO_SCL_NUM 0
222 #define QIB_EEPROM_WEN_NUM 14
223 #define QIB_TWSI_EEPROM_DEV 0xA2 /* All Production 7322 cards. */
225 /* HW counter clock is at 4nsec */
226 #define QIB_7322_PSXMITWAIT_CHECK_RATE 4000
228 /* full speed IB port 1 only */
229 #define PORT_SPD_CAP (QIB_IB_SDR | QIB_IB_DDR | QIB_IB_QDR)
230 #define PORT_SPD_CAP_SHIFT 3
232 /* full speed featuremask, both ports */
233 #define DUAL_PORT_CAP (PORT_SPD_CAP | (PORT_SPD_CAP << PORT_SPD_CAP_SHIFT))
236 * This file contains almost all the chip-specific register information and
237 * access functions for the FAKED QLogic InfiniPath 7322 PCI-Express chip.
240 /* Use defines to tie machine-generated names to lower-case names */
241 #define kr_contextcnt KREG_IDX(ContextCnt)
242 #define kr_control KREG_IDX(Control)
243 #define kr_counterregbase KREG_IDX(CntrRegBase)
244 #define kr_errclear KREG_IDX(ErrClear)
245 #define kr_errmask KREG_IDX(ErrMask)
246 #define kr_errstatus KREG_IDX(ErrStatus)
247 #define kr_extctrl KREG_IDX(EXTCtrl)
248 #define kr_extstatus KREG_IDX(EXTStatus)
249 #define kr_gpio_clear KREG_IDX(GPIOClear)
250 #define kr_gpio_mask KREG_IDX(GPIOMask)
251 #define kr_gpio_out KREG_IDX(GPIOOut)
252 #define kr_gpio_status KREG_IDX(GPIOStatus)
253 #define kr_hwdiagctrl KREG_IDX(HwDiagCtrl)
254 #define kr_debugportval KREG_IDX(DebugPortValueReg)
255 #define kr_fmask KREG_IDX(feature_mask)
256 #define kr_act_fmask KREG_IDX(active_feature_mask)
257 #define kr_hwerrclear KREG_IDX(HwErrClear)
258 #define kr_hwerrmask KREG_IDX(HwErrMask)
259 #define kr_hwerrstatus KREG_IDX(HwErrStatus)
260 #define kr_intclear KREG_IDX(IntClear)
261 #define kr_intmask KREG_IDX(IntMask)
262 #define kr_intredirect KREG_IDX(IntRedirect0)
263 #define kr_intstatus KREG_IDX(IntStatus)
264 #define kr_pagealign KREG_IDX(PageAlign)
265 #define kr_rcvavailtimeout KREG_IDX(RcvAvailTimeOut0)
266 #define kr_rcvctrl KREG_IDX(RcvCtrl) /* Common, but chip also has per-port */
267 #define kr_rcvegrbase KREG_IDX(RcvEgrBase)
268 #define kr_rcvegrcnt KREG_IDX(RcvEgrCnt)
269 #define kr_rcvhdrcnt KREG_IDX(RcvHdrCnt)
270 #define kr_rcvhdrentsize KREG_IDX(RcvHdrEntSize)
271 #define kr_rcvhdrsize KREG_IDX(RcvHdrSize)
272 #define kr_rcvtidbase KREG_IDX(RcvTIDBase)
273 #define kr_rcvtidcnt KREG_IDX(RcvTIDCnt)
274 #define kr_revision KREG_IDX(Revision)
275 #define kr_scratch KREG_IDX(Scratch)
276 #define kr_sendbuffererror KREG_IDX(SendBufErr0) /* and base for 1 and 2 */
277 #define kr_sendcheckmask KREG_IDX(SendCheckMask0) /* and 1, 2 */
278 #define kr_sendctrl KREG_IDX(SendCtrl)
279 #define kr_sendgrhcheckmask KREG_IDX(SendGRHCheckMask0) /* and 1, 2 */
280 #define kr_sendibpktmask KREG_IDX(SendIBPacketMask0) /* and 1, 2 */
281 #define kr_sendpioavailaddr KREG_IDX(SendBufAvailAddr)
282 #define kr_sendpiobufbase KREG_IDX(SendBufBase)
283 #define kr_sendpiobufcnt KREG_IDX(SendBufCnt)
284 #define kr_sendpiosize KREG_IDX(SendBufSize)
285 #define kr_sendregbase KREG_IDX(SendRegBase)
286 #define kr_sendbufavail0 KREG_IDX(SendBufAvail0)
287 #define kr_userregbase KREG_IDX(UserRegBase)
288 #define kr_intgranted KREG_IDX(Int_Granted)
289 #define kr_vecclr_wo_int KREG_IDX(vec_clr_without_int)
290 #define kr_intblocked KREG_IDX(IntBlocked)
291 #define kr_r_access KREG_IDX(SPC_JTAG_ACCESS_REG)
294 * per-port kernel registers. Access only with qib_read_kreg_port()
295 * or qib_write_kreg_port()
297 #define krp_errclear KREG_IBPORT_IDX(ErrClear)
298 #define krp_errmask KREG_IBPORT_IDX(ErrMask)
299 #define krp_errstatus KREG_IBPORT_IDX(ErrStatus)
300 #define krp_highprio_0 KREG_IBPORT_IDX(HighPriority0)
301 #define krp_highprio_limit KREG_IBPORT_IDX(HighPriorityLimit)
302 #define krp_hrtbt_guid KREG_IBPORT_IDX(HRTBT_GUID)
303 #define krp_ib_pcsconfig KREG_IBPORT_IDX(IBPCSConfig)
304 #define krp_ibcctrl_a KREG_IBPORT_IDX(IBCCtrlA)
305 #define krp_ibcctrl_b KREG_IBPORT_IDX(IBCCtrlB)
306 #define krp_ibcctrl_c KREG_IBPORT_IDX(IBCCtrlC)
307 #define krp_ibcstatus_a KREG_IBPORT_IDX(IBCStatusA)
308 #define krp_ibcstatus_b KREG_IBPORT_IDX(IBCStatusB)
309 #define krp_txestatus KREG_IBPORT_IDX(TXEStatus)
310 #define krp_lowprio_0 KREG_IBPORT_IDX(LowPriority0)
311 #define krp_ncmodectrl KREG_IBPORT_IDX(IBNCModeCtrl)
312 #define krp_partitionkey KREG_IBPORT_IDX(RcvPartitionKey)
313 #define krp_psinterval KREG_IBPORT_IDX(PSInterval)
314 #define krp_psstart KREG_IBPORT_IDX(PSStart)
315 #define krp_psstat KREG_IBPORT_IDX(PSStat)
316 #define krp_rcvbthqp KREG_IBPORT_IDX(RcvBTHQP)
317 #define krp_rcvctrl KREG_IBPORT_IDX(RcvCtrl)
318 #define krp_rcvpktledcnt KREG_IBPORT_IDX(RcvPktLEDCnt)
319 #define krp_rcvqpmaptable KREG_IBPORT_IDX(RcvQPMapTableA)
320 #define krp_rxcreditvl0 KREG_IBPORT_IDX(RxCreditVL0)
321 #define krp_rxcreditvl15 (KREG_IBPORT_IDX(RxCreditVL0)+15)
322 #define krp_sendcheckcontrol KREG_IBPORT_IDX(SendCheckControl)
323 #define krp_sendctrl KREG_IBPORT_IDX(SendCtrl)
324 #define krp_senddmabase KREG_IBPORT_IDX(SendDmaBase)
325 #define krp_senddmabufmask0 KREG_IBPORT_IDX(SendDmaBufMask0)
326 #define krp_senddmabufmask1 (KREG_IBPORT_IDX(SendDmaBufMask0) + 1)
327 #define krp_senddmabufmask2 (KREG_IBPORT_IDX(SendDmaBufMask0) + 2)
328 #define krp_senddmabuf_use0 KREG_IBPORT_IDX(SendDmaBufUsed0)
329 #define krp_senddmabuf_use1 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 1)
330 #define krp_senddmabuf_use2 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 2)
331 #define krp_senddmadesccnt KREG_IBPORT_IDX(SendDmaDescCnt)
332 #define krp_senddmahead KREG_IBPORT_IDX(SendDmaHead)
333 #define krp_senddmaheadaddr KREG_IBPORT_IDX(SendDmaHeadAddr)
334 #define krp_senddmaidlecnt KREG_IBPORT_IDX(SendDmaIdleCnt)
335 #define krp_senddmalengen KREG_IBPORT_IDX(SendDmaLenGen)
336 #define krp_senddmaprioritythld KREG_IBPORT_IDX(SendDmaPriorityThld)
337 #define krp_senddmareloadcnt KREG_IBPORT_IDX(SendDmaReloadCnt)
338 #define krp_senddmastatus KREG_IBPORT_IDX(SendDmaStatus)
339 #define krp_senddmatail KREG_IBPORT_IDX(SendDmaTail)
340 #define krp_sendhdrsymptom KREG_IBPORT_IDX(SendHdrErrSymptom)
341 #define krp_sendslid KREG_IBPORT_IDX(SendIBSLIDAssign)
342 #define krp_sendslidmask KREG_IBPORT_IDX(SendIBSLIDMask)
343 #define krp_ibsdtestiftx KREG_IBPORT_IDX(IB_SDTEST_IF_TX)
344 #define krp_adapt_dis_timer KREG_IBPORT_IDX(ADAPT_DISABLE_TIMER_THRESHOLD)
345 #define krp_tx_deemph_override KREG_IBPORT_IDX(IBSD_TX_DEEMPHASIS_OVERRIDE)
346 #define krp_serdesctrl KREG_IBPORT_IDX(IBSerdesCtrl)
349 * Per-context kernel registers. Access only with qib_read_kreg_ctxt()
350 * or qib_write_kreg_ctxt()
352 #define krc_rcvhdraddr KREG_IDX(RcvHdrAddr0)
353 #define krc_rcvhdrtailaddr KREG_IDX(RcvHdrTailAddr0)
356 * TID Flow table, per context. Reduces
357 * number of hdrq updates to one per flow (or on errors).
358 * context 0 and 1 share same memory, but have distinct
359 * addresses. Since for now, we never use expected sends
360 * on kernel contexts, we don't worry about that (we initialize
361 * those entries for ctxt 0/1 on driver load twice, for example).
363 #define NUM_TIDFLOWS_CTXT 0x20 /* 0x20 per context; have to hardcode */
364 #define ur_rcvflowtable (KREG_IDX(RcvTIDFlowTable0) - KREG_IDX(RcvHdrTail0))
366 /* these are the error bits in the tid flows, and are W1C */
367 #define TIDFLOW_ERRBITS ( \
368 (SYM_MASK(RcvTIDFlowTable0, GenMismatch) << \
369 SYM_LSB(RcvTIDFlowTable0, GenMismatch)) | \
370 (SYM_MASK(RcvTIDFlowTable0, SeqMismatch) << \
371 SYM_LSB(RcvTIDFlowTable0, SeqMismatch)))
373 /* Most (not all) Counters are per-IBport.
374 * Requires LBIntCnt is at offset 0 in the group
376 #define CREG_IDX(regname) \
377 ((QIB_7322_##regname##_0_OFFS - QIB_7322_LBIntCnt_OFFS) / sizeof(u64))
379 #define crp_badformat CREG_IDX(RxVersionErrCnt)
380 #define crp_err_rlen CREG_IDX(RxLenErrCnt)
381 #define crp_erricrc CREG_IDX(RxICRCErrCnt)
382 #define crp_errlink CREG_IDX(RxLinkMalformCnt)
383 #define crp_errlpcrc CREG_IDX(RxLPCRCErrCnt)
384 #define crp_errpkey CREG_IDX(RxPKeyMismatchCnt)
385 #define crp_errvcrc CREG_IDX(RxVCRCErrCnt)
386 #define crp_excessbufferovfl CREG_IDX(ExcessBufferOvflCnt)
387 #define crp_iblinkdown CREG_IDX(IBLinkDownedCnt)
388 #define crp_iblinkerrrecov CREG_IDX(IBLinkErrRecoveryCnt)
389 #define crp_ibstatuschange CREG_IDX(IBStatusChangeCnt)
390 #define crp_ibsymbolerr CREG_IDX(IBSymbolErrCnt)
391 #define crp_invalidrlen CREG_IDX(RxMaxMinLenErrCnt)
392 #define crp_locallinkintegrityerr CREG_IDX(LocalLinkIntegrityErrCnt)
393 #define crp_pktrcv CREG_IDX(RxDataPktCnt)
394 #define crp_pktrcvflowctrl CREG_IDX(RxFlowPktCnt)
395 #define crp_pktsend CREG_IDX(TxDataPktCnt)
396 #define crp_pktsendflow CREG_IDX(TxFlowPktCnt)
397 #define crp_psrcvdatacount CREG_IDX(PSRcvDataCount)
398 #define crp_psrcvpktscount CREG_IDX(PSRcvPktsCount)
399 #define crp_psxmitdatacount CREG_IDX(PSXmitDataCount)
400 #define crp_psxmitpktscount CREG_IDX(PSXmitPktsCount)
401 #define crp_psxmitwaitcount CREG_IDX(PSXmitWaitCount)
402 #define crp_rcvebp CREG_IDX(RxEBPCnt)
403 #define crp_rcvflowctrlviol CREG_IDX(RxFlowCtrlViolCnt)
404 #define crp_rcvovfl CREG_IDX(RxBufOvflCnt)
405 #define crp_rxdlidfltr CREG_IDX(RxDlidFltrCnt)
406 #define crp_rxdroppkt CREG_IDX(RxDroppedPktCnt)
407 #define crp_rxotherlocalphyerr CREG_IDX(RxOtherLocalPhyErrCnt)
408 #define crp_rxqpinvalidctxt CREG_IDX(RxQPInvalidContextCnt)
409 #define crp_rxvlerr CREG_IDX(RxVlErrCnt)
410 #define crp_sendstall CREG_IDX(TxFlowStallCnt)
411 #define crp_txdroppedpkt CREG_IDX(TxDroppedPktCnt)
412 #define crp_txhdrerr CREG_IDX(TxHeadersErrCnt)
413 #define crp_txlenerr CREG_IDX(TxLenErrCnt)
414 #define crp_txminmaxlenerr CREG_IDX(TxMaxMinLenErrCnt)
415 #define crp_txsdmadesc CREG_IDX(TxSDmaDescCnt)
416 #define crp_txunderrun CREG_IDX(TxUnderrunCnt)
417 #define crp_txunsupvl CREG_IDX(TxUnsupVLErrCnt)
418 #define crp_vl15droppedpkt CREG_IDX(RxVL15DroppedPktCnt)
419 #define crp_wordrcv CREG_IDX(RxDwordCnt)
420 #define crp_wordsend CREG_IDX(TxDwordCnt)
421 #define crp_tx_creditstalls CREG_IDX(TxCreditUpToDateTimeOut)
423 /* these are the (few) counters that are not port-specific */
424 #define CREG_DEVIDX(regname) ((QIB_7322_##regname##_OFFS - \
425 QIB_7322_LBIntCnt_OFFS) / sizeof(u64))
426 #define cr_base_egrovfl CREG_DEVIDX(RxP0HdrEgrOvflCnt)
427 #define cr_lbint CREG_DEVIDX(LBIntCnt)
428 #define cr_lbstall CREG_DEVIDX(LBFlowStallCnt)
429 #define cr_pcieretrydiag CREG_DEVIDX(PcieRetryBufDiagQwordCnt)
430 #define cr_rxtidflowdrop CREG_DEVIDX(RxTidFlowDropCnt)
431 #define cr_tidfull CREG_DEVIDX(RxTIDFullErrCnt)
432 #define cr_tidinvalid CREG_DEVIDX(RxTIDValidErrCnt)
434 /* no chip register for # of IB ports supported, so define */
435 #define NUM_IB_PORTS 2
437 /* 1 VL15 buffer per hardware IB port, no register for this, so define */
438 #define NUM_VL15_BUFS NUM_IB_PORTS
441 * context 0 and 1 are special, and there is no chip register that
442 * defines this value, so we have to define it here.
443 * These are all allocated to either 0 or 1 for single port
444 * hardware configuration, otherwise each gets half
446 #define KCTXT0_EGRCNT 2048
448 /* values for vl and port fields in PBC, 7322-specific */
449 #define PBC_PORT_SEL_LSB 26
450 #define PBC_PORT_SEL_RMASK 1
451 #define PBC_VL_NUM_LSB 27
452 #define PBC_VL_NUM_RMASK 7
453 #define PBC_7322_VL15_SEND (1ULL << 63) /* pbc; VL15, no credit check */
454 #define PBC_7322_VL15_SEND_CTRL (1ULL << 31) /* control version of same */
456 static u8 ib_rate_to_delay[IB_RATE_120_GBPS + 1] = {
457 [IB_RATE_2_5_GBPS] = 16,
458 [IB_RATE_5_GBPS] = 8,
459 [IB_RATE_10_GBPS] = 4,
460 [IB_RATE_20_GBPS] = 2,
461 [IB_RATE_30_GBPS] = 2,
462 [IB_RATE_40_GBPS] = 1
465 #define IBA7322_LINKSPEED_SHIFT SYM_LSB(IBCStatusA_0, LinkSpeedActive)
466 #define IBA7322_LINKWIDTH_SHIFT SYM_LSB(IBCStatusA_0, LinkWidthActive)
468 /* link training states, from IBC */
469 #define IB_7322_LT_STATE_DISABLED 0x00
470 #define IB_7322_LT_STATE_LINKUP 0x01
471 #define IB_7322_LT_STATE_POLLACTIVE 0x02
472 #define IB_7322_LT_STATE_POLLQUIET 0x03
473 #define IB_7322_LT_STATE_SLEEPDELAY 0x04
474 #define IB_7322_LT_STATE_SLEEPQUIET 0x05
475 #define IB_7322_LT_STATE_CFGDEBOUNCE 0x08
476 #define IB_7322_LT_STATE_CFGRCVFCFG 0x09
477 #define IB_7322_LT_STATE_CFGWAITRMT 0x0a
478 #define IB_7322_LT_STATE_CFGIDLE 0x0b
479 #define IB_7322_LT_STATE_RECOVERRETRAIN 0x0c
480 #define IB_7322_LT_STATE_TXREVLANES 0x0d
481 #define IB_7322_LT_STATE_RECOVERWAITRMT 0x0e
482 #define IB_7322_LT_STATE_RECOVERIDLE 0x0f
483 #define IB_7322_LT_STATE_CFGENH 0x10
484 #define IB_7322_LT_STATE_CFGTEST 0x11
485 #define IB_7322_LT_STATE_CFGWAITRMTTEST 0x12
486 #define IB_7322_LT_STATE_CFGWAITENH 0x13
488 /* link state machine states from IBC */
489 #define IB_7322_L_STATE_DOWN 0x0
490 #define IB_7322_L_STATE_INIT 0x1
491 #define IB_7322_L_STATE_ARM 0x2
492 #define IB_7322_L_STATE_ACTIVE 0x3
493 #define IB_7322_L_STATE_ACT_DEFER 0x4
495 static const u8 qib_7322_physportstate[0x20] = {
496 [IB_7322_LT_STATE_DISABLED] = IB_PHYSPORTSTATE_DISABLED,
497 [IB_7322_LT_STATE_LINKUP] = IB_PHYSPORTSTATE_LINKUP,
498 [IB_7322_LT_STATE_POLLACTIVE] = IB_PHYSPORTSTATE_POLL,
499 [IB_7322_LT_STATE_POLLQUIET] = IB_PHYSPORTSTATE_POLL,
500 [IB_7322_LT_STATE_SLEEPDELAY] = IB_PHYSPORTSTATE_SLEEP,
501 [IB_7322_LT_STATE_SLEEPQUIET] = IB_PHYSPORTSTATE_SLEEP,
502 [IB_7322_LT_STATE_CFGDEBOUNCE] = IB_PHYSPORTSTATE_CFG_TRAIN,
503 [IB_7322_LT_STATE_CFGRCVFCFG] =
504 IB_PHYSPORTSTATE_CFG_TRAIN,
505 [IB_7322_LT_STATE_CFGWAITRMT] =
506 IB_PHYSPORTSTATE_CFG_TRAIN,
507 [IB_7322_LT_STATE_CFGIDLE] = IB_PHYSPORTSTATE_CFG_IDLE,
508 [IB_7322_LT_STATE_RECOVERRETRAIN] =
509 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
510 [IB_7322_LT_STATE_RECOVERWAITRMT] =
511 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
512 [IB_7322_LT_STATE_RECOVERIDLE] =
513 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
514 [IB_7322_LT_STATE_CFGENH] = IB_PHYSPORTSTATE_CFG_ENH,
515 [IB_7322_LT_STATE_CFGTEST] = IB_PHYSPORTSTATE_CFG_TRAIN,
516 [IB_7322_LT_STATE_CFGWAITRMTTEST] =
517 IB_PHYSPORTSTATE_CFG_TRAIN,
518 [IB_7322_LT_STATE_CFGWAITENH] =
519 IB_PHYSPORTSTATE_CFG_WAIT_ENH,
520 [0x14] = IB_PHYSPORTSTATE_CFG_TRAIN,
521 [0x15] = IB_PHYSPORTSTATE_CFG_TRAIN,
522 [0x16] = IB_PHYSPORTSTATE_CFG_TRAIN,
523 [0x17] = IB_PHYSPORTSTATE_CFG_TRAIN
526 #ifdef CONFIG_INFINIBAND_QIB_DCA
527 struct qib_irq_notify {
530 struct irq_affinity_notify notify;
534 struct qib_chip_specific {
535 u64 __iomem *cregbase;
537 spinlock_t rcvmod_lock; /* protect rcvctrl shadow changes */
538 spinlock_t gpio_lock; /* RMW of shadows/regs for ExtCtrl and GPIO */
539 u64 main_int_mask; /* clear bits which have dedicated handlers */
540 u64 int_enable_mask; /* for per port interrupts in single port mode */
543 u64 gpio_out; /* shadow of kr_gpio_out, for rmw ops */
544 u64 gpio_mask; /* shadow the gpio mask register */
545 u64 extctrl; /* shadow the gpio output enable, etc... */
552 u32 updthresh; /* current AvailUpdThld */
553 u32 updthresh_dflt; /* default AvailUpdThld */
556 u32 num_msix_entries;
560 u32 recovery_ports_initted;
561 #ifdef CONFIG_INFINIBAND_QIB_DCA
565 u64 dca_rcvhdr_ctrl[5]; /* B, C, D, E, F */
567 struct qib_msix_entry *msix_entries;
568 unsigned long *sendchkenable;
569 unsigned long *sendgrhchk;
570 unsigned long *sendibchk;
571 u32 rcvavail_timeout[18];
572 char emsgbuf[128]; /* for device error interrupt msg buffer */
575 /* Table of entries in "human readable" form Tx Emphasis. */
583 struct vendor_txdds_ent {
584 u8 oui[QSFP_VOUI_LEN];
586 struct txdds_ent sdr;
587 struct txdds_ent ddr;
588 struct txdds_ent qdr;
591 static void write_tx_serdes_param(struct qib_pportdata *, struct txdds_ent *);
593 #define TXDDS_TABLE_SZ 16 /* number of entries per speed in onchip table */
594 #define TXDDS_EXTRA_SZ 18 /* number of extra tx settings entries */
595 #define TXDDS_MFG_SZ 2 /* number of mfg tx settings entries */
596 #define SERDES_CHANS 4 /* yes, it's obvious, but one less magic number */
598 #define H1_FORCE_VAL 8
599 #define H1_FORCE_QME 1 /* may be overridden via setup_txselect() */
600 #define H1_FORCE_QMH 7 /* may be overridden via setup_txselect() */
602 /* The static and dynamic registers are paired, and the pairs indexed by spd */
603 #define krp_static_adapt_dis(spd) (KREG_IBPORT_IDX(ADAPT_DISABLE_STATIC_SDR) \
606 #define QDR_DFE_DISABLE_DELAY 4000 /* msec after LINKUP */
607 #define QDR_STATIC_ADAPT_DOWN 0xf0f0f0f0ULL /* link down, H1-H4 QDR adapts */
608 #define QDR_STATIC_ADAPT_DOWN_R1 0ULL /* r1 link down, H1-H4 QDR adapts */
609 #define QDR_STATIC_ADAPT_INIT 0xffffffffffULL /* up, disable H0,H1-8, LE */
610 #define QDR_STATIC_ADAPT_INIT_R1 0xf0ffffffffULL /* r1 up, disable H0,H1-8 */
612 struct qib_chippport_specific {
613 u64 __iomem *kpregbase;
614 u64 __iomem *cpregbase;
616 struct qib_pportdata *ppd;
617 wait_queue_head_t autoneg_wait;
618 struct delayed_work autoneg_work;
619 struct delayed_work ipg_work;
620 struct timer_list chase_timer;
622 * these 5 fields are used to establish deltas for IB symbol
623 * errors and linkrecovery errors. They can be reported on
624 * some chips during link negotiation prior to INIT, and with
625 * DDR when faking DDR negotiations with non-IBTA switches.
626 * The chip counters are adjusted at driver unload if there is
638 u64 ibcctrl_a; /* krp_ibcctrl_a shadow */
639 u64 ibcctrl_b; /* krp_ibcctrl_b shadow */
640 unsigned long qdr_dfe_time;
641 unsigned long chase_end;
647 * Per-bay per-channel rcv QMH H1 values and Tx values for QDR.
648 * entry zero is unused, to simplify indexing
651 u8 no_eep; /* txselect table index to use if no qsfp info */
654 struct qib_qsfp_data qsfp_data;
655 char epmsgbuf[192]; /* for port error interrupt msg buffer */
656 char sdmamsgbuf[192]; /* for per-port sdma error messages */
661 irq_handler_t handler;
663 int port; /* 0 if not port-specific, else port # */
666 { "", qib_7322intr, -1, 0, 0 },
667 { " (buf avail)", qib_7322bufavail,
668 SYM_LSB(IntStatus, SendBufAvail), 0, 0},
669 { " (sdma 0)", sdma_intr,
670 SYM_LSB(IntStatus, SDmaInt_0), 1, 1 },
671 { " (sdma 1)", sdma_intr,
672 SYM_LSB(IntStatus, SDmaInt_1), 2, 1 },
673 { " (sdmaI 0)", sdma_idle_intr,
674 SYM_LSB(IntStatus, SDmaIdleInt_0), 1, 1},
675 { " (sdmaI 1)", sdma_idle_intr,
676 SYM_LSB(IntStatus, SDmaIdleInt_1), 2, 1},
677 { " (sdmaP 0)", sdma_progress_intr,
678 SYM_LSB(IntStatus, SDmaProgressInt_0), 1, 1 },
679 { " (sdmaP 1)", sdma_progress_intr,
680 SYM_LSB(IntStatus, SDmaProgressInt_1), 2, 1 },
681 { " (sdmaC 0)", sdma_cleanup_intr,
682 SYM_LSB(IntStatus, SDmaCleanupDone_0), 1, 0 },
683 { " (sdmaC 1)", sdma_cleanup_intr,
684 SYM_LSB(IntStatus, SDmaCleanupDone_1), 2 , 0},
687 #ifdef CONFIG_INFINIBAND_QIB_DCA
689 static const struct dca_reg_map {
694 } dca_rcvhdr_reg_map[] = {
695 { 0, SYM_LSB(DCACtrlB, RcvHdrq0DCAOPH),
696 ~SYM_MASK(DCACtrlB, RcvHdrq0DCAOPH) , KREG_IDX(DCACtrlB) },
697 { 0, SYM_LSB(DCACtrlB, RcvHdrq1DCAOPH),
698 ~SYM_MASK(DCACtrlB, RcvHdrq1DCAOPH) , KREG_IDX(DCACtrlB) },
699 { 0, SYM_LSB(DCACtrlB, RcvHdrq2DCAOPH),
700 ~SYM_MASK(DCACtrlB, RcvHdrq2DCAOPH) , KREG_IDX(DCACtrlB) },
701 { 0, SYM_LSB(DCACtrlB, RcvHdrq3DCAOPH),
702 ~SYM_MASK(DCACtrlB, RcvHdrq3DCAOPH) , KREG_IDX(DCACtrlB) },
703 { 1, SYM_LSB(DCACtrlC, RcvHdrq4DCAOPH),
704 ~SYM_MASK(DCACtrlC, RcvHdrq4DCAOPH) , KREG_IDX(DCACtrlC) },
705 { 1, SYM_LSB(DCACtrlC, RcvHdrq5DCAOPH),
706 ~SYM_MASK(DCACtrlC, RcvHdrq5DCAOPH) , KREG_IDX(DCACtrlC) },
707 { 1, SYM_LSB(DCACtrlC, RcvHdrq6DCAOPH),
708 ~SYM_MASK(DCACtrlC, RcvHdrq6DCAOPH) , KREG_IDX(DCACtrlC) },
709 { 1, SYM_LSB(DCACtrlC, RcvHdrq7DCAOPH),
710 ~SYM_MASK(DCACtrlC, RcvHdrq7DCAOPH) , KREG_IDX(DCACtrlC) },
711 { 2, SYM_LSB(DCACtrlD, RcvHdrq8DCAOPH),
712 ~SYM_MASK(DCACtrlD, RcvHdrq8DCAOPH) , KREG_IDX(DCACtrlD) },
713 { 2, SYM_LSB(DCACtrlD, RcvHdrq9DCAOPH),
714 ~SYM_MASK(DCACtrlD, RcvHdrq9DCAOPH) , KREG_IDX(DCACtrlD) },
715 { 2, SYM_LSB(DCACtrlD, RcvHdrq10DCAOPH),
716 ~SYM_MASK(DCACtrlD, RcvHdrq10DCAOPH) , KREG_IDX(DCACtrlD) },
717 { 2, SYM_LSB(DCACtrlD, RcvHdrq11DCAOPH),
718 ~SYM_MASK(DCACtrlD, RcvHdrq11DCAOPH) , KREG_IDX(DCACtrlD) },
719 { 3, SYM_LSB(DCACtrlE, RcvHdrq12DCAOPH),
720 ~SYM_MASK(DCACtrlE, RcvHdrq12DCAOPH) , KREG_IDX(DCACtrlE) },
721 { 3, SYM_LSB(DCACtrlE, RcvHdrq13DCAOPH),
722 ~SYM_MASK(DCACtrlE, RcvHdrq13DCAOPH) , KREG_IDX(DCACtrlE) },
723 { 3, SYM_LSB(DCACtrlE, RcvHdrq14DCAOPH),
724 ~SYM_MASK(DCACtrlE, RcvHdrq14DCAOPH) , KREG_IDX(DCACtrlE) },
725 { 3, SYM_LSB(DCACtrlE, RcvHdrq15DCAOPH),
726 ~SYM_MASK(DCACtrlE, RcvHdrq15DCAOPH) , KREG_IDX(DCACtrlE) },
727 { 4, SYM_LSB(DCACtrlF, RcvHdrq16DCAOPH),
728 ~SYM_MASK(DCACtrlF, RcvHdrq16DCAOPH) , KREG_IDX(DCACtrlF) },
729 { 4, SYM_LSB(DCACtrlF, RcvHdrq17DCAOPH),
730 ~SYM_MASK(DCACtrlF, RcvHdrq17DCAOPH) , KREG_IDX(DCACtrlF) },
735 #define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE 1
736 /* cycle through TS1/TS2 till OK */
737 #define QLOGIC_IB_IBCC_LINKINITCMD_POLL 2
738 /* wait for TS1, then go on */
739 #define QLOGIC_IB_IBCC_LINKINITCMD_SLEEP 3
740 #define QLOGIC_IB_IBCC_LINKINITCMD_SHIFT 16
742 #define QLOGIC_IB_IBCC_LINKCMD_DOWN 1 /* move to 0x11 */
743 #define QLOGIC_IB_IBCC_LINKCMD_ARMED 2 /* move to 0x21 */
744 #define QLOGIC_IB_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */
746 #define BLOB_7322_IBCHG 0x101
748 static inline void qib_write_kreg(const struct qib_devdata *dd,
749 const u32 regno, u64 value);
750 static inline u32 qib_read_kreg32(const struct qib_devdata *, const u32);
751 static void write_7322_initregs(struct qib_devdata *);
752 static void write_7322_init_portregs(struct qib_pportdata *);
753 static void setup_7322_link_recovery(struct qib_pportdata *, u32);
754 static void check_7322_rxe_status(struct qib_pportdata *);
755 static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *, u64, u32 *);
756 #ifdef CONFIG_INFINIBAND_QIB_DCA
757 static void qib_setup_dca(struct qib_devdata *dd);
758 static void setup_dca_notifier(struct qib_devdata *dd,
759 struct qib_msix_entry *m);
760 static void reset_dca_notifier(struct qib_devdata *dd,
761 struct qib_msix_entry *m);
765 * qib_read_ureg32 - read 32-bit virtualized per-context register
767 * @regno: register number
768 * @ctxt: context number
770 * Return the contents of a register that is virtualized to be per context.
771 * Returns -1 on errors (not distinguishable from valid contents at
772 * runtime; we may add a separate error variable at some point).
774 static inline u32 qib_read_ureg32(const struct qib_devdata *dd,
775 enum qib_ureg regno, int ctxt)
777 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
779 return readl(regno + (u64 __iomem *)(
780 (dd->ureg_align * ctxt) + (dd->userbase ?
781 (char __iomem *)dd->userbase :
782 (char __iomem *)dd->kregbase + dd->uregbase)));
786 * qib_read_ureg - read virtualized per-context register
788 * @regno: register number
789 * @ctxt: context number
791 * Return the contents of a register that is virtualized to be per context.
792 * Returns -1 on errors (not distinguishable from valid contents at
793 * runtime; we may add a separate error variable at some point).
795 static inline u64 qib_read_ureg(const struct qib_devdata *dd,
796 enum qib_ureg regno, int ctxt)
799 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
801 return readq(regno + (u64 __iomem *)(
802 (dd->ureg_align * ctxt) + (dd->userbase ?
803 (char __iomem *)dd->userbase :
804 (char __iomem *)dd->kregbase + dd->uregbase)));
808 * qib_write_ureg - write virtualized per-context register
810 * @regno: register number
814 * Write the contents of a register that is virtualized to be per context.
816 static inline void qib_write_ureg(const struct qib_devdata *dd,
817 enum qib_ureg regno, u64 value, int ctxt)
821 ubase = (u64 __iomem *)
822 ((char __iomem *) dd->userbase +
823 dd->ureg_align * ctxt);
825 ubase = (u64 __iomem *)
827 (char __iomem *) dd->kregbase +
828 dd->ureg_align * ctxt);
830 if (dd->kregbase && (dd->flags & QIB_PRESENT))
831 writeq(value, &ubase[regno]);
834 static inline u32 qib_read_kreg32(const struct qib_devdata *dd,
837 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
839 return readl((u32 __iomem *) &dd->kregbase[regno]);
842 static inline u64 qib_read_kreg64(const struct qib_devdata *dd,
845 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
847 return readq(&dd->kregbase[regno]);
850 static inline void qib_write_kreg(const struct qib_devdata *dd,
851 const u32 regno, u64 value)
853 if (dd->kregbase && (dd->flags & QIB_PRESENT))
854 writeq(value, &dd->kregbase[regno]);
858 * not many sanity checks for the port-specific kernel register routines,
859 * since they are only used when it's known to be safe.
861 static inline u64 qib_read_kreg_port(const struct qib_pportdata *ppd,
864 if (!ppd->cpspec->kpregbase || !(ppd->dd->flags & QIB_PRESENT))
866 return readq(&ppd->cpspec->kpregbase[regno]);
869 static inline void qib_write_kreg_port(const struct qib_pportdata *ppd,
870 const u16 regno, u64 value)
872 if (ppd->cpspec && ppd->dd && ppd->cpspec->kpregbase &&
873 (ppd->dd->flags & QIB_PRESENT))
874 writeq(value, &ppd->cpspec->kpregbase[regno]);
878 * qib_write_kreg_ctxt - write a device's per-ctxt 64-bit kernel register
879 * @dd: the qlogic_ib device
880 * @regno: the register number to write
881 * @ctxt: the context containing the register
882 * @value: the value to write
884 static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd,
885 const u16 regno, unsigned ctxt,
888 qib_write_kreg(dd, regno + ctxt, value);
891 static inline u64 read_7322_creg(const struct qib_devdata *dd, u16 regno)
893 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
895 return readq(&dd->cspec->cregbase[regno]);
900 static inline u32 read_7322_creg32(const struct qib_devdata *dd, u16 regno)
902 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
904 return readl(&dd->cspec->cregbase[regno]);
909 static inline void write_7322_creg_port(const struct qib_pportdata *ppd,
910 u16 regno, u64 value)
912 if (ppd->cpspec && ppd->cpspec->cpregbase &&
913 (ppd->dd->flags & QIB_PRESENT))
914 writeq(value, &ppd->cpspec->cpregbase[regno]);
917 static inline u64 read_7322_creg_port(const struct qib_pportdata *ppd,
920 if (!ppd->cpspec || !ppd->cpspec->cpregbase ||
921 !(ppd->dd->flags & QIB_PRESENT))
923 return readq(&ppd->cpspec->cpregbase[regno]);
926 static inline u32 read_7322_creg32_port(const struct qib_pportdata *ppd,
929 if (!ppd->cpspec || !ppd->cpspec->cpregbase ||
930 !(ppd->dd->flags & QIB_PRESENT))
932 return readl(&ppd->cpspec->cpregbase[regno]);
935 /* bits in Control register */
936 #define QLOGIC_IB_C_RESET SYM_MASK(Control, SyncReset)
937 #define QLOGIC_IB_C_SDMAFETCHPRIOEN SYM_MASK(Control, SDmaDescFetchPriorityEn)
939 /* bits in general interrupt regs */
940 #define QIB_I_RCVURG_LSB SYM_LSB(IntMask, RcvUrg0IntMask)
941 #define QIB_I_RCVURG_RMASK MASK_ACROSS(0, 17)
942 #define QIB_I_RCVURG_MASK (QIB_I_RCVURG_RMASK << QIB_I_RCVURG_LSB)
943 #define QIB_I_RCVAVAIL_LSB SYM_LSB(IntMask, RcvAvail0IntMask)
944 #define QIB_I_RCVAVAIL_RMASK MASK_ACROSS(0, 17)
945 #define QIB_I_RCVAVAIL_MASK (QIB_I_RCVAVAIL_RMASK << QIB_I_RCVAVAIL_LSB)
946 #define QIB_I_C_ERROR INT_MASK(Err)
948 #define QIB_I_SPIOSENT (INT_MASK_P(SendDone, 0) | INT_MASK_P(SendDone, 1))
949 #define QIB_I_SPIOBUFAVAIL INT_MASK(SendBufAvail)
950 #define QIB_I_GPIO INT_MASK(AssertGPIO)
951 #define QIB_I_P_SDMAINT(pidx) \
952 (INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \
953 INT_MASK_P(SDmaProgress, pidx) | \
954 INT_MASK_PM(SDmaCleanupDone, pidx))
956 /* Interrupt bits that are "per port" */
957 #define QIB_I_P_BITSEXTANT(pidx) \
958 (INT_MASK_P(Err, pidx) | INT_MASK_P(SendDone, pidx) | \
959 INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \
960 INT_MASK_P(SDmaProgress, pidx) | \
961 INT_MASK_PM(SDmaCleanupDone, pidx))
963 /* Interrupt bits that are common to a device */
964 /* currently unused: QIB_I_SPIOSENT */
965 #define QIB_I_C_BITSEXTANT \
966 (QIB_I_RCVURG_MASK | QIB_I_RCVAVAIL_MASK | \
968 QIB_I_C_ERROR | QIB_I_SPIOBUFAVAIL | QIB_I_GPIO)
970 #define QIB_I_BITSEXTANT (QIB_I_C_BITSEXTANT | \
971 QIB_I_P_BITSEXTANT(0) | QIB_I_P_BITSEXTANT(1))
974 * Error bits that are "per port".
976 #define QIB_E_P_IBSTATUSCHANGED ERR_MASK_N(IBStatusChanged)
977 #define QIB_E_P_SHDR ERR_MASK_N(SHeadersErr)
978 #define QIB_E_P_VL15_BUF_MISUSE ERR_MASK_N(VL15BufMisuseErr)
979 #define QIB_E_P_SND_BUF_MISUSE ERR_MASK_N(SendBufMisuseErr)
980 #define QIB_E_P_SUNSUPVL ERR_MASK_N(SendUnsupportedVLErr)
981 #define QIB_E_P_SUNEXP_PKTNUM ERR_MASK_N(SendUnexpectedPktNumErr)
982 #define QIB_E_P_SDROP_DATA ERR_MASK_N(SendDroppedDataPktErr)
983 #define QIB_E_P_SDROP_SMP ERR_MASK_N(SendDroppedSmpPktErr)
984 #define QIB_E_P_SPKTLEN ERR_MASK_N(SendPktLenErr)
985 #define QIB_E_P_SUNDERRUN ERR_MASK_N(SendUnderRunErr)
986 #define QIB_E_P_SMAXPKTLEN ERR_MASK_N(SendMaxPktLenErr)
987 #define QIB_E_P_SMINPKTLEN ERR_MASK_N(SendMinPktLenErr)
988 #define QIB_E_P_RIBLOSTLINK ERR_MASK_N(RcvIBLostLinkErr)
989 #define QIB_E_P_RHDR ERR_MASK_N(RcvHdrErr)
990 #define QIB_E_P_RHDRLEN ERR_MASK_N(RcvHdrLenErr)
991 #define QIB_E_P_RBADTID ERR_MASK_N(RcvBadTidErr)
992 #define QIB_E_P_RBADVERSION ERR_MASK_N(RcvBadVersionErr)
993 #define QIB_E_P_RIBFLOW ERR_MASK_N(RcvIBFlowErr)
994 #define QIB_E_P_REBP ERR_MASK_N(RcvEBPErr)
995 #define QIB_E_P_RUNSUPVL ERR_MASK_N(RcvUnsupportedVLErr)
996 #define QIB_E_P_RUNEXPCHAR ERR_MASK_N(RcvUnexpectedCharErr)
997 #define QIB_E_P_RSHORTPKTLEN ERR_MASK_N(RcvShortPktLenErr)
998 #define QIB_E_P_RLONGPKTLEN ERR_MASK_N(RcvLongPktLenErr)
999 #define QIB_E_P_RMAXPKTLEN ERR_MASK_N(RcvMaxPktLenErr)
1000 #define QIB_E_P_RMINPKTLEN ERR_MASK_N(RcvMinPktLenErr)
1001 #define QIB_E_P_RICRC ERR_MASK_N(RcvICRCErr)
1002 #define QIB_E_P_RVCRC ERR_MASK_N(RcvVCRCErr)
1003 #define QIB_E_P_RFORMATERR ERR_MASK_N(RcvFormatErr)
1005 #define QIB_E_P_SDMA1STDESC ERR_MASK_N(SDma1stDescErr)
1006 #define QIB_E_P_SDMABASE ERR_MASK_N(SDmaBaseErr)
1007 #define QIB_E_P_SDMADESCADDRMISALIGN ERR_MASK_N(SDmaDescAddrMisalignErr)
1008 #define QIB_E_P_SDMADWEN ERR_MASK_N(SDmaDwEnErr)
1009 #define QIB_E_P_SDMAGENMISMATCH ERR_MASK_N(SDmaGenMismatchErr)
1010 #define QIB_E_P_SDMAHALT ERR_MASK_N(SDmaHaltErr)
1011 #define QIB_E_P_SDMAMISSINGDW ERR_MASK_N(SDmaMissingDwErr)
1012 #define QIB_E_P_SDMAOUTOFBOUND ERR_MASK_N(SDmaOutOfBoundErr)
1013 #define QIB_E_P_SDMARPYTAG ERR_MASK_N(SDmaRpyTagErr)
1014 #define QIB_E_P_SDMATAILOUTOFBOUND ERR_MASK_N(SDmaTailOutOfBoundErr)
1015 #define QIB_E_P_SDMAUNEXPDATA ERR_MASK_N(SDmaUnexpDataErr)
1017 /* Error bits that are common to a device */
1018 #define QIB_E_RESET ERR_MASK(ResetNegated)
1019 #define QIB_E_HARDWARE ERR_MASK(HardwareErr)
1020 #define QIB_E_INVALIDADDR ERR_MASK(InvalidAddrErr)
1024 * Per chip (rather than per-port) errors. Most either do
1025 * nothing but trigger a print (because they self-recover, or
1026 * always occur in tandem with other errors that handle the
1027 * issue), or because they indicate errors with no recovery,
1028 * but we want to know that they happened.
1030 #define QIB_E_SBUF_VL15_MISUSE ERR_MASK(SBufVL15MisUseErr)
1031 #define QIB_E_BADEEP ERR_MASK(InvalidEEPCmd)
1032 #define QIB_E_VLMISMATCH ERR_MASK(SendVLMismatchErr)
1033 #define QIB_E_ARMLAUNCH ERR_MASK(SendArmLaunchErr)
1034 #define QIB_E_SPCLTRIG ERR_MASK(SendSpecialTriggerErr)
1035 #define QIB_E_RRCVHDRFULL ERR_MASK(RcvHdrFullErr)
1036 #define QIB_E_RRCVEGRFULL ERR_MASK(RcvEgrFullErr)
1037 #define QIB_E_RCVCTXTSHARE ERR_MASK(RcvContextShareErr)
1039 /* SDMA chip errors (not per port)
1040 * QIB_E_SDMA_BUF_DUP needs no special handling, because we will also get
1041 * the SDMAHALT error immediately, so we just print the dup error via the
1042 * E_AUTO mechanism. This is true of most of the per-port fatal errors
1043 * as well, but since this is port-independent, by definition, it's
1044 * handled a bit differently. SDMA_VL15 and SDMA_WRONG_PORT are per
1045 * packet send errors, and so are handled in the same manner as other
1046 * per-packet errors.
1048 #define QIB_E_SDMA_VL15 ERR_MASK(SDmaVL15Err)
1049 #define QIB_E_SDMA_WRONG_PORT ERR_MASK(SDmaWrongPortErr)
1050 #define QIB_E_SDMA_BUF_DUP ERR_MASK(SDmaBufMaskDuplicateErr)
1053 * Below functionally equivalent to legacy QLOGIC_IB_E_PKTERRS
1054 * it is used to print "common" packet errors.
1056 #define QIB_E_P_PKTERRS (QIB_E_P_SPKTLEN |\
1057 QIB_E_P_SDROP_DATA | QIB_E_P_RVCRC |\
1058 QIB_E_P_RICRC | QIB_E_P_RSHORTPKTLEN |\
1059 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \
1062 /* Error Bits that Packet-related (Receive, per-port) */
1063 #define QIB_E_P_RPKTERRS (\
1064 QIB_E_P_RHDRLEN | QIB_E_P_RBADTID | \
1065 QIB_E_P_RBADVERSION | QIB_E_P_RHDR | \
1066 QIB_E_P_RLONGPKTLEN | QIB_E_P_RSHORTPKTLEN |\
1067 QIB_E_P_RMAXPKTLEN | QIB_E_P_RMINPKTLEN | \
1068 QIB_E_P_RFORMATERR | QIB_E_P_RUNSUPVL | \
1069 QIB_E_P_RUNEXPCHAR | QIB_E_P_RIBFLOW | QIB_E_P_REBP)
1072 * Error bits that are Send-related (per port)
1073 * (ARMLAUNCH excluded from E_SPKTERRS because it gets special handling).
1074 * All of these potentially need to have a buffer disarmed
1076 #define QIB_E_P_SPKTERRS (\
1077 QIB_E_P_SUNEXP_PKTNUM |\
1078 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\
1079 QIB_E_P_SMAXPKTLEN |\
1080 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \
1081 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN | \
1082 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNSUPVL)
1084 #define QIB_E_SPKTERRS ( \
1085 QIB_E_SBUF_VL15_MISUSE | QIB_E_VLMISMATCH | \
1086 ERR_MASK_N(SendUnsupportedVLErr) | \
1087 QIB_E_SPCLTRIG | QIB_E_SDMA_VL15 | QIB_E_SDMA_WRONG_PORT)
1089 #define QIB_E_P_SDMAERRS ( \
1090 QIB_E_P_SDMAHALT | \
1091 QIB_E_P_SDMADESCADDRMISALIGN | \
1092 QIB_E_P_SDMAUNEXPDATA | \
1093 QIB_E_P_SDMAMISSINGDW | \
1094 QIB_E_P_SDMADWEN | \
1095 QIB_E_P_SDMARPYTAG | \
1096 QIB_E_P_SDMA1STDESC | \
1097 QIB_E_P_SDMABASE | \
1098 QIB_E_P_SDMATAILOUTOFBOUND | \
1099 QIB_E_P_SDMAOUTOFBOUND | \
1100 QIB_E_P_SDMAGENMISMATCH)
1103 * This sets some bits more than once, but makes it more obvious which
1104 * bits are not handled under other categories, and the repeat definition
1107 #define QIB_E_P_BITSEXTANT ( \
1108 QIB_E_P_SPKTERRS | QIB_E_P_PKTERRS | QIB_E_P_RPKTERRS | \
1109 QIB_E_P_RIBLOSTLINK | QIB_E_P_IBSTATUSCHANGED | \
1110 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNDERRUN | \
1111 QIB_E_P_SHDR | QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SDMAERRS \
1115 * These are errors that can occur when the link
1116 * changes state while a packet is being sent or received. This doesn't
1117 * cover things like EBP or VCRC that can be the result of a sending
1118 * having the link change state, so we receive a "known bad" packet.
1119 * All of these are "per port", so renamed:
1121 #define QIB_E_P_LINK_PKTERRS (\
1122 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\
1123 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN |\
1124 QIB_E_P_RSHORTPKTLEN | QIB_E_P_RMINPKTLEN |\
1128 * This sets some bits more than once, but makes it more obvious which
1129 * bits are not handled under other categories (such as QIB_E_SPKTERRS),
1130 * and the repeat definition is not a problem.
1132 #define QIB_E_C_BITSEXTANT (\
1133 QIB_E_HARDWARE | QIB_E_INVALIDADDR | QIB_E_BADEEP |\
1134 QIB_E_ARMLAUNCH | QIB_E_VLMISMATCH | QIB_E_RRCVHDRFULL |\
1135 QIB_E_RRCVEGRFULL | QIB_E_RESET | QIB_E_SBUF_VL15_MISUSE)
1137 /* Likewise Neuter E_SPKT_ERRS_IGNORE */
1138 #define E_SPKT_ERRS_IGNORE 0
1140 #define QIB_EXTS_MEMBIST_DISABLED \
1141 SYM_MASK(EXTStatus, MemBISTDisabled)
1142 #define QIB_EXTS_MEMBIST_ENDTEST \
1143 SYM_MASK(EXTStatus, MemBISTEndTest)
1145 #define QIB_E_SPIOARMLAUNCH \
1146 ERR_MASK(SendArmLaunchErr)
1148 #define IBA7322_IBCC_LINKINITCMD_MASK SYM_RMASK(IBCCtrlA_0, LinkInitCmd)
1149 #define IBA7322_IBCC_LINKCMD_SHIFT SYM_LSB(IBCCtrlA_0, LinkCmd)
1152 * IBTA_1_2 is set when multiple speeds are enabled (normal),
1153 * and also if forced QDR (only QDR enabled). It's enabled for the
1154 * forced QDR case so that scrambling will be enabled by the TS3
1155 * exchange, when supported by both sides of the link.
1157 #define IBA7322_IBC_IBTA_1_2_MASK SYM_MASK(IBCCtrlB_0, IB_ENHANCED_MODE)
1158 #define IBA7322_IBC_MAX_SPEED_MASK SYM_MASK(IBCCtrlB_0, SD_SPEED)
1159 #define IBA7322_IBC_SPEED_QDR SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR)
1160 #define IBA7322_IBC_SPEED_DDR SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR)
1161 #define IBA7322_IBC_SPEED_SDR SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR)
1162 #define IBA7322_IBC_SPEED_MASK (SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR) | \
1163 SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR) | SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR))
1164 #define IBA7322_IBC_SPEED_LSB SYM_LSB(IBCCtrlB_0, SD_SPEED_SDR)
1166 #define IBA7322_LEDBLINK_OFF_SHIFT SYM_LSB(RcvPktLEDCnt_0, OFFperiod)
1167 #define IBA7322_LEDBLINK_ON_SHIFT SYM_LSB(RcvPktLEDCnt_0, ONperiod)
1169 #define IBA7322_IBC_WIDTH_AUTONEG SYM_MASK(IBCCtrlB_0, IB_NUM_CHANNELS)
1170 #define IBA7322_IBC_WIDTH_4X_ONLY (1<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1171 #define IBA7322_IBC_WIDTH_1X_ONLY (0<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1173 #define IBA7322_IBC_RXPOL_MASK SYM_MASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1174 #define IBA7322_IBC_RXPOL_LSB SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1175 #define IBA7322_IBC_HRTBT_MASK (SYM_MASK(IBCCtrlB_0, HRTBT_AUTO) | \
1176 SYM_MASK(IBCCtrlB_0, HRTBT_ENB))
1177 #define IBA7322_IBC_HRTBT_RMASK (IBA7322_IBC_HRTBT_MASK >> \
1178 SYM_LSB(IBCCtrlB_0, HRTBT_ENB))
1179 #define IBA7322_IBC_HRTBT_LSB SYM_LSB(IBCCtrlB_0, HRTBT_ENB)
1181 #define IBA7322_REDIRECT_VEC_PER_REG 12
1183 #define IBA7322_SENDCHK_PKEY SYM_MASK(SendCheckControl_0, PKey_En)
1184 #define IBA7322_SENDCHK_BTHQP SYM_MASK(SendCheckControl_0, BTHQP_En)
1185 #define IBA7322_SENDCHK_SLID SYM_MASK(SendCheckControl_0, SLID_En)
1186 #define IBA7322_SENDCHK_RAW_IPV6 SYM_MASK(SendCheckControl_0, RawIPV6_En)
1187 #define IBA7322_SENDCHK_MINSZ SYM_MASK(SendCheckControl_0, PacketTooSmall_En)
1189 #define AUTONEG_TRIES 3 /* sequential retries to negotiate DDR */
1191 #define HWE_AUTO(fldname) { .mask = SYM_MASK(HwErrMask, fldname##Mask), \
1192 .msg = #fldname , .sz = sizeof(#fldname) }
1193 #define HWE_AUTO_P(fldname, port) { .mask = SYM_MASK(HwErrMask, \
1194 fldname##Mask##_##port), .msg = #fldname , .sz = sizeof(#fldname) }
1195 static const struct qib_hwerror_msgs qib_7322_hwerror_msgs[] = {
1196 HWE_AUTO_P(IBSerdesPClkNotDetect, 1),
1197 HWE_AUTO_P(IBSerdesPClkNotDetect, 0),
1198 HWE_AUTO(PCIESerdesPClkNotDetect),
1199 HWE_AUTO(PowerOnBISTFailed),
1200 HWE_AUTO(TempsenseTholdReached),
1201 HWE_AUTO(MemoryErr),
1202 HWE_AUTO(PCIeBusParityErr),
1203 HWE_AUTO(PcieCplTimeout),
1204 HWE_AUTO(PciePoisonedTLP),
1205 HWE_AUTO_P(SDmaMemReadErr, 1),
1206 HWE_AUTO_P(SDmaMemReadErr, 0),
1207 HWE_AUTO_P(IBCBusFromSPCParityErr, 1),
1208 HWE_AUTO_P(IBCBusToSPCParityErr, 1),
1209 HWE_AUTO_P(IBCBusFromSPCParityErr, 0),
1210 HWE_AUTO(statusValidNoEop),
1211 HWE_AUTO(LATriggered),
1212 { .mask = 0, .sz = 0 }
1215 #define E_AUTO(fldname) { .mask = SYM_MASK(ErrMask, fldname##Mask), \
1216 .msg = #fldname, .sz = sizeof(#fldname) }
1217 #define E_P_AUTO(fldname) { .mask = SYM_MASK(ErrMask_0, fldname##Mask), \
1218 .msg = #fldname, .sz = sizeof(#fldname) }
1219 static const struct qib_hwerror_msgs qib_7322error_msgs[] = {
1220 E_AUTO(RcvEgrFullErr),
1221 E_AUTO(RcvHdrFullErr),
1222 E_AUTO(ResetNegated),
1223 E_AUTO(HardwareErr),
1224 E_AUTO(InvalidAddrErr),
1225 E_AUTO(SDmaVL15Err),
1226 E_AUTO(SBufVL15MisUseErr),
1227 E_AUTO(InvalidEEPCmd),
1228 E_AUTO(RcvContextShareErr),
1229 E_AUTO(SendVLMismatchErr),
1230 E_AUTO(SendArmLaunchErr),
1231 E_AUTO(SendSpecialTriggerErr),
1232 E_AUTO(SDmaWrongPortErr),
1233 E_AUTO(SDmaBufMaskDuplicateErr),
1234 { .mask = 0, .sz = 0 }
1237 static const struct qib_hwerror_msgs qib_7322p_error_msgs[] = {
1238 E_P_AUTO(IBStatusChanged),
1239 E_P_AUTO(SHeadersErr),
1240 E_P_AUTO(VL15BufMisuseErr),
1242 * SDmaHaltErr is not really an error, make it clearer;
1244 {.mask = SYM_MASK(ErrMask_0, SDmaHaltErrMask), .msg = "SDmaHalted",
1246 E_P_AUTO(SDmaDescAddrMisalignErr),
1247 E_P_AUTO(SDmaUnexpDataErr),
1248 E_P_AUTO(SDmaMissingDwErr),
1249 E_P_AUTO(SDmaDwEnErr),
1250 E_P_AUTO(SDmaRpyTagErr),
1251 E_P_AUTO(SDma1stDescErr),
1252 E_P_AUTO(SDmaBaseErr),
1253 E_P_AUTO(SDmaTailOutOfBoundErr),
1254 E_P_AUTO(SDmaOutOfBoundErr),
1255 E_P_AUTO(SDmaGenMismatchErr),
1256 E_P_AUTO(SendBufMisuseErr),
1257 E_P_AUTO(SendUnsupportedVLErr),
1258 E_P_AUTO(SendUnexpectedPktNumErr),
1259 E_P_AUTO(SendDroppedDataPktErr),
1260 E_P_AUTO(SendDroppedSmpPktErr),
1261 E_P_AUTO(SendPktLenErr),
1262 E_P_AUTO(SendUnderRunErr),
1263 E_P_AUTO(SendMaxPktLenErr),
1264 E_P_AUTO(SendMinPktLenErr),
1265 E_P_AUTO(RcvIBLostLinkErr),
1266 E_P_AUTO(RcvHdrErr),
1267 E_P_AUTO(RcvHdrLenErr),
1268 E_P_AUTO(RcvBadTidErr),
1269 E_P_AUTO(RcvBadVersionErr),
1270 E_P_AUTO(RcvIBFlowErr),
1271 E_P_AUTO(RcvEBPErr),
1272 E_P_AUTO(RcvUnsupportedVLErr),
1273 E_P_AUTO(RcvUnexpectedCharErr),
1274 E_P_AUTO(RcvShortPktLenErr),
1275 E_P_AUTO(RcvLongPktLenErr),
1276 E_P_AUTO(RcvMaxPktLenErr),
1277 E_P_AUTO(RcvMinPktLenErr),
1278 E_P_AUTO(RcvICRCErr),
1279 E_P_AUTO(RcvVCRCErr),
1280 E_P_AUTO(RcvFormatErr),
1281 { .mask = 0, .sz = 0 }
1285 * Below generates "auto-message" for interrupts not specific to any port or
1288 #define INTR_AUTO(fldname) { .mask = SYM_MASK(IntMask, fldname##Mask), \
1289 .msg = #fldname, .sz = sizeof(#fldname) }
1290 /* Below generates "auto-message" for interrupts specific to a port */
1291 #define INTR_AUTO_P(fldname) { .mask = MASK_ACROSS(\
1292 SYM_LSB(IntMask, fldname##Mask##_0), \
1293 SYM_LSB(IntMask, fldname##Mask##_1)), \
1294 .msg = #fldname "_P", .sz = sizeof(#fldname "_P") }
1295 /* For some reason, the SerDesTrimDone bits are reversed */
1296 #define INTR_AUTO_PI(fldname) { .mask = MASK_ACROSS(\
1297 SYM_LSB(IntMask, fldname##Mask##_1), \
1298 SYM_LSB(IntMask, fldname##Mask##_0)), \
1299 .msg = #fldname "_P", .sz = sizeof(#fldname "_P") }
1301 * Below generates "auto-message" for interrupts specific to a context,
1302 * with ctxt-number appended
1304 #define INTR_AUTO_C(fldname) { .mask = MASK_ACROSS(\
1305 SYM_LSB(IntMask, fldname##0IntMask), \
1306 SYM_LSB(IntMask, fldname##17IntMask)), \
1307 .msg = #fldname "_C", .sz = sizeof(#fldname "_C") }
1309 static const struct qib_hwerror_msgs qib_7322_intr_msgs[] = {
1310 INTR_AUTO_P(SDmaInt),
1311 INTR_AUTO_P(SDmaProgressInt),
1312 INTR_AUTO_P(SDmaIdleInt),
1313 INTR_AUTO_P(SDmaCleanupDone),
1314 INTR_AUTO_C(RcvUrg),
1315 INTR_AUTO_P(ErrInt),
1316 INTR_AUTO(ErrInt), /* non-port-specific errs */
1317 INTR_AUTO(AssertGPIOInt),
1318 INTR_AUTO_P(SendDoneInt),
1319 INTR_AUTO(SendBufAvailInt),
1320 INTR_AUTO_C(RcvAvail),
1321 { .mask = 0, .sz = 0 }
1324 #define TXSYMPTOM_AUTO_P(fldname) \
1325 { .mask = SYM_MASK(SendHdrErrSymptom_0, fldname), \
1326 .msg = #fldname, .sz = sizeof(#fldname) }
1327 static const struct qib_hwerror_msgs hdrchk_msgs[] = {
1328 TXSYMPTOM_AUTO_P(NonKeyPacket),
1329 TXSYMPTOM_AUTO_P(GRHFail),
1330 TXSYMPTOM_AUTO_P(PkeyFail),
1331 TXSYMPTOM_AUTO_P(QPFail),
1332 TXSYMPTOM_AUTO_P(SLIDFail),
1333 TXSYMPTOM_AUTO_P(RawIPV6),
1334 TXSYMPTOM_AUTO_P(PacketTooSmall),
1335 { .mask = 0, .sz = 0 }
1338 #define IBA7322_HDRHEAD_PKTINT_SHIFT 32 /* interrupt cnt in upper 32 bits */
1341 * Called when we might have an error that is specific to a particular
1342 * PIO buffer, and may need to cancel that buffer, so it can be re-used,
1343 * because we don't need to force the update of pioavail
1345 static void qib_disarm_7322_senderrbufs(struct qib_pportdata *ppd)
1347 struct qib_devdata *dd = ppd->dd;
1350 u32 piobcnt = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
1351 u32 regcnt = (piobcnt + BITS_PER_LONG - 1) / BITS_PER_LONG;
1352 unsigned long sbuf[4];
1355 * It's possible that sendbuffererror could have bits set; might
1356 * have already done this as a result of hardware error handling.
1359 for (i = 0; i < regcnt; ++i) {
1360 sbuf[i] = qib_read_kreg64(dd, kr_sendbuffererror + i);
1363 qib_write_kreg(dd, kr_sendbuffererror + i, sbuf[i]);
1368 qib_disarm_piobufs_set(dd, sbuf, piobcnt);
1371 /* No txe_recover yet, if ever */
1373 /* No decode__errors yet */
1374 static void err_decode(char *msg, size_t len, u64 errs,
1375 const struct qib_hwerror_msgs *msp)
1378 int took, multi, n = 0;
1380 while (errs && msp && msp->mask) {
1381 multi = (msp->mask & (msp->mask - 1));
1382 while (errs & msp->mask) {
1383 these = (errs & msp->mask);
1384 lmask = (these & (these - 1)) ^ these;
1387 /* separate the strings */
1392 /* msp->sz counts the nul */
1393 took = min_t(size_t, msp->sz - (size_t)1, len);
1394 memcpy(msg, msp->msg, took);
1402 /* More than one bit this mask */
1405 while (lmask & msp->mask) {
1409 took = scnprintf(msg, len, "_%d", idx);
1416 /* If some bits are left, show in hex. */
1418 snprintf(msg, len, "%sMORE:%llX", n ? "," : "",
1419 (unsigned long long) errs);
1422 /* only called if r1 set */
1423 static void flush_fifo(struct qib_pportdata *ppd)
1425 struct qib_devdata *dd = ppd->dd;
1426 u32 __iomem *piobuf;
1430 const unsigned hdrwords = 7;
1431 static struct qib_ib_header ibhdr = {
1432 .lrh[0] = cpu_to_be16(0xF000 | QIB_LRH_BTH),
1433 .lrh[1] = IB_LID_PERMISSIVE,
1434 .lrh[2] = cpu_to_be16(hdrwords + SIZE_OF_CRC),
1435 .lrh[3] = IB_LID_PERMISSIVE,
1436 .u.oth.bth[0] = cpu_to_be32(
1437 (IB_OPCODE_UD_SEND_ONLY << 24) | QIB_DEFAULT_P_KEY),
1438 .u.oth.bth[1] = cpu_to_be32(0),
1439 .u.oth.bth[2] = cpu_to_be32(0),
1440 .u.oth.u.ud.deth[0] = cpu_to_be32(0),
1441 .u.oth.u.ud.deth[1] = cpu_to_be32(0),
1445 * Send a dummy VL15 packet to flush the launch FIFO.
1446 * This will not actually be sent since the TxeBypassIbc bit is set.
1448 pbc = PBC_7322_VL15_SEND |
1449 (((u64)ppd->hw_pidx) << (PBC_PORT_SEL_LSB + 32)) |
1450 (hdrwords + SIZE_OF_CRC);
1451 piobuf = qib_7322_getsendbuf(ppd, pbc, &bufn);
1454 writeq(pbc, piobuf);
1455 hdr = (u32 *) &ibhdr;
1456 if (dd->flags & QIB_PIO_FLUSH_WC) {
1458 qib_pio_copy(piobuf + 2, hdr, hdrwords - 1);
1460 __raw_writel(hdr[hdrwords - 1], piobuf + hdrwords + 1);
1463 qib_pio_copy(piobuf + 2, hdr, hdrwords);
1464 qib_sendbuf_done(dd, bufn);
1468 * This is called with interrupts disabled and sdma_lock held.
1470 static void qib_7322_sdma_sendctrl(struct qib_pportdata *ppd, unsigned op)
1472 struct qib_devdata *dd = ppd->dd;
1473 u64 set_sendctrl = 0;
1474 u64 clr_sendctrl = 0;
1476 if (op & QIB_SDMA_SENDCTRL_OP_ENABLE)
1477 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable);
1479 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable);
1481 if (op & QIB_SDMA_SENDCTRL_OP_INTENABLE)
1482 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable);
1484 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable);
1486 if (op & QIB_SDMA_SENDCTRL_OP_HALT)
1487 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt);
1489 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt);
1491 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN)
1492 set_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) |
1493 SYM_MASK(SendCtrl_0, TxeAbortIbc) |
1494 SYM_MASK(SendCtrl_0, TxeDrainRmFifo);
1496 clr_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) |
1497 SYM_MASK(SendCtrl_0, TxeAbortIbc) |
1498 SYM_MASK(SendCtrl_0, TxeDrainRmFifo);
1500 spin_lock(&dd->sendctrl_lock);
1502 /* If we are draining everything, block sends first */
1503 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) {
1504 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable);
1505 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1506 qib_write_kreg(dd, kr_scratch, 0);
1509 ppd->p_sendctrl |= set_sendctrl;
1510 ppd->p_sendctrl &= ~clr_sendctrl;
1512 if (op & QIB_SDMA_SENDCTRL_OP_CLEANUP)
1513 qib_write_kreg_port(ppd, krp_sendctrl,
1515 SYM_MASK(SendCtrl_0, SDmaCleanup));
1517 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1518 qib_write_kreg(dd, kr_scratch, 0);
1520 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) {
1521 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable);
1522 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1523 qib_write_kreg(dd, kr_scratch, 0);
1526 spin_unlock(&dd->sendctrl_lock);
1528 if ((op & QIB_SDMA_SENDCTRL_OP_DRAIN) && ppd->dd->cspec->r1)
1532 static void qib_7322_sdma_hw_clean_up(struct qib_pportdata *ppd)
1534 __qib_sdma_process_event(ppd, qib_sdma_event_e50_hw_cleaned);
1537 static void qib_sdma_7322_setlengen(struct qib_pportdata *ppd)
1540 * Set SendDmaLenGen and clear and set
1541 * the MSB of the generation count to enable generation checking
1542 * and load the internal generation counter.
1544 qib_write_kreg_port(ppd, krp_senddmalengen, ppd->sdma_descq_cnt);
1545 qib_write_kreg_port(ppd, krp_senddmalengen,
1546 ppd->sdma_descq_cnt |
1547 (1ULL << QIB_7322_SendDmaLenGen_0_Generation_MSB));
1551 * Must be called with sdma_lock held, or before init finished.
1553 static void qib_sdma_update_7322_tail(struct qib_pportdata *ppd, u16 tail)
1555 /* Commit writes to memory and advance the tail on the chip */
1557 ppd->sdma_descq_tail = tail;
1558 qib_write_kreg_port(ppd, krp_senddmatail, tail);
1562 * This is called with interrupts disabled and sdma_lock held.
1564 static void qib_7322_sdma_hw_start_up(struct qib_pportdata *ppd)
1568 * The hardware doesn't require this but we do it so that verbs
1569 * and user applications don't wait for link active to send stale
1572 sendctrl_7322_mod(ppd, QIB_SENDCTRL_FLUSH);
1574 qib_sdma_7322_setlengen(ppd);
1575 qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */
1576 ppd->sdma_head_dma[0] = 0;
1577 qib_7322_sdma_sendctrl(ppd,
1578 ppd->sdma_state.current_op | QIB_SDMA_SENDCTRL_OP_CLEANUP);
1581 #define DISABLES_SDMA ( \
1582 QIB_E_P_SDMAHALT | \
1583 QIB_E_P_SDMADESCADDRMISALIGN | \
1584 QIB_E_P_SDMAMISSINGDW | \
1585 QIB_E_P_SDMADWEN | \
1586 QIB_E_P_SDMARPYTAG | \
1587 QIB_E_P_SDMA1STDESC | \
1588 QIB_E_P_SDMABASE | \
1589 QIB_E_P_SDMATAILOUTOFBOUND | \
1590 QIB_E_P_SDMAOUTOFBOUND | \
1591 QIB_E_P_SDMAGENMISMATCH)
1593 static void sdma_7322_p_errors(struct qib_pportdata *ppd, u64 errs)
1595 unsigned long flags;
1596 struct qib_devdata *dd = ppd->dd;
1598 errs &= QIB_E_P_SDMAERRS;
1599 err_decode(ppd->cpspec->sdmamsgbuf, sizeof(ppd->cpspec->sdmamsgbuf),
1600 errs, qib_7322p_error_msgs);
1602 if (errs & QIB_E_P_SDMAUNEXPDATA)
1603 qib_dev_err(dd, "IB%u:%u SDmaUnexpData\n", dd->unit,
1606 spin_lock_irqsave(&ppd->sdma_lock, flags);
1608 if (errs != QIB_E_P_SDMAHALT) {
1609 /* SDMA errors have QIB_E_P_SDMAHALT and another bit set */
1610 qib_dev_porterr(dd, ppd->port,
1611 "SDMA %s 0x%016llx %s\n",
1612 qib_sdma_state_names[ppd->sdma_state.current_state],
1613 errs, ppd->cpspec->sdmamsgbuf);
1614 dump_sdma_7322_state(ppd);
1617 switch (ppd->sdma_state.current_state) {
1618 case qib_sdma_state_s00_hw_down:
1621 case qib_sdma_state_s10_hw_start_up_wait:
1622 if (errs & QIB_E_P_SDMAHALT)
1623 __qib_sdma_process_event(ppd,
1624 qib_sdma_event_e20_hw_started);
1627 case qib_sdma_state_s20_idle:
1630 case qib_sdma_state_s30_sw_clean_up_wait:
1633 case qib_sdma_state_s40_hw_clean_up_wait:
1634 if (errs & QIB_E_P_SDMAHALT)
1635 __qib_sdma_process_event(ppd,
1636 qib_sdma_event_e50_hw_cleaned);
1639 case qib_sdma_state_s50_hw_halt_wait:
1640 if (errs & QIB_E_P_SDMAHALT)
1641 __qib_sdma_process_event(ppd,
1642 qib_sdma_event_e60_hw_halted);
1645 case qib_sdma_state_s99_running:
1646 __qib_sdma_process_event(ppd, qib_sdma_event_e7322_err_halted);
1647 __qib_sdma_process_event(ppd, qib_sdma_event_e60_hw_halted);
1651 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
1655 * handle per-device errors (not per-port errors)
1657 static noinline void handle_7322_errors(struct qib_devdata *dd)
1665 qib_stats.sps_errints++;
1666 errs = qib_read_kreg64(dd, kr_errstatus);
1668 qib_devinfo(dd->pcidev,
1669 "device error interrupt, but no error bits set!\n");
1673 /* don't report errors that are masked */
1674 errs &= dd->cspec->errormask;
1675 msg = dd->cspec->emsgbuf;
1677 /* do these first, they are most important */
1678 if (errs & QIB_E_HARDWARE) {
1680 qib_7322_handle_hwerrors(dd, msg, sizeof dd->cspec->emsgbuf);
1682 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx)
1683 if (errs & dd->eep_st_masks[log_idx].errs_to_log)
1684 qib_inc_eeprom_err(dd, log_idx, 1);
1686 if (errs & QIB_E_SPKTERRS) {
1687 qib_disarm_7322_senderrbufs(dd->pport);
1688 qib_stats.sps_txerrs++;
1689 } else if (errs & QIB_E_INVALIDADDR)
1690 qib_stats.sps_txerrs++;
1691 else if (errs & QIB_E_ARMLAUNCH) {
1692 qib_stats.sps_txerrs++;
1693 qib_disarm_7322_senderrbufs(dd->pport);
1695 qib_write_kreg(dd, kr_errclear, errs);
1698 * The ones we mask off are handled specially below
1699 * or above. Also mask SDMADISABLED by default as it
1702 mask = QIB_E_HARDWARE;
1705 err_decode(msg, sizeof dd->cspec->emsgbuf, errs & ~mask,
1706 qib_7322error_msgs);
1709 * Getting reset is a tragedy for all ports. Mark the device
1710 * _and_ the ports as "offline" in way meaningful to each.
1712 if (errs & QIB_E_RESET) {
1716 "Got reset, requires re-init (unload and reload driver)\n");
1717 dd->flags &= ~QIB_INITTED; /* needs re-init */
1718 /* mark as having had error */
1719 *dd->devstatusp |= QIB_STATUS_HWERROR;
1720 for (pidx = 0; pidx < dd->num_pports; ++pidx)
1721 if (dd->pport[pidx].link_speed_supported)
1722 *dd->pport[pidx].statusp &= ~QIB_STATUS_IB_CONF;
1726 qib_dev_err(dd, "%s error\n", msg);
1729 * If there were hdrq or egrfull errors, wake up any processes
1730 * waiting in poll. We used to try to check which contexts had
1731 * the overflow, but given the cost of that and the chip reads
1732 * to support it, it's better to just wake everybody up if we
1733 * get an overflow; waiters can poll again if it's not them.
1735 if (errs & (ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr))) {
1736 qib_handle_urcv(dd, ~0U);
1737 if (errs & ERR_MASK(RcvEgrFullErr))
1738 qib_stats.sps_buffull++;
1740 qib_stats.sps_hdrfull++;
1747 static void qib_error_tasklet(unsigned long data)
1749 struct qib_devdata *dd = (struct qib_devdata *)data;
1751 handle_7322_errors(dd);
1752 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1755 static void reenable_chase(unsigned long opaque)
1757 struct qib_pportdata *ppd = (struct qib_pportdata *)opaque;
1759 ppd->cpspec->chase_timer.expires = 0;
1760 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
1761 QLOGIC_IB_IBCC_LINKINITCMD_POLL);
1764 static void disable_chase(struct qib_pportdata *ppd, unsigned long tnow,
1767 ppd->cpspec->chase_end = 0;
1772 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
1773 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1774 ppd->cpspec->chase_timer.expires = jiffies + QIB_CHASE_DIS_TIME;
1775 add_timer(&ppd->cpspec->chase_timer);
1778 static void handle_serdes_issues(struct qib_pportdata *ppd, u64 ibcst)
1783 ibclt = (u8)SYM_FIELD(ibcst, IBCStatusA_0, LinkTrainingState);
1786 * Detect and handle the state chase issue, where we can
1787 * get stuck if we are unlucky on timing on both sides of
1788 * the link. If we are, we disable, set a timer, and
1792 case IB_7322_LT_STATE_CFGRCVFCFG:
1793 case IB_7322_LT_STATE_CFGWAITRMT:
1794 case IB_7322_LT_STATE_TXREVLANES:
1795 case IB_7322_LT_STATE_CFGENH:
1797 if (ppd->cpspec->chase_end &&
1798 time_after(tnow, ppd->cpspec->chase_end))
1799 disable_chase(ppd, tnow, ibclt);
1800 else if (!ppd->cpspec->chase_end)
1801 ppd->cpspec->chase_end = tnow + QIB_CHASE_TIME;
1804 ppd->cpspec->chase_end = 0;
1808 if (((ibclt >= IB_7322_LT_STATE_CFGTEST &&
1809 ibclt <= IB_7322_LT_STATE_CFGWAITENH) ||
1810 ibclt == IB_7322_LT_STATE_LINKUP) &&
1811 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR))) {
1813 ppd->cpspec->qdr_reforce = 1;
1814 if (!ppd->dd->cspec->r1)
1815 serdes_7322_los_enable(ppd, 0);
1816 } else if (ppd->cpspec->qdr_reforce &&
1817 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) &&
1818 (ibclt == IB_7322_LT_STATE_CFGENH ||
1819 ibclt == IB_7322_LT_STATE_CFGIDLE ||
1820 ibclt == IB_7322_LT_STATE_LINKUP))
1823 if ((IS_QMH(ppd->dd) || IS_QME(ppd->dd)) &&
1824 ppd->link_speed_enabled == QIB_IB_QDR &&
1825 (ibclt == IB_7322_LT_STATE_CFGTEST ||
1826 ibclt == IB_7322_LT_STATE_CFGENH ||
1827 (ibclt >= IB_7322_LT_STATE_POLLACTIVE &&
1828 ibclt <= IB_7322_LT_STATE_SLEEPQUIET)))
1831 if (ibclt != IB_7322_LT_STATE_LINKUP) {
1832 u8 ltstate = qib_7322_phys_portstate(ibcst);
1833 u8 pibclt = (u8)SYM_FIELD(ppd->lastibcstat, IBCStatusA_0,
1835 if (!ppd->dd->cspec->r1 &&
1836 pibclt == IB_7322_LT_STATE_LINKUP &&
1837 ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER &&
1838 ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN &&
1839 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT &&
1840 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE)
1841 /* If the link went down (but no into recovery,
1842 * turn LOS back on */
1843 serdes_7322_los_enable(ppd, 1);
1844 if (!ppd->cpspec->qdr_dfe_on &&
1845 ibclt <= IB_7322_LT_STATE_SLEEPQUIET) {
1846 ppd->cpspec->qdr_dfe_on = 1;
1847 ppd->cpspec->qdr_dfe_time = 0;
1848 /* On link down, reenable QDR adaptation */
1849 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
1850 ppd->dd->cspec->r1 ?
1851 QDR_STATIC_ADAPT_DOWN_R1 :
1852 QDR_STATIC_ADAPT_DOWN);
1854 "IB%u:%u re-enabled QDR adaptation ibclt %x\n",
1855 ppd->dd->unit, ppd->port, ibclt);
1860 static int qib_7322_set_ib_cfg(struct qib_pportdata *, int, u32);
1863 * This is per-pport error handling.
1864 * will likely get it's own MSIx interrupt (one for each port,
1865 * although just a single handler).
1867 static noinline void handle_7322_p_errors(struct qib_pportdata *ppd)
1870 u64 ignore_this_time = 0, iserr = 0, errs, fmask;
1871 struct qib_devdata *dd = ppd->dd;
1873 /* do this as soon as possible */
1874 fmask = qib_read_kreg64(dd, kr_act_fmask);
1876 check_7322_rxe_status(ppd);
1878 errs = qib_read_kreg_port(ppd, krp_errstatus);
1880 qib_devinfo(dd->pcidev,
1881 "Port%d error interrupt, but no error bits set!\n",
1884 errs &= ~QIB_E_P_IBSTATUSCHANGED;
1888 msg = ppd->cpspec->epmsgbuf;
1891 if (errs & ~QIB_E_P_BITSEXTANT) {
1892 err_decode(msg, sizeof ppd->cpspec->epmsgbuf,
1893 errs & ~QIB_E_P_BITSEXTANT, qib_7322p_error_msgs);
1895 snprintf(msg, sizeof ppd->cpspec->epmsgbuf,
1897 qib_dev_porterr(dd, ppd->port,
1898 "error interrupt with unknown errors 0x%016Lx set (and %s)\n",
1899 (errs & ~QIB_E_P_BITSEXTANT), msg);
1903 if (errs & QIB_E_P_SHDR) {
1906 /* determine cause, then write to clear */
1907 symptom = qib_read_kreg_port(ppd, krp_sendhdrsymptom);
1908 qib_write_kreg_port(ppd, krp_sendhdrsymptom, 0);
1909 err_decode(msg, sizeof ppd->cpspec->epmsgbuf, symptom,
1912 /* senderrbuf cleared in SPKTERRS below */
1915 if (errs & QIB_E_P_SPKTERRS) {
1916 if ((errs & QIB_E_P_LINK_PKTERRS) &&
1917 !(ppd->lflags & QIBL_LINKACTIVE)) {
1919 * This can happen when trying to bring the link
1920 * up, but the IB link changes state at the "wrong"
1921 * time. The IB logic then complains that the packet
1922 * isn't valid. We don't want to confuse people, so
1923 * we just don't print them, except at debug
1925 err_decode(msg, sizeof ppd->cpspec->epmsgbuf,
1926 (errs & QIB_E_P_LINK_PKTERRS),
1927 qib_7322p_error_msgs);
1929 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS;
1931 qib_disarm_7322_senderrbufs(ppd);
1932 } else if ((errs & QIB_E_P_LINK_PKTERRS) &&
1933 !(ppd->lflags & QIBL_LINKACTIVE)) {
1935 * This can happen when SMA is trying to bring the link
1936 * up, but the IB link changes state at the "wrong" time.
1937 * The IB logic then complains that the packet isn't
1938 * valid. We don't want to confuse people, so we just
1939 * don't print them, except at debug
1941 err_decode(msg, sizeof ppd->cpspec->epmsgbuf, errs,
1942 qib_7322p_error_msgs);
1943 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS;
1947 qib_write_kreg_port(ppd, krp_errclear, errs);
1949 errs &= ~ignore_this_time;
1953 if (errs & QIB_E_P_RPKTERRS)
1954 qib_stats.sps_rcverrs++;
1955 if (errs & QIB_E_P_SPKTERRS)
1956 qib_stats.sps_txerrs++;
1958 iserr = errs & ~(QIB_E_P_RPKTERRS | QIB_E_P_PKTERRS);
1960 if (errs & QIB_E_P_SDMAERRS)
1961 sdma_7322_p_errors(ppd, errs);
1963 if (errs & QIB_E_P_IBSTATUSCHANGED) {
1967 ibcs = qib_read_kreg_port(ppd, krp_ibcstatus_a);
1968 ltstate = qib_7322_phys_portstate(ibcs);
1970 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
1971 handle_serdes_issues(ppd, ibcs);
1972 if (!(ppd->cpspec->ibcctrl_a &
1973 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn))) {
1975 * We got our interrupt, so init code should be
1976 * happy and not try alternatives. Now squelch
1977 * other "chatter" from link-negotiation (pre Init)
1979 ppd->cpspec->ibcctrl_a |=
1980 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
1981 qib_write_kreg_port(ppd, krp_ibcctrl_a,
1982 ppd->cpspec->ibcctrl_a);
1985 /* Update our picture of width and speed from chip */
1986 ppd->link_width_active =
1987 (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) ?
1988 IB_WIDTH_4X : IB_WIDTH_1X;
1989 ppd->link_speed_active = (ibcs & SYM_MASK(IBCStatusA_0,
1990 LinkSpeedQDR)) ? QIB_IB_QDR : (ibcs &
1991 SYM_MASK(IBCStatusA_0, LinkSpeedActive)) ?
1992 QIB_IB_DDR : QIB_IB_SDR;
1994 if ((ppd->lflags & QIBL_IB_LINK_DISABLED) && ltstate !=
1995 IB_PHYSPORTSTATE_DISABLED)
1996 qib_set_ib_7322_lstate(ppd, 0,
1997 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
2000 * Since going into a recovery state causes the link
2001 * state to go down and since recovery is transitory,
2002 * it is better if we "miss" ever seeing the link
2003 * training state go into recovery (i.e., ignore this
2004 * transition for link state special handling purposes)
2005 * without updating lastibcstat.
2007 if (ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER &&
2008 ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN &&
2009 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT &&
2010 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE)
2011 qib_handle_e_ibstatuschanged(ppd, ibcs);
2014 qib_dev_porterr(dd, ppd->port, "%s error\n", msg);
2016 if (ppd->state_wanted & ppd->lflags)
2017 wake_up_interruptible(&ppd->state_wait);
2022 /* enable/disable chip from delivering interrupts */
2023 static void qib_7322_set_intr_state(struct qib_devdata *dd, u32 enable)
2026 if (dd->flags & QIB_BADINTR)
2028 qib_write_kreg(dd, kr_intmask, dd->cspec->int_enable_mask);
2029 /* cause any pending enabled interrupts to be re-delivered */
2030 qib_write_kreg(dd, kr_intclear, 0ULL);
2031 if (dd->cspec->num_msix_entries) {
2032 /* and same for MSIx */
2033 u64 val = qib_read_kreg64(dd, kr_intgranted);
2035 qib_write_kreg(dd, kr_intgranted, val);
2038 qib_write_kreg(dd, kr_intmask, 0ULL);
2042 * Try to cleanup as much as possible for anything that might have gone
2043 * wrong while in freeze mode, such as pio buffers being written by user
2044 * processes (causing armlaunch), send errors due to going into freeze mode,
2045 * etc., and try to avoid causing extra interrupts while doing so.
2046 * Forcibly update the in-memory pioavail register copies after cleanup
2047 * because the chip won't do it while in freeze mode (the register values
2048 * themselves are kept correct).
2049 * Make sure that we don't lose any important interrupts by using the chip
2050 * feature that says that writing 0 to a bit in *clear that is set in
2051 * *status will cause an interrupt to be generated again (if allowed by
2053 * This is in chip-specific code because of all of the register accesses,
2054 * even though the details are similar on most chips.
2056 static void qib_7322_clear_freeze(struct qib_devdata *dd)
2060 /* disable error interrupts, to avoid confusion */
2061 qib_write_kreg(dd, kr_errmask, 0ULL);
2063 for (pidx = 0; pidx < dd->num_pports; ++pidx)
2064 if (dd->pport[pidx].link_speed_supported)
2065 qib_write_kreg_port(dd->pport + pidx, krp_errmask,
2068 /* also disable interrupts; errormask is sometimes overwriten */
2069 qib_7322_set_intr_state(dd, 0);
2071 /* clear the freeze, and be sure chip saw it */
2072 qib_write_kreg(dd, kr_control, dd->control);
2073 qib_read_kreg32(dd, kr_scratch);
2076 * Force new interrupt if any hwerr, error or interrupt bits are
2077 * still set, and clear "safe" send packet errors related to freeze
2078 * and cancelling sends. Re-enable error interrupts before possible
2079 * force of re-interrupt on pending interrupts.
2081 qib_write_kreg(dd, kr_hwerrclear, 0ULL);
2082 qib_write_kreg(dd, kr_errclear, E_SPKT_ERRS_IGNORE);
2083 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
2084 /* We need to purge per-port errs and reset mask, too */
2085 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
2086 if (!dd->pport[pidx].link_speed_supported)
2088 qib_write_kreg_port(dd->pport + pidx, krp_errclear, ~0Ull);
2089 qib_write_kreg_port(dd->pport + pidx, krp_errmask, ~0Ull);
2091 qib_7322_set_intr_state(dd, 1);
2094 /* no error handling to speak of */
2096 * qib_7322_handle_hwerrors - display hardware errors.
2097 * @dd: the qlogic_ib device
2098 * @msg: the output buffer
2099 * @msgl: the size of the output buffer
2101 * Use same msg buffer as regular errors to avoid excessive stack
2102 * use. Most hardware errors are catastrophic, but for right now,
2103 * we'll print them and continue. We reuse the same message buffer as
2104 * qib_handle_errors() to avoid excessive stack usage.
2106 static void qib_7322_handle_hwerrors(struct qib_devdata *dd, char *msg,
2113 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
2116 if (hwerrs == ~0ULL) {
2118 "Read of hardware error status failed (all bits set); ignoring\n");
2121 qib_stats.sps_hwerrs++;
2123 /* Always clear the error status register, except BIST fail */
2124 qib_write_kreg(dd, kr_hwerrclear, hwerrs &
2125 ~HWE_MASK(PowerOnBISTFailed));
2127 hwerrs &= dd->cspec->hwerrmask;
2129 /* no EEPROM logging, yet */
2132 qib_devinfo(dd->pcidev,
2133 "Hardware error: hwerr=0x%llx (cleared)\n",
2134 (unsigned long long) hwerrs);
2136 ctrl = qib_read_kreg32(dd, kr_control);
2137 if ((ctrl & SYM_MASK(Control, FreezeMode)) && !dd->diag_client) {
2139 * No recovery yet...
2141 if ((hwerrs & ~HWE_MASK(LATriggered)) ||
2142 dd->cspec->stay_in_freeze) {
2144 * If any set that we aren't ignoring only make the
2145 * complaint once, in case it's stuck or recurring,
2146 * and we get here multiple times
2147 * Force link down, so switch knows, and
2148 * LEDs are turned off.
2150 if (dd->flags & QIB_INITTED)
2153 qib_7322_clear_freeze(dd);
2156 if (hwerrs & HWE_MASK(PowerOnBISTFailed)) {
2159 "[Memory BIST test failed, InfiniPath hardware unusable]",
2161 /* ignore from now on, so disable until driver reloaded */
2162 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed);
2163 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2166 err_decode(msg, msgl, hwerrs, qib_7322_hwerror_msgs);
2168 /* Ignore esoteric PLL failures et al. */
2170 qib_dev_err(dd, "%s hardware error\n", msg);
2173 (SYM_MASK(HwErrMask, SDmaMemReadErrMask_0) |
2174 SYM_MASK(HwErrMask, SDmaMemReadErrMask_1))) {
2177 unsigned long flags;
2178 struct qib_pportdata *ppd = dd->pport;
2179 for (; pidx < dd->num_pports; ++pidx, ppd++) {
2181 if (pidx == 0 && (hwerrs &
2182 SYM_MASK(HwErrMask, SDmaMemReadErrMask_0)))
2184 if (pidx == 1 && (hwerrs &
2185 SYM_MASK(HwErrMask, SDmaMemReadErrMask_1)))
2188 spin_lock_irqsave(&ppd->sdma_lock, flags);
2189 dump_sdma_7322_state(ppd);
2190 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
2195 if (isfatal && !dd->diag_client) {
2197 "Fatal Hardware Error, no longer usable, SN %.16s\n",
2200 * for /sys status file and user programs to print; if no
2201 * trailing brace is copied, we'll know it was truncated.
2204 snprintf(dd->freezemsg, dd->freezelen,
2206 qib_disable_after_error(dd);
2212 * qib_7322_init_hwerrors - enable hardware errors
2213 * @dd: the qlogic_ib device
2215 * now that we have finished initializing everything that might reasonably
2216 * cause a hardware error, and cleared those errors bits as they occur,
2217 * we can enable hardware errors in the mask (potentially enabling
2218 * freeze mode), and enable hardware errors as errors (along with
2219 * everything else) in errormask
2221 static void qib_7322_init_hwerrors(struct qib_devdata *dd)
2226 extsval = qib_read_kreg64(dd, kr_extstatus);
2227 if (!(extsval & (QIB_EXTS_MEMBIST_DISABLED |
2228 QIB_EXTS_MEMBIST_ENDTEST)))
2229 qib_dev_err(dd, "MemBIST did not complete!\n");
2231 /* never clear BIST failure, so reported on each driver load */
2232 qib_write_kreg(dd, kr_hwerrclear, ~HWE_MASK(PowerOnBISTFailed));
2233 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2236 qib_write_kreg(dd, kr_errclear, ~0ULL);
2237 /* enable errors that are masked, at least this first time. */
2238 qib_write_kreg(dd, kr_errmask, ~0ULL);
2239 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask);
2240 for (pidx = 0; pidx < dd->num_pports; ++pidx)
2241 if (dd->pport[pidx].link_speed_supported)
2242 qib_write_kreg_port(dd->pport + pidx, krp_errmask,
2247 * Disable and enable the armlaunch error. Used for PIO bandwidth testing
2248 * on chips that are count-based, rather than trigger-based. There is no
2249 * reference counting, but that's also fine, given the intended use.
2250 * Only chip-specific because it's all register accesses
2252 static void qib_set_7322_armlaunch(struct qib_devdata *dd, u32 enable)
2255 qib_write_kreg(dd, kr_errclear, QIB_E_SPIOARMLAUNCH);
2256 dd->cspec->errormask |= QIB_E_SPIOARMLAUNCH;
2258 dd->cspec->errormask &= ~QIB_E_SPIOARMLAUNCH;
2259 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
2263 * Formerly took parameter <which> in pre-shifted,
2264 * pre-merged form with LinkCmd and LinkInitCmd
2265 * together, and assuming the zero was NOP.
2267 static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd,
2271 struct qib_devdata *dd = ppd->dd;
2272 unsigned long flags;
2274 if (linitcmd == QLOGIC_IB_IBCC_LINKINITCMD_DISABLE) {
2276 * If we are told to disable, note that so link-recovery
2277 * code does not attempt to bring us back up.
2278 * Also reset everything that we can, so we start
2279 * completely clean when re-enabled (before we
2280 * actually issue the disable to the IBC)
2282 qib_7322_mini_pcs_reset(ppd);
2283 spin_lock_irqsave(&ppd->lflags_lock, flags);
2284 ppd->lflags |= QIBL_IB_LINK_DISABLED;
2285 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2286 } else if (linitcmd || linkcmd == QLOGIC_IB_IBCC_LINKCMD_DOWN) {
2288 * Any other linkinitcmd will lead to LINKDOWN and then
2289 * to INIT (if all is well), so clear flag to let
2290 * link-recovery code attempt to bring us back up.
2292 spin_lock_irqsave(&ppd->lflags_lock, flags);
2293 ppd->lflags &= ~QIBL_IB_LINK_DISABLED;
2294 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2296 * Clear status change interrupt reduction so the
2297 * new state is seen.
2299 ppd->cpspec->ibcctrl_a &=
2300 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
2303 mod_wd = (linkcmd << IBA7322_IBCC_LINKCMD_SHIFT) |
2304 (linitcmd << QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
2306 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a |
2308 /* write to chip to prevent back-to-back writes of ibc reg */
2309 qib_write_kreg(dd, kr_scratch, 0);
2314 * The total RCV buffer memory is 64KB, used for both ports, and is
2315 * in units of 64 bytes (same as IB flow control credit unit).
2316 * The consumedVL unit in the same registers are in 32 byte units!
2317 * So, a VL15 packet needs 4.50 IB credits, and 9 rx buffer chunks,
2318 * and we can therefore allocate just 9 IB credits for 2 VL15 packets
2319 * in krp_rxcreditvl15, rather than 10.
2321 #define RCV_BUF_UNITSZ 64
2322 #define NUM_RCV_BUF_UNITS(dd) ((64 * 1024) / (RCV_BUF_UNITSZ * dd->num_pports))
2324 static void set_vls(struct qib_pportdata *ppd)
2326 int i, numvls, totcred, cred_vl, vl0extra;
2327 struct qib_devdata *dd = ppd->dd;
2330 numvls = qib_num_vls(ppd->vls_operational);
2333 * Set up per-VL credits. Below is kluge based on these assumptions:
2334 * 1) port is disabled at the time early_init is called.
2335 * 2) give VL15 17 credits, for two max-plausible packets.
2336 * 3) Give VL0-N the rest, with any rounding excess used for VL0
2338 /* 2 VL15 packets @ 288 bytes each (including IB headers) */
2339 totcred = NUM_RCV_BUF_UNITS(dd);
2340 cred_vl = (2 * 288 + RCV_BUF_UNITSZ - 1) / RCV_BUF_UNITSZ;
2342 qib_write_kreg_port(ppd, krp_rxcreditvl15, (u64) cred_vl);
2343 cred_vl = totcred / numvls;
2344 vl0extra = totcred - cred_vl * numvls;
2345 qib_write_kreg_port(ppd, krp_rxcreditvl0, cred_vl + vl0extra);
2346 for (i = 1; i < numvls; i++)
2347 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, cred_vl);
2348 for (; i < 8; i++) /* no buffer space for other VLs */
2349 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0);
2351 /* Notify IBC that credits need to be recalculated */
2352 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx);
2353 val |= SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
2354 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
2355 qib_write_kreg(dd, kr_scratch, 0ULL);
2356 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
2357 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
2359 for (i = 0; i < numvls; i++)
2360 val = qib_read_kreg_port(ppd, krp_rxcreditvl0 + i);
2361 val = qib_read_kreg_port(ppd, krp_rxcreditvl15);
2363 /* Change the number of operational VLs */
2364 ppd->cpspec->ibcctrl_a = (ppd->cpspec->ibcctrl_a &
2365 ~SYM_MASK(IBCCtrlA_0, NumVLane)) |
2366 ((u64)(numvls - 1) << SYM_LSB(IBCCtrlA_0, NumVLane));
2367 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
2368 qib_write_kreg(dd, kr_scratch, 0ULL);
2372 * The code that deals with actual SerDes is in serdes_7322_init().
2373 * Compared to the code for iba7220, it is minimal.
2375 static int serdes_7322_init(struct qib_pportdata *ppd);
2378 * qib_7322_bringup_serdes - bring up the serdes
2379 * @ppd: physical port on the qlogic_ib device
2381 static int qib_7322_bringup_serdes(struct qib_pportdata *ppd)
2383 struct qib_devdata *dd = ppd->dd;
2385 unsigned long flags;
2389 * SerDes model not in Pd, but still need to
2390 * set up much of IBCCtrl and IBCDDRCtrl; move elsewhere
2393 /* Put IBC in reset, sends disabled (should be in reset already) */
2394 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn);
2395 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
2396 qib_write_kreg(dd, kr_scratch, 0ULL);
2398 if (qib_compat_ddr_negotiate) {
2399 ppd->cpspec->ibdeltainprog = 1;
2400 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd,
2402 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd,
2403 crp_iblinkerrrecov);
2406 /* flowcontrolwatermark is in units of KBytes */
2407 ibc = 0x5ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlWaterMark);
2409 * Flow control is sent this often, even if no changes in
2410 * buffer space occur. Units are 128ns for this chip.
2413 ibc |= 24ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlPeriod);
2414 /* max error tolerance */
2415 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, PhyerrThreshold);
2416 /* IB credit flow control. */
2417 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, OverrunThreshold);
2419 * set initial max size pkt IBC will send, including ICRC; it's the
2420 * PIO buffer size in dwords, less 1; also see qib_set_mtu()
2422 ibc |= ((u64)(ppd->ibmaxlen >> 2) + 1) <<
2423 SYM_LSB(IBCCtrlA_0, MaxPktLen);
2424 ppd->cpspec->ibcctrl_a = ibc; /* without linkcmd or linkinitcmd! */
2427 * Reset the PCS interface to the serdes (and also ibc, which is still
2428 * in reset from above). Writes new value of ibcctrl_a as last step.
2430 qib_7322_mini_pcs_reset(ppd);
2432 if (!ppd->cpspec->ibcctrl_b) {
2433 unsigned lse = ppd->link_speed_enabled;
2436 * Not on re-init after reset, establish shadow
2437 * and force initial config.
2439 ppd->cpspec->ibcctrl_b = qib_read_kreg_port(ppd,
2441 ppd->cpspec->ibcctrl_b &= ~(IBA7322_IBC_SPEED_QDR |
2442 IBA7322_IBC_SPEED_DDR |
2443 IBA7322_IBC_SPEED_SDR |
2444 IBA7322_IBC_WIDTH_AUTONEG |
2445 SYM_MASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED));
2446 if (lse & (lse - 1)) /* Muliple speeds enabled */
2447 ppd->cpspec->ibcctrl_b |=
2448 (lse << IBA7322_IBC_SPEED_LSB) |
2449 IBA7322_IBC_IBTA_1_2_MASK |
2450 IBA7322_IBC_MAX_SPEED_MASK;
2452 ppd->cpspec->ibcctrl_b |= (lse == QIB_IB_QDR) ?
2453 IBA7322_IBC_SPEED_QDR |
2454 IBA7322_IBC_IBTA_1_2_MASK :
2455 (lse == QIB_IB_DDR) ?
2456 IBA7322_IBC_SPEED_DDR :
2457 IBA7322_IBC_SPEED_SDR;
2458 if ((ppd->link_width_enabled & (IB_WIDTH_1X | IB_WIDTH_4X)) ==
2459 (IB_WIDTH_1X | IB_WIDTH_4X))
2460 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_WIDTH_AUTONEG;
2462 ppd->cpspec->ibcctrl_b |=
2463 ppd->link_width_enabled == IB_WIDTH_4X ?
2464 IBA7322_IBC_WIDTH_4X_ONLY :
2465 IBA7322_IBC_WIDTH_1X_ONLY;
2467 /* always enable these on driver reload, not sticky */
2468 ppd->cpspec->ibcctrl_b |= (IBA7322_IBC_RXPOL_MASK |
2469 IBA7322_IBC_HRTBT_MASK);
2471 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
2473 /* setup so we have more time at CFGTEST to change H1 */
2474 val = qib_read_kreg_port(ppd, krp_ibcctrl_c);
2475 val &= ~SYM_MASK(IBCCtrlC_0, IB_FRONT_PORCH);
2476 val |= 0xfULL << SYM_LSB(IBCCtrlC_0, IB_FRONT_PORCH);
2477 qib_write_kreg_port(ppd, krp_ibcctrl_c, val);
2479 serdes_7322_init(ppd);
2481 guid = be64_to_cpu(ppd->guid);
2484 guid = be64_to_cpu(dd->base_guid) + ppd->port - 1;
2485 ppd->guid = cpu_to_be64(guid);
2488 qib_write_kreg_port(ppd, krp_hrtbt_guid, guid);
2489 /* write to chip to prevent back-to-back writes of ibc reg */
2490 qib_write_kreg(dd, kr_scratch, 0);
2493 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0, IBLinkEn);
2496 /* initially come up DISABLED, without sending anything. */
2497 val = ppd->cpspec->ibcctrl_a | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE <<
2498 QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
2499 qib_write_kreg_port(ppd, krp_ibcctrl_a, val);
2500 qib_write_kreg(dd, kr_scratch, 0ULL);
2501 /* clear the linkinit cmds */
2502 ppd->cpspec->ibcctrl_a = val & ~SYM_MASK(IBCCtrlA_0, LinkInitCmd);
2504 /* be paranoid against later code motion, etc. */
2505 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
2506 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvIBPortEnable);
2507 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl);
2508 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
2510 /* Also enable IBSTATUSCHG interrupt. */
2511 val = qib_read_kreg_port(ppd, krp_errmask);
2512 qib_write_kreg_port(ppd, krp_errmask,
2513 val | ERR_MASK_N(IBStatusChanged));
2515 /* Always zero until we start messing with SerDes for real */
2520 * qib_7322_quiet_serdes - set serdes to txidle
2521 * @dd: the qlogic_ib device
2522 * Called when driver is being unloaded
2524 static void qib_7322_mini_quiet_serdes(struct qib_pportdata *ppd)
2527 unsigned long flags;
2529 qib_set_ib_7322_lstate(ppd, 0, QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
2531 spin_lock_irqsave(&ppd->lflags_lock, flags);
2532 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
2533 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2534 wake_up(&ppd->cpspec->autoneg_wait);
2535 cancel_delayed_work_sync(&ppd->cpspec->autoneg_work);
2536 if (ppd->dd->cspec->r1)
2537 cancel_delayed_work_sync(&ppd->cpspec->ipg_work);
2539 ppd->cpspec->chase_end = 0;
2540 if (ppd->cpspec->chase_timer.data) /* if initted */
2541 del_timer_sync(&ppd->cpspec->chase_timer);
2544 * Despite the name, actually disables IBC as well. Do it when
2545 * we are as sure as possible that no more packets can be
2546 * received, following the down and the PCS reset.
2547 * The actual disabling happens in qib_7322_mini_pci_reset(),
2548 * along with the PCS being reset.
2550 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn);
2551 qib_7322_mini_pcs_reset(ppd);
2554 * Update the adjusted counters so the adjustment persists
2555 * across driver reload.
2557 if (ppd->cpspec->ibsymdelta || ppd->cpspec->iblnkerrdelta ||
2558 ppd->cpspec->ibdeltainprog || ppd->cpspec->iblnkdowndelta) {
2559 struct qib_devdata *dd = ppd->dd;
2562 /* enable counter writes */
2563 diagc = qib_read_kreg64(dd, kr_hwdiagctrl);
2564 qib_write_kreg(dd, kr_hwdiagctrl,
2565 diagc | SYM_MASK(HwDiagCtrl, CounterWrEnable));
2567 if (ppd->cpspec->ibsymdelta || ppd->cpspec->ibdeltainprog) {
2568 val = read_7322_creg32_port(ppd, crp_ibsymbolerr);
2569 if (ppd->cpspec->ibdeltainprog)
2570 val -= val - ppd->cpspec->ibsymsnap;
2571 val -= ppd->cpspec->ibsymdelta;
2572 write_7322_creg_port(ppd, crp_ibsymbolerr, val);
2574 if (ppd->cpspec->iblnkerrdelta || ppd->cpspec->ibdeltainprog) {
2575 val = read_7322_creg32_port(ppd, crp_iblinkerrrecov);
2576 if (ppd->cpspec->ibdeltainprog)
2577 val -= val - ppd->cpspec->iblnkerrsnap;
2578 val -= ppd->cpspec->iblnkerrdelta;
2579 write_7322_creg_port(ppd, crp_iblinkerrrecov, val);
2581 if (ppd->cpspec->iblnkdowndelta) {
2582 val = read_7322_creg32_port(ppd, crp_iblinkdown);
2583 val += ppd->cpspec->iblnkdowndelta;
2584 write_7322_creg_port(ppd, crp_iblinkdown, val);
2587 * No need to save ibmalfdelta since IB perfcounters
2588 * are cleared on driver reload.
2591 /* and disable counter writes */
2592 qib_write_kreg(dd, kr_hwdiagctrl, diagc);
2597 * qib_setup_7322_setextled - set the state of the two external LEDs
2598 * @ppd: physical port on the qlogic_ib device
2599 * @on: whether the link is up or not
2601 * The exact combo of LEDs if on is true is determined by looking
2604 * These LEDs indicate the physical and logical state of IB link.
2605 * For this chip (at least with recommended board pinouts), LED1
2606 * is Yellow (logical state) and LED2 is Green (physical state),
2608 * Note: We try to match the Mellanox HCA LED behavior as best
2609 * we can. Green indicates physical link state is OK (something is
2610 * plugged in, and we can train).
2611 * Amber indicates the link is logically up (ACTIVE).
2612 * Mellanox further blinks the amber LED to indicate data packet
2613 * activity, but we have no hardware support for that, so it would
2614 * require waking up every 10-20 msecs and checking the counters
2615 * on the chip, and then turning the LED off if appropriate. That's
2616 * visible overhead, so not something we will do.
2618 static void qib_setup_7322_setextled(struct qib_pportdata *ppd, u32 on)
2620 struct qib_devdata *dd = ppd->dd;
2621 u64 extctl, ledblink = 0, val;
2622 unsigned long flags;
2626 * The diags use the LED to indicate diag info, so we leave
2627 * the external LED alone when the diags are running.
2629 if (dd->diag_client)
2632 /* Allow override of LED display for, e.g. Locating system in rack */
2633 if (ppd->led_override) {
2634 grn = (ppd->led_override & QIB_LED_PHYS);
2635 yel = (ppd->led_override & QIB_LED_LOG);
2637 val = qib_read_kreg_port(ppd, krp_ibcstatus_a);
2638 grn = qib_7322_phys_portstate(val) ==
2639 IB_PHYSPORTSTATE_LINKUP;
2640 yel = qib_7322_iblink_state(val) == IB_PORT_ACTIVE;
2646 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2647 extctl = dd->cspec->extctrl & (ppd->port == 1 ?
2648 ~ExtLED_IB1_MASK : ~ExtLED_IB2_MASK);
2650 extctl |= ppd->port == 1 ? ExtLED_IB1_GRN : ExtLED_IB2_GRN;
2652 * Counts are in chip clock (4ns) periods.
2653 * This is 1/16 sec (66.6ms) on,
2654 * 3/16 sec (187.5 ms) off, with packets rcvd.
2656 ledblink = ((66600 * 1000UL / 4) << IBA7322_LEDBLINK_ON_SHIFT) |
2657 ((187500 * 1000UL / 4) << IBA7322_LEDBLINK_OFF_SHIFT);
2660 extctl |= ppd->port == 1 ? ExtLED_IB1_YEL : ExtLED_IB2_YEL;
2661 dd->cspec->extctrl = extctl;
2662 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
2663 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2665 if (ledblink) /* blink the LED on packet receive */
2666 qib_write_kreg_port(ppd, krp_rcvpktledcnt, ledblink);
2669 #ifdef CONFIG_INFINIBAND_QIB_DCA
2671 static int qib_7322_notify_dca(struct qib_devdata *dd, unsigned long event)
2674 case DCA_PROVIDER_ADD:
2675 if (dd->flags & QIB_DCA_ENABLED)
2677 if (!dca_add_requester(&dd->pcidev->dev)) {
2678 qib_devinfo(dd->pcidev, "DCA enabled\n");
2679 dd->flags |= QIB_DCA_ENABLED;
2683 case DCA_PROVIDER_REMOVE:
2684 if (dd->flags & QIB_DCA_ENABLED) {
2685 dca_remove_requester(&dd->pcidev->dev);
2686 dd->flags &= ~QIB_DCA_ENABLED;
2687 dd->cspec->dca_ctrl = 0;
2688 qib_write_kreg(dd, KREG_IDX(DCACtrlA),
2689 dd->cspec->dca_ctrl);
2696 static void qib_update_rhdrq_dca(struct qib_ctxtdata *rcd, int cpu)
2698 struct qib_devdata *dd = rcd->dd;
2699 struct qib_chip_specific *cspec = dd->cspec;
2701 if (!(dd->flags & QIB_DCA_ENABLED))
2703 if (cspec->rhdr_cpu[rcd->ctxt] != cpu) {
2704 const struct dca_reg_map *rmp;
2706 cspec->rhdr_cpu[rcd->ctxt] = cpu;
2707 rmp = &dca_rcvhdr_reg_map[rcd->ctxt];
2708 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx] &= rmp->mask;
2709 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx] |=
2710 (u64) dca3_get_tag(&dd->pcidev->dev, cpu) << rmp->lsb;
2711 qib_devinfo(dd->pcidev,
2712 "Ctxt %d cpu %d dca %llx\n", rcd->ctxt, cpu,
2713 (long long) cspec->dca_rcvhdr_ctrl[rmp->shadow_inx]);
2714 qib_write_kreg(dd, rmp->regno,
2715 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx]);
2716 cspec->dca_ctrl |= SYM_MASK(DCACtrlA, RcvHdrqDCAEnable);
2717 qib_write_kreg(dd, KREG_IDX(DCACtrlA), cspec->dca_ctrl);
2721 static void qib_update_sdma_dca(struct qib_pportdata *ppd, int cpu)
2723 struct qib_devdata *dd = ppd->dd;
2724 struct qib_chip_specific *cspec = dd->cspec;
2725 unsigned pidx = ppd->port - 1;
2727 if (!(dd->flags & QIB_DCA_ENABLED))
2729 if (cspec->sdma_cpu[pidx] != cpu) {
2730 cspec->sdma_cpu[pidx] = cpu;
2731 cspec->dca_rcvhdr_ctrl[4] &= ~(ppd->hw_pidx ?
2732 SYM_MASK(DCACtrlF, SendDma1DCAOPH) :
2733 SYM_MASK(DCACtrlF, SendDma0DCAOPH));
2734 cspec->dca_rcvhdr_ctrl[4] |=
2735 (u64) dca3_get_tag(&dd->pcidev->dev, cpu) <<
2737 SYM_LSB(DCACtrlF, SendDma1DCAOPH) :
2738 SYM_LSB(DCACtrlF, SendDma0DCAOPH));
2739 qib_devinfo(dd->pcidev,
2740 "sdma %d cpu %d dca %llx\n", ppd->hw_pidx, cpu,
2741 (long long) cspec->dca_rcvhdr_ctrl[4]);
2742 qib_write_kreg(dd, KREG_IDX(DCACtrlF),
2743 cspec->dca_rcvhdr_ctrl[4]);
2744 cspec->dca_ctrl |= ppd->hw_pidx ?
2745 SYM_MASK(DCACtrlA, SendDMAHead1DCAEnable) :
2746 SYM_MASK(DCACtrlA, SendDMAHead0DCAEnable);
2747 qib_write_kreg(dd, KREG_IDX(DCACtrlA), cspec->dca_ctrl);
2751 static void qib_setup_dca(struct qib_devdata *dd)
2753 struct qib_chip_specific *cspec = dd->cspec;
2756 for (i = 0; i < ARRAY_SIZE(cspec->rhdr_cpu); i++)
2757 cspec->rhdr_cpu[i] = -1;
2758 for (i = 0; i < ARRAY_SIZE(cspec->sdma_cpu); i++)
2759 cspec->sdma_cpu[i] = -1;
2760 cspec->dca_rcvhdr_ctrl[0] =
2761 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq0DCAXfrCnt)) |
2762 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq1DCAXfrCnt)) |
2763 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq2DCAXfrCnt)) |
2764 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq3DCAXfrCnt));
2765 cspec->dca_rcvhdr_ctrl[1] =
2766 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq4DCAXfrCnt)) |
2767 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq5DCAXfrCnt)) |
2768 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq6DCAXfrCnt)) |
2769 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq7DCAXfrCnt));
2770 cspec->dca_rcvhdr_ctrl[2] =
2771 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq8DCAXfrCnt)) |
2772 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq9DCAXfrCnt)) |
2773 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq10DCAXfrCnt)) |
2774 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq11DCAXfrCnt));
2775 cspec->dca_rcvhdr_ctrl[3] =
2776 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq12DCAXfrCnt)) |
2777 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq13DCAXfrCnt)) |
2778 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq14DCAXfrCnt)) |
2779 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq15DCAXfrCnt));
2780 cspec->dca_rcvhdr_ctrl[4] =
2781 (1ULL << SYM_LSB(DCACtrlF, RcvHdrq16DCAXfrCnt)) |
2782 (1ULL << SYM_LSB(DCACtrlF, RcvHdrq17DCAXfrCnt));
2783 for (i = 0; i < ARRAY_SIZE(cspec->sdma_cpu); i++)
2784 qib_write_kreg(dd, KREG_IDX(DCACtrlB) + i,
2785 cspec->dca_rcvhdr_ctrl[i]);
2786 for (i = 0; i < cspec->num_msix_entries; i++)
2787 setup_dca_notifier(dd, &cspec->msix_entries[i]);
2790 static void qib_irq_notifier_notify(struct irq_affinity_notify *notify,
2791 const cpumask_t *mask)
2793 struct qib_irq_notify *n =
2794 container_of(notify, struct qib_irq_notify, notify);
2795 int cpu = cpumask_first(mask);
2798 struct qib_ctxtdata *rcd = (struct qib_ctxtdata *)n->arg;
2799 qib_update_rhdrq_dca(rcd, cpu);
2801 struct qib_pportdata *ppd = (struct qib_pportdata *)n->arg;
2802 qib_update_sdma_dca(ppd, cpu);
2806 static void qib_irq_notifier_release(struct kref *ref)
2808 struct qib_irq_notify *n =
2809 container_of(ref, struct qib_irq_notify, notify.kref);
2810 struct qib_devdata *dd;
2813 struct qib_ctxtdata *rcd = (struct qib_ctxtdata *)n->arg;
2816 struct qib_pportdata *ppd = (struct qib_pportdata *)n->arg;
2819 qib_devinfo(dd->pcidev,
2820 "release on HCA notify 0x%p n 0x%p\n", ref, n);
2826 * Disable MSIx interrupt if enabled, call generic MSIx code
2827 * to cleanup, and clear pending MSIx interrupts.
2828 * Used for fallback to INTx, after reset, and when MSIx setup fails.
2830 static void qib_7322_nomsix(struct qib_devdata *dd)
2835 dd->cspec->main_int_mask = ~0ULL;
2836 n = dd->cspec->num_msix_entries;
2840 dd->cspec->num_msix_entries = 0;
2841 for (i = 0; i < n; i++) {
2842 #ifdef CONFIG_INFINIBAND_QIB_DCA
2843 reset_dca_notifier(dd, &dd->cspec->msix_entries[i]);
2845 irq_set_affinity_hint(
2846 dd->cspec->msix_entries[i].msix.vector, NULL);
2847 free_cpumask_var(dd->cspec->msix_entries[i].mask);
2848 free_irq(dd->cspec->msix_entries[i].msix.vector,
2849 dd->cspec->msix_entries[i].arg);
2853 /* make sure no MSIx interrupts are left pending */
2854 intgranted = qib_read_kreg64(dd, kr_intgranted);
2856 qib_write_kreg(dd, kr_intgranted, intgranted);
2859 static void qib_7322_free_irq(struct qib_devdata *dd)
2861 if (dd->cspec->irq) {
2862 free_irq(dd->cspec->irq, dd);
2865 qib_7322_nomsix(dd);
2868 static void qib_setup_7322_cleanup(struct qib_devdata *dd)
2872 #ifdef CONFIG_INFINIBAND_QIB_DCA
2873 if (dd->flags & QIB_DCA_ENABLED) {
2874 dca_remove_requester(&dd->pcidev->dev);
2875 dd->flags &= ~QIB_DCA_ENABLED;
2876 dd->cspec->dca_ctrl = 0;
2877 qib_write_kreg(dd, KREG_IDX(DCACtrlA), dd->cspec->dca_ctrl);
2881 qib_7322_free_irq(dd);
2882 kfree(dd->cspec->cntrs);
2883 kfree(dd->cspec->sendchkenable);
2884 kfree(dd->cspec->sendgrhchk);
2885 kfree(dd->cspec->sendibchk);
2886 kfree(dd->cspec->msix_entries);
2887 for (i = 0; i < dd->num_pports; i++) {
2888 unsigned long flags;
2889 u32 mask = QSFP_GPIO_MOD_PRS_N |
2890 (QSFP_GPIO_MOD_PRS_N << QSFP_GPIO_PORT2_SHIFT);
2892 kfree(dd->pport[i].cpspec->portcntrs);
2893 if (dd->flags & QIB_HAS_QSFP) {
2894 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2895 dd->cspec->gpio_mask &= ~mask;
2896 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
2897 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2898 qib_qsfp_deinit(&dd->pport[i].cpspec->qsfp_data);
2900 if (dd->pport[i].ibport_data.smi_ah)
2901 ib_destroy_ah(&dd->pport[i].ibport_data.smi_ah->ibah);
2905 /* handle SDMA interrupts */
2906 static void sdma_7322_intr(struct qib_devdata *dd, u64 istat)
2908 struct qib_pportdata *ppd0 = &dd->pport[0];
2909 struct qib_pportdata *ppd1 = &dd->pport[1];
2910 u64 intr0 = istat & (INT_MASK_P(SDma, 0) |
2911 INT_MASK_P(SDmaIdle, 0) | INT_MASK_P(SDmaProgress, 0));
2912 u64 intr1 = istat & (INT_MASK_P(SDma, 1) |
2913 INT_MASK_P(SDmaIdle, 1) | INT_MASK_P(SDmaProgress, 1));
2916 qib_sdma_intr(ppd0);
2918 qib_sdma_intr(ppd1);
2920 if (istat & INT_MASK_PM(SDmaCleanupDone, 0))
2921 qib_sdma_process_event(ppd0, qib_sdma_event_e20_hw_started);
2922 if (istat & INT_MASK_PM(SDmaCleanupDone, 1))
2923 qib_sdma_process_event(ppd1, qib_sdma_event_e20_hw_started);
2927 * Set or clear the Send buffer available interrupt enable bit.
2929 static void qib_wantpiobuf_7322_intr(struct qib_devdata *dd, u32 needint)
2931 unsigned long flags;
2933 spin_lock_irqsave(&dd->sendctrl_lock, flags);
2935 dd->sendctrl |= SYM_MASK(SendCtrl, SendIntBufAvail);
2937 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendIntBufAvail);
2938 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
2939 qib_write_kreg(dd, kr_scratch, 0ULL);
2940 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
2944 * Somehow got an interrupt with reserved bits set in interrupt status.
2945 * Print a message so we know it happened, then clear them.
2946 * keep mainline interrupt handler cache-friendly
2948 static noinline void unknown_7322_ibits(struct qib_devdata *dd, u64 istat)
2953 kills = istat & ~QIB_I_BITSEXTANT;
2955 "Clearing reserved interrupt(s) 0x%016llx: %s\n",
2956 (unsigned long long) kills, msg);
2957 qib_write_kreg(dd, kr_intmask, (dd->cspec->int_enable_mask & ~kills));
2960 /* keep mainline interrupt handler cache-friendly */
2961 static noinline void unknown_7322_gpio_intr(struct qib_devdata *dd)
2968 * Boards for this chip currently don't use GPIO interrupts,
2969 * so clear by writing GPIOstatus to GPIOclear, and complain
2970 * to developer. To avoid endless repeats, clear
2971 * the bits in the mask, since there is some kind of
2972 * programming error or chip problem.
2974 gpiostatus = qib_read_kreg32(dd, kr_gpio_status);
2976 * In theory, writing GPIOstatus to GPIOclear could
2977 * have a bad side-effect on some diagnostic that wanted
2978 * to poll for a status-change, but the various shadows
2979 * make that problematic at best. Diags will just suppress
2980 * all GPIO interrupts during such tests.
2982 qib_write_kreg(dd, kr_gpio_clear, gpiostatus);
2984 * Check for QSFP MOD_PRS changes
2985 * only works for single port if IB1 != pidx1
2987 for (pidx = 0; pidx < dd->num_pports && (dd->flags & QIB_HAS_QSFP);
2989 struct qib_pportdata *ppd;
2990 struct qib_qsfp_data *qd;
2992 if (!dd->pport[pidx].link_speed_supported)
2994 mask = QSFP_GPIO_MOD_PRS_N;
2995 ppd = dd->pport + pidx;
2996 mask <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx);
2997 if (gpiostatus & dd->cspec->gpio_mask & mask) {
2999 qd = &ppd->cpspec->qsfp_data;
3000 gpiostatus &= ~mask;
3001 pins = qib_read_kreg64(dd, kr_extstatus);
3002 pins >>= SYM_LSB(EXTStatus, GPIOIn);
3003 if (!(pins & mask)) {
3005 qd->t_insert = jiffies;
3006 queue_work(ib_wq, &qd->work);
3011 if (gpiostatus && !handled) {
3012 const u32 mask = qib_read_kreg32(dd, kr_gpio_mask);
3013 u32 gpio_irq = mask & gpiostatus;
3016 * Clear any troublemakers, and update chip from shadow
3018 dd->cspec->gpio_mask &= ~gpio_irq;
3019 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
3024 * Handle errors and unusual events first, separate function
3025 * to improve cache hits for fast path interrupt handling.
3027 static noinline void unlikely_7322_intr(struct qib_devdata *dd, u64 istat)
3029 if (istat & ~QIB_I_BITSEXTANT)
3030 unknown_7322_ibits(dd, istat);
3031 if (istat & QIB_I_GPIO)
3032 unknown_7322_gpio_intr(dd);
3033 if (istat & QIB_I_C_ERROR) {
3034 qib_write_kreg(dd, kr_errmask, 0ULL);
3035 tasklet_schedule(&dd->error_tasklet);
3037 if (istat & INT_MASK_P(Err, 0) && dd->rcd[0])
3038 handle_7322_p_errors(dd->rcd[0]->ppd);
3039 if (istat & INT_MASK_P(Err, 1) && dd->rcd[1])
3040 handle_7322_p_errors(dd->rcd[1]->ppd);
3044 * Dynamically adjust the rcv int timeout for a context based on incoming
3047 static void adjust_rcv_timeout(struct qib_ctxtdata *rcd, int npkts)
3049 struct qib_devdata *dd = rcd->dd;
3050 u32 timeout = dd->cspec->rcvavail_timeout[rcd->ctxt];
3053 * Dynamically adjust idle timeout on chip
3054 * based on number of packets processed.
3056 if (npkts < rcv_int_count && timeout > 2)
3058 else if (npkts >= rcv_int_count && timeout < rcv_int_timeout)
3059 timeout = min(timeout << 1, rcv_int_timeout);
3063 dd->cspec->rcvavail_timeout[rcd->ctxt] = timeout;
3064 qib_write_kreg(dd, kr_rcvavailtimeout + rcd->ctxt, timeout);
3068 * This is the main interrupt handler.
3069 * It will normally only be used for low frequency interrupts but may
3070 * have to handle all interrupts if INTx is enabled or fewer than normal
3071 * MSIx interrupts were allocated.
3072 * This routine should ignore the interrupt bits for any of the
3073 * dedicated MSIx handlers.
3075 static irqreturn_t qib_7322intr(int irq, void *data)
3077 struct qib_devdata *dd = data;
3085 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) {
3087 * This return value is not great, but we do not want the
3088 * interrupt core code to remove our interrupt handler
3089 * because we don't appear to be handling an interrupt
3090 * during a chip reset.
3096 istat = qib_read_kreg64(dd, kr_intstatus);
3098 if (unlikely(istat == ~0ULL)) {
3099 qib_bad_intrstatus(dd);
3100 qib_dev_err(dd, "Interrupt status all f's, skipping\n");
3101 /* don't know if it was our interrupt or not */
3106 istat &= dd->cspec->main_int_mask;
3107 if (unlikely(!istat)) {
3108 /* already handled, or shared and not us */
3113 qib_stats.sps_ints++;
3114 if (dd->int_counter != (u32) -1)
3117 /* handle "errors" of various kinds first, device ahead of port */
3118 if (unlikely(istat & (~QIB_I_BITSEXTANT | QIB_I_GPIO |
3119 QIB_I_C_ERROR | INT_MASK_P(Err, 0) |
3120 INT_MASK_P(Err, 1))))
3121 unlikely_7322_intr(dd, istat);
3124 * Clear the interrupt bits we found set, relatively early, so we
3125 * "know" know the chip will have seen this by the time we process
3126 * the queue, and will re-interrupt if necessary. The processor
3127 * itself won't take the interrupt again until we return.
3129 qib_write_kreg(dd, kr_intclear, istat);
3132 * Handle kernel receive queues before checking for pio buffers
3133 * available since receives can overflow; piobuf waiters can afford
3134 * a few extra cycles, since they were waiting anyway.
3136 ctxtrbits = istat & (QIB_I_RCVAVAIL_MASK | QIB_I_RCVURG_MASK);
3138 rmask = (1ULL << QIB_I_RCVAVAIL_LSB) |
3139 (1ULL << QIB_I_RCVURG_LSB);
3140 for (i = 0; i < dd->first_user_ctxt; i++) {
3141 if (ctxtrbits & rmask) {
3142 ctxtrbits &= ~rmask;
3144 qib_kreceive(dd->rcd[i], NULL, &npkts);
3149 ctxtrbits = (ctxtrbits >> QIB_I_RCVAVAIL_LSB) |
3150 (ctxtrbits >> QIB_I_RCVURG_LSB);
3151 qib_handle_urcv(dd, ctxtrbits);
3155 if (istat & (QIB_I_P_SDMAINT(0) | QIB_I_P_SDMAINT(1)))
3156 sdma_7322_intr(dd, istat);
3158 if ((istat & QIB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED))
3159 qib_ib_piobufavail(dd);
3167 * Dedicated receive packet available interrupt handler.
3169 static irqreturn_t qib_7322pintr(int irq, void *data)
3171 struct qib_ctxtdata *rcd = data;
3172 struct qib_devdata *dd = rcd->dd;
3175 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3177 * This return value is not great, but we do not want the
3178 * interrupt core code to remove our interrupt handler
3179 * because we don't appear to be handling an interrupt
3180 * during a chip reset.
3184 qib_stats.sps_ints++;
3185 if (dd->int_counter != (u32) -1)
3188 /* Clear the interrupt bit we expect to be set. */
3189 qib_write_kreg(dd, kr_intclear, ((1ULL << QIB_I_RCVAVAIL_LSB) |
3190 (1ULL << QIB_I_RCVURG_LSB)) << rcd->ctxt);
3192 qib_kreceive(rcd, NULL, &npkts);
3198 * Dedicated Send buffer available interrupt handler.
3200 static irqreturn_t qib_7322bufavail(int irq, void *data)
3202 struct qib_devdata *dd = data;
3204 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3206 * This return value is not great, but we do not want the
3207 * interrupt core code to remove our interrupt handler
3208 * because we don't appear to be handling an interrupt
3209 * during a chip reset.
3213 qib_stats.sps_ints++;
3214 if (dd->int_counter != (u32) -1)
3217 /* Clear the interrupt bit we expect to be set. */
3218 qib_write_kreg(dd, kr_intclear, QIB_I_SPIOBUFAVAIL);
3220 /* qib_ib_piobufavail() will clear the want PIO interrupt if needed */
3221 if (dd->flags & QIB_INITTED)
3222 qib_ib_piobufavail(dd);
3224 qib_wantpiobuf_7322_intr(dd, 0);
3230 * Dedicated Send DMA interrupt handler.
3232 static irqreturn_t sdma_intr(int irq, void *data)
3234 struct qib_pportdata *ppd = data;
3235 struct qib_devdata *dd = ppd->dd;
3237 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3239 * This return value is not great, but we do not want the
3240 * interrupt core code to remove our interrupt handler
3241 * because we don't appear to be handling an interrupt
3242 * during a chip reset.
3246 qib_stats.sps_ints++;
3247 if (dd->int_counter != (u32) -1)
3250 /* Clear the interrupt bit we expect to be set. */
3251 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3252 INT_MASK_P(SDma, 1) : INT_MASK_P(SDma, 0));
3259 * Dedicated Send DMA idle interrupt handler.
3261 static irqreturn_t sdma_idle_intr(int irq, void *data)
3263 struct qib_pportdata *ppd = data;
3264 struct qib_devdata *dd = ppd->dd;
3266 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3268 * This return value is not great, but we do not want the
3269 * interrupt core code to remove our interrupt handler
3270 * because we don't appear to be handling an interrupt
3271 * during a chip reset.
3275 qib_stats.sps_ints++;
3276 if (dd->int_counter != (u32) -1)
3279 /* Clear the interrupt bit we expect to be set. */
3280 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3281 INT_MASK_P(SDmaIdle, 1) : INT_MASK_P(SDmaIdle, 0));
3288 * Dedicated Send DMA progress interrupt handler.
3290 static irqreturn_t sdma_progress_intr(int irq, void *data)
3292 struct qib_pportdata *ppd = data;
3293 struct qib_devdata *dd = ppd->dd;
3295 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3297 * This return value is not great, but we do not want the
3298 * interrupt core code to remove our interrupt handler
3299 * because we don't appear to be handling an interrupt
3300 * during a chip reset.
3304 qib_stats.sps_ints++;
3305 if (dd->int_counter != (u32) -1)
3308 /* Clear the interrupt bit we expect to be set. */
3309 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3310 INT_MASK_P(SDmaProgress, 1) :
3311 INT_MASK_P(SDmaProgress, 0));
3318 * Dedicated Send DMA cleanup interrupt handler.
3320 static irqreturn_t sdma_cleanup_intr(int irq, void *data)
3322 struct qib_pportdata *ppd = data;
3323 struct qib_devdata *dd = ppd->dd;
3325 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3327 * This return value is not great, but we do not want the
3328 * interrupt core code to remove our interrupt handler
3329 * because we don't appear to be handling an interrupt
3330 * during a chip reset.
3334 qib_stats.sps_ints++;
3335 if (dd->int_counter != (u32) -1)
3338 /* Clear the interrupt bit we expect to be set. */
3339 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3340 INT_MASK_PM(SDmaCleanupDone, 1) :
3341 INT_MASK_PM(SDmaCleanupDone, 0));
3342 qib_sdma_process_event(ppd, qib_sdma_event_e20_hw_started);
3347 #ifdef CONFIG_INFINIBAND_QIB_DCA
3349 static void reset_dca_notifier(struct qib_devdata *dd, struct qib_msix_entry *m)
3353 qib_devinfo(dd->pcidev,
3354 "Disabling notifier on HCA %d irq %d\n",
3357 irq_set_affinity_notifier(
3363 static void setup_dca_notifier(struct qib_devdata *dd, struct qib_msix_entry *m)
3365 struct qib_irq_notify *n;
3369 n = kzalloc(sizeof(*n), GFP_KERNEL);
3374 n->notify.irq = m->msix.vector;
3375 n->notify.notify = qib_irq_notifier_notify;
3376 n->notify.release = qib_irq_notifier_release;
3379 qib_devinfo(dd->pcidev,
3380 "set notifier irq %d rcv %d notify %p\n",
3381 n->notify.irq, n->rcv, &n->notify);
3382 ret = irq_set_affinity_notifier(
3395 * Set up our chip-specific interrupt handler.
3396 * The interrupt type has already been setup, so
3397 * we just need to do the registration and error checking.
3398 * If we are using MSIx interrupts, we may fall back to
3399 * INTx later, if the interrupt handler doesn't get called
3400 * within 1/2 second (see verify_interrupt()).
3402 static void qib_setup_7322_interrupt(struct qib_devdata *dd, int clearpend)
3404 int ret, i, msixnum;
3407 const struct cpumask *local_mask;
3408 int firstcpu, secondcpu = 0, currrcvcpu = 0;
3410 if (!dd->num_pports)
3415 * if not switching interrupt types, be sure interrupts are
3416 * disabled, and then clear anything pending at this point,
3417 * because we are starting clean.
3419 qib_7322_set_intr_state(dd, 0);
3421 /* clear the reset error, init error/hwerror mask */
3422 qib_7322_init_hwerrors(dd);
3424 /* clear any interrupt bits that might be set */
3425 qib_write_kreg(dd, kr_intclear, ~0ULL);
3427 /* make sure no pending MSIx intr, and clear diag reg */
3428 qib_write_kreg(dd, kr_intgranted, ~0ULL);
3429 qib_write_kreg(dd, kr_vecclr_wo_int, ~0ULL);
3432 if (!dd->cspec->num_msix_entries) {
3433 /* Try to get INTx interrupt */
3435 if (!dd->pcidev->irq) {
3437 "irq is 0, BIOS error? Interrupts won't work\n");
3440 ret = request_irq(dd->pcidev->irq, qib_7322intr,
3441 IRQF_SHARED, QIB_DRV_NAME, dd);
3444 "Couldn't setup INTx interrupt (irq=%d): %d\n",
3445 dd->pcidev->irq, ret);
3448 dd->cspec->irq = dd->pcidev->irq;
3449 dd->cspec->main_int_mask = ~0ULL;
3453 /* Try to get MSIx interrupts */
3454 memset(redirect, 0, sizeof redirect);
3457 local_mask = cpumask_of_pcibus(dd->pcidev->bus);
3458 firstcpu = cpumask_first(local_mask);
3459 if (firstcpu >= nr_cpu_ids ||
3460 cpumask_weight(local_mask) == num_online_cpus()) {
3461 local_mask = topology_core_cpumask(0);
3462 firstcpu = cpumask_first(local_mask);
3464 if (firstcpu < nr_cpu_ids) {
3465 secondcpu = cpumask_next(firstcpu, local_mask);
3466 if (secondcpu >= nr_cpu_ids)
3467 secondcpu = firstcpu;
3468 currrcvcpu = secondcpu;
3470 for (i = 0; msixnum < dd->cspec->num_msix_entries; i++) {
3471 irq_handler_t handler;
3475 #ifdef CONFIG_INFINIBAND_QIB_DCA
3479 dd->cspec->msix_entries[msixnum].
3480 name[sizeof(dd->cspec->msix_entries[msixnum].name) - 1]
3482 if (i < ARRAY_SIZE(irq_table)) {
3483 if (irq_table[i].port) {
3484 /* skip if for a non-configured port */
3485 if (irq_table[i].port > dd->num_pports)
3487 arg = dd->pport + irq_table[i].port - 1;
3490 #ifdef CONFIG_INFINIBAND_QIB_DCA
3491 dca = irq_table[i].dca;
3493 lsb = irq_table[i].lsb;
3494 handler = irq_table[i].handler;
3495 snprintf(dd->cspec->msix_entries[msixnum].name,
3496 sizeof(dd->cspec->msix_entries[msixnum].name)
3498 QIB_DRV_NAME "%d%s", dd->unit,
3503 ctxt = i - ARRAY_SIZE(irq_table);
3504 /* per krcvq context receive interrupt */
3505 arg = dd->rcd[ctxt];
3508 if (qib_krcvq01_no_msi && ctxt < 2)
3510 #ifdef CONFIG_INFINIBAND_QIB_DCA
3513 lsb = QIB_I_RCVAVAIL_LSB + ctxt;
3514 handler = qib_7322pintr;
3515 snprintf(dd->cspec->msix_entries[msixnum].name,
3516 sizeof(dd->cspec->msix_entries[msixnum].name)
3518 QIB_DRV_NAME "%d (kctx)", dd->unit);
3521 dd->cspec->msix_entries[msixnum].msix.vector,
3522 handler, 0, dd->cspec->msix_entries[msixnum].name,
3526 * Shouldn't happen since the enable said we could
3527 * have as many as we are trying to setup here.
3530 "Couldn't setup MSIx interrupt (vec=%d, irq=%d): %d\n",
3532 dd->cspec->msix_entries[msixnum].msix.vector,
3534 qib_7322_nomsix(dd);
3537 dd->cspec->msix_entries[msixnum].arg = arg;
3538 #ifdef CONFIG_INFINIBAND_QIB_DCA
3539 dd->cspec->msix_entries[msixnum].dca = dca;
3540 dd->cspec->msix_entries[msixnum].rcv =
3541 handler == qib_7322pintr;
3544 reg = lsb / IBA7322_REDIRECT_VEC_PER_REG;
3545 sh = (lsb % IBA7322_REDIRECT_VEC_PER_REG) *
3546 SYM_LSB(IntRedirect0, vec1);
3547 mask &= ~(1ULL << lsb);
3548 redirect[reg] |= ((u64) msixnum) << sh;
3550 val = qib_read_kreg64(dd, 2 * msixnum + 1 +
3551 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3552 if (firstcpu < nr_cpu_ids &&
3554 &dd->cspec->msix_entries[msixnum].mask,
3556 if (handler == qib_7322pintr) {
3557 cpumask_set_cpu(currrcvcpu,
3558 dd->cspec->msix_entries[msixnum].mask);
3559 currrcvcpu = cpumask_next(currrcvcpu,
3561 if (currrcvcpu >= nr_cpu_ids)
3562 currrcvcpu = secondcpu;
3564 cpumask_set_cpu(firstcpu,
3565 dd->cspec->msix_entries[msixnum].mask);
3567 irq_set_affinity_hint(
3568 dd->cspec->msix_entries[msixnum].msix.vector,
3569 dd->cspec->msix_entries[msixnum].mask);
3573 /* Initialize the vector mapping */
3574 for (i = 0; i < ARRAY_SIZE(redirect); i++)
3575 qib_write_kreg(dd, kr_intredirect + i, redirect[i]);
3576 dd->cspec->main_int_mask = mask;
3577 tasklet_init(&dd->error_tasklet, qib_error_tasklet,
3583 * qib_7322_boardname - fill in the board name and note features
3584 * @dd: the qlogic_ib device
3586 * info will be based on the board revision register
3588 static unsigned qib_7322_boardname(struct qib_devdata *dd)
3590 /* Will need enumeration of board-types here */
3592 u32 boardid, namelen;
3593 unsigned features = DUAL_PORT_CAP;
3595 boardid = SYM_FIELD(dd->revision, Revision, BoardID);
3599 n = "InfiniPath_QLE7342_Emulation";
3602 n = "InfiniPath_QLE7340";
3603 dd->flags |= QIB_HAS_QSFP;
3604 features = PORT_SPD_CAP;
3607 n = "InfiniPath_QLE7342";
3608 dd->flags |= QIB_HAS_QSFP;
3611 n = "InfiniPath_QMI7342";
3614 n = "InfiniPath_Unsupported7342";
3615 qib_dev_err(dd, "Unsupported version of QMH7342\n");
3619 n = "InfiniPath_QMH7342";
3623 n = "InfiniPath_QME7342";
3626 n = "InfiniPath_QME7362";
3627 dd->flags |= QIB_HAS_QSFP;
3630 n = "InfiniPath_QLE7342_TEST";
3631 dd->flags |= QIB_HAS_QSFP;
3634 n = "InfiniPath_QLE73xy_UNKNOWN";
3635 qib_dev_err(dd, "Unknown 7322 board type %u\n", boardid);
3638 dd->board_atten = 1; /* index into txdds_Xdr */
3640 namelen = strlen(n) + 1;
3641 dd->boardname = kmalloc(namelen, GFP_KERNEL);
3643 qib_dev_err(dd, "Failed allocation for board name: %s\n", n);
3645 snprintf(dd->boardname, namelen, "%s", n);
3647 snprintf(dd->boardversion, sizeof(dd->boardversion),
3648 "ChipABI %u.%u, %s, InfiniPath%u %u.%u, SW Compat %u\n",
3649 QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname,
3650 (unsigned)SYM_FIELD(dd->revision, Revision_R, Arch),
3651 dd->majrev, dd->minrev,
3652 (unsigned)SYM_FIELD(dd->revision, Revision_R, SW));
3654 if (qib_singleport && (features >> PORT_SPD_CAP_SHIFT) & PORT_SPD_CAP) {
3655 qib_devinfo(dd->pcidev,
3656 "IB%u: Forced to single port mode by module parameter\n",
3658 features &= PORT_SPD_CAP;
3665 * This routine sleeps, so it can only be called from user context, not
3666 * from interrupt context.
3668 static int qib_do_7322_reset(struct qib_devdata *dd)
3672 int i, msix_entries, ret = 1;
3674 u8 int_line, clinesz;
3675 unsigned long flags;
3677 /* Use dev_err so it shows up in logs, etc. */
3678 qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit);
3680 qib_pcie_getcmd(dd, &cmdval, &int_line, &clinesz);
3682 msix_entries = dd->cspec->num_msix_entries;
3684 /* no interrupts till re-initted */
3685 qib_7322_set_intr_state(dd, 0);
3688 qib_7322_nomsix(dd);
3689 /* can be up to 512 bytes, too big for stack */
3690 msix_vecsave = kmalloc(2 * dd->cspec->num_msix_entries *
3691 sizeof(u64), GFP_KERNEL);
3693 qib_dev_err(dd, "No mem to save MSIx data\n");
3695 msix_vecsave = NULL;
3698 * Core PCI (as of 2.6.18) doesn't save or rewrite the full vector
3699 * info that is set up by the BIOS, so we have to save and restore
3700 * it ourselves. There is some risk something could change it,
3701 * after we save it, but since we have disabled the MSIx, it
3702 * shouldn't be touched...
3704 for (i = 0; i < msix_entries; i++) {
3705 u64 vecaddr, vecdata;
3706 vecaddr = qib_read_kreg64(dd, 2 * i +
3707 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3708 vecdata = qib_read_kreg64(dd, 1 + 2 * i +
3709 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3711 msix_vecsave[2 * i] = vecaddr;
3712 /* save it without the masked bit set */
3713 msix_vecsave[1 + 2 * i] = vecdata & ~0x100000000ULL;
3717 dd->pport->cpspec->ibdeltainprog = 0;
3718 dd->pport->cpspec->ibsymdelta = 0;
3719 dd->pport->cpspec->iblnkerrdelta = 0;
3720 dd->pport->cpspec->ibmalfdelta = 0;
3721 dd->int_counter = 0; /* so we check interrupts work again */
3724 * Keep chip from being accessed until we are ready. Use
3725 * writeq() directly, to allow the write even though QIB_PRESENT
3728 dd->flags &= ~(QIB_INITTED | QIB_PRESENT | QIB_BADINTR);
3729 dd->flags |= QIB_DOING_RESET;
3730 val = dd->control | QLOGIC_IB_C_RESET;
3731 writeq(val, &dd->kregbase[kr_control]);
3733 for (i = 1; i <= 5; i++) {
3735 * Allow MBIST, etc. to complete; longer on each retry.
3736 * We sometimes get machine checks from bus timeout if no
3737 * response, so for now, make it *really* long.
3739 msleep(1000 + (1 + i) * 3000);
3741 qib_pcie_reenable(dd, cmdval, int_line, clinesz);
3744 * Use readq directly, so we don't need to mark it as PRESENT
3745 * until we get a successful indication that all is well.
3747 val = readq(&dd->kregbase[kr_revision]);
3748 if (val == dd->revision)
3752 "Failed to initialize after reset, unusable\n");
3758 dd->flags |= QIB_PRESENT; /* it's back */
3761 /* restore the MSIx vector address and data if saved above */
3762 for (i = 0; i < msix_entries; i++) {
3763 dd->cspec->msix_entries[i].msix.entry = i;
3764 if (!msix_vecsave || !msix_vecsave[2 * i])
3766 qib_write_kreg(dd, 2 * i +
3767 (QIB_7322_MsixTable_OFFS / sizeof(u64)),
3768 msix_vecsave[2 * i]);
3769 qib_write_kreg(dd, 1 + 2 * i +
3770 (QIB_7322_MsixTable_OFFS / sizeof(u64)),
3771 msix_vecsave[1 + 2 * i]);
3775 /* initialize the remaining registers. */
3776 for (i = 0; i < dd->num_pports; ++i)
3777 write_7322_init_portregs(&dd->pport[i]);
3778 write_7322_initregs(dd);
3780 if (qib_pcie_params(dd, dd->lbus_width,
3781 &dd->cspec->num_msix_entries,
3782 dd->cspec->msix_entries))
3784 "Reset failed to setup PCIe or interrupts; continuing anyway\n");
3786 qib_setup_7322_interrupt(dd, 1);
3788 for (i = 0; i < dd->num_pports; ++i) {
3789 struct qib_pportdata *ppd = &dd->pport[i];
3791 spin_lock_irqsave(&ppd->lflags_lock, flags);
3792 ppd->lflags |= QIBL_IB_FORCE_NOTIFY;
3793 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
3794 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3798 dd->flags &= ~QIB_DOING_RESET; /* OK or not, no longer resetting */
3799 kfree(msix_vecsave);
3804 * qib_7322_put_tid - write a TID to the chip
3805 * @dd: the qlogic_ib device
3806 * @tidptr: pointer to the expected TID (in chip) to update
3807 * @tidtype: 0 for eager, 1 for expected
3808 * @pa: physical address of in memory buffer; tidinvalid if freeing
3810 static void qib_7322_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr,
3811 u32 type, unsigned long pa)
3813 if (!(dd->flags & QIB_PRESENT))
3815 if (pa != dd->tidinvalid) {
3816 u64 chippa = pa >> IBA7322_TID_PA_SHIFT;
3818 /* paranoia checks */
3819 if (pa != (chippa << IBA7322_TID_PA_SHIFT)) {
3820 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n",
3824 if (chippa >= (1UL << IBA7322_TID_SZ_SHIFT)) {
3826 "Physical page address 0x%lx larger than supported\n",
3831 if (type == RCVHQ_RCV_TYPE_EAGER)
3832 chippa |= dd->tidtemplate;
3833 else /* for now, always full 4KB page */
3834 chippa |= IBA7322_TID_SZ_4K;
3842 * qib_7322_clear_tids - clear all TID entries for a ctxt, expected and eager
3843 * @dd: the qlogic_ib device
3846 * clear all TID entries for a ctxt, expected and eager.
3847 * Used from qib_close().
3849 static void qib_7322_clear_tids(struct qib_devdata *dd,
3850 struct qib_ctxtdata *rcd)
3852 u64 __iomem *tidbase;
3853 unsigned long tidinv;
3857 if (!dd->kregbase || !rcd)
3862 tidinv = dd->tidinvalid;
3863 tidbase = (u64 __iomem *)
3864 ((char __iomem *) dd->kregbase +
3866 ctxt * dd->rcvtidcnt * sizeof(*tidbase));
3868 for (i = 0; i < dd->rcvtidcnt; i++)
3869 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
3872 tidbase = (u64 __iomem *)
3873 ((char __iomem *) dd->kregbase +
3875 rcd->rcvegr_tid_base * sizeof(*tidbase));
3877 for (i = 0; i < rcd->rcvegrcnt; i++)
3878 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
3883 * qib_7322_tidtemplate - setup constants for TID updates
3884 * @dd: the qlogic_ib device
3886 * We setup stuff that we use a lot, to avoid calculating each time
3888 static void qib_7322_tidtemplate(struct qib_devdata *dd)
3891 * For now, we always allocate 4KB buffers (at init) so we can
3892 * receive max size packets. We may want a module parameter to
3893 * specify 2KB or 4KB and/or make it per port instead of per device
3894 * for those who want to reduce memory footprint. Note that the
3895 * rcvhdrentsize size must be large enough to hold the largest
3896 * IB header (currently 96 bytes) that we expect to handle (plus of
3897 * course the 2 dwords of RHF).
3899 if (dd->rcvegrbufsize == 2048)
3900 dd->tidtemplate = IBA7322_TID_SZ_2K;
3901 else if (dd->rcvegrbufsize == 4096)
3902 dd->tidtemplate = IBA7322_TID_SZ_4K;
3907 * qib_init_7322_get_base_info - set chip-specific flags for user code
3908 * @rcd: the qlogic_ib ctxt
3909 * @kbase: qib_base_info pointer
3911 * We set the PCIE flag because the lower bandwidth on PCIe vs
3912 * HyperTransport can affect some user packet algorithims.
3915 static int qib_7322_get_base_info(struct qib_ctxtdata *rcd,
3916 struct qib_base_info *kinfo)
3918 kinfo->spi_runtime_flags |= QIB_RUNTIME_CTXT_MSB_IN_QP |
3919 QIB_RUNTIME_PCIE | QIB_RUNTIME_NODMA_RTAIL |
3920 QIB_RUNTIME_HDRSUPP | QIB_RUNTIME_SDMA;
3921 if (rcd->dd->cspec->r1)
3922 kinfo->spi_runtime_flags |= QIB_RUNTIME_RCHK;
3923 if (rcd->dd->flags & QIB_USE_SPCL_TRIG)
3924 kinfo->spi_runtime_flags |= QIB_RUNTIME_SPECIAL_TRIGGER;
3929 static struct qib_message_header *
3930 qib_7322_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr)
3932 u32 offset = qib_hdrget_offset(rhf_addr);
3934 return (struct qib_message_header *)
3935 (rhf_addr - dd->rhf_offset + offset);
3939 * Configure number of contexts.
3941 static void qib_7322_config_ctxts(struct qib_devdata *dd)
3943 unsigned long flags;
3946 nchipctxts = qib_read_kreg32(dd, kr_contextcnt);
3947 dd->cspec->numctxts = nchipctxts;
3948 if (qib_n_krcv_queues > 1 && dd->num_pports) {
3949 dd->first_user_ctxt = NUM_IB_PORTS +
3950 (qib_n_krcv_queues - 1) * dd->num_pports;
3951 if (dd->first_user_ctxt > nchipctxts)
3952 dd->first_user_ctxt = nchipctxts;
3953 dd->n_krcv_queues = dd->first_user_ctxt / dd->num_pports;
3955 dd->first_user_ctxt = NUM_IB_PORTS;
3956 dd->n_krcv_queues = 1;
3959 if (!qib_cfgctxts) {
3960 int nctxts = dd->first_user_ctxt + num_online_cpus();
3964 else if (nctxts <= 10)
3966 else if (nctxts <= nchipctxts)
3967 dd->ctxtcnt = nchipctxts;
3968 } else if (qib_cfgctxts < dd->num_pports)
3969 dd->ctxtcnt = dd->num_pports;
3970 else if (qib_cfgctxts <= nchipctxts)
3971 dd->ctxtcnt = qib_cfgctxts;
3972 if (!dd->ctxtcnt) /* none of the above, set to max */
3973 dd->ctxtcnt = nchipctxts;
3976 * Chip can be configured for 6, 10, or 18 ctxts, and choice
3977 * affects number of eager TIDs per ctxt (1K, 2K, 4K).
3978 * Lock to be paranoid about later motion, etc.
3980 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
3981 if (dd->ctxtcnt > 10)
3982 dd->rcvctrl |= 2ULL << SYM_LSB(RcvCtrl, ContextCfg);
3983 else if (dd->ctxtcnt > 6)
3984 dd->rcvctrl |= 1ULL << SYM_LSB(RcvCtrl, ContextCfg);
3985 /* else configure for default 6 receive ctxts */
3987 /* The XRC opcode is 5. */
3988 dd->rcvctrl |= 5ULL << SYM_LSB(RcvCtrl, XrcTypeCode);
3991 * RcvCtrl *must* be written here so that the
3992 * chip understands how to change rcvegrcnt below.
3994 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
3995 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
3997 /* kr_rcvegrcnt changes based on the number of contexts enabled */
3998 dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt);
4000 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, qib_rcvhdrcnt);
4002 dd->rcvhdrcnt = 2 * max(dd->cspec->rcvegrcnt,
4003 dd->num_pports > 1 ? 1024U : 2048U);
4006 static int qib_7322_get_ib_cfg(struct qib_pportdata *ppd, int which)
4010 u64 maskr; /* right-justified mask */
4014 case QIB_IB_CFG_LWID_ENB: /* Get allowed Link-width */
4015 ret = ppd->link_width_enabled;
4018 case QIB_IB_CFG_LWID: /* Get currently active Link-width */
4019 ret = ppd->link_width_active;
4022 case QIB_IB_CFG_SPD_ENB: /* Get allowed Link speeds */
4023 ret = ppd->link_speed_enabled;
4026 case QIB_IB_CFG_SPD: /* Get current Link spd */
4027 ret = ppd->link_speed_active;
4030 case QIB_IB_CFG_RXPOL_ENB: /* Get Auto-RX-polarity enable */
4031 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
4032 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
4035 case QIB_IB_CFG_LREV_ENB: /* Get Auto-Lane-reversal enable */
4036 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
4037 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
4040 case QIB_IB_CFG_LINKLATENCY:
4041 ret = qib_read_kreg_port(ppd, krp_ibcstatus_b) &
4042 SYM_MASK(IBCStatusB_0, LinkRoundTripLatency);
4045 case QIB_IB_CFG_OP_VLS:
4046 ret = ppd->vls_operational;
4049 case QIB_IB_CFG_VL_HIGH_CAP:
4053 case QIB_IB_CFG_VL_LOW_CAP:
4057 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
4058 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
4062 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
4063 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
4067 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
4068 /* will only take effect when the link state changes */
4069 ret = (ppd->cpspec->ibcctrl_a &
4070 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState)) ?
4071 IB_LINKINITCMD_SLEEP : IB_LINKINITCMD_POLL;
4074 case QIB_IB_CFG_HRTBT: /* Get Heartbeat off/enable/auto */
4075 lsb = IBA7322_IBC_HRTBT_LSB;
4076 maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */
4079 case QIB_IB_CFG_PMA_TICKS:
4081 * 0x00 = 10x link transfer rate or 4 nsec. for 2.5Gbs
4082 * Since the clock is always 250MHz, the value is 3, 1 or 0.
4084 if (ppd->link_speed_active == QIB_IB_QDR)
4086 else if (ppd->link_speed_active == QIB_IB_DDR)
4096 ret = (int)((ppd->cpspec->ibcctrl_b >> lsb) & maskr);
4102 * Below again cribbed liberally from older version. Do not lean
4105 #define IBA7322_IBC_DLIDLMC_SHIFT QIB_7322_IBCCtrlB_0_IB_DLID_LSB
4106 #define IBA7322_IBC_DLIDLMC_MASK (QIB_7322_IBCCtrlB_0_IB_DLID_RMASK \
4107 | (QIB_7322_IBCCtrlB_0_IB_DLID_MASK_RMASK << 16))
4109 static int qib_7322_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val)
4111 struct qib_devdata *dd = ppd->dd;
4112 u64 maskr; /* right-justified mask */
4115 unsigned long flags;
4118 case QIB_IB_CFG_LIDLMC:
4120 * Set LID and LMC. Combined to avoid possible hazard
4121 * caller puts LMC in 16MSbits, DLID in 16LSbits of val
4123 lsb = IBA7322_IBC_DLIDLMC_SHIFT;
4124 maskr = IBA7322_IBC_DLIDLMC_MASK;
4126 * For header-checking, the SLID in the packet will
4127 * be masked with SendIBSLMCMask, and compared
4128 * with SendIBSLIDAssignMask. Make sure we do not
4129 * set any bits not covered by the mask, or we get
4132 qib_write_kreg_port(ppd, krp_sendslid,
4133 val & (val >> 16) & SendIBSLIDAssignMask);
4134 qib_write_kreg_port(ppd, krp_sendslidmask,
4135 (val >> 16) & SendIBSLMCMask);
4138 case QIB_IB_CFG_LWID_ENB: /* set allowed Link-width */
4139 ppd->link_width_enabled = val;
4140 /* convert IB value to chip register value */
4141 if (val == IB_WIDTH_1X)
4143 else if (val == IB_WIDTH_4X)
4147 maskr = SYM_RMASK(IBCCtrlB_0, IB_NUM_CHANNELS);
4148 lsb = SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS);
4151 case QIB_IB_CFG_SPD_ENB: /* set allowed Link speeds */
4153 * As with width, only write the actual register if the
4154 * link is currently down, otherwise takes effect on next
4155 * link change. Since setting is being explicitly requested
4156 * (via MAD or sysfs), clear autoneg failure status if speed
4157 * autoneg is enabled.
4159 ppd->link_speed_enabled = val;
4160 val <<= IBA7322_IBC_SPEED_LSB;
4161 maskr = IBA7322_IBC_SPEED_MASK | IBA7322_IBC_IBTA_1_2_MASK |
4162 IBA7322_IBC_MAX_SPEED_MASK;
4163 if (val & (val - 1)) {
4164 /* Muliple speeds enabled */
4165 val |= IBA7322_IBC_IBTA_1_2_MASK |
4166 IBA7322_IBC_MAX_SPEED_MASK;
4167 spin_lock_irqsave(&ppd->lflags_lock, flags);
4168 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
4169 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
4170 } else if (val & IBA7322_IBC_SPEED_QDR)
4171 val |= IBA7322_IBC_IBTA_1_2_MASK;
4172 /* IBTA 1.2 mode + min/max + speed bits are contiguous */
4173 lsb = SYM_LSB(IBCCtrlB_0, IB_ENHANCED_MODE);
4176 case QIB_IB_CFG_RXPOL_ENB: /* set Auto-RX-polarity enable */
4177 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
4178 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
4181 case QIB_IB_CFG_LREV_ENB: /* set Auto-Lane-reversal enable */
4182 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
4183 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
4186 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
4187 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
4190 ppd->cpspec->ibcctrl_a &=
4191 ~SYM_MASK(IBCCtrlA_0, OverrunThreshold);
4192 ppd->cpspec->ibcctrl_a |= (u64) val <<
4193 SYM_LSB(IBCCtrlA_0, OverrunThreshold);
4194 qib_write_kreg_port(ppd, krp_ibcctrl_a,
4195 ppd->cpspec->ibcctrl_a);
4196 qib_write_kreg(dd, kr_scratch, 0ULL);
4200 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
4201 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
4204 ppd->cpspec->ibcctrl_a &=
4205 ~SYM_MASK(IBCCtrlA_0, PhyerrThreshold);
4206 ppd->cpspec->ibcctrl_a |= (u64) val <<
4207 SYM_LSB(IBCCtrlA_0, PhyerrThreshold);
4208 qib_write_kreg_port(ppd, krp_ibcctrl_a,
4209 ppd->cpspec->ibcctrl_a);
4210 qib_write_kreg(dd, kr_scratch, 0ULL);
4214 case QIB_IB_CFG_PKEYS: /* update pkeys */
4215 maskr = (u64) ppd->pkeys[0] | ((u64) ppd->pkeys[1] << 16) |
4216 ((u64) ppd->pkeys[2] << 32) |
4217 ((u64) ppd->pkeys[3] << 48);
4218 qib_write_kreg_port(ppd, krp_partitionkey, maskr);
4221 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
4222 /* will only take effect when the link state changes */
4223 if (val == IB_LINKINITCMD_POLL)
4224 ppd->cpspec->ibcctrl_a &=
4225 ~SYM_MASK(IBCCtrlA_0, LinkDownDefaultState);
4227 ppd->cpspec->ibcctrl_a |=
4228 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState);
4229 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
4230 qib_write_kreg(dd, kr_scratch, 0ULL);
4233 case QIB_IB_CFG_MTU: /* update the MTU in IBC */
4235 * Update our housekeeping variables, and set IBC max
4236 * size, same as init code; max IBC is max we allow in
4237 * buffer, less the qword pbc, plus 1 for ICRC, in dwords
4238 * Set even if it's unchanged, print debug message only
4241 val = (ppd->ibmaxlen >> 2) + 1;
4242 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, MaxPktLen);
4243 ppd->cpspec->ibcctrl_a |= (u64)val <<
4244 SYM_LSB(IBCCtrlA_0, MaxPktLen);
4245 qib_write_kreg_port(ppd, krp_ibcctrl_a,
4246 ppd->cpspec->ibcctrl_a);
4247 qib_write_kreg(dd, kr_scratch, 0ULL);
4250 case QIB_IB_CFG_LSTATE: /* set the IB link state */
4251 switch (val & 0xffff0000) {
4252 case IB_LINKCMD_DOWN:
4253 lcmd = QLOGIC_IB_IBCC_LINKCMD_DOWN;
4254 ppd->cpspec->ibmalfusesnap = 1;
4255 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd,
4257 if (!ppd->cpspec->ibdeltainprog &&
4258 qib_compat_ddr_negotiate) {
4259 ppd->cpspec->ibdeltainprog = 1;
4260 ppd->cpspec->ibsymsnap =
4261 read_7322_creg32_port(ppd,
4263 ppd->cpspec->iblnkerrsnap =
4264 read_7322_creg32_port(ppd,
4265 crp_iblinkerrrecov);
4269 case IB_LINKCMD_ARMED:
4270 lcmd = QLOGIC_IB_IBCC_LINKCMD_ARMED;
4271 if (ppd->cpspec->ibmalfusesnap) {
4272 ppd->cpspec->ibmalfusesnap = 0;
4273 ppd->cpspec->ibmalfdelta +=
4274 read_7322_creg32_port(ppd,
4276 ppd->cpspec->ibmalfsnap;
4280 case IB_LINKCMD_ACTIVE:
4281 lcmd = QLOGIC_IB_IBCC_LINKCMD_ACTIVE;
4286 qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16);
4289 switch (val & 0xffff) {
4290 case IB_LINKINITCMD_NOP:
4294 case IB_LINKINITCMD_POLL:
4295 licmd = QLOGIC_IB_IBCC_LINKINITCMD_POLL;
4298 case IB_LINKINITCMD_SLEEP:
4299 licmd = QLOGIC_IB_IBCC_LINKINITCMD_SLEEP;
4302 case IB_LINKINITCMD_DISABLE:
4303 licmd = QLOGIC_IB_IBCC_LINKINITCMD_DISABLE;
4304 ppd->cpspec->chase_end = 0;
4306 * stop state chase counter and timer, if running.
4307 * wait forpending timer, but don't clear .data (ppd)!
4309 if (ppd->cpspec->chase_timer.expires) {
4310 del_timer_sync(&ppd->cpspec->chase_timer);
4311 ppd->cpspec->chase_timer.expires = 0;
4317 qib_dev_err(dd, "bad linkinitcmd req 0x%x\n",
4321 qib_set_ib_7322_lstate(ppd, lcmd, licmd);
4324 case QIB_IB_CFG_OP_VLS:
4325 if (ppd->vls_operational != val) {
4326 ppd->vls_operational = val;
4331 case QIB_IB_CFG_VL_HIGH_LIMIT:
4332 qib_write_kreg_port(ppd, krp_highprio_limit, val);
4335 case QIB_IB_CFG_HRTBT: /* set Heartbeat off/enable/auto */
4340 lsb = IBA7322_IBC_HRTBT_LSB;
4341 maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */
4344 case QIB_IB_CFG_PORT:
4345 /* val is the port number of the switch we are connected to. */
4346 if (ppd->dd->cspec->r1) {
4347 cancel_delayed_work(&ppd->cpspec->ipg_work);
4348 ppd->cpspec->ipg_tries = 0;
4356 ppd->cpspec->ibcctrl_b &= ~(maskr << lsb);
4357 ppd->cpspec->ibcctrl_b |= (((u64) val & maskr) << lsb);
4358 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
4359 qib_write_kreg(dd, kr_scratch, 0);
4364 static int qib_7322_set_loopback(struct qib_pportdata *ppd, const char *what)
4369 /* only IBC loopback, may add serdes and xgxs loopbacks later */
4370 if (!strncmp(what, "ibc", 3)) {
4371 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0,
4373 val = 0; /* disable heart beat, so link will come up */
4374 qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n",
4375 ppd->dd->unit, ppd->port);
4376 } else if (!strncmp(what, "off", 3)) {
4377 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0,
4379 /* enable heart beat again */
4380 val = IBA7322_IBC_HRTBT_RMASK << IBA7322_IBC_HRTBT_LSB;
4381 qib_devinfo(ppd->dd->pcidev,
4382 "Disabling IB%u:%u IBC loopback (normal)\n",
4383 ppd->dd->unit, ppd->port);
4387 qib_write_kreg_port(ppd, krp_ibcctrl_a,
4388 ppd->cpspec->ibcctrl_a);
4389 ctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_HRTBT_MASK
4390 << IBA7322_IBC_HRTBT_LSB);
4391 ppd->cpspec->ibcctrl_b = ctrlb | val;
4392 qib_write_kreg_port(ppd, krp_ibcctrl_b,
4393 ppd->cpspec->ibcctrl_b);
4394 qib_write_kreg(ppd->dd, kr_scratch, 0);
4399 static void get_vl_weights(struct qib_pportdata *ppd, unsigned regno,
4400 struct ib_vl_weight_elem *vl)
4404 for (i = 0; i < 16; i++, regno++, vl++) {
4405 u32 val = qib_read_kreg_port(ppd, regno);
4407 vl->vl = (val >> SYM_LSB(LowPriority0_0, VirtualLane)) &
4408 SYM_RMASK(LowPriority0_0, VirtualLane);
4409 vl->weight = (val >> SYM_LSB(LowPriority0_0, Weight)) &
4410 SYM_RMASK(LowPriority0_0, Weight);
4414 static void set_vl_weights(struct qib_pportdata *ppd, unsigned regno,
4415 struct ib_vl_weight_elem *vl)
4419 for (i = 0; i < 16; i++, regno++, vl++) {
4422 val = ((vl->vl & SYM_RMASK(LowPriority0_0, VirtualLane)) <<
4423 SYM_LSB(LowPriority0_0, VirtualLane)) |
4424 ((vl->weight & SYM_RMASK(LowPriority0_0, Weight)) <<
4425 SYM_LSB(LowPriority0_0, Weight));
4426 qib_write_kreg_port(ppd, regno, val);
4428 if (!(ppd->p_sendctrl & SYM_MASK(SendCtrl_0, IBVLArbiterEn))) {
4429 struct qib_devdata *dd = ppd->dd;
4430 unsigned long flags;
4432 spin_lock_irqsave(&dd->sendctrl_lock, flags);
4433 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, IBVLArbiterEn);
4434 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
4435 qib_write_kreg(dd, kr_scratch, 0);
4436 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4440 static int qib_7322_get_ib_table(struct qib_pportdata *ppd, int which, void *t)
4443 case QIB_IB_TBL_VL_HIGH_ARB:
4444 get_vl_weights(ppd, krp_highprio_0, t);
4447 case QIB_IB_TBL_VL_LOW_ARB:
4448 get_vl_weights(ppd, krp_lowprio_0, t);
4457 static int qib_7322_set_ib_table(struct qib_pportdata *ppd, int which, void *t)
4460 case QIB_IB_TBL_VL_HIGH_ARB:
4461 set_vl_weights(ppd, krp_highprio_0, t);
4464 case QIB_IB_TBL_VL_LOW_ARB:
4465 set_vl_weights(ppd, krp_lowprio_0, t);
4474 static void qib_update_7322_usrhead(struct qib_ctxtdata *rcd, u64 hd,
4475 u32 updegr, u32 egrhd, u32 npkts)
4478 * Need to write timeout register before updating rcvhdrhead to ensure
4479 * that the timer is enabled on reception of a packet.
4481 if (hd >> IBA7322_HDRHEAD_PKTINT_SHIFT)
4482 adjust_rcv_timeout(rcd, npkts);
4484 qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt);
4486 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
4487 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
4491 static u32 qib_7322_hdrqempty(struct qib_ctxtdata *rcd)
4495 head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt);
4496 if (rcd->rcvhdrtail_kvaddr)
4497 tail = qib_get_rcvhdrtail(rcd);
4499 tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt);
4500 return head == tail;
4503 #define RCVCTRL_COMMON_MODS (QIB_RCVCTRL_CTXT_ENB | \
4504 QIB_RCVCTRL_CTXT_DIS | \
4505 QIB_RCVCTRL_TIDFLOW_ENB | \
4506 QIB_RCVCTRL_TIDFLOW_DIS | \
4507 QIB_RCVCTRL_TAILUPD_ENB | \
4508 QIB_RCVCTRL_TAILUPD_DIS | \
4509 QIB_RCVCTRL_INTRAVAIL_ENB | \
4510 QIB_RCVCTRL_INTRAVAIL_DIS | \
4511 QIB_RCVCTRL_BP_ENB | \
4514 #define RCVCTRL_PORT_MODS (QIB_RCVCTRL_CTXT_ENB | \
4515 QIB_RCVCTRL_CTXT_DIS | \
4516 QIB_RCVCTRL_PKEY_DIS | \
4517 QIB_RCVCTRL_PKEY_ENB)
4520 * Modify the RCVCTRL register in chip-specific way. This
4521 * is a function because bit positions and (future) register
4522 * location is chip-specifc, but the needed operations are
4523 * generic. <op> is a bit-mask because we often want to
4524 * do multiple modifications.
4526 static void rcvctrl_7322_mod(struct qib_pportdata *ppd, unsigned int op,
4529 struct qib_devdata *dd = ppd->dd;
4530 struct qib_ctxtdata *rcd;
4532 unsigned long flags;
4534 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
4536 if (op & QIB_RCVCTRL_TIDFLOW_ENB)
4537 dd->rcvctrl |= SYM_MASK(RcvCtrl, TidFlowEnable);
4538 if (op & QIB_RCVCTRL_TIDFLOW_DIS)
4539 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TidFlowEnable);
4540 if (op & QIB_RCVCTRL_TAILUPD_ENB)
4541 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd);
4542 if (op & QIB_RCVCTRL_TAILUPD_DIS)
4543 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TailUpd);
4544 if (op & QIB_RCVCTRL_PKEY_ENB)
4545 ppd->p_rcvctrl &= ~SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable);
4546 if (op & QIB_RCVCTRL_PKEY_DIS)
4547 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable);
4549 mask = (1ULL << dd->ctxtcnt) - 1;
4552 mask = (1ULL << ctxt);
4553 rcd = dd->rcd[ctxt];
4555 if ((op & QIB_RCVCTRL_CTXT_ENB) && rcd) {
4557 (mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel));
4558 if (!(dd->flags & QIB_NODMA_RTAIL)) {
4559 op |= QIB_RCVCTRL_TAILUPD_ENB; /* need reg write */
4560 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd);
4562 /* Write these registers before the context is enabled. */
4563 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt,
4564 rcd->rcvhdrqtailaddr_phys);
4565 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt,
4569 if (op & QIB_RCVCTRL_CTXT_DIS)
4571 ~(mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel));
4572 if (op & QIB_RCVCTRL_BP_ENB)
4573 dd->rcvctrl |= mask << SYM_LSB(RcvCtrl, dontDropRHQFull);
4574 if (op & QIB_RCVCTRL_BP_DIS)
4575 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, dontDropRHQFull));
4576 if (op & QIB_RCVCTRL_INTRAVAIL_ENB)
4577 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, IntrAvail));
4578 if (op & QIB_RCVCTRL_INTRAVAIL_DIS)
4579 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, IntrAvail));
4581 * Decide which registers to write depending on the ops enabled.
4582 * Special case is "flush" (no bits set at all)
4583 * which needs to write both.
4585 if (op == 0 || (op & RCVCTRL_COMMON_MODS))
4586 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
4587 if (op == 0 || (op & RCVCTRL_PORT_MODS))
4588 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl);
4589 if ((op & QIB_RCVCTRL_CTXT_ENB) && dd->rcd[ctxt]) {
4591 * Init the context registers also; if we were
4592 * disabled, tail and head should both be zero
4593 * already from the enable, but since we don't
4594 * know, we have to do it explicitly.
4596 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt);
4597 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt);
4599 /* be sure enabling write seen; hd/tl should be 0 */
4600 (void) qib_read_kreg32(dd, kr_scratch);
4601 val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt);
4602 dd->rcd[ctxt]->head = val;
4603 /* If kctxt, interrupt on next receive. */
4604 if (ctxt < dd->first_user_ctxt)
4605 val |= dd->rhdrhead_intr_off;
4606 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
4607 } else if ((op & QIB_RCVCTRL_INTRAVAIL_ENB) &&
4608 dd->rcd[ctxt] && dd->rhdrhead_intr_off) {
4609 /* arm rcv interrupt */
4610 val = dd->rcd[ctxt]->head | dd->rhdrhead_intr_off;
4611 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
4613 if (op & QIB_RCVCTRL_CTXT_DIS) {
4616 /* Now that the context is disabled, clear these registers. */
4618 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt, 0);
4619 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt, 0);
4620 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++)
4621 qib_write_ureg(dd, ur_rcvflowtable + f,
4622 TIDFLOW_ERRBITS, ctxt);
4626 for (i = 0; i < dd->cfgctxts; i++) {
4627 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr,
4629 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, i, 0);
4630 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++)
4631 qib_write_ureg(dd, ur_rcvflowtable + f,
4632 TIDFLOW_ERRBITS, i);
4636 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
4640 * Modify the SENDCTRL register in chip-specific way. This
4641 * is a function where there are multiple such registers with
4642 * slightly different layouts.
4643 * The chip doesn't allow back-to-back sendctrl writes, so write
4644 * the scratch register after writing sendctrl.
4646 * Which register is written depends on the operation.
4647 * Most operate on the common register, while
4648 * SEND_ENB and SEND_DIS operate on the per-port ones.
4649 * SEND_ENB is included in common because it can change SPCL_TRIG
4651 #define SENDCTRL_COMMON_MODS (\
4652 QIB_SENDCTRL_CLEAR | \
4653 QIB_SENDCTRL_AVAIL_DIS | \
4654 QIB_SENDCTRL_AVAIL_ENB | \
4655 QIB_SENDCTRL_AVAIL_BLIP | \
4656 QIB_SENDCTRL_DISARM | \
4657 QIB_SENDCTRL_DISARM_ALL | \
4658 QIB_SENDCTRL_SEND_ENB)
4660 #define SENDCTRL_PORT_MODS (\
4661 QIB_SENDCTRL_CLEAR | \
4662 QIB_SENDCTRL_SEND_ENB | \
4663 QIB_SENDCTRL_SEND_DIS | \
4666 static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op)
4668 struct qib_devdata *dd = ppd->dd;
4669 u64 tmp_dd_sendctrl;
4670 unsigned long flags;
4672 spin_lock_irqsave(&dd->sendctrl_lock, flags);
4674 /* First the dd ones that are "sticky", saved in shadow */
4675 if (op & QIB_SENDCTRL_CLEAR)
4677 if (op & QIB_SENDCTRL_AVAIL_DIS)
4678 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4679 else if (op & QIB_SENDCTRL_AVAIL_ENB) {
4680 dd->sendctrl |= SYM_MASK(SendCtrl, SendBufAvailUpd);
4681 if (dd->flags & QIB_USE_SPCL_TRIG)
4682 dd->sendctrl |= SYM_MASK(SendCtrl, SpecialTriggerEn);
4685 /* Then the ppd ones that are "sticky", saved in shadow */
4686 if (op & QIB_SENDCTRL_SEND_DIS)
4687 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable);
4688 else if (op & QIB_SENDCTRL_SEND_ENB)
4689 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable);
4691 if (op & QIB_SENDCTRL_DISARM_ALL) {
4694 tmp_dd_sendctrl = dd->sendctrl;
4695 last = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
4697 * Disarm any buffers that are not yet launched,
4698 * disabling updates until done.
4700 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4701 for (i = 0; i < last; i++) {
4702 qib_write_kreg(dd, kr_sendctrl,
4704 SYM_MASK(SendCtrl, Disarm) | i);
4705 qib_write_kreg(dd, kr_scratch, 0);
4709 if (op & QIB_SENDCTRL_FLUSH) {
4710 u64 tmp_ppd_sendctrl = ppd->p_sendctrl;
4713 * Now drain all the fifos. The Abort bit should never be
4714 * needed, so for now, at least, we don't use it.
4717 SYM_MASK(SendCtrl_0, TxeDrainRmFifo) |
4718 SYM_MASK(SendCtrl_0, TxeDrainLaFifo) |
4719 SYM_MASK(SendCtrl_0, TxeBypassIbc);
4720 qib_write_kreg_port(ppd, krp_sendctrl, tmp_ppd_sendctrl);
4721 qib_write_kreg(dd, kr_scratch, 0);
4724 tmp_dd_sendctrl = dd->sendctrl;
4726 if (op & QIB_SENDCTRL_DISARM)
4727 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Disarm) |
4728 ((op & QIB_7322_SendCtrl_DisarmSendBuf_RMASK) <<
4729 SYM_LSB(SendCtrl, DisarmSendBuf));
4730 if ((op & QIB_SENDCTRL_AVAIL_BLIP) &&
4731 (dd->sendctrl & SYM_MASK(SendCtrl, SendBufAvailUpd)))
4732 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4734 if (op == 0 || (op & SENDCTRL_COMMON_MODS)) {
4735 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl);
4736 qib_write_kreg(dd, kr_scratch, 0);
4739 if (op == 0 || (op & SENDCTRL_PORT_MODS)) {
4740 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
4741 qib_write_kreg(dd, kr_scratch, 0);
4744 if (op & QIB_SENDCTRL_AVAIL_BLIP) {
4745 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
4746 qib_write_kreg(dd, kr_scratch, 0);
4749 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4751 if (op & QIB_SENDCTRL_FLUSH) {
4754 * ensure writes have hit chip, then do a few
4755 * more reads, to allow DMA of pioavail registers
4756 * to occur, so in-memory copy is in sync with
4757 * the chip. Not always safe to sleep.
4759 v = qib_read_kreg32(dd, kr_scratch);
4760 qib_write_kreg(dd, kr_scratch, v);
4761 v = qib_read_kreg32(dd, kr_scratch);
4762 qib_write_kreg(dd, kr_scratch, v);
4763 qib_read_kreg32(dd, kr_scratch);
4767 #define _PORT_VIRT_FLAG 0x8000U /* "virtual", need adjustments */
4768 #define _PORT_64BIT_FLAG 0x10000U /* not "virtual", but 64bit */
4769 #define _PORT_CNTR_IDXMASK 0x7fffU /* mask off flags above */
4772 * qib_portcntr_7322 - read a per-port chip counter
4773 * @ppd: the qlogic_ib pport
4774 * @creg: the counter to read (not a chip offset)
4776 static u64 qib_portcntr_7322(struct qib_pportdata *ppd, u32 reg)
4778 struct qib_devdata *dd = ppd->dd;
4781 /* 0xffff for unimplemented or synthesized counters */
4782 static const u32 xlator[] = {
4783 [QIBPORTCNTR_PKTSEND] = crp_pktsend | _PORT_64BIT_FLAG,
4784 [QIBPORTCNTR_WORDSEND] = crp_wordsend | _PORT_64BIT_FLAG,
4785 [QIBPORTCNTR_PSXMITDATA] = crp_psxmitdatacount,
4786 [QIBPORTCNTR_PSXMITPKTS] = crp_psxmitpktscount,
4787 [QIBPORTCNTR_PSXMITWAIT] = crp_psxmitwaitcount,
4788 [QIBPORTCNTR_SENDSTALL] = crp_sendstall,
4789 [QIBPORTCNTR_PKTRCV] = crp_pktrcv | _PORT_64BIT_FLAG,
4790 [QIBPORTCNTR_PSRCVDATA] = crp_psrcvdatacount,
4791 [QIBPORTCNTR_PSRCVPKTS] = crp_psrcvpktscount,
4792 [QIBPORTCNTR_RCVEBP] = crp_rcvebp,
4793 [QIBPORTCNTR_RCVOVFL] = crp_rcvovfl,
4794 [QIBPORTCNTR_WORDRCV] = crp_wordrcv | _PORT_64BIT_FLAG,
4795 [QIBPORTCNTR_RXDROPPKT] = 0xffff, /* not needed for 7322 */
4796 [QIBPORTCNTR_RXLOCALPHYERR] = crp_rxotherlocalphyerr,
4797 [QIBPORTCNTR_RXVLERR] = crp_rxvlerr,
4798 [QIBPORTCNTR_ERRICRC] = crp_erricrc,
4799 [QIBPORTCNTR_ERRVCRC] = crp_errvcrc,
4800 [QIBPORTCNTR_ERRLPCRC] = crp_errlpcrc,
4801 [QIBPORTCNTR_BADFORMAT] = crp_badformat,
4802 [QIBPORTCNTR_ERR_RLEN] = crp_err_rlen,
4803 [QIBPORTCNTR_IBSYMBOLERR] = crp_ibsymbolerr,
4804 [QIBPORTCNTR_INVALIDRLEN] = crp_invalidrlen,
4805 [QIBPORTCNTR_UNSUPVL] = crp_txunsupvl,
4806 [QIBPORTCNTR_EXCESSBUFOVFL] = crp_excessbufferovfl,
4807 [QIBPORTCNTR_ERRLINK] = crp_errlink,
4808 [QIBPORTCNTR_IBLINKDOWN] = crp_iblinkdown,
4809 [QIBPORTCNTR_IBLINKERRRECOV] = crp_iblinkerrrecov,
4810 [QIBPORTCNTR_LLI] = crp_locallinkintegrityerr,
4811 [QIBPORTCNTR_VL15PKTDROP] = crp_vl15droppedpkt,
4812 [QIBPORTCNTR_ERRPKEY] = crp_errpkey,
4814 * the next 3 aren't really counters, but were implemented
4815 * as counters in older chips, so still get accessed as
4816 * though they were counters from this code.
4818 [QIBPORTCNTR_PSINTERVAL] = krp_psinterval,
4819 [QIBPORTCNTR_PSSTART] = krp_psstart,
4820 [QIBPORTCNTR_PSSTAT] = krp_psstat,
4821 /* pseudo-counter, summed for all ports */
4822 [QIBPORTCNTR_KHDROVFL] = 0xffff,
4825 if (reg >= ARRAY_SIZE(xlator)) {
4826 qib_devinfo(ppd->dd->pcidev,
4827 "Unimplemented portcounter %u\n", reg);
4830 creg = xlator[reg] & _PORT_CNTR_IDXMASK;
4832 /* handle non-counters and special cases first */
4833 if (reg == QIBPORTCNTR_KHDROVFL) {
4836 /* sum over all kernel contexts (skip if mini_init) */
4837 for (i = 0; dd->rcd && i < dd->first_user_ctxt; i++) {
4838 struct qib_ctxtdata *rcd = dd->rcd[i];
4840 if (!rcd || rcd->ppd != ppd)
4842 ret += read_7322_creg32(dd, cr_base_egrovfl + i);
4845 } else if (reg == QIBPORTCNTR_RXDROPPKT) {
4847 * Used as part of the synthesis of port_rcv_errors
4848 * in the verbs code for IBTA counters. Not needed for 7322,
4849 * because all the errors are already counted by other cntrs.
4852 } else if (reg == QIBPORTCNTR_PSINTERVAL ||
4853 reg == QIBPORTCNTR_PSSTART || reg == QIBPORTCNTR_PSSTAT) {
4854 /* were counters in older chips, now per-port kernel regs */
4855 ret = qib_read_kreg_port(ppd, creg);
4860 * Only fast increment counters are 64 bits; use 32 bit reads to
4861 * avoid two independent reads when on Opteron.
4863 if (xlator[reg] & _PORT_64BIT_FLAG)
4864 ret = read_7322_creg_port(ppd, creg);
4866 ret = read_7322_creg32_port(ppd, creg);
4867 if (creg == crp_ibsymbolerr) {
4868 if (ppd->cpspec->ibdeltainprog)
4869 ret -= ret - ppd->cpspec->ibsymsnap;
4870 ret -= ppd->cpspec->ibsymdelta;
4871 } else if (creg == crp_iblinkerrrecov) {
4872 if (ppd->cpspec->ibdeltainprog)
4873 ret -= ret - ppd->cpspec->iblnkerrsnap;
4874 ret -= ppd->cpspec->iblnkerrdelta;
4875 } else if (creg == crp_errlink)
4876 ret -= ppd->cpspec->ibmalfdelta;
4877 else if (creg == crp_iblinkdown)
4878 ret += ppd->cpspec->iblnkdowndelta;
4884 * Device counter names (not port-specific), one line per stat,
4885 * single string. Used by utilities like ipathstats to print the stats
4886 * in a way which works for different versions of drivers, without changing
4887 * the utility. Names need to be 12 chars or less (w/o newline), for proper
4888 * display by utility.
4889 * Non-error counters are first.
4890 * Start of "error" conters is indicated by a leading "E " on the first
4891 * "error" counter, and doesn't count in label length.
4892 * The EgrOvfl list needs to be last so we truncate them at the configured
4893 * context count for the device.
4894 * cntr7322indices contains the corresponding register indices.
4896 static const char cntr7322names[] =
4901 "RxTIDFloDrop\n" /* 7322 only */
4922 static const u32 cntr7322indices[] = {
4923 cr_lbint | _PORT_64BIT_FLAG,
4924 cr_lbstall | _PORT_64BIT_FLAG,
4928 cr_base_egrovfl + 0,
4929 cr_base_egrovfl + 1,
4930 cr_base_egrovfl + 2,
4931 cr_base_egrovfl + 3,
4932 cr_base_egrovfl + 4,
4933 cr_base_egrovfl + 5,
4934 cr_base_egrovfl + 6,
4935 cr_base_egrovfl + 7,
4936 cr_base_egrovfl + 8,
4937 cr_base_egrovfl + 9,
4938 cr_base_egrovfl + 10,
4939 cr_base_egrovfl + 11,
4940 cr_base_egrovfl + 12,
4941 cr_base_egrovfl + 13,
4942 cr_base_egrovfl + 14,
4943 cr_base_egrovfl + 15,
4944 cr_base_egrovfl + 16,
4945 cr_base_egrovfl + 17,
4949 * same as cntr7322names and cntr7322indices, but for port-specific counters.
4950 * portcntr7322indices is somewhat complicated by some registers needing
4951 * adjustments of various kinds, and those are ORed with _PORT_VIRT_FLAG
4953 static const char portcntr7322names[] =
4961 "TxDmaDesc\n" /* 7220 and 7322-only */
4962 "E RxDlidFltr\n" /* 7220 and 7322-only */
4985 "RxLclPhyErr\n" /* 7220 and 7322-only from here down */
4989 "RxQPBadCtxt\n" /* 7322-only from here down */
4993 static const u32 portcntr7322indices[] = {
4994 QIBPORTCNTR_PKTSEND | _PORT_VIRT_FLAG,
4996 QIBPORTCNTR_WORDSEND | _PORT_VIRT_FLAG,
4997 QIBPORTCNTR_PKTRCV | _PORT_VIRT_FLAG,
4999 QIBPORTCNTR_WORDRCV | _PORT_VIRT_FLAG,
5000 QIBPORTCNTR_SENDSTALL | _PORT_VIRT_FLAG,
5001 crp_txsdmadesc | _PORT_64BIT_FLAG,
5004 QIBPORTCNTR_IBLINKDOWN | _PORT_VIRT_FLAG,
5005 QIBPORTCNTR_IBLINKERRRECOV | _PORT_VIRT_FLAG,
5006 QIBPORTCNTR_ERRLINK | _PORT_VIRT_FLAG,
5007 QIBPORTCNTR_IBSYMBOLERR | _PORT_VIRT_FLAG,
5008 QIBPORTCNTR_LLI | _PORT_VIRT_FLAG,
5009 QIBPORTCNTR_BADFORMAT | _PORT_VIRT_FLAG,
5010 QIBPORTCNTR_ERR_RLEN | _PORT_VIRT_FLAG,
5011 QIBPORTCNTR_RCVOVFL | _PORT_VIRT_FLAG,
5012 QIBPORTCNTR_RCVEBP | _PORT_VIRT_FLAG,
5013 crp_rcvflowctrlviol,
5014 QIBPORTCNTR_ERRICRC | _PORT_VIRT_FLAG,
5015 QIBPORTCNTR_ERRLPCRC | _PORT_VIRT_FLAG,
5016 QIBPORTCNTR_ERRVCRC | _PORT_VIRT_FLAG,
5017 QIBPORTCNTR_INVALIDRLEN | _PORT_VIRT_FLAG,
5018 QIBPORTCNTR_ERRPKEY | _PORT_VIRT_FLAG,
5019 QIBPORTCNTR_RXDROPPKT | _PORT_VIRT_FLAG,
5025 QIBPORTCNTR_RXLOCALPHYERR | _PORT_VIRT_FLAG,
5026 QIBPORTCNTR_VL15PKTDROP | _PORT_VIRT_FLAG,
5027 QIBPORTCNTR_RXVLERR | _PORT_VIRT_FLAG,
5028 QIBPORTCNTR_EXCESSBUFOVFL | _PORT_VIRT_FLAG,
5029 crp_rxqpinvalidctxt,
5033 /* do all the setup to make the counter reads efficient later */
5034 static void init_7322_cntrnames(struct qib_devdata *dd)
5039 for (i = 0, s = (char *)cntr7322names; s && j <= dd->cfgctxts;
5041 /* we always have at least one counter before the egrovfl */
5042 if (!j && !strncmp("Ctxt0EgrOvfl", s + 1, 12))
5044 s = strchr(s + 1, '\n');
5048 dd->cspec->ncntrs = i;
5050 /* full list; size is without terminating null */
5051 dd->cspec->cntrnamelen = sizeof(cntr7322names) - 1;
5053 dd->cspec->cntrnamelen = 1 + s - cntr7322names;
5054 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs
5055 * sizeof(u64), GFP_KERNEL);
5056 if (!dd->cspec->cntrs)
5057 qib_dev_err(dd, "Failed allocation for counters\n");
5059 for (i = 0, s = (char *)portcntr7322names; s; i++)
5060 s = strchr(s + 1, '\n');
5061 dd->cspec->nportcntrs = i - 1;
5062 dd->cspec->portcntrnamelen = sizeof(portcntr7322names) - 1;
5063 for (i = 0; i < dd->num_pports; ++i) {
5064 dd->pport[i].cpspec->portcntrs = kmalloc(dd->cspec->nportcntrs
5065 * sizeof(u64), GFP_KERNEL);
5066 if (!dd->pport[i].cpspec->portcntrs)
5068 "Failed allocation for portcounters\n");
5072 static u32 qib_read_7322cntrs(struct qib_devdata *dd, loff_t pos, char **namep,
5078 ret = dd->cspec->cntrnamelen;
5080 ret = 0; /* final read after getting everything */
5082 *namep = (char *) cntr7322names;
5084 u64 *cntr = dd->cspec->cntrs;
5087 ret = dd->cspec->ncntrs * sizeof(u64);
5088 if (!cntr || pos >= ret) {
5089 /* everything read, or couldn't get memory */
5094 for (i = 0; i < dd->cspec->ncntrs; i++)
5095 if (cntr7322indices[i] & _PORT_64BIT_FLAG)
5096 *cntr++ = read_7322_creg(dd,
5097 cntr7322indices[i] &
5098 _PORT_CNTR_IDXMASK);
5100 *cntr++ = read_7322_creg32(dd,
5101 cntr7322indices[i]);
5107 static u32 qib_read_7322portcntrs(struct qib_devdata *dd, loff_t pos, u32 port,
5108 char **namep, u64 **cntrp)
5113 ret = dd->cspec->portcntrnamelen;
5115 ret = 0; /* final read after getting everything */
5117 *namep = (char *)portcntr7322names;
5119 struct qib_pportdata *ppd = &dd->pport[port];
5120 u64 *cntr = ppd->cpspec->portcntrs;
5123 ret = dd->cspec->nportcntrs * sizeof(u64);
5124 if (!cntr || pos >= ret) {
5125 /* everything read, or couldn't get memory */
5130 for (i = 0; i < dd->cspec->nportcntrs; i++) {
5131 if (portcntr7322indices[i] & _PORT_VIRT_FLAG)
5132 *cntr++ = qib_portcntr_7322(ppd,
5133 portcntr7322indices[i] &
5134 _PORT_CNTR_IDXMASK);
5135 else if (portcntr7322indices[i] & _PORT_64BIT_FLAG)
5136 *cntr++ = read_7322_creg_port(ppd,
5137 portcntr7322indices[i] &
5138 _PORT_CNTR_IDXMASK);
5140 *cntr++ = read_7322_creg32_port(ppd,
5141 portcntr7322indices[i]);
5149 * qib_get_7322_faststats - get word counters from chip before they overflow
5150 * @opaque - contains a pointer to the qlogic_ib device qib_devdata
5152 * VESTIGIAL IBA7322 has no "small fast counters", so the only
5153 * real purpose of this function is to maintain the notion of
5154 * "active time", which in turn is only logged into the eeprom,
5155 * which we don;t have, yet, for 7322-based boards.
5157 * called from add_timer
5159 static void qib_get_7322_faststats(unsigned long opaque)
5161 struct qib_devdata *dd = (struct qib_devdata *) opaque;
5162 struct qib_pportdata *ppd;
5163 unsigned long flags;
5167 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
5168 ppd = dd->pport + pidx;
5171 * If port isn't enabled or not operational ports, or
5172 * diags is running (can cause memory diags to fail)
5173 * skip this port this time.
5175 if (!ppd->link_speed_supported || !(dd->flags & QIB_INITTED)
5180 * Maintain an activity timer, based on traffic
5181 * exceeding a threshold, so we need to check the word-counts
5182 * even if they are 64-bit.
5184 traffic_wds = qib_portcntr_7322(ppd, QIBPORTCNTR_WORDRCV) +
5185 qib_portcntr_7322(ppd, QIBPORTCNTR_WORDSEND);
5186 spin_lock_irqsave(&ppd->dd->eep_st_lock, flags);
5187 traffic_wds -= ppd->dd->traffic_wds;
5188 ppd->dd->traffic_wds += traffic_wds;
5189 if (traffic_wds >= QIB_TRAFFIC_ACTIVE_THRESHOLD)
5190 atomic_add(ACTIVITY_TIMER, &ppd->dd->active_time);
5191 spin_unlock_irqrestore(&ppd->dd->eep_st_lock, flags);
5192 if (ppd->cpspec->qdr_dfe_on && (ppd->link_speed_active &
5194 (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED |
5195 QIBL_LINKACTIVE)) &&
5196 ppd->cpspec->qdr_dfe_time &&
5197 time_is_before_jiffies(ppd->cpspec->qdr_dfe_time)) {
5198 ppd->cpspec->qdr_dfe_on = 0;
5200 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
5201 ppd->dd->cspec->r1 ?
5202 QDR_STATIC_ADAPT_INIT_R1 :
5203 QDR_STATIC_ADAPT_INIT);
5207 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER);
5211 * If we were using MSIx, try to fallback to INTx.
5213 static int qib_7322_intr_fallback(struct qib_devdata *dd)
5215 if (!dd->cspec->num_msix_entries)
5216 return 0; /* already using INTx */
5218 qib_devinfo(dd->pcidev,
5219 "MSIx interrupt not detected, trying INTx interrupts\n");
5220 qib_7322_nomsix(dd);
5221 qib_enable_intx(dd->pcidev);
5222 qib_setup_7322_interrupt(dd, 0);
5227 * Reset the XGXS (between serdes and IBC). Slightly less intrusive
5228 * than resetting the IBC or external link state, and useful in some
5229 * cases to cause some retraining. To do this right, we reset IBC
5230 * as well, then return to previous state (which may be still in reset)
5231 * NOTE: some callers of this "know" this writes the current value
5232 * of cpspec->ibcctrl_a as part of it's operation, so if that changes,
5233 * check all callers.
5235 static void qib_7322_mini_pcs_reset(struct qib_pportdata *ppd)
5238 struct qib_devdata *dd = ppd->dd;
5239 const u64 reset_bits = SYM_MASK(IBPCSConfig_0, xcv_rreset) |
5240 SYM_MASK(IBPCSConfig_0, xcv_treset) |
5241 SYM_MASK(IBPCSConfig_0, tx_rx_reset);
5243 val = qib_read_kreg_port(ppd, krp_ib_pcsconfig);
5244 qib_write_kreg(dd, kr_hwerrmask,
5245 dd->cspec->hwerrmask & ~HWE_MASK(statusValidNoEop));
5246 qib_write_kreg_port(ppd, krp_ibcctrl_a,
5247 ppd->cpspec->ibcctrl_a &
5248 ~SYM_MASK(IBCCtrlA_0, IBLinkEn));
5250 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val | reset_bits);
5251 qib_read_kreg32(dd, kr_scratch);
5252 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val & ~reset_bits);
5253 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
5254 qib_write_kreg(dd, kr_scratch, 0ULL);
5255 qib_write_kreg(dd, kr_hwerrclear,
5256 SYM_MASK(HwErrClear, statusValidNoEopClear));
5257 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
5261 * This code for non-IBTA-compliant IB speed negotiation is only known to
5262 * work for the SDR to DDR transition, and only between an HCA and a switch
5263 * with recent firmware. It is based on observed heuristics, rather than
5264 * actual knowledge of the non-compliant speed negotiation.
5265 * It has a number of hard-coded fields, since the hope is to rewrite this
5266 * when a spec is available on how the negoation is intended to work.
5268 static void autoneg_7322_sendpkt(struct qib_pportdata *ppd, u32 *hdr,
5269 u32 dcnt, u32 *data)
5273 u32 __iomem *piobuf;
5274 u32 pnum, control, len;
5275 struct qib_devdata *dd = ppd->dd;
5278 len = 7 + dcnt + 1; /* 7 dword header, dword data, icrc */
5279 control = qib_7322_setpbc_control(ppd, len, 0, 15);
5280 pbc = ((u64) control << 32) | len;
5281 while (!(piobuf = qib_7322_getsendbuf(ppd, pbc, &pnum))) {
5286 /* disable header check on this packet, since it can't be valid */
5287 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_DIS1, NULL);
5288 writeq(pbc, piobuf);
5290 qib_pio_copy(piobuf + 2, hdr, 7);
5291 qib_pio_copy(piobuf + 9, data, dcnt);
5292 if (dd->flags & QIB_USE_SPCL_TRIG) {
5293 u32 spcl_off = (pnum >= dd->piobcnt2k) ? 2047 : 1023;
5296 __raw_writel(0xaebecede, piobuf + spcl_off);
5299 qib_sendbuf_done(dd, pnum);
5300 /* and re-enable hdr check */
5301 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_ENAB1, NULL);
5305 * _start packet gets sent twice at start, _done gets sent twice at end
5307 static void qib_autoneg_7322_send(struct qib_pportdata *ppd, int which)
5309 struct qib_devdata *dd = ppd->dd;
5311 u32 dw, i, hcnt, dcnt, *data;
5312 static u32 hdr[7] = { 0xf002ffff, 0x48ffff, 0x6400abba };
5313 static u32 madpayload_start[0x40] = {
5314 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
5315 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
5316 0x1, 0x1388, 0x15e, 0x1, /* rest 0's */
5318 static u32 madpayload_done[0x40] = {
5319 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
5320 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
5321 0x40000001, 0x1388, 0x15e, /* rest 0's */
5324 dcnt = ARRAY_SIZE(madpayload_start);
5325 hcnt = ARRAY_SIZE(hdr);
5327 /* for maintainability, do it at runtime */
5328 for (i = 0; i < hcnt; i++) {
5329 dw = (__force u32) cpu_to_be32(hdr[i]);
5332 for (i = 0; i < dcnt; i++) {
5333 dw = (__force u32) cpu_to_be32(madpayload_start[i]);
5334 madpayload_start[i] = dw;
5335 dw = (__force u32) cpu_to_be32(madpayload_done[i]);
5336 madpayload_done[i] = dw;
5341 data = which ? madpayload_done : madpayload_start;
5343 autoneg_7322_sendpkt(ppd, hdr, dcnt, data);
5344 qib_read_kreg64(dd, kr_scratch);
5346 autoneg_7322_sendpkt(ppd, hdr, dcnt, data);
5347 qib_read_kreg64(dd, kr_scratch);
5352 * Do the absolute minimum to cause an IB speed change, and make it
5353 * ready, but don't actually trigger the change. The caller will
5354 * do that when ready (if link is in Polling training state, it will
5355 * happen immediately, otherwise when link next goes down)
5357 * This routine should only be used as part of the DDR autonegotation
5358 * code for devices that are not compliant with IB 1.2 (or code that
5359 * fixes things up for same).
5361 * When link has gone down, and autoneg enabled, or autoneg has
5362 * failed and we give up until next time we set both speeds, and
5363 * then we want IBTA enabled as well as "use max enabled speed.
5365 static void set_7322_ibspeed_fast(struct qib_pportdata *ppd, u32 speed)
5368 newctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_SPEED_MASK |
5369 IBA7322_IBC_IBTA_1_2_MASK |
5370 IBA7322_IBC_MAX_SPEED_MASK);
5372 if (speed & (speed - 1)) /* multiple speeds */
5373 newctrlb |= (speed << IBA7322_IBC_SPEED_LSB) |
5374 IBA7322_IBC_IBTA_1_2_MASK |
5375 IBA7322_IBC_MAX_SPEED_MASK;
5377 newctrlb |= speed == QIB_IB_QDR ?
5378 IBA7322_IBC_SPEED_QDR | IBA7322_IBC_IBTA_1_2_MASK :
5379 ((speed == QIB_IB_DDR ?
5380 IBA7322_IBC_SPEED_DDR : IBA7322_IBC_SPEED_SDR));
5382 if (newctrlb == ppd->cpspec->ibcctrl_b)
5385 ppd->cpspec->ibcctrl_b = newctrlb;
5386 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
5387 qib_write_kreg(ppd->dd, kr_scratch, 0);
5391 * This routine is only used when we are not talking to another
5392 * IB 1.2-compliant device that we think can do DDR.
5393 * (This includes all existing switch chips as of Oct 2007.)
5394 * 1.2-compliant devices go directly to DDR prior to reaching INIT
5396 static void try_7322_autoneg(struct qib_pportdata *ppd)
5398 unsigned long flags;
5400 spin_lock_irqsave(&ppd->lflags_lock, flags);
5401 ppd->lflags |= QIBL_IB_AUTONEG_INPROG;
5402 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5403 qib_autoneg_7322_send(ppd, 0);
5404 set_7322_ibspeed_fast(ppd, QIB_IB_DDR);
5405 qib_7322_mini_pcs_reset(ppd);
5406 /* 2 msec is minimum length of a poll cycle */
5407 queue_delayed_work(ib_wq, &ppd->cpspec->autoneg_work,
5408 msecs_to_jiffies(2));
5412 * Handle the empirically determined mechanism for auto-negotiation
5413 * of DDR speed with switches.
5415 static void autoneg_7322_work(struct work_struct *work)
5417 struct qib_pportdata *ppd;
5418 struct qib_devdata *dd;
5421 unsigned long flags;
5423 ppd = container_of(work, struct qib_chippport_specific,
5424 autoneg_work.work)->ppd;
5427 startms = jiffies_to_msecs(jiffies);
5430 * Busy wait for this first part, it should be at most a
5431 * few hundred usec, since we scheduled ourselves for 2msec.
5433 for (i = 0; i < 25; i++) {
5434 if (SYM_FIELD(ppd->lastibcstat, IBCStatusA_0, LinkState)
5435 == IB_7322_LT_STATE_POLLQUIET) {
5436 qib_set_linkstate(ppd, QIB_IB_LINKDOWN_DISABLE);
5442 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
5443 goto done; /* we got there early or told to stop */
5445 /* we expect this to timeout */
5446 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
5447 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5448 msecs_to_jiffies(90)))
5450 qib_7322_mini_pcs_reset(ppd);
5452 /* we expect this to timeout */
5453 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
5454 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5455 msecs_to_jiffies(1700)))
5457 qib_7322_mini_pcs_reset(ppd);
5459 set_7322_ibspeed_fast(ppd, QIB_IB_SDR);
5462 * Wait up to 250 msec for link to train and get to INIT at DDR;
5463 * this should terminate early.
5465 wait_event_timeout(ppd->cpspec->autoneg_wait,
5466 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5467 msecs_to_jiffies(250));
5469 if (ppd->lflags & QIBL_IB_AUTONEG_INPROG) {
5470 spin_lock_irqsave(&ppd->lflags_lock, flags);
5471 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
5472 if (ppd->cpspec->autoneg_tries == AUTONEG_TRIES) {
5473 ppd->lflags |= QIBL_IB_AUTONEG_FAILED;
5474 ppd->cpspec->autoneg_tries = 0;
5476 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5477 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5482 * This routine is used to request IPG set in the QLogic switch.
5483 * Only called if r1.
5485 static void try_7322_ipg(struct qib_pportdata *ppd)
5487 struct qib_ibport *ibp = &ppd->ibport_data;
5488 struct ib_mad_send_buf *send_buf;
5489 struct ib_mad_agent *agent;
5494 agent = ibp->send_agent;
5498 send_buf = ib_create_send_mad(agent, 0, 0, 0, IB_MGMT_MAD_HDR,
5499 IB_MGMT_MAD_DATA, GFP_ATOMIC);
5500 if (IS_ERR(send_buf))
5506 ah = qib_create_qp0_ah(ibp, be16_to_cpu(IB_LID_PERMISSIVE));
5511 ibp->smi_ah = to_iah(ah);
5515 send_buf->ah = &ibp->smi_ah->ibah;
5519 smp = send_buf->mad;
5520 smp->base_version = IB_MGMT_BASE_VERSION;
5521 smp->mgmt_class = IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE;
5522 smp->class_version = 1;
5523 smp->method = IB_MGMT_METHOD_SEND;
5525 smp->attr_id = QIB_VENDOR_IPG;
5529 ret = ib_post_send_mad(send_buf, NULL);
5531 ib_free_send_mad(send_buf);
5533 delay = 2 << ppd->cpspec->ipg_tries;
5534 queue_delayed_work(ib_wq, &ppd->cpspec->ipg_work,
5535 msecs_to_jiffies(delay));
5539 * Timeout handler for setting IPG.
5540 * Only called if r1.
5542 static void ipg_7322_work(struct work_struct *work)
5544 struct qib_pportdata *ppd;
5546 ppd = container_of(work, struct qib_chippport_specific,
5547 ipg_work.work)->ppd;
5548 if ((ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED | QIBL_LINKACTIVE))
5549 && ++ppd->cpspec->ipg_tries <= 10)
5553 static u32 qib_7322_iblink_state(u64 ibcs)
5555 u32 state = (u32)SYM_FIELD(ibcs, IBCStatusA_0, LinkState);
5558 case IB_7322_L_STATE_INIT:
5559 state = IB_PORT_INIT;
5561 case IB_7322_L_STATE_ARM:
5562 state = IB_PORT_ARMED;
5564 case IB_7322_L_STATE_ACTIVE:
5566 case IB_7322_L_STATE_ACT_DEFER:
5567 state = IB_PORT_ACTIVE;
5569 default: /* fall through */
5570 case IB_7322_L_STATE_DOWN:
5571 state = IB_PORT_DOWN;
5577 /* returns the IBTA port state, rather than the IBC link training state */
5578 static u8 qib_7322_phys_portstate(u64 ibcs)
5580 u8 state = (u8)SYM_FIELD(ibcs, IBCStatusA_0, LinkTrainingState);
5581 return qib_7322_physportstate[state];
5584 static int qib_7322_ib_updown(struct qib_pportdata *ppd, int ibup, u64 ibcs)
5586 int ret = 0, symadj = 0;
5587 unsigned long flags;
5590 spin_lock_irqsave(&ppd->lflags_lock, flags);
5591 ppd->lflags &= ~QIBL_IB_FORCE_NOTIFY;
5592 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5594 /* Update our picture of width and speed from chip */
5595 if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) {
5596 ppd->link_speed_active = QIB_IB_QDR;
5598 } else if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedActive)) {
5599 ppd->link_speed_active = QIB_IB_DDR;
5602 ppd->link_speed_active = QIB_IB_SDR;
5605 if (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) {
5606 ppd->link_width_active = IB_WIDTH_4X;
5609 ppd->link_width_active = IB_WIDTH_1X;
5610 ppd->delay_mult = ib_rate_to_delay[mult_to_ib_rate(mult)];
5615 /* Link went down. */
5616 /* do IPG MAD again after linkdown, even if last time failed */
5617 ppd->cpspec->ipg_tries = 0;
5618 clr = qib_read_kreg_port(ppd, krp_ibcstatus_b) &
5619 (SYM_MASK(IBCStatusB_0, heartbeat_timed_out) |
5620 SYM_MASK(IBCStatusB_0, heartbeat_crosstalk));
5622 qib_write_kreg_port(ppd, krp_ibcstatus_b, clr);
5623 if (!(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
5624 QIBL_IB_AUTONEG_INPROG)))
5625 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5626 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5627 struct qib_qsfp_data *qd =
5628 &ppd->cpspec->qsfp_data;
5629 /* unlock the Tx settings, speed may change */
5630 qib_write_kreg_port(ppd, krp_tx_deemph_override,
5631 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
5632 reset_tx_deemphasis_override));
5633 qib_cancel_sends(ppd);
5634 /* on link down, ensure sane pcs state */
5635 qib_7322_mini_pcs_reset(ppd);
5636 /* schedule the qsfp refresh which should turn the link
5638 if (ppd->dd->flags & QIB_HAS_QSFP) {
5639 qd->t_insert = jiffies;
5640 queue_work(ib_wq, &qd->work);
5642 spin_lock_irqsave(&ppd->sdma_lock, flags);
5643 if (__qib_sdma_running(ppd))
5644 __qib_sdma_process_event(ppd,
5645 qib_sdma_event_e70_go_idle);
5646 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
5648 clr = read_7322_creg32_port(ppd, crp_iblinkdown);
5649 if (clr == ppd->cpspec->iblnkdownsnap)
5650 ppd->cpspec->iblnkdowndelta++;
5652 if (qib_compat_ddr_negotiate &&
5653 !(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
5654 QIBL_IB_AUTONEG_INPROG)) &&
5655 ppd->link_speed_active == QIB_IB_SDR &&
5656 (ppd->link_speed_enabled & QIB_IB_DDR)
5657 && ppd->cpspec->autoneg_tries < AUTONEG_TRIES) {
5658 /* we are SDR, and auto-negotiation enabled */
5659 ++ppd->cpspec->autoneg_tries;
5660 if (!ppd->cpspec->ibdeltainprog) {
5661 ppd->cpspec->ibdeltainprog = 1;
5662 ppd->cpspec->ibsymdelta +=
5663 read_7322_creg32_port(ppd,
5665 ppd->cpspec->ibsymsnap;
5666 ppd->cpspec->iblnkerrdelta +=
5667 read_7322_creg32_port(ppd,
5668 crp_iblinkerrrecov) -
5669 ppd->cpspec->iblnkerrsnap;
5671 try_7322_autoneg(ppd);
5672 ret = 1; /* no other IB status change processing */
5673 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
5674 ppd->link_speed_active == QIB_IB_SDR) {
5675 qib_autoneg_7322_send(ppd, 1);
5676 set_7322_ibspeed_fast(ppd, QIB_IB_DDR);
5677 qib_7322_mini_pcs_reset(ppd);
5679 ret = 1; /* no other IB status change processing */
5680 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
5681 (ppd->link_speed_active & QIB_IB_DDR)) {
5682 spin_lock_irqsave(&ppd->lflags_lock, flags);
5683 ppd->lflags &= ~(QIBL_IB_AUTONEG_INPROG |
5684 QIBL_IB_AUTONEG_FAILED);
5685 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5686 ppd->cpspec->autoneg_tries = 0;
5687 /* re-enable SDR, for next link down */
5688 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5689 wake_up(&ppd->cpspec->autoneg_wait);
5691 } else if (ppd->lflags & QIBL_IB_AUTONEG_FAILED) {
5693 * Clear autoneg failure flag, and do setup
5694 * so we'll try next time link goes down and
5695 * back to INIT (possibly connected to a
5696 * different device).
5698 spin_lock_irqsave(&ppd->lflags_lock, flags);
5699 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
5700 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5701 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_IBTA_1_2_MASK;
5704 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5706 if (ppd->dd->cspec->r1 && ppd->cpspec->ipg_tries <= 10)
5708 if (!ppd->cpspec->recovery_init)
5709 setup_7322_link_recovery(ppd, 0);
5710 ppd->cpspec->qdr_dfe_time = jiffies +
5711 msecs_to_jiffies(QDR_DFE_DISABLE_DELAY);
5713 ppd->cpspec->ibmalfusesnap = 0;
5714 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd,
5718 ppd->cpspec->iblnkdownsnap =
5719 read_7322_creg32_port(ppd, crp_iblinkdown);
5720 if (ppd->cpspec->ibdeltainprog) {
5721 ppd->cpspec->ibdeltainprog = 0;
5722 ppd->cpspec->ibsymdelta += read_7322_creg32_port(ppd,
5723 crp_ibsymbolerr) - ppd->cpspec->ibsymsnap;
5724 ppd->cpspec->iblnkerrdelta += read_7322_creg32_port(ppd,
5725 crp_iblinkerrrecov) - ppd->cpspec->iblnkerrsnap;
5727 } else if (!ibup && qib_compat_ddr_negotiate &&
5728 !ppd->cpspec->ibdeltainprog &&
5729 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5730 ppd->cpspec->ibdeltainprog = 1;
5731 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd,
5733 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd,
5734 crp_iblinkerrrecov);
5738 qib_setup_7322_setextled(ppd, ibup);
5743 * Does read/modify/write to appropriate registers to
5744 * set output and direction bits selected by mask.
5745 * these are in their canonical postions (e.g. lsb of
5746 * dir will end up in D48 of extctrl on existing chips).
5747 * returns contents of GP Inputs.
5749 static int gpio_7322_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask)
5751 u64 read_val, new_out;
5752 unsigned long flags;
5755 /* some bits being written, lock access to GPIO */
5758 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
5759 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe));
5760 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe));
5761 new_out = (dd->cspec->gpio_out & ~mask) | out;
5763 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
5764 qib_write_kreg(dd, kr_gpio_out, new_out);
5765 dd->cspec->gpio_out = new_out;
5766 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
5769 * It is unlikely that a read at this time would get valid
5770 * data on a pin whose direction line was set in the same
5771 * call to this function. We include the read here because
5772 * that allows us to potentially combine a change on one pin with
5773 * a read on another, and because the old code did something like
5776 read_val = qib_read_kreg64(dd, kr_extstatus);
5777 return SYM_FIELD(read_val, EXTStatus, GPIOIn);
5780 /* Enable writes to config EEPROM, if possible. Returns previous state */
5781 static int qib_7322_eeprom_wen(struct qib_devdata *dd, int wen)
5786 mask = 1 << QIB_EEPROM_WEN_NUM;
5787 prev_wen = ~gpio_7322_mod(dd, 0, 0, 0) >> QIB_EEPROM_WEN_NUM;
5788 gpio_7322_mod(dd, wen ? 0 : mask, mask, mask);
5790 return prev_wen & 1;
5794 * Read fundamental info we need to use the chip. These are
5795 * the registers that describe chip capabilities, and are
5796 * saved in shadow registers.
5798 static void get_7322_chip_params(struct qib_devdata *dd)
5804 dd->palign = qib_read_kreg32(dd, kr_pagealign);
5806 dd->uregbase = qib_read_kreg32(dd, kr_userregbase);
5808 dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt);
5809 dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase);
5810 dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase);
5811 dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase);
5812 dd->pio2k_bufbase = dd->piobufbase & 0xffffffff;
5814 val = qib_read_kreg64(dd, kr_sendpiobufcnt);
5815 dd->piobcnt2k = val & ~0U;
5816 dd->piobcnt4k = val >> 32;
5817 val = qib_read_kreg64(dd, kr_sendpiosize);
5818 dd->piosize2k = val & ~0U;
5819 dd->piosize4k = val >> 32;
5821 mtu = ib_mtu_enum_to_int(qib_ibmtu);
5823 mtu = QIB_DEFAULT_MTU;
5824 dd->pport[0].ibmtu = (u32)mtu;
5825 dd->pport[1].ibmtu = (u32)mtu;
5827 /* these may be adjusted in init_chip_wc_pat() */
5828 dd->pio2kbase = (u32 __iomem *)
5829 ((char __iomem *) dd->kregbase + dd->pio2k_bufbase);
5830 dd->pio4kbase = (u32 __iomem *)
5831 ((char __iomem *) dd->kregbase +
5832 (dd->piobufbase >> 32));
5834 * 4K buffers take 2 pages; we use roundup just to be
5835 * paranoid; we calculate it once here, rather than on
5838 dd->align4k = ALIGN(dd->piosize4k, dd->palign);
5840 piobufs = dd->piobcnt4k + dd->piobcnt2k + NUM_VL15_BUFS;
5842 dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) /
5843 (sizeof(u64) * BITS_PER_BYTE / 2);
5847 * The chip base addresses in cspec and cpspec have to be set
5848 * after possible init_chip_wc_pat(), rather than in
5849 * get_7322_chip_params(), so split out as separate function
5851 static void qib_7322_set_baseaddrs(struct qib_devdata *dd)
5854 cregbase = qib_read_kreg32(dd, kr_counterregbase);
5856 dd->cspec->cregbase = (u64 __iomem *)(cregbase +
5857 (char __iomem *)dd->kregbase);
5859 dd->egrtidbase = (u64 __iomem *)
5860 ((char __iomem *) dd->kregbase + dd->rcvegrbase);
5862 /* port registers are defined as relative to base of chip */
5863 dd->pport[0].cpspec->kpregbase =
5864 (u64 __iomem *)((char __iomem *)dd->kregbase);
5865 dd->pport[1].cpspec->kpregbase =
5866 (u64 __iomem *)(dd->palign +
5867 (char __iomem *)dd->kregbase);
5868 dd->pport[0].cpspec->cpregbase =
5869 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[0],
5870 kr_counterregbase) + (char __iomem *)dd->kregbase);
5871 dd->pport[1].cpspec->cpregbase =
5872 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[1],
5873 kr_counterregbase) + (char __iomem *)dd->kregbase);
5877 * This is a fairly special-purpose observer, so we only support
5878 * the port-specific parts of SendCtrl
5881 #define SENDCTRL_SHADOWED (SYM_MASK(SendCtrl_0, SendEnable) | \
5882 SYM_MASK(SendCtrl_0, SDmaEnable) | \
5883 SYM_MASK(SendCtrl_0, SDmaIntEnable) | \
5884 SYM_MASK(SendCtrl_0, SDmaSingleDescriptor) | \
5885 SYM_MASK(SendCtrl_0, SDmaHalt) | \
5886 SYM_MASK(SendCtrl_0, IBVLArbiterEn) | \
5887 SYM_MASK(SendCtrl_0, ForceCreditUpToDate))
5889 static int sendctrl_hook(struct qib_devdata *dd,
5890 const struct diag_observer *op, u32 offs,
5891 u64 *data, u64 mask, int only_32)
5893 unsigned long flags;
5896 struct qib_pportdata *ppd = NULL;
5897 u64 local_data, all_bits;
5900 * The fixed correspondence between Physical ports and pports is
5901 * severed. We need to hunt for the ppd that corresponds
5902 * to the offset we got. And we have to do that without admitting
5903 * we know the stride, apparently.
5905 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
5909 ppd = dd->pport + pidx;
5910 if (!ppd->cpspec->kpregbase)
5913 psptr = ppd->cpspec->kpregbase + krp_sendctrl;
5914 psoffs = (u32) (psptr - dd->kregbase) * sizeof(*psptr);
5919 /* If pport is not being managed by driver, just avoid shadows. */
5920 if (pidx >= dd->num_pports)
5923 /* In any case, "idx" is flat index in kreg space */
5924 idx = offs / sizeof(u64);
5930 spin_lock_irqsave(&dd->sendctrl_lock, flags);
5931 if (!ppd || (mask & all_bits) != all_bits) {
5933 * At least some mask bits are zero, so we need
5934 * to read. The judgement call is whether from
5935 * reg or shadow. First-cut: read reg, and complain
5936 * if any bits which should be shadowed are different
5937 * from their shadowed value.
5940 local_data = (u64)qib_read_kreg32(dd, idx);
5942 local_data = qib_read_kreg64(dd, idx);
5943 *data = (local_data & ~mask) | (*data & mask);
5947 * At least some mask bits are one, so we need
5948 * to write, but only shadow some bits.
5950 u64 sval, tval; /* Shadowed, transient */
5953 * New shadow val is bits we don't want to touch,
5954 * ORed with bits we do, that are intended for shadow.
5957 sval = ppd->p_sendctrl & ~mask;
5958 sval |= *data & SENDCTRL_SHADOWED & mask;
5959 ppd->p_sendctrl = sval;
5961 sval = *data & SENDCTRL_SHADOWED & mask;
5962 tval = sval | (*data & ~SENDCTRL_SHADOWED & mask);
5963 qib_write_kreg(dd, idx, tval);
5964 qib_write_kreg(dd, kr_scratch, 0Ull);
5966 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
5967 return only_32 ? 4 : 8;
5970 static const struct diag_observer sendctrl_0_observer = {
5971 sendctrl_hook, KREG_IDX(SendCtrl_0) * sizeof(u64),
5972 KREG_IDX(SendCtrl_0) * sizeof(u64)
5975 static const struct diag_observer sendctrl_1_observer = {
5976 sendctrl_hook, KREG_IDX(SendCtrl_1) * sizeof(u64),
5977 KREG_IDX(SendCtrl_1) * sizeof(u64)
5980 static ushort sdma_fetch_prio = 8;
5981 module_param_named(sdma_fetch_prio, sdma_fetch_prio, ushort, S_IRUGO);
5982 MODULE_PARM_DESC(sdma_fetch_prio, "SDMA descriptor fetch priority");
5984 /* Besides logging QSFP events, we set appropriate TxDDS values */
5985 static void init_txdds_table(struct qib_pportdata *ppd, int override);
5987 static void qsfp_7322_event(struct work_struct *work)
5989 struct qib_qsfp_data *qd;
5990 struct qib_pportdata *ppd;
5991 unsigned long pwrup;
5992 unsigned long flags;
5996 qd = container_of(work, struct qib_qsfp_data, work);
5998 pwrup = qd->t_insert +
5999 msecs_to_jiffies(QSFP_PWR_LAG_MSEC - QSFP_MODPRS_LAG_MSEC);
6001 /* Delay for 20 msecs to allow ModPrs resistor to setup */
6002 mdelay(QSFP_MODPRS_LAG_MSEC);
6004 if (!qib_qsfp_mod_present(ppd)) {
6005 ppd->cpspec->qsfp_data.modpresent = 0;
6006 /* Set the physical link to disabled */
6007 qib_set_ib_7322_lstate(ppd, 0,
6008 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
6009 spin_lock_irqsave(&ppd->lflags_lock, flags);
6010 ppd->lflags &= ~QIBL_LINKV;
6011 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
6014 * Some QSFP's not only do not respond until the full power-up
6015 * time, but may behave badly if we try. So hold off responding
6019 if (time_is_before_jiffies(pwrup))
6024 ret = qib_refresh_qsfp_cache(ppd, &qd->cache);
6027 * Need to change LE2 back to defaults if we couldn't
6028 * read the cable type (to handle cable swaps), so do this
6029 * even on failure to read cable information. We don't
6030 * get here for QME, so IS_QME check not needed here.
6032 if (!ret && !ppd->dd->cspec->r1) {
6033 if (QSFP_IS_ACTIVE_FAR(qd->cache.tech))
6035 else if (qd->cache.atten[1] >= qib_long_atten &&
6036 QSFP_IS_CU(qd->cache.tech))
6042 ibsd_wr_allchans(ppd, 13, (le2 << 7), BMASK(9, 7));
6044 * We always change parameteters, since we can choose
6045 * values for cables without eeproms, and the cable may have
6046 * changed from a cable with full or partial eeprom content
6047 * to one with partial or no content.
6049 init_txdds_table(ppd, 0);
6050 /* The physical link is being re-enabled only when the
6051 * previous state was DISABLED and the VALID bit is not
6052 * set. This should only happen when the cable has been
6053 * physically pulled. */
6054 if (!ppd->cpspec->qsfp_data.modpresent &&
6055 (ppd->lflags & (QIBL_LINKV | QIBL_IB_LINK_DISABLED))) {
6056 ppd->cpspec->qsfp_data.modpresent = 1;
6057 qib_set_ib_7322_lstate(ppd, 0,
6058 QLOGIC_IB_IBCC_LINKINITCMD_SLEEP);
6059 spin_lock_irqsave(&ppd->lflags_lock, flags);
6060 ppd->lflags |= QIBL_LINKV;
6061 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
6067 * There is little we can do but complain to the user if QSFP
6068 * initialization fails.
6070 static void qib_init_7322_qsfp(struct qib_pportdata *ppd)
6072 unsigned long flags;
6073 struct qib_qsfp_data *qd = &ppd->cpspec->qsfp_data;
6074 struct qib_devdata *dd = ppd->dd;
6075 u64 mod_prs_bit = QSFP_GPIO_MOD_PRS_N;
6077 mod_prs_bit <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx);
6079 qib_qsfp_init(qd, qsfp_7322_event);
6080 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
6081 dd->cspec->extctrl |= (mod_prs_bit << SYM_LSB(EXTCtrl, GPIOInvert));
6082 dd->cspec->gpio_mask |= mod_prs_bit;
6083 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
6084 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
6085 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
6089 * called at device initialization time, and also if the txselect
6090 * module parameter is changed. This is used for cables that don't
6091 * have valid QSFP EEPROMs (not present, or attenuation is zero).
6092 * We initialize to the default, then if there is a specific
6093 * unit,port match, we use that (and set it immediately, for the
6094 * current speed, if the link is at INIT or better).
6095 * String format is "default# unit#,port#=# ... u,p=#", separators must
6096 * be a SPACE character. A newline terminates. The u,p=# tuples may
6097 * optionally have "u,p=#,#", where the final # is the H1 value
6098 * The last specific match is used (actually, all are used, but last
6099 * one is the one that winds up set); if none at all, fall back on default.
6101 static void set_no_qsfp_atten(struct qib_devdata *dd, int change)
6104 u32 pidx, unit, port, deflt, h1;
6109 str = txselect_list;
6111 /* default number is validated in setup_txselect() */
6112 deflt = simple_strtoul(str, &nxt, 0);
6113 for (pidx = 0; pidx < dd->num_pports; ++pidx)
6114 dd->pport[pidx].cpspec->no_eep = deflt;
6116 txdds_size = TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ;
6117 if (IS_QME(dd) || IS_QMH(dd))
6118 txdds_size += TXDDS_MFG_SZ;
6120 while (*nxt && nxt[1]) {
6122 unit = simple_strtoul(str, &nxt, 0);
6123 if (nxt == str || !*nxt || *nxt != ',') {
6124 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
6129 port = simple_strtoul(str, &nxt, 0);
6130 if (nxt == str || *nxt != '=') {
6131 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
6136 val = simple_strtoul(str, &nxt, 0);
6138 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
6142 if (val >= txdds_size)
6145 h1 = 0; /* gcc thinks it might be used uninitted */
6146 if (*nxt == ',' && nxt[1]) {
6148 h1 = (u32)simple_strtoul(str, &nxt, 0);
6150 while (*nxt && *nxt++ != ' ') /* skip */
6155 for (pidx = 0; dd->unit == unit && pidx < dd->num_pports;
6157 struct qib_pportdata *ppd = &dd->pport[pidx];
6159 if (ppd->port != port || !ppd->link_speed_supported)
6161 ppd->cpspec->no_eep = val;
6163 ppd->cpspec->h1_val = h1;
6164 /* now change the IBC and serdes, overriding generic */
6165 init_txdds_table(ppd, 1);
6166 /* Re-enable the physical state machine on mezz boards
6167 * now that the correct settings have been set.
6168 * QSFP boards are handles by the QSFP event handler */
6169 if (IS_QMH(dd) || IS_QME(dd))
6170 qib_set_ib_7322_lstate(ppd, 0,
6171 QLOGIC_IB_IBCC_LINKINITCMD_SLEEP);
6177 if (change && !any) {
6178 /* no specific setting, use the default.
6179 * Change the IBC and serdes, but since it's
6180 * general, don't override specific settings.
6182 for (pidx = 0; pidx < dd->num_pports; ++pidx)
6183 if (dd->pport[pidx].link_speed_supported)
6184 init_txdds_table(&dd->pport[pidx], 0);
6188 /* handle the txselect parameter changing */
6189 static int setup_txselect(const char *str, struct kernel_param *kp)
6191 struct qib_devdata *dd;
6195 if (strlen(str) >= MAX_ATTEN_LEN) {
6196 pr_info("txselect_values string too long\n");
6199 ret = kstrtoul(str, 0, &val);
6200 if (ret || val >= (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ +
6202 pr_info("txselect_values must start with a number < %d\n",
6203 TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ + TXDDS_MFG_SZ);
6204 return ret ? ret : -EINVAL;
6207 strcpy(txselect_list, str);
6208 list_for_each_entry(dd, &qib_dev_list, list)
6209 if (dd->deviceid == PCI_DEVICE_ID_QLOGIC_IB_7322)
6210 set_no_qsfp_atten(dd, 1);
6215 * Write the final few registers that depend on some of the
6216 * init setup. Done late in init, just before bringing up
6219 static int qib_late_7322_initreg(struct qib_devdata *dd)
6224 qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize);
6225 qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize);
6226 qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt);
6227 qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys);
6228 val = qib_read_kreg64(dd, kr_sendpioavailaddr);
6229 if (val != dd->pioavailregs_phys) {
6231 "Catastrophic software error, SendPIOAvailAddr written as %lx, read back as %llx\n",
6232 (unsigned long) dd->pioavailregs_phys,
6233 (unsigned long long) val);
6237 n = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
6238 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_KERN, NULL);
6239 /* driver sends get pkey, lid, etc. checking also, to catch bugs */
6240 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_ENAB1, NULL);
6242 qib_register_observer(dd, &sendctrl_0_observer);
6243 qib_register_observer(dd, &sendctrl_1_observer);
6245 dd->control &= ~QLOGIC_IB_C_SDMAFETCHPRIOEN;
6246 qib_write_kreg(dd, kr_control, dd->control);
6248 * Set SendDmaFetchPriority and init Tx params, including
6249 * QSFP handler on boards that have QSFP.
6250 * First set our default attenuation entry for cables that
6251 * don't have valid attenuation.
6253 set_no_qsfp_atten(dd, 0);
6254 for (n = 0; n < dd->num_pports; ++n) {
6255 struct qib_pportdata *ppd = dd->pport + n;
6257 qib_write_kreg_port(ppd, krp_senddmaprioritythld,
6258 sdma_fetch_prio & 0xf);
6259 /* Initialize qsfp if present on board. */
6260 if (dd->flags & QIB_HAS_QSFP)
6261 qib_init_7322_qsfp(ppd);
6263 dd->control |= QLOGIC_IB_C_SDMAFETCHPRIOEN;
6264 qib_write_kreg(dd, kr_control, dd->control);
6269 /* per IB port errors. */
6270 #define SENDCTRL_PIBP (MASK_ACROSS(0, 1) | MASK_ACROSS(3, 3) | \
6272 #define RCVCTRL_PIBP (MASK_ACROSS(0, 17) | MASK_ACROSS(39, 41))
6273 #define ERRS_PIBP (MASK_ACROSS(57, 58) | MASK_ACROSS(54, 54) | \
6274 MASK_ACROSS(36, 49) | MASK_ACROSS(29, 34) | MASK_ACROSS(14, 17) | \
6278 * Write the initialization per-port registers that need to be done at
6279 * driver load and after reset completes (i.e., that aren't done as part
6280 * of other init procedures called from qib_init.c).
6281 * Some of these should be redundant on reset, but play safe.
6283 static void write_7322_init_portregs(struct qib_pportdata *ppd)
6288 if (!ppd->link_speed_supported) {
6289 /* no buffer credits for this port */
6290 for (i = 1; i < 8; i++)
6291 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0);
6292 qib_write_kreg_port(ppd, krp_ibcctrl_b, 0);
6293 qib_write_kreg(ppd->dd, kr_scratch, 0);
6298 * Set the number of supported virtual lanes in IBC,
6299 * for flow control packet handling on unsupported VLs
6301 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx);
6302 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, VL_CAP);
6303 val |= (u64)(ppd->vls_supported - 1) <<
6304 SYM_LSB(IB_SDTEST_IF_TX_0, VL_CAP);
6305 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
6307 qib_write_kreg_port(ppd, krp_rcvbthqp, QIB_KD_QP);
6309 /* enable tx header checking */
6310 qib_write_kreg_port(ppd, krp_sendcheckcontrol, IBA7322_SENDCHK_PKEY |
6311 IBA7322_SENDCHK_BTHQP | IBA7322_SENDCHK_SLID |
6312 IBA7322_SENDCHK_RAW_IPV6 | IBA7322_SENDCHK_MINSZ);
6314 qib_write_kreg_port(ppd, krp_ncmodectrl,
6315 SYM_MASK(IBNCModeCtrl_0, ScrambleCapLocal));
6318 * Unconditionally clear the bufmask bits. If SDMA is
6319 * enabled, we'll set them appropriately later.
6321 qib_write_kreg_port(ppd, krp_senddmabufmask0, 0);
6322 qib_write_kreg_port(ppd, krp_senddmabufmask1, 0);
6323 qib_write_kreg_port(ppd, krp_senddmabufmask2, 0);
6324 if (ppd->dd->cspec->r1)
6325 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, ForceCreditUpToDate);
6329 * Write the initialization per-device registers that need to be done at
6330 * driver load and after reset completes (i.e., that aren't done as part
6331 * of other init procedures called from qib_init.c). Also write per-port
6332 * registers that are affected by overall device config, such as QP mapping
6333 * Some of these should be redundant on reset, but play safe.
6335 static void write_7322_initregs(struct qib_devdata *dd)
6337 struct qib_pportdata *ppd;
6341 /* Set Multicast QPs received by port 2 to map to context one. */
6342 qib_write_kreg(dd, KREG_IDX(RcvQPMulticastContext_1), 1);
6344 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
6346 unsigned long flags;
6348 if (dd->n_krcv_queues < 2 ||
6349 !dd->pport[pidx].link_speed_supported)
6352 ppd = &dd->pport[pidx];
6354 /* be paranoid against later code motion, etc. */
6355 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
6356 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvQPMapEnable);
6357 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
6359 /* Initialize QP to context mapping */
6360 regno = krp_rcvqpmaptable;
6362 if (dd->num_pports > 1)
6363 n = dd->first_user_ctxt / dd->num_pports;
6365 n = dd->first_user_ctxt - 1;
6366 for (i = 0; i < 32; ) {
6369 if (dd->num_pports > 1)
6370 ctxt = (i % n) * dd->num_pports + pidx;
6374 ctxt = ppd->hw_pidx;
6375 val |= ctxt << (5 * (i % 6));
6378 qib_write_kreg_port(ppd, regno, val);
6383 qib_write_kreg_port(ppd, regno, val);
6387 * Setup up interrupt mitigation for kernel contexts, but
6388 * not user contexts (user contexts use interrupts when
6389 * stalled waiting for any packet, so want those interrupts
6392 for (i = 0; i < dd->first_user_ctxt; i++) {
6393 dd->cspec->rcvavail_timeout[i] = rcv_int_timeout;
6394 qib_write_kreg(dd, kr_rcvavailtimeout + i, rcv_int_timeout);
6398 * Initialize as (disabled) rcvflow tables. Application code
6399 * will setup each flow as it uses the flow.
6400 * Doesn't clear any of the error bits that might be set.
6402 val = TIDFLOW_ERRBITS; /* these are W1C */
6403 for (i = 0; i < dd->cfgctxts; i++) {
6405 for (flow = 0; flow < NUM_TIDFLOWS_CTXT; flow++)
6406 qib_write_ureg(dd, ur_rcvflowtable+flow, val, i);
6410 * dual cards init to dual port recovery, single port cards to
6411 * the one port. Dual port cards may later adjust to 1 port,
6412 * and then back to dual port if both ports are connected
6415 setup_7322_link_recovery(dd->pport, dd->num_pports > 1);
6418 static int qib_init_7322_variables(struct qib_devdata *dd)
6420 struct qib_pportdata *ppd;
6421 unsigned features, pidx, sbufcnt;
6423 u32 sbufs, updthresh;
6425 /* pport structs are contiguous, allocated after devdata */
6426 ppd = (struct qib_pportdata *)(dd + 1);
6431 dd->cspec = (struct qib_chip_specific *)(ppd + 2);
6433 ppd[0].cpspec = (struct qib_chippport_specific *)(dd->cspec + 1);
6434 ppd[1].cpspec = &ppd[0].cpspec[1];
6435 ppd[0].cpspec->ppd = &ppd[0]; /* for autoneg_7322_work() */
6436 ppd[1].cpspec->ppd = &ppd[1]; /* for autoneg_7322_work() */
6438 spin_lock_init(&dd->cspec->rcvmod_lock);
6439 spin_lock_init(&dd->cspec->gpio_lock);
6441 /* we haven't yet set QIB_PRESENT, so use read directly */
6442 dd->revision = readq(&dd->kregbase[kr_revision]);
6444 if ((dd->revision & 0xffffffffU) == 0xffffffffU) {
6446 "Revision register read failure, giving up initialization\n");
6450 dd->flags |= QIB_PRESENT; /* now register routines work */
6452 dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMajor);
6453 dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMinor);
6454 dd->cspec->r1 = dd->minrev == 1;
6456 get_7322_chip_params(dd);
6457 features = qib_7322_boardname(dd);
6459 /* now that piobcnt2k and 4k set, we can allocate these */
6460 sbufcnt = dd->piobcnt2k + dd->piobcnt4k +
6461 NUM_VL15_BUFS + BITS_PER_LONG - 1;
6462 sbufcnt /= BITS_PER_LONG;
6463 dd->cspec->sendchkenable = kmalloc(sbufcnt *
6464 sizeof(*dd->cspec->sendchkenable), GFP_KERNEL);
6465 dd->cspec->sendgrhchk = kmalloc(sbufcnt *
6466 sizeof(*dd->cspec->sendgrhchk), GFP_KERNEL);
6467 dd->cspec->sendibchk = kmalloc(sbufcnt *
6468 sizeof(*dd->cspec->sendibchk), GFP_KERNEL);
6469 if (!dd->cspec->sendchkenable || !dd->cspec->sendgrhchk ||
6470 !dd->cspec->sendibchk) {
6471 qib_dev_err(dd, "Failed allocation for hdrchk bitmaps\n");
6479 * GPIO bits for TWSI data and clock,
6480 * used for serial EEPROM.
6482 dd->gpio_sda_num = _QIB_GPIO_SDA_NUM;
6483 dd->gpio_scl_num = _QIB_GPIO_SCL_NUM;
6484 dd->twsi_eeprom_dev = QIB_TWSI_EEPROM_DEV;
6486 dd->flags |= QIB_HAS_INTX | QIB_HAS_LINK_LATENCY |
6487 QIB_NODMA_RTAIL | QIB_HAS_VLSUPP | QIB_HAS_HDRSUPP |
6488 QIB_HAS_THRESH_UPDATE |
6489 (sdma_idle_cnt ? QIB_HAS_SDMA_TIMEOUT : 0);
6490 dd->flags |= qib_special_trigger ?
6491 QIB_USE_SPCL_TRIG : QIB_HAS_SEND_DMA;
6494 * Setup initial values. These may change when PAT is enabled, but
6495 * we need these to do initial chip register accesses.
6497 qib_7322_set_baseaddrs(dd);
6499 mtu = ib_mtu_enum_to_int(qib_ibmtu);
6501 mtu = QIB_DEFAULT_MTU;
6503 dd->cspec->int_enable_mask = QIB_I_BITSEXTANT;
6504 /* all hwerrors become interrupts, unless special purposed */
6505 dd->cspec->hwerrmask = ~0ULL;
6506 /* link_recovery setup causes these errors, so ignore them,
6507 * other than clearing them when they occur */
6508 dd->cspec->hwerrmask &=
6509 ~(SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_0) |
6510 SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_1) |
6511 HWE_MASK(LATriggered));
6513 for (pidx = 0; pidx < NUM_IB_PORTS; ++pidx) {
6514 struct qib_chippport_specific *cp = ppd->cpspec;
6515 ppd->link_speed_supported = features & PORT_SPD_CAP;
6516 features >>= PORT_SPD_CAP_SHIFT;
6517 if (!ppd->link_speed_supported) {
6518 /* single port mode (7340, or configured) */
6519 dd->skip_kctxt_mask |= 1 << pidx;
6521 /* Make sure port is disabled. */
6522 qib_write_kreg_port(ppd, krp_rcvctrl, 0);
6523 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0);
6525 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6526 IBSerdesPClkNotDetectMask_0)
6527 | SYM_MASK(HwErrMask,
6528 SDmaMemReadErrMask_0));
6529 dd->cspec->int_enable_mask &= ~(
6530 SYM_MASK(IntMask, SDmaCleanupDoneMask_0) |
6531 SYM_MASK(IntMask, SDmaIdleIntMask_0) |
6532 SYM_MASK(IntMask, SDmaProgressIntMask_0) |
6533 SYM_MASK(IntMask, SDmaIntMask_0) |
6534 SYM_MASK(IntMask, ErrIntMask_0) |
6535 SYM_MASK(IntMask, SendDoneIntMask_0));
6537 /* Make sure port is disabled. */
6538 qib_write_kreg_port(ppd, krp_rcvctrl, 0);
6539 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0);
6540 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6541 IBSerdesPClkNotDetectMask_1)
6542 | SYM_MASK(HwErrMask,
6543 SDmaMemReadErrMask_1));
6544 dd->cspec->int_enable_mask &= ~(
6545 SYM_MASK(IntMask, SDmaCleanupDoneMask_1) |
6546 SYM_MASK(IntMask, SDmaIdleIntMask_1) |
6547 SYM_MASK(IntMask, SDmaProgressIntMask_1) |
6548 SYM_MASK(IntMask, SDmaIntMask_1) |
6549 SYM_MASK(IntMask, ErrIntMask_1) |
6550 SYM_MASK(IntMask, SendDoneIntMask_1));
6556 qib_init_pportdata(ppd, dd, pidx, dd->num_pports);
6558 ppd->link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
6559 ppd->link_width_enabled = IB_WIDTH_4X;
6560 ppd->link_speed_enabled = ppd->link_speed_supported;
6562 * Set the initial values to reasonable default, will be set
6563 * for real when link is up.
6565 ppd->link_width_active = IB_WIDTH_4X;
6566 ppd->link_speed_active = QIB_IB_SDR;
6567 ppd->delay_mult = ib_rate_to_delay[IB_RATE_10_GBPS];
6568 switch (qib_num_cfg_vls) {
6570 ppd->vls_supported = IB_VL_VL0;
6573 ppd->vls_supported = IB_VL_VL0_1;
6576 qib_devinfo(dd->pcidev,
6577 "Invalid num_vls %u, using 4 VLs\n",
6579 qib_num_cfg_vls = 4;
6582 ppd->vls_supported = IB_VL_VL0_3;
6586 ppd->vls_supported = IB_VL_VL0_7;
6588 qib_devinfo(dd->pcidev,
6589 "Invalid num_vls %u for MTU %d "
6591 qib_num_cfg_vls, mtu);
6592 ppd->vls_supported = IB_VL_VL0_3;
6593 qib_num_cfg_vls = 4;
6597 ppd->vls_operational = ppd->vls_supported;
6599 init_waitqueue_head(&cp->autoneg_wait);
6600 INIT_DELAYED_WORK(&cp->autoneg_work,
6602 if (ppd->dd->cspec->r1)
6603 INIT_DELAYED_WORK(&cp->ipg_work, ipg_7322_work);
6606 * For Mez and similar cards, no qsfp info, so do
6607 * the "cable info" setup here. Can be overridden
6608 * in adapter-specific routines.
6610 if (!(dd->flags & QIB_HAS_QSFP)) {
6611 if (!IS_QMH(dd) && !IS_QME(dd))
6612 qib_devinfo(dd->pcidev,
6613 "IB%u:%u: Unknown mezzanine card type\n",
6614 dd->unit, ppd->port);
6615 cp->h1_val = IS_QMH(dd) ? H1_FORCE_QMH : H1_FORCE_QME;
6617 * Choose center value as default tx serdes setting
6618 * until changed through module parameter.
6620 ppd->cpspec->no_eep = IS_QMH(dd) ?
6621 TXDDS_TABLE_SZ + 2 : TXDDS_TABLE_SZ + 4;
6623 cp->h1_val = H1_FORCE_VAL;
6625 /* Avoid writes to chip for mini_init */
6627 write_7322_init_portregs(ppd);
6629 init_timer(&cp->chase_timer);
6630 cp->chase_timer.function = reenable_chase;
6631 cp->chase_timer.data = (unsigned long)ppd;
6636 dd->rcvhdrentsize = qib_rcvhdrentsize ?
6637 qib_rcvhdrentsize : QIB_RCVHDR_ENTSIZE;
6638 dd->rcvhdrsize = qib_rcvhdrsize ?
6639 qib_rcvhdrsize : QIB_DFLT_RCVHDRSIZE;
6640 dd->rhf_offset = dd->rcvhdrentsize - sizeof(u64) / sizeof(u32);
6642 /* we always allocate at least 2048 bytes for eager buffers */
6643 dd->rcvegrbufsize = max(mtu, 2048);
6644 BUG_ON(!is_power_of_2(dd->rcvegrbufsize));
6645 dd->rcvegrbufsize_shift = ilog2(dd->rcvegrbufsize);
6647 qib_7322_tidtemplate(dd);
6650 * We can request a receive interrupt for 1 or
6651 * more packets from current offset.
6653 dd->rhdrhead_intr_off =
6654 (u64) rcv_int_count << IBA7322_HDRHEAD_PKTINT_SHIFT;
6656 /* setup the stats timer; the add_timer is done at end of init */
6657 init_timer(&dd->stats_timer);
6658 dd->stats_timer.function = qib_get_7322_faststats;
6659 dd->stats_timer.data = (unsigned long) dd;
6661 dd->ureg_align = 0x10000; /* 64KB alignment */
6663 dd->piosize2kmax_dwords = dd->piosize2k >> 2;
6665 qib_7322_config_ctxts(dd);
6666 qib_set_ctxtcnt(dd);
6669 resource_size_t vl15off;
6671 * We do not set WC on the VL15 buffers to avoid
6672 * a rare problem with unaligned writes from
6673 * interrupt-flushed store buffers, so we need
6674 * to map those separately here. We can't solve
6675 * this for the rarely used mtrr case.
6677 ret = init_chip_wc_pat(dd, 0);
6681 /* vl15 buffers start just after the 4k buffers */
6682 vl15off = dd->physaddr + (dd->piobufbase >> 32) +
6683 dd->piobcnt4k * dd->align4k;
6684 dd->piovl15base = ioremap_nocache(vl15off,
6685 NUM_VL15_BUFS * dd->align4k);
6686 if (!dd->piovl15base) {
6691 qib_7322_set_baseaddrs(dd); /* set chip access pointers now */
6696 if (!dd->num_pports) {
6697 qib_dev_err(dd, "No ports enabled, giving up initialization\n");
6698 goto bail; /* no error, so can still figure out why err */
6701 write_7322_initregs(dd);
6702 ret = qib_create_ctxts(dd);
6703 init_7322_cntrnames(dd);
6705 updthresh = 8U; /* update threshold */
6707 /* use all of 4KB buffers for the kernel SDMA, zero if !SDMA.
6708 * reserve the update threshold amount for other kernel use, such
6709 * as sending SMI, MAD, and ACKs, or 3, whichever is greater,
6710 * unless we aren't enabling SDMA, in which case we want to use
6711 * all the 4k bufs for the kernel.
6712 * if this was less than the update threshold, we could wait
6713 * a long time for an update. Coded this way because we
6714 * sometimes change the update threshold for various reasons,
6715 * and we want this to remain robust.
6717 if (dd->flags & QIB_HAS_SEND_DMA) {
6718 dd->cspec->sdmabufcnt = dd->piobcnt4k;
6719 sbufs = updthresh > 3 ? updthresh : 3;
6721 dd->cspec->sdmabufcnt = 0;
6722 sbufs = dd->piobcnt4k;
6724 dd->cspec->lastbuf_for_pio = dd->piobcnt2k + dd->piobcnt4k -
6725 dd->cspec->sdmabufcnt;
6726 dd->lastctxt_piobuf = dd->cspec->lastbuf_for_pio - sbufs;
6727 dd->cspec->lastbuf_for_pio--; /* range is <= , not < */
6728 dd->last_pio = dd->cspec->lastbuf_for_pio;
6729 dd->pbufsctxt = (dd->cfgctxts > dd->first_user_ctxt) ?
6730 dd->lastctxt_piobuf / (dd->cfgctxts - dd->first_user_ctxt) : 0;
6733 * If we have 16 user contexts, we will have 7 sbufs
6734 * per context, so reduce the update threshold to match. We
6735 * want to update before we actually run out, at low pbufs/ctxt
6736 * so give ourselves some margin.
6738 if (dd->pbufsctxt >= 2 && dd->pbufsctxt - 2 < updthresh)
6739 updthresh = dd->pbufsctxt - 2;
6740 dd->cspec->updthresh_dflt = updthresh;
6741 dd->cspec->updthresh = updthresh;
6743 /* before full enable, no interrupts, no locking needed */
6744 dd->sendctrl |= ((updthresh & SYM_RMASK(SendCtrl, AvailUpdThld))
6745 << SYM_LSB(SendCtrl, AvailUpdThld)) |
6746 SYM_MASK(SendCtrl, SendBufAvailPad64Byte);
6748 dd->psxmitwait_supported = 1;
6749 dd->psxmitwait_check_rate = QIB_7322_PSXMITWAIT_CHECK_RATE;
6752 dd->ctxtcnt = 1; /* for other initialization code */
6757 static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *ppd, u64 pbc,
6760 u32 first, last, plen = pbc & QIB_PBC_LENGTH_MASK;
6761 struct qib_devdata *dd = ppd->dd;
6763 /* last is same for 2k and 4k, because we use 4k if all 2k busy */
6764 if (pbc & PBC_7322_VL15_SEND) {
6765 first = dd->piobcnt2k + dd->piobcnt4k + ppd->hw_pidx;
6768 if ((plen + 1) > dd->piosize2kmax_dwords)
6769 first = dd->piobcnt2k;
6772 last = dd->cspec->lastbuf_for_pio;
6774 return qib_getsendbuf_range(dd, pbufnum, first, last);
6777 static void qib_set_cntr_7322_sample(struct qib_pportdata *ppd, u32 intv,
6780 qib_write_kreg_port(ppd, krp_psinterval, intv);
6781 qib_write_kreg_port(ppd, krp_psstart, start);
6785 * Must be called with sdma_lock held, or before init finished.
6787 static void qib_sdma_set_7322_desc_cnt(struct qib_pportdata *ppd, unsigned cnt)
6789 qib_write_kreg_port(ppd, krp_senddmadesccnt, cnt);
6793 * sdma_lock should be acquired before calling this routine
6795 static void dump_sdma_7322_state(struct qib_pportdata *ppd)
6797 u64 reg, reg1, reg2;
6799 reg = qib_read_kreg_port(ppd, krp_senddmastatus);
6800 qib_dev_porterr(ppd->dd, ppd->port,
6801 "SDMA senddmastatus: 0x%016llx\n", reg);
6803 reg = qib_read_kreg_port(ppd, krp_sendctrl);
6804 qib_dev_porterr(ppd->dd, ppd->port,
6805 "SDMA sendctrl: 0x%016llx\n", reg);
6807 reg = qib_read_kreg_port(ppd, krp_senddmabase);
6808 qib_dev_porterr(ppd->dd, ppd->port,
6809 "SDMA senddmabase: 0x%016llx\n", reg);
6811 reg = qib_read_kreg_port(ppd, krp_senddmabufmask0);
6812 reg1 = qib_read_kreg_port(ppd, krp_senddmabufmask1);
6813 reg2 = qib_read_kreg_port(ppd, krp_senddmabufmask2);
6814 qib_dev_porterr(ppd->dd, ppd->port,
6815 "SDMA senddmabufmask 0:%llx 1:%llx 2:%llx\n",
6818 /* get bufuse bits, clear them, and print them again if non-zero */
6819 reg = qib_read_kreg_port(ppd, krp_senddmabuf_use0);
6820 qib_write_kreg_port(ppd, krp_senddmabuf_use0, reg);
6821 reg1 = qib_read_kreg_port(ppd, krp_senddmabuf_use1);
6822 qib_write_kreg_port(ppd, krp_senddmabuf_use0, reg1);
6823 reg2 = qib_read_kreg_port(ppd, krp_senddmabuf_use2);
6824 qib_write_kreg_port(ppd, krp_senddmabuf_use0, reg2);
6825 /* 0 and 1 should always be zero, so print as short form */
6826 qib_dev_porterr(ppd->dd, ppd->port,
6827 "SDMA current senddmabuf_use 0:%llx 1:%llx 2:%llx\n",
6829 reg = qib_read_kreg_port(ppd, krp_senddmabuf_use0);
6830 reg1 = qib_read_kreg_port(ppd, krp_senddmabuf_use1);
6831 reg2 = qib_read_kreg_port(ppd, krp_senddmabuf_use2);
6832 /* 0 and 1 should always be zero, so print as short form */
6833 qib_dev_porterr(ppd->dd, ppd->port,
6834 "SDMA cleared senddmabuf_use 0:%llx 1:%llx 2:%llx\n",
6837 reg = qib_read_kreg_port(ppd, krp_senddmatail);
6838 qib_dev_porterr(ppd->dd, ppd->port,
6839 "SDMA senddmatail: 0x%016llx\n", reg);
6841 reg = qib_read_kreg_port(ppd, krp_senddmahead);
6842 qib_dev_porterr(ppd->dd, ppd->port,
6843 "SDMA senddmahead: 0x%016llx\n", reg);
6845 reg = qib_read_kreg_port(ppd, krp_senddmaheadaddr);
6846 qib_dev_porterr(ppd->dd, ppd->port,
6847 "SDMA senddmaheadaddr: 0x%016llx\n", reg);
6849 reg = qib_read_kreg_port(ppd, krp_senddmalengen);
6850 qib_dev_porterr(ppd->dd, ppd->port,
6851 "SDMA senddmalengen: 0x%016llx\n", reg);
6853 reg = qib_read_kreg_port(ppd, krp_senddmadesccnt);
6854 qib_dev_porterr(ppd->dd, ppd->port,
6855 "SDMA senddmadesccnt: 0x%016llx\n", reg);
6857 reg = qib_read_kreg_port(ppd, krp_senddmaidlecnt);
6858 qib_dev_porterr(ppd->dd, ppd->port,
6859 "SDMA senddmaidlecnt: 0x%016llx\n", reg);
6861 reg = qib_read_kreg_port(ppd, krp_senddmaprioritythld);
6862 qib_dev_porterr(ppd->dd, ppd->port,
6863 "SDMA senddmapriorityhld: 0x%016llx\n", reg);
6865 reg = qib_read_kreg_port(ppd, krp_senddmareloadcnt);
6866 qib_dev_porterr(ppd->dd, ppd->port,
6867 "SDMA senddmareloadcnt: 0x%016llx\n", reg);
6869 dump_sdma_state(ppd);
6872 static struct sdma_set_state_action sdma_7322_action_table[] = {
6873 [qib_sdma_state_s00_hw_down] = {
6874 .go_s99_running_tofalse = 1,
6880 [qib_sdma_state_s10_hw_start_up_wait] = {
6886 [qib_sdma_state_s20_idle] = {
6892 [qib_sdma_state_s30_sw_clean_up_wait] = {
6898 [qib_sdma_state_s40_hw_clean_up_wait] = {
6904 [qib_sdma_state_s50_hw_halt_wait] = {
6910 [qib_sdma_state_s99_running] = {
6915 .go_s99_running_totrue = 1,
6919 static void qib_7322_sdma_init_early(struct qib_pportdata *ppd)
6921 ppd->sdma_state.set_state_action = sdma_7322_action_table;
6924 static int init_sdma_7322_regs(struct qib_pportdata *ppd)
6926 struct qib_devdata *dd = ppd->dd;
6927 unsigned lastbuf, erstbuf;
6928 u64 senddmabufmask[3] = { 0 };
6931 qib_write_kreg_port(ppd, krp_senddmabase, ppd->sdma_descq_phys);
6932 qib_sdma_7322_setlengen(ppd);
6933 qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */
6934 qib_write_kreg_port(ppd, krp_senddmareloadcnt, sdma_idle_cnt);
6935 qib_write_kreg_port(ppd, krp_senddmadesccnt, 0);
6936 qib_write_kreg_port(ppd, krp_senddmaheadaddr, ppd->sdma_head_phys);
6939 n = dd->cspec->sdmabufcnt / dd->num_pports; /* no remainder */
6941 n = dd->cspec->sdmabufcnt; /* failsafe for init */
6942 erstbuf = (dd->piobcnt2k + dd->piobcnt4k) -
6943 ((dd->num_pports == 1 || ppd->port == 2) ? n :
6944 dd->cspec->sdmabufcnt);
6945 lastbuf = erstbuf + n;
6947 ppd->sdma_state.first_sendbuf = erstbuf;
6948 ppd->sdma_state.last_sendbuf = lastbuf;
6949 for (; erstbuf < lastbuf; ++erstbuf) {
6950 unsigned word = erstbuf / BITS_PER_LONG;
6951 unsigned bit = erstbuf & (BITS_PER_LONG - 1);
6954 senddmabufmask[word] |= 1ULL << bit;
6956 qib_write_kreg_port(ppd, krp_senddmabufmask0, senddmabufmask[0]);
6957 qib_write_kreg_port(ppd, krp_senddmabufmask1, senddmabufmask[1]);
6958 qib_write_kreg_port(ppd, krp_senddmabufmask2, senddmabufmask[2]);
6962 /* sdma_lock must be held */
6963 static u16 qib_sdma_7322_gethead(struct qib_pportdata *ppd)
6965 struct qib_devdata *dd = ppd->dd;
6973 use_dmahead = __qib_sdma_running(ppd) &&
6974 (dd->flags & QIB_HAS_SDMA_TIMEOUT);
6976 hwhead = use_dmahead ?
6977 (u16) le64_to_cpu(*ppd->sdma_head_dma) :
6978 (u16) qib_read_kreg_port(ppd, krp_senddmahead);
6980 swhead = ppd->sdma_descq_head;
6981 swtail = ppd->sdma_descq_tail;
6982 cnt = ppd->sdma_descq_cnt;
6984 if (swhead < swtail)
6986 sane = (hwhead >= swhead) & (hwhead <= swtail);
6987 else if (swhead > swtail)
6988 /* wrapped around */
6989 sane = ((hwhead >= swhead) && (hwhead < cnt)) ||
6993 sane = (hwhead == swhead);
6995 if (unlikely(!sane)) {
6997 /* try one more time, directly from the register */
7001 /* proceed as if no progress */
7008 static int qib_sdma_7322_busy(struct qib_pportdata *ppd)
7010 u64 hwstatus = qib_read_kreg_port(ppd, krp_senddmastatus);
7012 return (hwstatus & SYM_MASK(SendDmaStatus_0, ScoreBoardDrainInProg)) ||
7013 (hwstatus & SYM_MASK(SendDmaStatus_0, HaltInProg)) ||
7014 !(hwstatus & SYM_MASK(SendDmaStatus_0, InternalSDmaHalt)) ||
7015 !(hwstatus & SYM_MASK(SendDmaStatus_0, ScbEmpty));
7019 * Compute the amount of delay before sending the next packet if the
7020 * port's send rate differs from the static rate set for the QP.
7021 * The delay affects the next packet and the amount of the delay is
7022 * based on the length of the this packet.
7024 static u32 qib_7322_setpbc_control(struct qib_pportdata *ppd, u32 plen,
7027 u8 snd_mult = ppd->delay_mult;
7028 u8 rcv_mult = ib_rate_to_delay[srate];
7031 ret = rcv_mult > snd_mult ? ((plen + 1) >> 1) * snd_mult : 0;
7033 /* Indicate VL15, else set the VL in the control word */
7035 ret |= PBC_7322_VL15_SEND_CTRL;
7037 ret |= vl << PBC_VL_NUM_LSB;
7038 ret |= ((u32)(ppd->hw_pidx)) << PBC_PORT_SEL_LSB;
7044 * Enable the per-port VL15 send buffers for use.
7045 * They follow the rest of the buffers, without a config parameter.
7046 * This was in initregs, but that is done before the shadow
7047 * is set up, and this has to be done after the shadow is
7050 static void qib_7322_initvl15_bufs(struct qib_devdata *dd)
7054 vl15bufs = dd->piobcnt2k + dd->piobcnt4k;
7055 qib_chg_pioavailkernel(dd, vl15bufs, NUM_VL15_BUFS,
7056 TXCHK_CHG_TYPE_KERN, NULL);
7059 static void qib_7322_init_ctxt(struct qib_ctxtdata *rcd)
7061 if (rcd->ctxt < NUM_IB_PORTS) {
7062 if (rcd->dd->num_pports > 1) {
7063 rcd->rcvegrcnt = KCTXT0_EGRCNT / 2;
7064 rcd->rcvegr_tid_base = rcd->ctxt ? rcd->rcvegrcnt : 0;
7066 rcd->rcvegrcnt = KCTXT0_EGRCNT;
7067 rcd->rcvegr_tid_base = 0;
7070 rcd->rcvegrcnt = rcd->dd->cspec->rcvegrcnt;
7071 rcd->rcvegr_tid_base = KCTXT0_EGRCNT +
7072 (rcd->ctxt - NUM_IB_PORTS) * rcd->rcvegrcnt;
7076 #define QTXSLEEPS 5000
7077 static void qib_7322_txchk_change(struct qib_devdata *dd, u32 start,
7078 u32 len, u32 which, struct qib_ctxtdata *rcd)
7081 const int last = start + len - 1;
7082 const int lastr = last / BITS_PER_LONG;
7084 int wait = rcd != NULL;
7085 unsigned long flags;
7088 unsigned long shadow;
7089 int cstart, previ = -1;
7092 * when flipping from kernel to user, we can't change
7093 * the checking type if the buffer is allocated to the
7094 * driver. It's OK the other direction, because it's
7095 * from close, and we have just disarm'ed all the
7096 * buffers. All the kernel to kernel changes are also
7099 for (cstart = start; cstart <= last; cstart++) {
7100 i = ((2 * cstart) + QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT)
7103 shadow = (unsigned long)
7104 le64_to_cpu(dd->pioavailregs_dma[i]);
7107 if (test_bit(((2 * cstart) +
7108 QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT)
7109 % BITS_PER_LONG, &shadow))
7116 if (sleeps == QTXSLEEPS)
7118 /* make sure we see an updated copy next time around */
7119 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
7125 case TXCHK_CHG_TYPE_DIS1:
7127 * disable checking on a range; used by diags; just
7128 * one buffer, but still written generically
7130 for (i = start; i <= last; i++)
7131 clear_bit(i, dd->cspec->sendchkenable);
7134 case TXCHK_CHG_TYPE_ENAB1:
7136 * (re)enable checking on a range; used by diags; just
7137 * one buffer, but still written generically; read
7138 * scratch to be sure buffer actually triggered, not
7139 * just flushed from processor.
7141 qib_read_kreg32(dd, kr_scratch);
7142 for (i = start; i <= last; i++)
7143 set_bit(i, dd->cspec->sendchkenable);
7146 case TXCHK_CHG_TYPE_KERN:
7147 /* usable by kernel */
7148 for (i = start; i <= last; i++) {
7149 set_bit(i, dd->cspec->sendibchk);
7150 clear_bit(i, dd->cspec->sendgrhchk);
7152 spin_lock_irqsave(&dd->uctxt_lock, flags);
7153 /* see if we need to raise avail update threshold */
7154 for (i = dd->first_user_ctxt;
7155 dd->cspec->updthresh != dd->cspec->updthresh_dflt
7156 && i < dd->cfgctxts; i++)
7157 if (dd->rcd[i] && dd->rcd[i]->subctxt_cnt &&
7158 ((dd->rcd[i]->piocnt / dd->rcd[i]->subctxt_cnt) - 1)
7159 < dd->cspec->updthresh_dflt)
7161 spin_unlock_irqrestore(&dd->uctxt_lock, flags);
7162 if (i == dd->cfgctxts) {
7163 spin_lock_irqsave(&dd->sendctrl_lock, flags);
7164 dd->cspec->updthresh = dd->cspec->updthresh_dflt;
7165 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
7166 dd->sendctrl |= (dd->cspec->updthresh &
7167 SYM_RMASK(SendCtrl, AvailUpdThld)) <<
7168 SYM_LSB(SendCtrl, AvailUpdThld);
7169 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
7170 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
7174 case TXCHK_CHG_TYPE_USER:
7175 /* for user process */
7176 for (i = start; i <= last; i++) {
7177 clear_bit(i, dd->cspec->sendibchk);
7178 set_bit(i, dd->cspec->sendgrhchk);
7180 spin_lock_irqsave(&dd->sendctrl_lock, flags);
7181 if (rcd && rcd->subctxt_cnt && ((rcd->piocnt
7182 / rcd->subctxt_cnt) - 1) < dd->cspec->updthresh) {
7183 dd->cspec->updthresh = (rcd->piocnt /
7184 rcd->subctxt_cnt) - 1;
7185 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
7186 dd->sendctrl |= (dd->cspec->updthresh &
7187 SYM_RMASK(SendCtrl, AvailUpdThld))
7188 << SYM_LSB(SendCtrl, AvailUpdThld);
7189 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
7190 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
7192 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
7199 for (i = start / BITS_PER_LONG; which >= 2 && i <= lastr; ++i)
7200 qib_write_kreg(dd, kr_sendcheckmask + i,
7201 dd->cspec->sendchkenable[i]);
7203 for (i = start / BITS_PER_LONG; which < 2 && i <= lastr; ++i) {
7204 qib_write_kreg(dd, kr_sendgrhcheckmask + i,
7205 dd->cspec->sendgrhchk[i]);
7206 qib_write_kreg(dd, kr_sendibpktmask + i,
7207 dd->cspec->sendibchk[i]);
7211 * Be sure whatever we did was seen by the chip and acted upon,
7212 * before we return. Mostly important for which >= 2.
7214 qib_read_kreg32(dd, kr_scratch);
7218 /* useful for trigger analyzers, etc. */
7219 static void writescratch(struct qib_devdata *dd, u32 val)
7221 qib_write_kreg(dd, kr_scratch, val);
7224 /* Dummy for now, use chip regs soon */
7225 static int qib_7322_tempsense_rd(struct qib_devdata *dd, int regnum)
7231 * qib_init_iba7322_funcs - set up the chip-specific function pointers
7232 * @dev: the pci_dev for qlogic_ib device
7233 * @ent: pci_device_id struct for this dev
7235 * Also allocates, inits, and returns the devdata struct for this
7238 * This is global, and is called directly at init to set up the
7239 * chip-specific function pointers for later use.
7241 struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *pdev,
7242 const struct pci_device_id *ent)
7244 struct qib_devdata *dd;
7246 u32 tabsize, actual_cnt = 0;
7248 dd = qib_alloc_devdata(pdev,
7249 NUM_IB_PORTS * sizeof(struct qib_pportdata) +
7250 sizeof(struct qib_chip_specific) +
7251 NUM_IB_PORTS * sizeof(struct qib_chippport_specific));
7255 dd->f_bringup_serdes = qib_7322_bringup_serdes;
7256 dd->f_cleanup = qib_setup_7322_cleanup;
7257 dd->f_clear_tids = qib_7322_clear_tids;
7258 dd->f_free_irq = qib_7322_free_irq;
7259 dd->f_get_base_info = qib_7322_get_base_info;
7260 dd->f_get_msgheader = qib_7322_get_msgheader;
7261 dd->f_getsendbuf = qib_7322_getsendbuf;
7262 dd->f_gpio_mod = gpio_7322_mod;
7263 dd->f_eeprom_wen = qib_7322_eeprom_wen;
7264 dd->f_hdrqempty = qib_7322_hdrqempty;
7265 dd->f_ib_updown = qib_7322_ib_updown;
7266 dd->f_init_ctxt = qib_7322_init_ctxt;
7267 dd->f_initvl15_bufs = qib_7322_initvl15_bufs;
7268 dd->f_intr_fallback = qib_7322_intr_fallback;
7269 dd->f_late_initreg = qib_late_7322_initreg;
7270 dd->f_setpbc_control = qib_7322_setpbc_control;
7271 dd->f_portcntr = qib_portcntr_7322;
7272 dd->f_put_tid = qib_7322_put_tid;
7273 dd->f_quiet_serdes = qib_7322_mini_quiet_serdes;
7274 dd->f_rcvctrl = rcvctrl_7322_mod;
7275 dd->f_read_cntrs = qib_read_7322cntrs;
7276 dd->f_read_portcntrs = qib_read_7322portcntrs;
7277 dd->f_reset = qib_do_7322_reset;
7278 dd->f_init_sdma_regs = init_sdma_7322_regs;
7279 dd->f_sdma_busy = qib_sdma_7322_busy;
7280 dd->f_sdma_gethead = qib_sdma_7322_gethead;
7281 dd->f_sdma_sendctrl = qib_7322_sdma_sendctrl;
7282 dd->f_sdma_set_desc_cnt = qib_sdma_set_7322_desc_cnt;
7283 dd->f_sdma_update_tail = qib_sdma_update_7322_tail;
7284 dd->f_sendctrl = sendctrl_7322_mod;
7285 dd->f_set_armlaunch = qib_set_7322_armlaunch;
7286 dd->f_set_cntr_sample = qib_set_cntr_7322_sample;
7287 dd->f_iblink_state = qib_7322_iblink_state;
7288 dd->f_ibphys_portstate = qib_7322_phys_portstate;
7289 dd->f_get_ib_cfg = qib_7322_get_ib_cfg;
7290 dd->f_set_ib_cfg = qib_7322_set_ib_cfg;
7291 dd->f_set_ib_loopback = qib_7322_set_loopback;
7292 dd->f_get_ib_table = qib_7322_get_ib_table;
7293 dd->f_set_ib_table = qib_7322_set_ib_table;
7294 dd->f_set_intr_state = qib_7322_set_intr_state;
7295 dd->f_setextled = qib_setup_7322_setextled;
7296 dd->f_txchk_change = qib_7322_txchk_change;
7297 dd->f_update_usrhead = qib_update_7322_usrhead;
7298 dd->f_wantpiobuf_intr = qib_wantpiobuf_7322_intr;
7299 dd->f_xgxs_reset = qib_7322_mini_pcs_reset;
7300 dd->f_sdma_hw_clean_up = qib_7322_sdma_hw_clean_up;
7301 dd->f_sdma_hw_start_up = qib_7322_sdma_hw_start_up;
7302 dd->f_sdma_init_early = qib_7322_sdma_init_early;
7303 dd->f_writescratch = writescratch;
7304 dd->f_tempsense_rd = qib_7322_tempsense_rd;
7305 #ifdef CONFIG_INFINIBAND_QIB_DCA
7306 dd->f_notify_dca = qib_7322_notify_dca;
7309 * Do remaining PCIe setup and save PCIe values in dd.
7310 * Any error printing is already done by the init code.
7311 * On return, we have the chip mapped, but chip registers
7312 * are not set up until start of qib_init_7322_variables.
7314 ret = qib_pcie_ddinit(dd, pdev, ent);
7318 /* initialize chip-specific variables */
7319 ret = qib_init_7322_variables(dd);
7323 if (qib_mini_init || !dd->num_pports)
7327 * Determine number of vectors we want; depends on port count
7328 * and number of configured kernel receive queues actually used.
7329 * Should also depend on whether sdma is enabled or not, but
7330 * that's such a rare testing case it's not worth worrying about.
7332 tabsize = dd->first_user_ctxt + ARRAY_SIZE(irq_table);
7333 for (i = 0; i < tabsize; i++)
7334 if ((i < ARRAY_SIZE(irq_table) &&
7335 irq_table[i].port <= dd->num_pports) ||
7336 (i >= ARRAY_SIZE(irq_table) &&
7337 dd->rcd[i - ARRAY_SIZE(irq_table)]))
7339 /* reduce by ctxt's < 2 */
7340 if (qib_krcvq01_no_msi)
7341 actual_cnt -= dd->num_pports;
7343 tabsize = actual_cnt;
7344 dd->cspec->msix_entries = kzalloc(tabsize *
7345 sizeof(struct qib_msix_entry), GFP_KERNEL);
7346 if (!dd->cspec->msix_entries) {
7347 qib_dev_err(dd, "No memory for MSIx table\n");
7350 for (i = 0; i < tabsize; i++)
7351 dd->cspec->msix_entries[i].msix.entry = i;
7353 if (qib_pcie_params(dd, 8, &tabsize, dd->cspec->msix_entries))
7355 "Failed to setup PCIe or interrupts; continuing anyway\n");
7356 /* may be less than we wanted, if not enough available */
7357 dd->cspec->num_msix_entries = tabsize;
7359 /* setup interrupt handler */
7360 qib_setup_7322_interrupt(dd, 1);
7362 /* clear diagctrl register, in case diags were running and crashed */
7363 qib_write_kreg(dd, kr_hwdiagctrl, 0);
7364 #ifdef CONFIG_INFINIBAND_QIB_DCA
7365 if (!dca_add_requester(&pdev->dev)) {
7366 qib_devinfo(dd->pcidev, "DCA enabled\n");
7367 dd->flags |= QIB_DCA_ENABLED;
7374 qib_pcie_ddcleanup(dd);
7376 qib_free_devdata(dd);
7383 * Set the table entry at the specified index from the table specifed.
7384 * There are 3 * TXDDS_TABLE_SZ entries in all per port, with the first
7385 * TXDDS_TABLE_SZ for SDR, the next for DDR, and the last for QDR.
7386 * 'idx' below addresses the correct entry, while its 4 LSBs select the
7387 * corresponding entry (one of TXDDS_TABLE_SZ) from the selected table.
7389 #define DDS_ENT_AMP_LSB 14
7390 #define DDS_ENT_MAIN_LSB 9
7391 #define DDS_ENT_POST_LSB 5
7392 #define DDS_ENT_PRE_XTRA_LSB 3
7393 #define DDS_ENT_PRE_LSB 0
7396 * Set one entry in the TxDDS table for spec'd port
7397 * ridx picks one of the entries, while tp points
7398 * to the appropriate table entry.
7400 static void set_txdds(struct qib_pportdata *ppd, int ridx,
7401 const struct txdds_ent *tp)
7403 struct qib_devdata *dd = ppd->dd;
7407 /* Get correct offset in chip-space, and in source table */
7408 regidx = KREG_IBPORT_IDX(IBSD_DDS_MAP_TABLE) + ridx;
7410 * We do not use qib_write_kreg_port() because it was intended
7411 * only for registers in the lower "port specific" pages.
7412 * So do index calculation by hand.
7415 regidx += (dd->palign / sizeof(u64));
7417 pack_ent = tp->amp << DDS_ENT_AMP_LSB;
7418 pack_ent |= tp->main << DDS_ENT_MAIN_LSB;
7419 pack_ent |= tp->pre << DDS_ENT_PRE_LSB;
7420 pack_ent |= tp->post << DDS_ENT_POST_LSB;
7421 qib_write_kreg(dd, regidx, pack_ent);
7422 /* Prevent back-to-back writes by hitting scratch */
7423 qib_write_kreg(ppd->dd, kr_scratch, 0);
7426 static const struct vendor_txdds_ent vendor_txdds[] = {
7427 { /* Amphenol 1m 30awg NoEq */
7428 { 0x41, 0x50, 0x48 }, "584470002 ",
7429 { 10, 0, 0, 5 }, { 10, 0, 0, 9 }, { 7, 1, 0, 13 },
7431 { /* Amphenol 3m 28awg NoEq */
7432 { 0x41, 0x50, 0x48 }, "584470004 ",
7433 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 7, 15 },
7435 { /* Finisar 3m OM2 Optical */
7436 { 0x00, 0x90, 0x65 }, "FCBG410QB1C03-QL",
7437 { 0, 0, 0, 3 }, { 0, 0, 0, 4 }, { 0, 0, 0, 13 },
7439 { /* Finisar 30m OM2 Optical */
7440 { 0x00, 0x90, 0x65 }, "FCBG410QB1C30-QL",
7441 { 0, 0, 0, 1 }, { 0, 0, 0, 5 }, { 0, 0, 0, 11 },
7443 { /* Finisar Default OM2 Optical */
7444 { 0x00, 0x90, 0x65 }, NULL,
7445 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 0, 0, 12 },
7447 { /* Gore 1m 30awg NoEq */
7448 { 0x00, 0x21, 0x77 }, "QSN3300-1 ",
7449 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 0, 15 },
7451 { /* Gore 2m 30awg NoEq */
7452 { 0x00, 0x21, 0x77 }, "QSN3300-2 ",
7453 { 0, 0, 0, 8 }, { 0, 0, 0, 10 }, { 0, 1, 7, 15 },
7455 { /* Gore 1m 28awg NoEq */
7456 { 0x00, 0x21, 0x77 }, "QSN3800-1 ",
7457 { 0, 0, 0, 6 }, { 0, 0, 0, 8 }, { 0, 1, 0, 15 },
7459 { /* Gore 3m 28awg NoEq */
7460 { 0x00, 0x21, 0x77 }, "QSN3800-3 ",
7461 { 0, 0, 0, 9 }, { 0, 0, 0, 13 }, { 0, 1, 7, 15 },
7463 { /* Gore 5m 24awg Eq */
7464 { 0x00, 0x21, 0x77 }, "QSN7000-5 ",
7465 { 0, 0, 0, 7 }, { 0, 0, 0, 9 }, { 0, 1, 3, 15 },
7467 { /* Gore 7m 24awg Eq */
7468 { 0x00, 0x21, 0x77 }, "QSN7000-7 ",
7469 { 0, 0, 0, 9 }, { 0, 0, 0, 11 }, { 0, 2, 6, 15 },
7471 { /* Gore 5m 26awg Eq */
7472 { 0x00, 0x21, 0x77 }, "QSN7600-5 ",
7473 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 9, 13 },
7475 { /* Gore 7m 26awg Eq */
7476 { 0x00, 0x21, 0x77 }, "QSN7600-7 ",
7477 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 10, 1, 8, 15 },
7479 { /* Intersil 12m 24awg Active */
7480 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1224",
7481 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 3, 0, 9 },
7483 { /* Intersil 10m 28awg Active */
7484 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1028",
7485 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 2, 0, 2 },
7487 { /* Intersil 7m 30awg Active */
7488 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0730",
7489 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 1, 0, 3 },
7491 { /* Intersil 5m 32awg Active */
7492 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0532",
7493 { 0, 0, 0, 6 }, { 0, 0, 0, 6 }, { 0, 2, 0, 8 },
7495 { /* Intersil Default Active */
7496 { 0x00, 0x30, 0xB4 }, NULL,
7497 { 0, 0, 0, 6 }, { 0, 0, 0, 5 }, { 0, 2, 0, 5 },
7499 { /* Luxtera 20m Active Optical */
7500 { 0x00, 0x25, 0x63 }, NULL,
7501 { 0, 0, 0, 5 }, { 0, 0, 0, 8 }, { 0, 2, 0, 12 },
7503 { /* Molex 1M Cu loopback */
7504 { 0x00, 0x09, 0x3A }, "74763-0025 ",
7505 { 2, 2, 6, 15 }, { 2, 2, 6, 15 }, { 2, 2, 6, 15 },
7507 { /* Molex 2m 28awg NoEq */
7508 { 0x00, 0x09, 0x3A }, "74757-2201 ",
7509 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 1, 15 },
7513 static const struct txdds_ent txdds_sdr[TXDDS_TABLE_SZ] = {
7514 /* amp, pre, main, post */
7515 { 2, 2, 15, 6 }, /* Loopback */
7516 { 0, 0, 0, 1 }, /* 2 dB */
7517 { 0, 0, 0, 2 }, /* 3 dB */
7518 { 0, 0, 0, 3 }, /* 4 dB */
7519 { 0, 0, 0, 4 }, /* 5 dB */
7520 { 0, 0, 0, 5 }, /* 6 dB */
7521 { 0, 0, 0, 6 }, /* 7 dB */
7522 { 0, 0, 0, 7 }, /* 8 dB */
7523 { 0, 0, 0, 8 }, /* 9 dB */
7524 { 0, 0, 0, 9 }, /* 10 dB */
7525 { 0, 0, 0, 10 }, /* 11 dB */
7526 { 0, 0, 0, 11 }, /* 12 dB */
7527 { 0, 0, 0, 12 }, /* 13 dB */
7528 { 0, 0, 0, 13 }, /* 14 dB */
7529 { 0, 0, 0, 14 }, /* 15 dB */
7530 { 0, 0, 0, 15 }, /* 16 dB */
7533 static const struct txdds_ent txdds_ddr[TXDDS_TABLE_SZ] = {
7534 /* amp, pre, main, post */
7535 { 2, 2, 15, 6 }, /* Loopback */
7536 { 0, 0, 0, 8 }, /* 2 dB */
7537 { 0, 0, 0, 8 }, /* 3 dB */
7538 { 0, 0, 0, 9 }, /* 4 dB */
7539 { 0, 0, 0, 9 }, /* 5 dB */
7540 { 0, 0, 0, 10 }, /* 6 dB */
7541 { 0, 0, 0, 10 }, /* 7 dB */
7542 { 0, 0, 0, 11 }, /* 8 dB */
7543 { 0, 0, 0, 11 }, /* 9 dB */
7544 { 0, 0, 0, 12 }, /* 10 dB */
7545 { 0, 0, 0, 12 }, /* 11 dB */
7546 { 0, 0, 0, 13 }, /* 12 dB */
7547 { 0, 0, 0, 13 }, /* 13 dB */
7548 { 0, 0, 0, 14 }, /* 14 dB */
7549 { 0, 0, 0, 14 }, /* 15 dB */
7550 { 0, 0, 0, 15 }, /* 16 dB */
7553 static const struct txdds_ent txdds_qdr[TXDDS_TABLE_SZ] = {
7554 /* amp, pre, main, post */
7555 { 2, 2, 15, 6 }, /* Loopback */
7556 { 0, 1, 0, 7 }, /* 2 dB (also QMH7342) */
7557 { 0, 1, 0, 9 }, /* 3 dB (also QMH7342) */
7558 { 0, 1, 0, 11 }, /* 4 dB */
7559 { 0, 1, 0, 13 }, /* 5 dB */
7560 { 0, 1, 0, 15 }, /* 6 dB */
7561 { 0, 1, 3, 15 }, /* 7 dB */
7562 { 0, 1, 7, 15 }, /* 8 dB */
7563 { 0, 1, 7, 15 }, /* 9 dB */
7564 { 0, 1, 8, 15 }, /* 10 dB */
7565 { 0, 1, 9, 15 }, /* 11 dB */
7566 { 0, 1, 10, 15 }, /* 12 dB */
7567 { 0, 2, 6, 15 }, /* 13 dB */
7568 { 0, 2, 7, 15 }, /* 14 dB */
7569 { 0, 2, 8, 15 }, /* 15 dB */
7570 { 0, 2, 9, 15 }, /* 16 dB */
7574 * extra entries for use with txselect, for indices >= TXDDS_TABLE_SZ.
7575 * These are mostly used for mez cards going through connectors
7576 * and backplane traces, but can be used to add other "unusual"
7577 * table values as well.
7579 static const struct txdds_ent txdds_extra_sdr[TXDDS_EXTRA_SZ] = {
7580 /* amp, pre, main, post */
7581 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */
7582 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */
7583 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */
7584 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */
7585 { 0, 0, 0, 3 }, /* QMH7342 backplane settings */
7586 { 0, 0, 0, 4 }, /* QMH7342 backplane settings */
7587 { 0, 1, 4, 15 }, /* QME7342 backplane settings 1.0 */
7588 { 0, 1, 3, 15 }, /* QME7342 backplane settings 1.0 */
7589 { 0, 1, 0, 12 }, /* QME7342 backplane settings 1.0 */
7590 { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.0 */
7591 { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.0 */
7592 { 0, 1, 0, 14 }, /* QME7342 backplane settings 1.0 */
7593 { 0, 1, 2, 15 }, /* QME7342 backplane settings 1.0 */
7594 { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.1 */
7595 { 0, 1, 0, 7 }, /* QME7342 backplane settings 1.1 */
7596 { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.1 */
7597 { 0, 1, 0, 6 }, /* QME7342 backplane settings 1.1 */
7598 { 0, 1, 0, 8 }, /* QME7342 backplane settings 1.1 */
7601 static const struct txdds_ent txdds_extra_ddr[TXDDS_EXTRA_SZ] = {
7602 /* amp, pre, main, post */
7603 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */
7604 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */
7605 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */
7606 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */
7607 { 0, 0, 0, 9 }, /* QMH7342 backplane settings */
7608 { 0, 0, 0, 10 }, /* QMH7342 backplane settings */
7609 { 0, 1, 4, 15 }, /* QME7342 backplane settings 1.0 */
7610 { 0, 1, 3, 15 }, /* QME7342 backplane settings 1.0 */
7611 { 0, 1, 0, 12 }, /* QME7342 backplane settings 1.0 */
7612 { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.0 */
7613 { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.0 */
7614 { 0, 1, 0, 14 }, /* QME7342 backplane settings 1.0 */
7615 { 0, 1, 2, 15 }, /* QME7342 backplane settings 1.0 */
7616 { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.1 */
7617 { 0, 1, 0, 7 }, /* QME7342 backplane settings 1.1 */
7618 { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.1 */
7619 { 0, 1, 0, 6 }, /* QME7342 backplane settings 1.1 */
7620 { 0, 1, 0, 8 }, /* QME7342 backplane settings 1.1 */
7623 static const struct txdds_ent txdds_extra_qdr[TXDDS_EXTRA_SZ] = {
7624 /* amp, pre, main, post */
7625 { 0, 1, 0, 4 }, /* QMH7342 backplane settings */
7626 { 0, 1, 0, 5 }, /* QMH7342 backplane settings */
7627 { 0, 1, 0, 6 }, /* QMH7342 backplane settings */
7628 { 0, 1, 0, 8 }, /* QMH7342 backplane settings */
7629 { 0, 1, 0, 10 }, /* QMH7342 backplane settings */
7630 { 0, 1, 0, 12 }, /* QMH7342 backplane settings */
7631 { 0, 1, 4, 15 }, /* QME7342 backplane settings 1.0 */
7632 { 0, 1, 3, 15 }, /* QME7342 backplane settings 1.0 */
7633 { 0, 1, 0, 12 }, /* QME7342 backplane settings 1.0 */
7634 { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.0 */
7635 { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.0 */
7636 { 0, 1, 0, 14 }, /* QME7342 backplane settings 1.0 */
7637 { 0, 1, 2, 15 }, /* QME7342 backplane settings 1.0 */
7638 { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.1 */
7639 { 0, 1, 0, 7 }, /* QME7342 backplane settings 1.1 */
7640 { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.1 */
7641 { 0, 1, 0, 6 }, /* QME7342 backplane settings 1.1 */
7642 { 0, 1, 0, 8 }, /* QME7342 backplane settings 1.1 */
7645 static const struct txdds_ent txdds_extra_mfg[TXDDS_MFG_SZ] = {
7646 /* amp, pre, main, post */
7647 { 0, 0, 0, 0 }, /* QME7342 mfg settings */
7648 { 0, 0, 0, 6 }, /* QME7342 P2 mfg settings */
7651 static const struct txdds_ent *get_atten_table(const struct txdds_ent *txdds,
7655 * The attenuation table starts at 2dB for entry 1,
7656 * with entry 0 being the loopback entry.
7660 else if (atten > TXDDS_TABLE_SZ)
7661 atten = TXDDS_TABLE_SZ - 1;
7664 return txdds + atten;
7668 * if override is set, the module parameter txselect has a value
7669 * for this specific port, so use it, rather than our normal mechanism.
7671 static void find_best_ent(struct qib_pportdata *ppd,
7672 const struct txdds_ent **sdr_dds,
7673 const struct txdds_ent **ddr_dds,
7674 const struct txdds_ent **qdr_dds, int override)
7676 struct qib_qsfp_cache *qd = &ppd->cpspec->qsfp_data.cache;
7679 /* Search table of known cables */
7680 for (idx = 0; !override && idx < ARRAY_SIZE(vendor_txdds); ++idx) {
7681 const struct vendor_txdds_ent *v = vendor_txdds + idx;
7683 if (!memcmp(v->oui, qd->oui, QSFP_VOUI_LEN) &&
7685 !memcmp(v->partnum, qd->partnum, QSFP_PN_LEN))) {
7693 /* Active cables don't have attenuation so we only set SERDES
7694 * settings to account for the attenuation of the board traces. */
7695 if (!override && QSFP_IS_ACTIVE(qd->tech)) {
7696 *sdr_dds = txdds_sdr + ppd->dd->board_atten;
7697 *ddr_dds = txdds_ddr + ppd->dd->board_atten;
7698 *qdr_dds = txdds_qdr + ppd->dd->board_atten;
7702 if (!override && QSFP_HAS_ATTEN(qd->tech) && (qd->atten[0] ||
7704 *sdr_dds = get_atten_table(txdds_sdr, qd->atten[0]);
7705 *ddr_dds = get_atten_table(txdds_ddr, qd->atten[0]);
7706 *qdr_dds = get_atten_table(txdds_qdr, qd->atten[1]);
7708 } else if (ppd->cpspec->no_eep < TXDDS_TABLE_SZ) {
7710 * If we have no (or incomplete) data from the cable
7711 * EEPROM, or no QSFP, or override is set, use the
7712 * module parameter value to index into the attentuation
7715 idx = ppd->cpspec->no_eep;
7716 *sdr_dds = &txdds_sdr[idx];
7717 *ddr_dds = &txdds_ddr[idx];
7718 *qdr_dds = &txdds_qdr[idx];
7719 } else if (ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ)) {
7720 /* similar to above, but index into the "extra" table. */
7721 idx = ppd->cpspec->no_eep - TXDDS_TABLE_SZ;
7722 *sdr_dds = &txdds_extra_sdr[idx];
7723 *ddr_dds = &txdds_extra_ddr[idx];
7724 *qdr_dds = &txdds_extra_qdr[idx];
7725 } else if ((IS_QME(ppd->dd) || IS_QMH(ppd->dd)) &&
7726 ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ +
7728 idx = ppd->cpspec->no_eep - (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ);
7729 pr_info("IB%u:%u use idx %u into txdds_mfg\n",
7730 ppd->dd->unit, ppd->port, idx);
7731 *sdr_dds = &txdds_extra_mfg[idx];
7732 *ddr_dds = &txdds_extra_mfg[idx];
7733 *qdr_dds = &txdds_extra_mfg[idx];
7735 /* this shouldn't happen, it's range checked */
7736 *sdr_dds = txdds_sdr + qib_long_atten;
7737 *ddr_dds = txdds_ddr + qib_long_atten;
7738 *qdr_dds = txdds_qdr + qib_long_atten;
7742 static void init_txdds_table(struct qib_pportdata *ppd, int override)
7744 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds;
7745 struct txdds_ent *dds;
7749 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, override);
7751 /* for mez cards or override, use the selected value for all entries */
7752 if (!(ppd->dd->flags & QIB_HAS_QSFP) || override)
7755 /* Fill in the first entry with the best entry found. */
7756 set_txdds(ppd, 0, sdr_dds);
7757 set_txdds(ppd, TXDDS_TABLE_SZ, ddr_dds);
7758 set_txdds(ppd, 2 * TXDDS_TABLE_SZ, qdr_dds);
7759 if (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED |
7761 dds = (struct txdds_ent *)(ppd->link_speed_active ==
7762 QIB_IB_QDR ? qdr_dds :
7763 (ppd->link_speed_active ==
7764 QIB_IB_DDR ? ddr_dds : sdr_dds));
7765 write_tx_serdes_param(ppd, dds);
7768 /* Fill in the remaining entries with the default table values. */
7769 for (idx = 1; idx < ARRAY_SIZE(txdds_sdr); ++idx) {
7770 set_txdds(ppd, idx, single_ent ? sdr_dds : txdds_sdr + idx);
7771 set_txdds(ppd, idx + TXDDS_TABLE_SZ,
7772 single_ent ? ddr_dds : txdds_ddr + idx);
7773 set_txdds(ppd, idx + 2 * TXDDS_TABLE_SZ,
7774 single_ent ? qdr_dds : txdds_qdr + idx);
7778 #define KR_AHB_ACC KREG_IDX(ahb_access_ctrl)
7779 #define KR_AHB_TRANS KREG_IDX(ahb_transaction_reg)
7780 #define AHB_TRANS_RDY SYM_MASK(ahb_transaction_reg, ahb_rdy)
7781 #define AHB_ADDR_LSB SYM_LSB(ahb_transaction_reg, ahb_address)
7782 #define AHB_DATA_LSB SYM_LSB(ahb_transaction_reg, ahb_data)
7783 #define AHB_WR SYM_MASK(ahb_transaction_reg, write_not_read)
7784 #define AHB_TRANS_TRIES 10
7787 * The chan argument is 0=chan0, 1=chan1, 2=pll, 3=chan2, 4=chan4,
7788 * 5=subsystem which is why most calls have "chan + chan >> 1"
7789 * for the channel argument.
7791 static u32 ahb_mod(struct qib_devdata *dd, int quad, int chan, int addr,
7794 u32 rd_data, wr_data, sz_mask;
7795 u64 trans, acc, prev_acc;
7796 u32 ret = 0xBAD0BAD;
7799 prev_acc = qib_read_kreg64(dd, KR_AHB_ACC);
7800 /* From this point on, make sure we return access */
7801 acc = (quad << 1) | 1;
7802 qib_write_kreg(dd, KR_AHB_ACC, acc);
7804 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7805 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7806 if (trans & AHB_TRANS_RDY)
7809 if (tries >= AHB_TRANS_TRIES) {
7810 qib_dev_err(dd, "No ahb_rdy in %d tries\n", AHB_TRANS_TRIES);
7814 /* If mask is not all 1s, we need to read, but different SerDes
7815 * entities have different sizes
7817 sz_mask = (1UL << ((quad == 1) ? 32 : 16)) - 1;
7818 wr_data = data & mask & sz_mask;
7819 if ((~mask & sz_mask) != 0) {
7820 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1);
7821 qib_write_kreg(dd, KR_AHB_TRANS, trans);
7823 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7824 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7825 if (trans & AHB_TRANS_RDY)
7828 if (tries >= AHB_TRANS_TRIES) {
7829 qib_dev_err(dd, "No Rd ahb_rdy in %d tries\n",
7833 /* Re-read in case host split reads and read data first */
7834 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7835 rd_data = (uint32_t)(trans >> AHB_DATA_LSB);
7836 wr_data |= (rd_data & ~mask & sz_mask);
7839 /* If mask is not zero, we need to write. */
7840 if (mask & sz_mask) {
7841 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1);
7842 trans |= ((uint64_t)wr_data << AHB_DATA_LSB);
7844 qib_write_kreg(dd, KR_AHB_TRANS, trans);
7846 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7847 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7848 if (trans & AHB_TRANS_RDY)
7851 if (tries >= AHB_TRANS_TRIES) {
7852 qib_dev_err(dd, "No Wr ahb_rdy in %d tries\n",
7859 qib_write_kreg(dd, KR_AHB_ACC, prev_acc);
7863 static void ibsd_wr_allchans(struct qib_pportdata *ppd, int addr, unsigned data,
7866 struct qib_devdata *dd = ppd->dd;
7870 for (chan = 0; chan < SERDES_CHANS; ++chan) {
7871 ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), addr,
7873 rbc = ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7878 static void serdes_7322_los_enable(struct qib_pportdata *ppd, int enable)
7880 u64 data = qib_read_kreg_port(ppd, krp_serdesctrl);
7881 u8 state = SYM_FIELD(data, IBSerdesCtrl_0, RXLOSEN);
7883 if (enable && !state) {
7884 pr_info("IB%u:%u Turning LOS on\n",
7885 ppd->dd->unit, ppd->port);
7886 data |= SYM_MASK(IBSerdesCtrl_0, RXLOSEN);
7887 } else if (!enable && state) {
7888 pr_info("IB%u:%u Turning LOS off\n",
7889 ppd->dd->unit, ppd->port);
7890 data &= ~SYM_MASK(IBSerdesCtrl_0, RXLOSEN);
7892 qib_write_kreg_port(ppd, krp_serdesctrl, data);
7895 static int serdes_7322_init(struct qib_pportdata *ppd)
7898 if (ppd->dd->cspec->r1)
7899 ret = serdes_7322_init_old(ppd);
7901 ret = serdes_7322_init_new(ppd);
7905 static int serdes_7322_init_old(struct qib_pportdata *ppd)
7910 * Initialize the Tx DDS tables. Also done every QSFP event,
7911 * for adapters with QSFP
7913 init_txdds_table(ppd, 0);
7915 /* ensure no tx overrides from earlier driver loads */
7916 qib_write_kreg_port(ppd, krp_tx_deemph_override,
7917 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7918 reset_tx_deemphasis_override));
7920 /* Patch some SerDes defaults to "Better for IB" */
7921 /* Timing Loop Bandwidth: cdr_timing[11:9] = 0 */
7922 ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9));
7924 /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */
7925 ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11));
7926 /* Enable LE2: rxle2en_r2a addr 13 bit [6] = 1 */
7927 ibsd_wr_allchans(ppd, 13, (1 << 6), (1 << 6));
7929 /* May be overridden in qsfp_7322_event */
7930 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT;
7931 ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7));
7933 /* enable LE1 adaptation for all but QME, which is disabled */
7934 le_val = IS_QME(ppd->dd) ? 0 : 1;
7935 ibsd_wr_allchans(ppd, 13, (le_val << 5), (1 << 5));
7937 /* Clear cmode-override, may be set from older driver */
7938 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14);
7940 /* Timing Recovery: rxtapsel addr 5 bits [9:8] = 0 */
7941 ibsd_wr_allchans(ppd, 5, (0 << 8), BMASK(9, 8));
7943 /* setup LoS params; these are subsystem, so chan == 5 */
7944 /* LoS filter threshold_count on, ch 0-3, set to 8 */
7945 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11));
7946 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4));
7947 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11));
7948 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4));
7950 /* LoS filter threshold_count off, ch 0-3, set to 4 */
7951 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0));
7952 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8));
7953 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0));
7954 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8));
7956 /* LoS filter select enabled */
7957 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15);
7959 /* LoS target data: SDR=4, DDR=2, QDR=1 */
7960 ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */
7961 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */
7962 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */
7964 serdes_7322_los_enable(ppd, 1);
7966 /* rxbistena; set 0 to avoid effects of it switch later */
7967 ibsd_wr_allchans(ppd, 9, 0 << 15, 1 << 15);
7969 /* Configure 4 DFE taps, and only they adapt */
7970 ibsd_wr_allchans(ppd, 16, 0 << 0, BMASK(1, 0));
7972 /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */
7973 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac;
7974 ibsd_wr_allchans(ppd, 21, le_val, 0xfffe);
7977 * Set receive adaptation mode. SDR and DDR adaptation are
7978 * always on, and QDR is initially enabled; later disabled.
7980 qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL);
7981 qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL);
7982 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
7983 ppd->dd->cspec->r1 ?
7984 QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN);
7985 ppd->cpspec->qdr_dfe_on = 1;
7987 /* FLoop LOS gate: PPM filter enabled */
7988 ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10);
7990 /* rx offset center enabled */
7991 ibsd_wr_allchans(ppd, 12, 1 << 4, 1 << 4);
7993 if (!ppd->dd->cspec->r1) {
7994 ibsd_wr_allchans(ppd, 12, 1 << 12, 1 << 12);
7995 ibsd_wr_allchans(ppd, 12, 2 << 8, 0x0f << 8);
7998 /* Set the frequency loop bandwidth to 15 */
7999 ibsd_wr_allchans(ppd, 2, 15 << 5, BMASK(8, 5));
8004 static int serdes_7322_init_new(struct qib_pportdata *ppd)
8007 u32 le_val, rxcaldone;
8008 int chan, chan_done = (1 << SERDES_CHANS) - 1;
8010 /* Clear cmode-override, may be set from older driver */
8011 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14);
8013 /* ensure no tx overrides from earlier driver loads */
8014 qib_write_kreg_port(ppd, krp_tx_deemph_override,
8015 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8016 reset_tx_deemphasis_override));
8018 /* START OF LSI SUGGESTED SERDES BRINGUP */
8019 /* Reset - Calibration Setup */
8020 /* Stop DFE adaptaion */
8021 ibsd_wr_allchans(ppd, 1, 0, BMASK(9, 1));
8023 ibsd_wr_allchans(ppd, 13, 0, BMASK(5, 5));
8024 /* Disable autoadapt for LE1 */
8025 ibsd_wr_allchans(ppd, 1, 0, BMASK(15, 15));
8027 ibsd_wr_allchans(ppd, 13, 0, BMASK(6, 6));
8029 ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0));
8030 /* Disable AFE Offset Cancel */
8031 ibsd_wr_allchans(ppd, 12, 0, BMASK(12, 12));
8032 /* Disable Timing Loop */
8033 ibsd_wr_allchans(ppd, 2, 0, BMASK(3, 3));
8034 /* Disable Frequency Loop */
8035 ibsd_wr_allchans(ppd, 2, 0, BMASK(4, 4));
8036 /* Disable Baseline Wander Correction */
8037 ibsd_wr_allchans(ppd, 13, 0, BMASK(13, 13));
8038 /* Disable RX Calibration */
8039 ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10));
8040 /* Disable RX Offset Calibration */
8041 ibsd_wr_allchans(ppd, 12, 0, BMASK(4, 4));
8043 ibsd_wr_allchans(ppd, 2, (1 << 15), BMASK(15, 15));
8045 ibsd_wr_allchans(ppd, 5, 0, BMASK(9, 8));
8046 /* Enable phase Calibration */
8047 ibsd_wr_allchans(ppd, 12, (1 << 5), BMASK(5, 5));
8048 /* DFE Bandwidth [2:14-12] */
8049 ibsd_wr_allchans(ppd, 2, (4 << 12), BMASK(14, 12));
8050 /* DFE Config (4 taps only) */
8051 ibsd_wr_allchans(ppd, 16, 0, BMASK(1, 0));
8052 /* Gain Loop Bandwidth */
8053 if (!ppd->dd->cspec->r1) {
8054 ibsd_wr_allchans(ppd, 12, 1 << 12, BMASK(12, 12));
8055 ibsd_wr_allchans(ppd, 12, 2 << 8, BMASK(11, 8));
8057 ibsd_wr_allchans(ppd, 19, (3 << 11), BMASK(13, 11));
8059 /* Baseline Wander Correction Gain [13:4-0] (leave as default) */
8060 /* Baseline Wander Correction Gain [3:7-5] (leave as default) */
8061 /* Data Rate Select [5:7-6] (leave as default) */
8062 /* RX Parallel Word Width [3:10-8] (leave as default) */
8065 /* Single- or Multi-channel reset */
8066 /* RX Analog reset */
8067 /* RX Digital reset */
8068 ibsd_wr_allchans(ppd, 0, 0, BMASK(15, 13));
8070 /* RX Analog reset */
8071 ibsd_wr_allchans(ppd, 0, (1 << 14), BMASK(14, 14));
8073 /* RX Digital reset */
8074 ibsd_wr_allchans(ppd, 0, (1 << 13), BMASK(13, 13));
8077 /* setup LoS params; these are subsystem, so chan == 5 */
8078 /* LoS filter threshold_count on, ch 0-3, set to 8 */
8079 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11));
8080 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4));
8081 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11));
8082 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4));
8084 /* LoS filter threshold_count off, ch 0-3, set to 4 */
8085 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0));
8086 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8));
8087 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0));
8088 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8));
8090 /* LoS filter select enabled */
8091 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15);
8093 /* LoS target data: SDR=4, DDR=2, QDR=1 */
8094 ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */
8095 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */
8096 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */
8098 /* Turn on LOS on initial SERDES init */
8099 serdes_7322_los_enable(ppd, 1);
8100 /* FLoop LOS gate: PPM filter enabled */
8101 ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10);
8103 /* RX LATCH CALIBRATION */
8104 /* Enable Eyefinder Phase Calibration latch */
8105 ibsd_wr_allchans(ppd, 15, 1, BMASK(0, 0));
8106 /* Enable RX Offset Calibration latch */
8107 ibsd_wr_allchans(ppd, 12, (1 << 4), BMASK(4, 4));
8109 /* Start Calibration */
8110 ibsd_wr_allchans(ppd, 4, (1 << 10), BMASK(10, 10));
8111 tend = jiffies + msecs_to_jiffies(500);
8112 while (chan_done && !time_is_before_jiffies(tend)) {
8114 for (chan = 0; chan < SERDES_CHANS; ++chan) {
8115 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx),
8116 (chan + (chan >> 1)),
8118 if ((~rxcaldone & (u32)BMASK(9, 9)) == 0 &&
8119 (~chan_done & (1 << chan)) == 0)
8120 chan_done &= ~(1 << chan);
8124 pr_info("Serdes %d calibration not done after .5 sec: 0x%x\n",
8125 IBSD(ppd->hw_pidx), chan_done);
8127 for (chan = 0; chan < SERDES_CHANS; ++chan) {
8128 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx),
8129 (chan + (chan >> 1)),
8131 if ((~rxcaldone & (u32)BMASK(10, 10)) == 0)
8132 pr_info("Serdes %d chan %d calibration failed\n",
8133 IBSD(ppd->hw_pidx), chan);
8137 /* Turn off Calibration */
8138 ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10));
8142 /* Set LE2 value (May be overridden in qsfp_7322_event) */
8143 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT;
8144 ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7));
8145 /* Set LE2 Loop bandwidth */
8146 ibsd_wr_allchans(ppd, 3, (7 << 5), BMASK(7, 5));
8148 ibsd_wr_allchans(ppd, 13, (1 << 6), BMASK(6, 6));
8150 /* Enable H0 only */
8151 ibsd_wr_allchans(ppd, 1, 1, BMASK(9, 1));
8152 /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */
8153 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac;
8154 ibsd_wr_allchans(ppd, 21, le_val, 0xfffe);
8156 ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0));
8158 /* Set Frequency Loop Bandwidth */
8159 ibsd_wr_allchans(ppd, 2, (15 << 5), BMASK(8, 5));
8160 /* Enable Frequency Loop */
8161 ibsd_wr_allchans(ppd, 2, (1 << 4), BMASK(4, 4));
8162 /* Set Timing Loop Bandwidth */
8163 ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9));
8164 /* Enable Timing Loop */
8165 ibsd_wr_allchans(ppd, 2, (1 << 3), BMASK(3, 3));
8168 * Set receive adaptation mode. SDR and DDR adaptation are
8169 * always on, and QDR is initially enabled; later disabled.
8171 qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL);
8172 qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL);
8173 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
8174 ppd->dd->cspec->r1 ?
8175 QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN);
8176 ppd->cpspec->qdr_dfe_on = 1;
8178 ibsd_wr_allchans(ppd, 13, (0 << 5), (1 << 5));
8179 /* Disable auto adapt for LE1 */
8180 ibsd_wr_allchans(ppd, 1, (0 << 15), BMASK(15, 15));
8182 /* Enable AFE Offset Cancel */
8183 ibsd_wr_allchans(ppd, 12, (1 << 12), BMASK(12, 12));
8184 /* Enable Baseline Wander Correction */
8185 ibsd_wr_allchans(ppd, 12, (1 << 13), BMASK(13, 13));
8186 /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */
8187 ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11));
8188 /* VGA output common mode */
8189 ibsd_wr_allchans(ppd, 12, (3 << 2), BMASK(3, 2));
8192 * Initialize the Tx DDS tables. Also done every QSFP event,
8193 * for adapters with QSFP
8195 init_txdds_table(ppd, 0);
8200 /* start adjust QMH serdes parameters */
8202 static void set_man_code(struct qib_pportdata *ppd, int chan, int code)
8204 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
8205 9, code << 9, 0x3f << 9);
8208 static void set_man_mode_h1(struct qib_pportdata *ppd, int chan,
8209 int enable, u32 tapenable)
8212 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
8213 1, 3 << 10, 0x1f << 10);
8215 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
8219 /* Set clock to 1, 0, 1, 0 */
8220 static void clock_man(struct qib_pportdata *ppd, int chan)
8222 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
8224 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
8226 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
8228 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
8233 * write the current Tx serdes pre,post,main,amp settings into the serdes.
8234 * The caller must pass the settings appropriate for the current speed,
8235 * or not care if they are correct for the current speed.
8237 static void write_tx_serdes_param(struct qib_pportdata *ppd,
8238 struct txdds_ent *txdds)
8242 deemph = qib_read_kreg_port(ppd, krp_tx_deemph_override);
8243 /* field names for amp, main, post, pre, respectively */
8244 deemph &= ~(SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txampcntl_d2a) |
8245 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txc0_ena) |
8246 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcp1_ena) |
8247 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcn1_ena));
8249 deemph |= SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8250 tx_override_deemphasis_select);
8251 deemph |= (txdds->amp & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8252 txampcntl_d2a)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8254 deemph |= (txdds->main & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8255 txc0_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8257 deemph |= (txdds->post & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8258 txcp1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8260 deemph |= (txdds->pre & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8261 txcn1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8263 qib_write_kreg_port(ppd, krp_tx_deemph_override, deemph);
8267 * Set the parameters for mez cards on link bounce, so they are
8268 * always exactly what was requested. Similar logic to init_txdds
8269 * but does just the serdes.
8271 static void adj_tx_serdes(struct qib_pportdata *ppd)
8273 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds;
8274 struct txdds_ent *dds;
8276 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, 1);
8277 dds = (struct txdds_ent *)(ppd->link_speed_active == QIB_IB_QDR ?
8278 qdr_dds : (ppd->link_speed_active == QIB_IB_DDR ?
8279 ddr_dds : sdr_dds));
8280 write_tx_serdes_param(ppd, dds);
8283 /* set QDR forced value for H1, if needed */
8284 static void force_h1(struct qib_pportdata *ppd)
8288 ppd->cpspec->qdr_reforce = 0;
8289 if (!ppd->dd->cspec->r1)
8292 for (chan = 0; chan < SERDES_CHANS; chan++) {
8293 set_man_mode_h1(ppd, chan, 1, 0);
8294 set_man_code(ppd, chan, ppd->cpspec->h1_val);
8295 clock_man(ppd, chan);
8296 set_man_mode_h1(ppd, chan, 0, 0);
8300 #define SJA_EN SYM_MASK(SPC_JTAG_ACCESS_REG, SPC_JTAG_ACCESS_EN)
8301 #define BISTEN_LSB SYM_LSB(SPC_JTAG_ACCESS_REG, bist_en)
8303 #define R_OPCODE_LSB 3
8305 #define R_OP_SHIFT 2
8306 #define R_OP_UPDATE 3
8311 static int qib_r_grab(struct qib_devdata *dd)
8315 qib_write_kreg(dd, kr_r_access, val);
8316 qib_read_kreg32(dd, kr_scratch);
8320 /* qib_r_wait_for_rdy() not only waits for the ready bit, it
8321 * returns the current state of R_TDO
8323 static int qib_r_wait_for_rdy(struct qib_devdata *dd)
8327 for (timeout = 0; timeout < 100 ; ++timeout) {
8328 val = qib_read_kreg32(dd, kr_r_access);
8330 return (val >> R_TDO_LSB) & 1;
8335 static int qib_r_shift(struct qib_devdata *dd, int bisten,
8336 int len, u8 *inp, u8 *outp)
8341 valbase = SJA_EN | (bisten << BISTEN_LSB) |
8342 (R_OP_SHIFT << R_OPCODE_LSB);
8343 ret = qib_r_wait_for_rdy(dd);
8346 for (pos = 0; pos < len; ++pos) {
8349 outp[pos >> 3] &= ~(1 << (pos & 7));
8350 outp[pos >> 3] |= (ret << (pos & 7));
8353 int tdi = inp[pos >> 3] >> (pos & 7);
8354 val |= ((tdi & 1) << R_TDI_LSB);
8356 qib_write_kreg(dd, kr_r_access, val);
8357 qib_read_kreg32(dd, kr_scratch);
8358 ret = qib_r_wait_for_rdy(dd);
8362 /* Restore to NOP between operations. */
8363 val = SJA_EN | (bisten << BISTEN_LSB);
8364 qib_write_kreg(dd, kr_r_access, val);
8365 qib_read_kreg32(dd, kr_scratch);
8366 ret = qib_r_wait_for_rdy(dd);
8374 static int qib_r_update(struct qib_devdata *dd, int bisten)
8379 val = SJA_EN | (bisten << BISTEN_LSB) | (R_OP_UPDATE << R_OPCODE_LSB);
8380 ret = qib_r_wait_for_rdy(dd);
8382 qib_write_kreg(dd, kr_r_access, val);
8383 qib_read_kreg32(dd, kr_scratch);
8388 #define BISTEN_PORT_SEL 15
8389 #define LEN_PORT_SEL 625
8390 #define BISTEN_AT 17
8392 #define BISTEN_ETM 16
8395 #define BIT2BYTE(x) (((x) + BITS_PER_BYTE - 1) / BITS_PER_BYTE)
8397 /* these are common for all IB port use cases. */
8398 static u8 reset_at[BIT2BYTE(LEN_AT)] = {
8399 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8400 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
8402 static u8 reset_atetm[BIT2BYTE(LEN_ETM)] = {
8403 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8404 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8405 0x00, 0x00, 0x00, 0x80, 0xe3, 0x81, 0x73, 0x3c, 0x70, 0x8e,
8406 0x07, 0xce, 0xf1, 0xc0, 0x39, 0x1e, 0x38, 0xc7, 0x03, 0xe7,
8407 0x78, 0xe0, 0x1c, 0x0f, 0x9c, 0x7f, 0x80, 0x73, 0x0f, 0x70,
8408 0xde, 0x01, 0xce, 0x39, 0xc0, 0xf9, 0x06, 0x38, 0xd7, 0x00,
8409 0xe7, 0x19, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8410 0x00, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00,
8412 static u8 at[BIT2BYTE(LEN_AT)] = {
8413 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00,
8414 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
8417 /* used for IB1 or IB2, only one in use */
8418 static u8 atetm_1port[BIT2BYTE(LEN_ETM)] = {
8419 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8420 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8421 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8422 0x00, 0x10, 0xf2, 0x80, 0x83, 0x1e, 0x38, 0x00, 0x00, 0x00,
8423 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8424 0x00, 0x00, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xc8, 0x03,
8425 0x07, 0x7b, 0xa0, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x18, 0x00,
8426 0x18, 0x00, 0x00, 0x00, 0x00, 0x4b, 0x00, 0x00, 0x00,
8429 /* used when both IB1 and IB2 are in use */
8430 static u8 atetm_2port[BIT2BYTE(LEN_ETM)] = {
8431 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8432 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x79,
8433 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8434 0x00, 0x00, 0xf8, 0x80, 0x83, 0x1e, 0x38, 0xe0, 0x03, 0x05,
8435 0x7b, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
8436 0xa2, 0x0f, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xd1, 0x07,
8437 0x02, 0x7c, 0x80, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x3e, 0x00,
8438 0x02, 0x00, 0x00, 0x00, 0x00, 0x64, 0x00, 0x00, 0x00,
8441 /* used when only IB1 is in use */
8442 static u8 portsel_port1[BIT2BYTE(LEN_PORT_SEL)] = {
8443 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13,
8444 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c,
8445 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
8446 0x13, 0x78, 0x78, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
8447 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32,
8448 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
8449 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
8450 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
8453 /* used when only IB2 is in use */
8454 static u8 portsel_port2[BIT2BYTE(LEN_PORT_SEL)] = {
8455 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x39, 0x39,
8456 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x73, 0x32, 0x32, 0x32,
8457 0x32, 0x32, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39,
8458 0x39, 0x78, 0x78, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39,
8459 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x74, 0x32,
8460 0x32, 0x32, 0x32, 0x32, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a,
8461 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a,
8462 0x3a, 0x3a, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01,
8465 /* used when both IB1 and IB2 are in use */
8466 static u8 portsel_2port[BIT2BYTE(LEN_PORT_SEL)] = {
8467 0x32, 0xba, 0x54, 0x76, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13,
8468 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c,
8469 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
8470 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
8471 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32,
8472 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x3a,
8473 0x3a, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
8474 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
8478 * Do setup to properly handle IB link recovery; if port is zero, we
8479 * are initializing to cover both ports; otherwise we are initializing
8480 * to cover a single port card, or the port has reached INIT and we may
8481 * need to switch coverage types.
8483 static void setup_7322_link_recovery(struct qib_pportdata *ppd, u32 both)
8486 struct qib_devdata *dd = ppd->dd;
8488 if (!ppd->dd->cspec->r1)
8491 dd->cspec->recovery_ports_initted++;
8492 ppd->cpspec->recovery_init = 1;
8494 if (!both && dd->cspec->recovery_ports_initted == 1) {
8495 portsel = ppd->port == 1 ? portsel_port1 : portsel_port2;
8498 portsel = portsel_2port;
8502 if (qib_r_grab(dd) < 0 ||
8503 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, reset_atetm, NULL) < 0 ||
8504 qib_r_update(dd, BISTEN_ETM) < 0 ||
8505 qib_r_shift(dd, BISTEN_AT, LEN_AT, reset_at, NULL) < 0 ||
8506 qib_r_update(dd, BISTEN_AT) < 0 ||
8507 qib_r_shift(dd, BISTEN_PORT_SEL, LEN_PORT_SEL,
8508 portsel, NULL) < 0 ||
8509 qib_r_update(dd, BISTEN_PORT_SEL) < 0 ||
8510 qib_r_shift(dd, BISTEN_AT, LEN_AT, at, NULL) < 0 ||
8511 qib_r_update(dd, BISTEN_AT) < 0 ||
8512 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, etm, NULL) < 0 ||
8513 qib_r_update(dd, BISTEN_ETM) < 0)
8514 qib_dev_err(dd, "Failed IB link recovery setup\n");
8517 static void check_7322_rxe_status(struct qib_pportdata *ppd)
8519 struct qib_devdata *dd = ppd->dd;
8522 if (dd->cspec->recovery_ports_initted != 1)
8523 return; /* rest doesn't apply to dualport */
8524 qib_write_kreg(dd, kr_control, dd->control |
8525 SYM_MASK(Control, FreezeMode));
8526 (void)qib_read_kreg64(dd, kr_scratch);
8527 udelay(3); /* ibcreset asserted 400ns, be sure that's over */
8528 fmask = qib_read_kreg64(dd, kr_act_fmask);
8531 * require a powercycle before we'll work again, and make
8532 * sure we get no more interrupts, and don't turn off
8535 ppd->dd->cspec->stay_in_freeze = 1;
8536 qib_7322_set_intr_state(ppd->dd, 0);
8537 qib_write_kreg(dd, kr_fmask, 0ULL);
8538 qib_dev_err(dd, "HCA unusable until powercycled\n");
8539 return; /* eventually reset */
8542 qib_write_kreg(ppd->dd, kr_hwerrclear,
8543 SYM_MASK(HwErrClear, IBSerdesPClkNotDetectClear_1));
8545 /* don't do the full clear_freeze(), not needed for this */
8546 qib_write_kreg(dd, kr_control, dd->control);
8547 qib_read_kreg32(dd, kr_scratch);
8548 /* take IBC out of reset */
8549 if (ppd->link_speed_supported) {
8550 ppd->cpspec->ibcctrl_a &=
8551 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
8552 qib_write_kreg_port(ppd, krp_ibcctrl_a,
8553 ppd->cpspec->ibcctrl_a);
8554 qib_read_kreg32(dd, kr_scratch);
8555 if (ppd->lflags & QIBL_IB_LINK_DISABLED)
8556 qib_set_ib_7322_lstate(ppd, 0,
8557 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);