2 * Copyright (c) 2008, 2009, 2010 QLogic Corporation. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * This file contains all of the code that is specific to the
35 * InfiniPath 7322 chip
38 #include <linux/interrupt.h>
39 #include <linux/pci.h>
40 #include <linux/delay.h>
42 #include <linux/jiffies.h>
43 #include <rdma/ib_verbs.h>
44 #include <rdma/ib_smi.h>
47 #include "qib_7322_regs.h"
52 static void qib_setup_7322_setextled(struct qib_pportdata *, u32);
53 static void qib_7322_handle_hwerrors(struct qib_devdata *, char *, size_t);
54 static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op);
55 static irqreturn_t qib_7322intr(int irq, void *data);
56 static irqreturn_t qib_7322bufavail(int irq, void *data);
57 static irqreturn_t sdma_intr(int irq, void *data);
58 static irqreturn_t sdma_idle_intr(int irq, void *data);
59 static irqreturn_t sdma_progress_intr(int irq, void *data);
60 static irqreturn_t sdma_cleanup_intr(int irq, void *data);
61 static void qib_7322_txchk_change(struct qib_devdata *, u32, u32, u32,
62 struct qib_ctxtdata *rcd);
63 static u8 qib_7322_phys_portstate(u64);
64 static u32 qib_7322_iblink_state(u64);
65 static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd,
67 static void force_h1(struct qib_pportdata *);
68 static void adj_tx_serdes(struct qib_pportdata *);
69 static u32 qib_7322_setpbc_control(struct qib_pportdata *, u32, u8, u8);
70 static void qib_7322_mini_pcs_reset(struct qib_pportdata *);
72 static u32 ahb_mod(struct qib_devdata *, int, int, int, u32, u32);
73 static void ibsd_wr_allchans(struct qib_pportdata *, int, unsigned, unsigned);
75 #define BMASK(msb, lsb) (((1 << ((msb) + 1 - (lsb))) - 1) << (lsb))
77 /* LE2 serdes values for different cases */
82 /* Below is special-purpose, so only really works for the IB SerDes blocks. */
83 #define IBSD(hw_pidx) (hw_pidx + 2)
85 /* these are variables for documentation and experimentation purposes */
86 static const unsigned rcv_int_timeout = 375;
87 static const unsigned rcv_int_count = 16;
88 static const unsigned sdma_idle_cnt = 64;
90 /* Time to stop altering Rx Equalization parameters, after link up. */
91 #define RXEQ_DISABLE_MSECS 2500
94 * Number of VLs we are configured to use (to allow for more
95 * credits per vl, etc.)
97 ushort qib_num_cfg_vls = 2;
98 module_param_named(num_vls, qib_num_cfg_vls, ushort, S_IRUGO);
99 MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");
101 static ushort qib_chase = 1;
102 module_param_named(chase, qib_chase, ushort, S_IRUGO);
103 MODULE_PARM_DESC(chase, "Enable state chase handling");
105 static ushort qib_long_atten = 10; /* 10 dB ~= 5m length */
106 module_param_named(long_attenuation, qib_long_atten, ushort, S_IRUGO);
107 MODULE_PARM_DESC(long_attenuation, \
108 "attenuation cutoff (dB) for long copper cable setup");
110 static ushort qib_singleport;
111 module_param_named(singleport, qib_singleport, ushort, S_IRUGO);
112 MODULE_PARM_DESC(singleport, "Use only IB port 1; more per-port buffer space");
115 * Receive header queue sizes
117 static unsigned qib_rcvhdrcnt;
118 module_param_named(rcvhdrcnt, qib_rcvhdrcnt, uint, S_IRUGO);
119 MODULE_PARM_DESC(rcvhdrcnt, "receive header count");
121 static unsigned qib_rcvhdrsize;
122 module_param_named(rcvhdrsize, qib_rcvhdrsize, uint, S_IRUGO);
123 MODULE_PARM_DESC(rcvhdrsize, "receive header size in 32-bit words");
125 static unsigned qib_rcvhdrentsize;
126 module_param_named(rcvhdrentsize, qib_rcvhdrentsize, uint, S_IRUGO);
127 MODULE_PARM_DESC(rcvhdrentsize, "receive header entry size in 32-bit words");
129 #define MAX_ATTEN_LEN 64 /* plenty for any real system */
130 /* for read back, default index is ~5m copper cable */
131 static char txselect_list[MAX_ATTEN_LEN] = "10";
132 static struct kparam_string kp_txselect = {
133 .string = txselect_list,
134 .maxlen = MAX_ATTEN_LEN
136 static int setup_txselect(const char *, struct kernel_param *);
137 module_param_call(txselect, setup_txselect, param_get_string,
138 &kp_txselect, S_IWUSR | S_IRUGO);
139 MODULE_PARM_DESC(txselect, \
140 "Tx serdes indices (for no QSFP or invalid QSFP data)");
142 #define BOARD_QME7342 5
143 #define BOARD_QMH7342 6
144 #define IS_QMH(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
146 #define IS_QME(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
149 #define KREG_IDX(regname) (QIB_7322_##regname##_OFFS / sizeof(u64))
151 #define KREG_IBPORT_IDX(regname) ((QIB_7322_##regname##_0_OFFS / sizeof(u64)))
153 #define MASK_ACROSS(lsb, msb) \
154 (((1ULL << ((msb) + 1 - (lsb))) - 1) << (lsb))
156 #define SYM_RMASK(regname, fldname) ((u64) \
157 QIB_7322_##regname##_##fldname##_RMASK)
159 #define SYM_MASK(regname, fldname) ((u64) \
160 QIB_7322_##regname##_##fldname##_RMASK << \
161 QIB_7322_##regname##_##fldname##_LSB)
163 #define SYM_FIELD(value, regname, fldname) ((u64) \
164 (((value) >> SYM_LSB(regname, fldname)) & \
165 SYM_RMASK(regname, fldname)))
167 /* useful for things like LaFifoEmpty_0...7, TxCreditOK_0...7, etc. */
168 #define SYM_FIELD_ACROSS(value, regname, fldname, nbits) \
169 (((value) >> SYM_LSB(regname, fldname)) & MASK_ACROSS(0, nbits))
171 #define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask)
172 #define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask)
173 #define ERR_MASK_N(fldname) SYM_MASK(ErrMask_0, fldname##Mask)
174 #define INT_MASK(fldname) SYM_MASK(IntMask, fldname##IntMask)
175 #define INT_MASK_P(fldname, port) SYM_MASK(IntMask, fldname##IntMask##_##port)
176 /* Below because most, but not all, fields of IntMask have that full suffix */
177 #define INT_MASK_PM(fldname, port) SYM_MASK(IntMask, fldname##Mask##_##port)
180 #define SYM_LSB(regname, fldname) (QIB_7322_##regname##_##fldname##_LSB)
183 * the size bits give us 2^N, in KB units. 0 marks as invalid,
184 * and 7 is reserved. We currently use only 2KB and 4KB
186 #define IBA7322_TID_SZ_SHIFT QIB_7322_RcvTIDArray0_RT_BufSize_LSB
187 #define IBA7322_TID_SZ_2K (1UL<<IBA7322_TID_SZ_SHIFT) /* 2KB */
188 #define IBA7322_TID_SZ_4K (2UL<<IBA7322_TID_SZ_SHIFT) /* 4KB */
189 #define IBA7322_TID_PA_SHIFT 11U /* TID addr in chip stored w/o low bits */
191 #define SendIBSLIDAssignMask \
192 QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_RMASK
193 #define SendIBSLMCMask \
194 QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_RMASK
196 #define ExtLED_IB1_YEL SYM_MASK(EXTCtrl, LEDPort0YellowOn)
197 #define ExtLED_IB1_GRN SYM_MASK(EXTCtrl, LEDPort0GreenOn)
198 #define ExtLED_IB2_YEL SYM_MASK(EXTCtrl, LEDPort1YellowOn)
199 #define ExtLED_IB2_GRN SYM_MASK(EXTCtrl, LEDPort1GreenOn)
200 #define ExtLED_IB1_MASK (ExtLED_IB1_YEL | ExtLED_IB1_GRN)
201 #define ExtLED_IB2_MASK (ExtLED_IB2_YEL | ExtLED_IB2_GRN)
203 #define _QIB_GPIO_SDA_NUM 1
204 #define _QIB_GPIO_SCL_NUM 0
205 #define QIB_EEPROM_WEN_NUM 14
206 #define QIB_TWSI_EEPROM_DEV 0xA2 /* All Production 7322 cards. */
208 /* HW counter clock is at 4nsec */
209 #define QIB_7322_PSXMITWAIT_CHECK_RATE 4000
211 /* full speed IB port 1 only */
212 #define PORT_SPD_CAP (QIB_IB_SDR | QIB_IB_DDR | QIB_IB_QDR)
213 #define PORT_SPD_CAP_SHIFT 3
215 /* full speed featuremask, both ports */
216 #define DUAL_PORT_CAP (PORT_SPD_CAP | (PORT_SPD_CAP << PORT_SPD_CAP_SHIFT))
219 * This file contains almost all the chip-specific register information and
220 * access functions for the FAKED QLogic InfiniPath 7322 PCI-Express chip.
223 /* Use defines to tie machine-generated names to lower-case names */
224 #define kr_contextcnt KREG_IDX(ContextCnt)
225 #define kr_control KREG_IDX(Control)
226 #define kr_counterregbase KREG_IDX(CntrRegBase)
227 #define kr_errclear KREG_IDX(ErrClear)
228 #define kr_errmask KREG_IDX(ErrMask)
229 #define kr_errstatus KREG_IDX(ErrStatus)
230 #define kr_extctrl KREG_IDX(EXTCtrl)
231 #define kr_extstatus KREG_IDX(EXTStatus)
232 #define kr_gpio_clear KREG_IDX(GPIOClear)
233 #define kr_gpio_mask KREG_IDX(GPIOMask)
234 #define kr_gpio_out KREG_IDX(GPIOOut)
235 #define kr_gpio_status KREG_IDX(GPIOStatus)
236 #define kr_hwdiagctrl KREG_IDX(HwDiagCtrl)
237 #define kr_debugportval KREG_IDX(DebugPortValueReg)
238 #define kr_fmask KREG_IDX(feature_mask)
239 #define kr_act_fmask KREG_IDX(active_feature_mask)
240 #define kr_hwerrclear KREG_IDX(HwErrClear)
241 #define kr_hwerrmask KREG_IDX(HwErrMask)
242 #define kr_hwerrstatus KREG_IDX(HwErrStatus)
243 #define kr_intclear KREG_IDX(IntClear)
244 #define kr_intmask KREG_IDX(IntMask)
245 #define kr_intredirect KREG_IDX(IntRedirect0)
246 #define kr_intstatus KREG_IDX(IntStatus)
247 #define kr_pagealign KREG_IDX(PageAlign)
248 #define kr_rcvavailtimeout KREG_IDX(RcvAvailTimeOut0)
249 #define kr_rcvctrl KREG_IDX(RcvCtrl) /* Common, but chip also has per-port */
250 #define kr_rcvegrbase KREG_IDX(RcvEgrBase)
251 #define kr_rcvegrcnt KREG_IDX(RcvEgrCnt)
252 #define kr_rcvhdrcnt KREG_IDX(RcvHdrCnt)
253 #define kr_rcvhdrentsize KREG_IDX(RcvHdrEntSize)
254 #define kr_rcvhdrsize KREG_IDX(RcvHdrSize)
255 #define kr_rcvtidbase KREG_IDX(RcvTIDBase)
256 #define kr_rcvtidcnt KREG_IDX(RcvTIDCnt)
257 #define kr_revision KREG_IDX(Revision)
258 #define kr_scratch KREG_IDX(Scratch)
259 #define kr_sendbuffererror KREG_IDX(SendBufErr0) /* and base for 1 and 2 */
260 #define kr_sendcheckmask KREG_IDX(SendCheckMask0) /* and 1, 2 */
261 #define kr_sendctrl KREG_IDX(SendCtrl)
262 #define kr_sendgrhcheckmask KREG_IDX(SendGRHCheckMask0) /* and 1, 2 */
263 #define kr_sendibpktmask KREG_IDX(SendIBPacketMask0) /* and 1, 2 */
264 #define kr_sendpioavailaddr KREG_IDX(SendBufAvailAddr)
265 #define kr_sendpiobufbase KREG_IDX(SendBufBase)
266 #define kr_sendpiobufcnt KREG_IDX(SendBufCnt)
267 #define kr_sendpiosize KREG_IDX(SendBufSize)
268 #define kr_sendregbase KREG_IDX(SendRegBase)
269 #define kr_sendbufavail0 KREG_IDX(SendBufAvail0)
270 #define kr_userregbase KREG_IDX(UserRegBase)
271 #define kr_intgranted KREG_IDX(Int_Granted)
272 #define kr_vecclr_wo_int KREG_IDX(vec_clr_without_int)
273 #define kr_intblocked KREG_IDX(IntBlocked)
274 #define kr_r_access KREG_IDX(SPC_JTAG_ACCESS_REG)
277 * per-port kernel registers. Access only with qib_read_kreg_port()
278 * or qib_write_kreg_port()
280 #define krp_errclear KREG_IBPORT_IDX(ErrClear)
281 #define krp_errmask KREG_IBPORT_IDX(ErrMask)
282 #define krp_errstatus KREG_IBPORT_IDX(ErrStatus)
283 #define krp_highprio_0 KREG_IBPORT_IDX(HighPriority0)
284 #define krp_highprio_limit KREG_IBPORT_IDX(HighPriorityLimit)
285 #define krp_hrtbt_guid KREG_IBPORT_IDX(HRTBT_GUID)
286 #define krp_ib_pcsconfig KREG_IBPORT_IDX(IBPCSConfig)
287 #define krp_ibcctrl_a KREG_IBPORT_IDX(IBCCtrlA)
288 #define krp_ibcctrl_b KREG_IBPORT_IDX(IBCCtrlB)
289 #define krp_ibcctrl_c KREG_IBPORT_IDX(IBCCtrlC)
290 #define krp_ibcstatus_a KREG_IBPORT_IDX(IBCStatusA)
291 #define krp_ibcstatus_b KREG_IBPORT_IDX(IBCStatusB)
292 #define krp_txestatus KREG_IBPORT_IDX(TXEStatus)
293 #define krp_lowprio_0 KREG_IBPORT_IDX(LowPriority0)
294 #define krp_ncmodectrl KREG_IBPORT_IDX(IBNCModeCtrl)
295 #define krp_partitionkey KREG_IBPORT_IDX(RcvPartitionKey)
296 #define krp_psinterval KREG_IBPORT_IDX(PSInterval)
297 #define krp_psstart KREG_IBPORT_IDX(PSStart)
298 #define krp_psstat KREG_IBPORT_IDX(PSStat)
299 #define krp_rcvbthqp KREG_IBPORT_IDX(RcvBTHQP)
300 #define krp_rcvctrl KREG_IBPORT_IDX(RcvCtrl)
301 #define krp_rcvpktledcnt KREG_IBPORT_IDX(RcvPktLEDCnt)
302 #define krp_rcvqpmaptable KREG_IBPORT_IDX(RcvQPMapTableA)
303 #define krp_rxcreditvl0 KREG_IBPORT_IDX(RxCreditVL0)
304 #define krp_rxcreditvl15 (KREG_IBPORT_IDX(RxCreditVL0)+15)
305 #define krp_sendcheckcontrol KREG_IBPORT_IDX(SendCheckControl)
306 #define krp_sendctrl KREG_IBPORT_IDX(SendCtrl)
307 #define krp_senddmabase KREG_IBPORT_IDX(SendDmaBase)
308 #define krp_senddmabufmask0 KREG_IBPORT_IDX(SendDmaBufMask0)
309 #define krp_senddmabufmask1 (KREG_IBPORT_IDX(SendDmaBufMask0) + 1)
310 #define krp_senddmabufmask2 (KREG_IBPORT_IDX(SendDmaBufMask0) + 2)
311 #define krp_senddmabuf_use0 KREG_IBPORT_IDX(SendDmaBufUsed0)
312 #define krp_senddmabuf_use1 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 1)
313 #define krp_senddmabuf_use2 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 2)
314 #define krp_senddmadesccnt KREG_IBPORT_IDX(SendDmaDescCnt)
315 #define krp_senddmahead KREG_IBPORT_IDX(SendDmaHead)
316 #define krp_senddmaheadaddr KREG_IBPORT_IDX(SendDmaHeadAddr)
317 #define krp_senddmaidlecnt KREG_IBPORT_IDX(SendDmaIdleCnt)
318 #define krp_senddmalengen KREG_IBPORT_IDX(SendDmaLenGen)
319 #define krp_senddmaprioritythld KREG_IBPORT_IDX(SendDmaPriorityThld)
320 #define krp_senddmareloadcnt KREG_IBPORT_IDX(SendDmaReloadCnt)
321 #define krp_senddmastatus KREG_IBPORT_IDX(SendDmaStatus)
322 #define krp_senddmatail KREG_IBPORT_IDX(SendDmaTail)
323 #define krp_sendhdrsymptom KREG_IBPORT_IDX(SendHdrErrSymptom)
324 #define krp_sendslid KREG_IBPORT_IDX(SendIBSLIDAssign)
325 #define krp_sendslidmask KREG_IBPORT_IDX(SendIBSLIDMask)
326 #define krp_ibsdtestiftx KREG_IBPORT_IDX(IB_SDTEST_IF_TX)
327 #define krp_adapt_dis_timer KREG_IBPORT_IDX(ADAPT_DISABLE_TIMER_THRESHOLD)
328 #define krp_tx_deemph_override KREG_IBPORT_IDX(IBSD_TX_DEEMPHASIS_OVERRIDE)
329 #define krp_serdesctrl KREG_IBPORT_IDX(IBSerdesCtrl)
332 * Per-context kernel registers. Acess only with qib_read_kreg_ctxt()
333 * or qib_write_kreg_ctxt()
335 #define krc_rcvhdraddr KREG_IDX(RcvHdrAddr0)
336 #define krc_rcvhdrtailaddr KREG_IDX(RcvHdrTailAddr0)
339 * TID Flow table, per context. Reduces
340 * number of hdrq updates to one per flow (or on errors).
341 * context 0 and 1 share same memory, but have distinct
342 * addresses. Since for now, we never use expected sends
343 * on kernel contexts, we don't worry about that (we initialize
344 * those entries for ctxt 0/1 on driver load twice, for example).
346 #define NUM_TIDFLOWS_CTXT 0x20 /* 0x20 per context; have to hardcode */
347 #define ur_rcvflowtable (KREG_IDX(RcvTIDFlowTable0) - KREG_IDX(RcvHdrTail0))
349 /* these are the error bits in the tid flows, and are W1C */
350 #define TIDFLOW_ERRBITS ( \
351 (SYM_MASK(RcvTIDFlowTable0, GenMismatch) << \
352 SYM_LSB(RcvTIDFlowTable0, GenMismatch)) | \
353 (SYM_MASK(RcvTIDFlowTable0, SeqMismatch) << \
354 SYM_LSB(RcvTIDFlowTable0, SeqMismatch)))
356 /* Most (not all) Counters are per-IBport.
357 * Requires LBIntCnt is at offset 0 in the group
359 #define CREG_IDX(regname) \
360 ((QIB_7322_##regname##_0_OFFS - QIB_7322_LBIntCnt_OFFS) / sizeof(u64))
362 #define crp_badformat CREG_IDX(RxVersionErrCnt)
363 #define crp_err_rlen CREG_IDX(RxLenErrCnt)
364 #define crp_erricrc CREG_IDX(RxICRCErrCnt)
365 #define crp_errlink CREG_IDX(RxLinkMalformCnt)
366 #define crp_errlpcrc CREG_IDX(RxLPCRCErrCnt)
367 #define crp_errpkey CREG_IDX(RxPKeyMismatchCnt)
368 #define crp_errvcrc CREG_IDX(RxVCRCErrCnt)
369 #define crp_excessbufferovfl CREG_IDX(ExcessBufferOvflCnt)
370 #define crp_iblinkdown CREG_IDX(IBLinkDownedCnt)
371 #define crp_iblinkerrrecov CREG_IDX(IBLinkErrRecoveryCnt)
372 #define crp_ibstatuschange CREG_IDX(IBStatusChangeCnt)
373 #define crp_ibsymbolerr CREG_IDX(IBSymbolErrCnt)
374 #define crp_invalidrlen CREG_IDX(RxMaxMinLenErrCnt)
375 #define crp_locallinkintegrityerr CREG_IDX(LocalLinkIntegrityErrCnt)
376 #define crp_pktrcv CREG_IDX(RxDataPktCnt)
377 #define crp_pktrcvflowctrl CREG_IDX(RxFlowPktCnt)
378 #define crp_pktsend CREG_IDX(TxDataPktCnt)
379 #define crp_pktsendflow CREG_IDX(TxFlowPktCnt)
380 #define crp_psrcvdatacount CREG_IDX(PSRcvDataCount)
381 #define crp_psrcvpktscount CREG_IDX(PSRcvPktsCount)
382 #define crp_psxmitdatacount CREG_IDX(PSXmitDataCount)
383 #define crp_psxmitpktscount CREG_IDX(PSXmitPktsCount)
384 #define crp_psxmitwaitcount CREG_IDX(PSXmitWaitCount)
385 #define crp_rcvebp CREG_IDX(RxEBPCnt)
386 #define crp_rcvflowctrlviol CREG_IDX(RxFlowCtrlViolCnt)
387 #define crp_rcvovfl CREG_IDX(RxBufOvflCnt)
388 #define crp_rxdlidfltr CREG_IDX(RxDlidFltrCnt)
389 #define crp_rxdroppkt CREG_IDX(RxDroppedPktCnt)
390 #define crp_rxotherlocalphyerr CREG_IDX(RxOtherLocalPhyErrCnt)
391 #define crp_rxqpinvalidctxt CREG_IDX(RxQPInvalidContextCnt)
392 #define crp_rxvlerr CREG_IDX(RxVlErrCnt)
393 #define crp_sendstall CREG_IDX(TxFlowStallCnt)
394 #define crp_txdroppedpkt CREG_IDX(TxDroppedPktCnt)
395 #define crp_txhdrerr CREG_IDX(TxHeadersErrCnt)
396 #define crp_txlenerr CREG_IDX(TxLenErrCnt)
397 #define crp_txlenerr CREG_IDX(TxLenErrCnt)
398 #define crp_txminmaxlenerr CREG_IDX(TxMaxMinLenErrCnt)
399 #define crp_txsdmadesc CREG_IDX(TxSDmaDescCnt)
400 #define crp_txunderrun CREG_IDX(TxUnderrunCnt)
401 #define crp_txunsupvl CREG_IDX(TxUnsupVLErrCnt)
402 #define crp_vl15droppedpkt CREG_IDX(RxVL15DroppedPktCnt)
403 #define crp_wordrcv CREG_IDX(RxDwordCnt)
404 #define crp_wordsend CREG_IDX(TxDwordCnt)
405 #define crp_tx_creditstalls CREG_IDX(TxCreditUpToDateTimeOut)
407 /* these are the (few) counters that are not port-specific */
408 #define CREG_DEVIDX(regname) ((QIB_7322_##regname##_OFFS - \
409 QIB_7322_LBIntCnt_OFFS) / sizeof(u64))
410 #define cr_base_egrovfl CREG_DEVIDX(RxP0HdrEgrOvflCnt)
411 #define cr_lbint CREG_DEVIDX(LBIntCnt)
412 #define cr_lbstall CREG_DEVIDX(LBFlowStallCnt)
413 #define cr_pcieretrydiag CREG_DEVIDX(PcieRetryBufDiagQwordCnt)
414 #define cr_rxtidflowdrop CREG_DEVIDX(RxTidFlowDropCnt)
415 #define cr_tidfull CREG_DEVIDX(RxTIDFullErrCnt)
416 #define cr_tidinvalid CREG_DEVIDX(RxTIDValidErrCnt)
418 /* no chip register for # of IB ports supported, so define */
419 #define NUM_IB_PORTS 2
421 /* 1 VL15 buffer per hardware IB port, no register for this, so define */
422 #define NUM_VL15_BUFS NUM_IB_PORTS
425 * context 0 and 1 are special, and there is no chip register that
426 * defines this value, so we have to define it here.
427 * These are all allocated to either 0 or 1 for single port
428 * hardware configuration, otherwise each gets half
430 #define KCTXT0_EGRCNT 2048
432 /* values for vl and port fields in PBC, 7322-specific */
433 #define PBC_PORT_SEL_LSB 26
434 #define PBC_PORT_SEL_RMASK 1
435 #define PBC_VL_NUM_LSB 27
436 #define PBC_VL_NUM_RMASK 7
437 #define PBC_7322_VL15_SEND (1ULL << 63) /* pbc; VL15, no credit check */
438 #define PBC_7322_VL15_SEND_CTRL (1ULL << 31) /* control version of same */
440 static u8 ib_rate_to_delay[IB_RATE_120_GBPS + 1] = {
441 [IB_RATE_2_5_GBPS] = 16,
442 [IB_RATE_5_GBPS] = 8,
443 [IB_RATE_10_GBPS] = 4,
444 [IB_RATE_20_GBPS] = 2,
445 [IB_RATE_30_GBPS] = 2,
446 [IB_RATE_40_GBPS] = 1
449 #define IBA7322_LINKSPEED_SHIFT SYM_LSB(IBCStatusA_0, LinkSpeedActive)
450 #define IBA7322_LINKWIDTH_SHIFT SYM_LSB(IBCStatusA_0, LinkWidthActive)
452 /* link training states, from IBC */
453 #define IB_7322_LT_STATE_DISABLED 0x00
454 #define IB_7322_LT_STATE_LINKUP 0x01
455 #define IB_7322_LT_STATE_POLLACTIVE 0x02
456 #define IB_7322_LT_STATE_POLLQUIET 0x03
457 #define IB_7322_LT_STATE_SLEEPDELAY 0x04
458 #define IB_7322_LT_STATE_SLEEPQUIET 0x05
459 #define IB_7322_LT_STATE_CFGDEBOUNCE 0x08
460 #define IB_7322_LT_STATE_CFGRCVFCFG 0x09
461 #define IB_7322_LT_STATE_CFGWAITRMT 0x0a
462 #define IB_7322_LT_STATE_CFGIDLE 0x0b
463 #define IB_7322_LT_STATE_RECOVERRETRAIN 0x0c
464 #define IB_7322_LT_STATE_TXREVLANES 0x0d
465 #define IB_7322_LT_STATE_RECOVERWAITRMT 0x0e
466 #define IB_7322_LT_STATE_RECOVERIDLE 0x0f
467 #define IB_7322_LT_STATE_CFGENH 0x10
468 #define IB_7322_LT_STATE_CFGTEST 0x11
470 /* link state machine states from IBC */
471 #define IB_7322_L_STATE_DOWN 0x0
472 #define IB_7322_L_STATE_INIT 0x1
473 #define IB_7322_L_STATE_ARM 0x2
474 #define IB_7322_L_STATE_ACTIVE 0x3
475 #define IB_7322_L_STATE_ACT_DEFER 0x4
477 static const u8 qib_7322_physportstate[0x20] = {
478 [IB_7322_LT_STATE_DISABLED] = IB_PHYSPORTSTATE_DISABLED,
479 [IB_7322_LT_STATE_LINKUP] = IB_PHYSPORTSTATE_LINKUP,
480 [IB_7322_LT_STATE_POLLACTIVE] = IB_PHYSPORTSTATE_POLL,
481 [IB_7322_LT_STATE_POLLQUIET] = IB_PHYSPORTSTATE_POLL,
482 [IB_7322_LT_STATE_SLEEPDELAY] = IB_PHYSPORTSTATE_SLEEP,
483 [IB_7322_LT_STATE_SLEEPQUIET] = IB_PHYSPORTSTATE_SLEEP,
484 [IB_7322_LT_STATE_CFGDEBOUNCE] = IB_PHYSPORTSTATE_CFG_TRAIN,
485 [IB_7322_LT_STATE_CFGRCVFCFG] =
486 IB_PHYSPORTSTATE_CFG_TRAIN,
487 [IB_7322_LT_STATE_CFGWAITRMT] =
488 IB_PHYSPORTSTATE_CFG_TRAIN,
489 [IB_7322_LT_STATE_CFGIDLE] = IB_PHYSPORTSTATE_CFG_IDLE,
490 [IB_7322_LT_STATE_RECOVERRETRAIN] =
491 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
492 [IB_7322_LT_STATE_RECOVERWAITRMT] =
493 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
494 [IB_7322_LT_STATE_RECOVERIDLE] =
495 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
496 [IB_7322_LT_STATE_CFGENH] = IB_PHYSPORTSTATE_CFG_ENH,
497 [IB_7322_LT_STATE_CFGTEST] = IB_PHYSPORTSTATE_CFG_TRAIN,
498 [0x12] = IB_PHYSPORTSTATE_CFG_TRAIN,
499 [0x13] = IB_PHYSPORTSTATE_CFG_WAIT_ENH,
500 [0x14] = IB_PHYSPORTSTATE_CFG_TRAIN,
501 [0x15] = IB_PHYSPORTSTATE_CFG_TRAIN,
502 [0x16] = IB_PHYSPORTSTATE_CFG_TRAIN,
503 [0x17] = IB_PHYSPORTSTATE_CFG_TRAIN
506 struct qib_chip_specific {
507 u64 __iomem *cregbase;
509 spinlock_t rcvmod_lock; /* protect rcvctrl shadow changes */
510 spinlock_t gpio_lock; /* RMW of shadows/regs for ExtCtrl and GPIO */
511 u64 main_int_mask; /* clear bits which have dedicated handlers */
512 u64 int_enable_mask; /* for per port interrupts in single port mode */
515 u64 gpio_out; /* shadow of kr_gpio_out, for rmw ops */
516 u64 gpio_mask; /* shadow the gpio mask register */
517 u64 extctrl; /* shadow the gpio output enable, etc... */
524 u32 updthresh; /* current AvailUpdThld */
525 u32 updthresh_dflt; /* default AvailUpdThld */
528 u32 num_msix_entries;
532 u32 recovery_ports_initted;
533 struct msix_entry *msix_entries;
535 unsigned long *sendchkenable;
536 unsigned long *sendgrhchk;
537 unsigned long *sendibchk;
538 u32 rcvavail_timeout[18];
539 char emsgbuf[128]; /* for device error interrupt msg buffer */
542 /* Table of entries in "human readable" form Tx Emphasis. */
550 struct vendor_txdds_ent {
551 u8 oui[QSFP_VOUI_LEN];
553 struct txdds_ent sdr;
554 struct txdds_ent ddr;
555 struct txdds_ent qdr;
558 static void write_tx_serdes_param(struct qib_pportdata *, struct txdds_ent *);
560 #define TXDDS_TABLE_SZ 16 /* number of entries per speed in onchip table */
561 #define TXDDS_EXTRA_SZ 13 /* number of extra tx settings entries */
562 #define SERDES_CHANS 4 /* yes, it's obvious, but one less magic number */
564 #define H1_FORCE_VAL 8
565 #define H1_FORCE_QME 1 /* may be overridden via setup_txselect() */
566 #define H1_FORCE_QMH 7 /* may be overridden via setup_txselect() */
568 /* The static and dynamic registers are paired, and the pairs indexed by spd */
569 #define krp_static_adapt_dis(spd) (KREG_IBPORT_IDX(ADAPT_DISABLE_STATIC_SDR) \
572 #define QDR_DFE_DISABLE_DELAY 4000 /* msec after LINKUP */
573 #define QDR_STATIC_ADAPT_DOWN 0xf0f0f0f0ULL /* link down, H1-H4 QDR adapts */
574 #define QDR_STATIC_ADAPT_DOWN_R1 0ULL /* r1 link down, H1-H4 QDR adapts */
575 #define QDR_STATIC_ADAPT_INIT 0xffffffffffULL /* up, disable H0,H1-8, LE */
576 #define QDR_STATIC_ADAPT_INIT_R1 0xf0ffffffffULL /* r1 up, disable H0,H1-8 */
578 struct qib_chippport_specific {
579 u64 __iomem *kpregbase;
580 u64 __iomem *cpregbase;
582 struct qib_pportdata *ppd;
583 wait_queue_head_t autoneg_wait;
584 struct delayed_work autoneg_work;
585 struct delayed_work ipg_work;
586 struct timer_list chase_timer;
588 * these 5 fields are used to establish deltas for IB symbol
589 * errors and linkrecovery errors. They can be reported on
590 * some chips during link negotiation prior to INIT, and with
591 * DDR when faking DDR negotiations with non-IBTA switches.
592 * The chip counters are adjusted at driver unload if there is
604 u64 ibcctrl_a; /* krp_ibcctrl_a shadow */
605 u64 ibcctrl_b; /* krp_ibcctrl_b shadow */
613 * Per-bay per-channel rcv QMH H1 values and Tx values for QDR.
614 * entry zero is unused, to simplify indexing
617 u8 no_eep; /* txselect table index to use if no qsfp info */
620 struct qib_qsfp_data qsfp_data;
621 char epmsgbuf[192]; /* for port error interrupt msg buffer */
626 irq_handler_t handler;
628 int port; /* 0 if not port-specific, else port # */
630 { QIB_DRV_NAME, qib_7322intr, -1, 0 },
631 { QIB_DRV_NAME " (buf avail)", qib_7322bufavail,
632 SYM_LSB(IntStatus, SendBufAvail), 0 },
633 { QIB_DRV_NAME " (sdma 0)", sdma_intr,
634 SYM_LSB(IntStatus, SDmaInt_0), 1 },
635 { QIB_DRV_NAME " (sdma 1)", sdma_intr,
636 SYM_LSB(IntStatus, SDmaInt_1), 2 },
637 { QIB_DRV_NAME " (sdmaI 0)", sdma_idle_intr,
638 SYM_LSB(IntStatus, SDmaIdleInt_0), 1 },
639 { QIB_DRV_NAME " (sdmaI 1)", sdma_idle_intr,
640 SYM_LSB(IntStatus, SDmaIdleInt_1), 2 },
641 { QIB_DRV_NAME " (sdmaP 0)", sdma_progress_intr,
642 SYM_LSB(IntStatus, SDmaProgressInt_0), 1 },
643 { QIB_DRV_NAME " (sdmaP 1)", sdma_progress_intr,
644 SYM_LSB(IntStatus, SDmaProgressInt_1), 2 },
645 { QIB_DRV_NAME " (sdmaC 0)", sdma_cleanup_intr,
646 SYM_LSB(IntStatus, SDmaCleanupDone_0), 1 },
647 { QIB_DRV_NAME " (sdmaC 1)", sdma_cleanup_intr,
648 SYM_LSB(IntStatus, SDmaCleanupDone_1), 2 },
652 #define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE 1
653 /* cycle through TS1/TS2 till OK */
654 #define QLOGIC_IB_IBCC_LINKINITCMD_POLL 2
655 /* wait for TS1, then go on */
656 #define QLOGIC_IB_IBCC_LINKINITCMD_SLEEP 3
657 #define QLOGIC_IB_IBCC_LINKINITCMD_SHIFT 16
659 #define QLOGIC_IB_IBCC_LINKCMD_DOWN 1 /* move to 0x11 */
660 #define QLOGIC_IB_IBCC_LINKCMD_ARMED 2 /* move to 0x21 */
661 #define QLOGIC_IB_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */
663 #define BLOB_7322_IBCHG 0x101
665 static inline void qib_write_kreg(const struct qib_devdata *dd,
666 const u32 regno, u64 value);
667 static inline u32 qib_read_kreg32(const struct qib_devdata *, const u32);
668 static void write_7322_initregs(struct qib_devdata *);
669 static void write_7322_init_portregs(struct qib_pportdata *);
670 static void setup_7322_link_recovery(struct qib_pportdata *, u32);
671 static void check_7322_rxe_status(struct qib_pportdata *);
672 static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *, u64, u32 *);
675 * qib_read_ureg32 - read 32-bit virtualized per-context register
677 * @regno: register number
678 * @ctxt: context number
680 * Return the contents of a register that is virtualized to be per context.
681 * Returns -1 on errors (not distinguishable from valid contents at
682 * runtime; we may add a separate error variable at some point).
684 static inline u32 qib_read_ureg32(const struct qib_devdata *dd,
685 enum qib_ureg regno, int ctxt)
687 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
689 return readl(regno + (u64 __iomem *)(
690 (dd->ureg_align * ctxt) + (dd->userbase ?
691 (char __iomem *)dd->userbase :
692 (char __iomem *)dd->kregbase + dd->uregbase)));
696 * qib_read_ureg - read virtualized per-context register
698 * @regno: register number
699 * @ctxt: context number
701 * Return the contents of a register that is virtualized to be per context.
702 * Returns -1 on errors (not distinguishable from valid contents at
703 * runtime; we may add a separate error variable at some point).
705 static inline u64 qib_read_ureg(const struct qib_devdata *dd,
706 enum qib_ureg regno, int ctxt)
709 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
711 return readq(regno + (u64 __iomem *)(
712 (dd->ureg_align * ctxt) + (dd->userbase ?
713 (char __iomem *)dd->userbase :
714 (char __iomem *)dd->kregbase + dd->uregbase)));
718 * qib_write_ureg - write virtualized per-context register
720 * @regno: register number
724 * Write the contents of a register that is virtualized to be per context.
726 static inline void qib_write_ureg(const struct qib_devdata *dd,
727 enum qib_ureg regno, u64 value, int ctxt)
731 ubase = (u64 __iomem *)
732 ((char __iomem *) dd->userbase +
733 dd->ureg_align * ctxt);
735 ubase = (u64 __iomem *)
737 (char __iomem *) dd->kregbase +
738 dd->ureg_align * ctxt);
740 if (dd->kregbase && (dd->flags & QIB_PRESENT))
741 writeq(value, &ubase[regno]);
744 static inline u32 qib_read_kreg32(const struct qib_devdata *dd,
747 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
749 return readl((u32 __iomem *) &dd->kregbase[regno]);
752 static inline u64 qib_read_kreg64(const struct qib_devdata *dd,
755 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
757 return readq(&dd->kregbase[regno]);
760 static inline void qib_write_kreg(const struct qib_devdata *dd,
761 const u32 regno, u64 value)
763 if (dd->kregbase && (dd->flags & QIB_PRESENT))
764 writeq(value, &dd->kregbase[regno]);
768 * not many sanity checks for the port-specific kernel register routines,
769 * since they are only used when it's known to be safe.
771 static inline u64 qib_read_kreg_port(const struct qib_pportdata *ppd,
774 if (!ppd->cpspec->kpregbase || !(ppd->dd->flags & QIB_PRESENT))
776 return readq(&ppd->cpspec->kpregbase[regno]);
779 static inline void qib_write_kreg_port(const struct qib_pportdata *ppd,
780 const u16 regno, u64 value)
782 if (ppd->cpspec && ppd->dd && ppd->cpspec->kpregbase &&
783 (ppd->dd->flags & QIB_PRESENT))
784 writeq(value, &ppd->cpspec->kpregbase[regno]);
788 * qib_write_kreg_ctxt - write a device's per-ctxt 64-bit kernel register
789 * @dd: the qlogic_ib device
790 * @regno: the register number to write
791 * @ctxt: the context containing the register
792 * @value: the value to write
794 static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd,
795 const u16 regno, unsigned ctxt,
798 qib_write_kreg(dd, regno + ctxt, value);
801 static inline u64 read_7322_creg(const struct qib_devdata *dd, u16 regno)
803 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
805 return readq(&dd->cspec->cregbase[regno]);
810 static inline u32 read_7322_creg32(const struct qib_devdata *dd, u16 regno)
812 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
814 return readl(&dd->cspec->cregbase[regno]);
819 static inline void write_7322_creg_port(const struct qib_pportdata *ppd,
820 u16 regno, u64 value)
822 if (ppd->cpspec && ppd->cpspec->cpregbase &&
823 (ppd->dd->flags & QIB_PRESENT))
824 writeq(value, &ppd->cpspec->cpregbase[regno]);
827 static inline u64 read_7322_creg_port(const struct qib_pportdata *ppd,
830 if (!ppd->cpspec || !ppd->cpspec->cpregbase ||
831 !(ppd->dd->flags & QIB_PRESENT))
833 return readq(&ppd->cpspec->cpregbase[regno]);
836 static inline u32 read_7322_creg32_port(const struct qib_pportdata *ppd,
839 if (!ppd->cpspec || !ppd->cpspec->cpregbase ||
840 !(ppd->dd->flags & QIB_PRESENT))
842 return readl(&ppd->cpspec->cpregbase[regno]);
845 /* bits in Control register */
846 #define QLOGIC_IB_C_RESET SYM_MASK(Control, SyncReset)
847 #define QLOGIC_IB_C_SDMAFETCHPRIOEN SYM_MASK(Control, SDmaDescFetchPriorityEn)
849 /* bits in general interrupt regs */
850 #define QIB_I_RCVURG_LSB SYM_LSB(IntMask, RcvUrg0IntMask)
851 #define QIB_I_RCVURG_RMASK MASK_ACROSS(0, 17)
852 #define QIB_I_RCVURG_MASK (QIB_I_RCVURG_RMASK << QIB_I_RCVURG_LSB)
853 #define QIB_I_RCVAVAIL_LSB SYM_LSB(IntMask, RcvAvail0IntMask)
854 #define QIB_I_RCVAVAIL_RMASK MASK_ACROSS(0, 17)
855 #define QIB_I_RCVAVAIL_MASK (QIB_I_RCVAVAIL_RMASK << QIB_I_RCVAVAIL_LSB)
856 #define QIB_I_C_ERROR INT_MASK(Err)
858 #define QIB_I_SPIOSENT (INT_MASK_P(SendDone, 0) | INT_MASK_P(SendDone, 1))
859 #define QIB_I_SPIOBUFAVAIL INT_MASK(SendBufAvail)
860 #define QIB_I_GPIO INT_MASK(AssertGPIO)
861 #define QIB_I_P_SDMAINT(pidx) \
862 (INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \
863 INT_MASK_P(SDmaProgress, pidx) | \
864 INT_MASK_PM(SDmaCleanupDone, pidx))
866 /* Interrupt bits that are "per port" */
867 #define QIB_I_P_BITSEXTANT(pidx) \
868 (INT_MASK_P(Err, pidx) | INT_MASK_P(SendDone, pidx) | \
869 INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \
870 INT_MASK_P(SDmaProgress, pidx) | \
871 INT_MASK_PM(SDmaCleanupDone, pidx))
873 /* Interrupt bits that are common to a device */
874 /* currently unused: QIB_I_SPIOSENT */
875 #define QIB_I_C_BITSEXTANT \
876 (QIB_I_RCVURG_MASK | QIB_I_RCVAVAIL_MASK | \
878 QIB_I_C_ERROR | QIB_I_SPIOBUFAVAIL | QIB_I_GPIO)
880 #define QIB_I_BITSEXTANT (QIB_I_C_BITSEXTANT | \
881 QIB_I_P_BITSEXTANT(0) | QIB_I_P_BITSEXTANT(1))
884 * Error bits that are "per port".
886 #define QIB_E_P_IBSTATUSCHANGED ERR_MASK_N(IBStatusChanged)
887 #define QIB_E_P_SHDR ERR_MASK_N(SHeadersErr)
888 #define QIB_E_P_VL15_BUF_MISUSE ERR_MASK_N(VL15BufMisuseErr)
889 #define QIB_E_P_SND_BUF_MISUSE ERR_MASK_N(SendBufMisuseErr)
890 #define QIB_E_P_SUNSUPVL ERR_MASK_N(SendUnsupportedVLErr)
891 #define QIB_E_P_SUNEXP_PKTNUM ERR_MASK_N(SendUnexpectedPktNumErr)
892 #define QIB_E_P_SDROP_DATA ERR_MASK_N(SendDroppedDataPktErr)
893 #define QIB_E_P_SDROP_SMP ERR_MASK_N(SendDroppedSmpPktErr)
894 #define QIB_E_P_SPKTLEN ERR_MASK_N(SendPktLenErr)
895 #define QIB_E_P_SUNDERRUN ERR_MASK_N(SendUnderRunErr)
896 #define QIB_E_P_SMAXPKTLEN ERR_MASK_N(SendMaxPktLenErr)
897 #define QIB_E_P_SMINPKTLEN ERR_MASK_N(SendMinPktLenErr)
898 #define QIB_E_P_RIBLOSTLINK ERR_MASK_N(RcvIBLostLinkErr)
899 #define QIB_E_P_RHDR ERR_MASK_N(RcvHdrErr)
900 #define QIB_E_P_RHDRLEN ERR_MASK_N(RcvHdrLenErr)
901 #define QIB_E_P_RBADTID ERR_MASK_N(RcvBadTidErr)
902 #define QIB_E_P_RBADVERSION ERR_MASK_N(RcvBadVersionErr)
903 #define QIB_E_P_RIBFLOW ERR_MASK_N(RcvIBFlowErr)
904 #define QIB_E_P_REBP ERR_MASK_N(RcvEBPErr)
905 #define QIB_E_P_RUNSUPVL ERR_MASK_N(RcvUnsupportedVLErr)
906 #define QIB_E_P_RUNEXPCHAR ERR_MASK_N(RcvUnexpectedCharErr)
907 #define QIB_E_P_RSHORTPKTLEN ERR_MASK_N(RcvShortPktLenErr)
908 #define QIB_E_P_RLONGPKTLEN ERR_MASK_N(RcvLongPktLenErr)
909 #define QIB_E_P_RMAXPKTLEN ERR_MASK_N(RcvMaxPktLenErr)
910 #define QIB_E_P_RMINPKTLEN ERR_MASK_N(RcvMinPktLenErr)
911 #define QIB_E_P_RICRC ERR_MASK_N(RcvICRCErr)
912 #define QIB_E_P_RVCRC ERR_MASK_N(RcvVCRCErr)
913 #define QIB_E_P_RFORMATERR ERR_MASK_N(RcvFormatErr)
915 #define QIB_E_P_SDMA1STDESC ERR_MASK_N(SDma1stDescErr)
916 #define QIB_E_P_SDMABASE ERR_MASK_N(SDmaBaseErr)
917 #define QIB_E_P_SDMADESCADDRMISALIGN ERR_MASK_N(SDmaDescAddrMisalignErr)
918 #define QIB_E_P_SDMADWEN ERR_MASK_N(SDmaDwEnErr)
919 #define QIB_E_P_SDMAGENMISMATCH ERR_MASK_N(SDmaGenMismatchErr)
920 #define QIB_E_P_SDMAHALT ERR_MASK_N(SDmaHaltErr)
921 #define QIB_E_P_SDMAMISSINGDW ERR_MASK_N(SDmaMissingDwErr)
922 #define QIB_E_P_SDMAOUTOFBOUND ERR_MASK_N(SDmaOutOfBoundErr)
923 #define QIB_E_P_SDMARPYTAG ERR_MASK_N(SDmaRpyTagErr)
924 #define QIB_E_P_SDMATAILOUTOFBOUND ERR_MASK_N(SDmaTailOutOfBoundErr)
925 #define QIB_E_P_SDMAUNEXPDATA ERR_MASK_N(SDmaUnexpDataErr)
927 /* Error bits that are common to a device */
928 #define QIB_E_RESET ERR_MASK(ResetNegated)
929 #define QIB_E_HARDWARE ERR_MASK(HardwareErr)
930 #define QIB_E_INVALIDADDR ERR_MASK(InvalidAddrErr)
934 * Per chip (rather than per-port) errors. Most either do
935 * nothing but trigger a print (because they self-recover, or
936 * always occur in tandem with other errors that handle the
937 * issue), or because they indicate errors with no recovery,
938 * but we want to know that they happened.
940 #define QIB_E_SBUF_VL15_MISUSE ERR_MASK(SBufVL15MisUseErr)
941 #define QIB_E_BADEEP ERR_MASK(InvalidEEPCmd)
942 #define QIB_E_VLMISMATCH ERR_MASK(SendVLMismatchErr)
943 #define QIB_E_ARMLAUNCH ERR_MASK(SendArmLaunchErr)
944 #define QIB_E_SPCLTRIG ERR_MASK(SendSpecialTriggerErr)
945 #define QIB_E_RRCVHDRFULL ERR_MASK(RcvHdrFullErr)
946 #define QIB_E_RRCVEGRFULL ERR_MASK(RcvEgrFullErr)
947 #define QIB_E_RCVCTXTSHARE ERR_MASK(RcvContextShareErr)
949 /* SDMA chip errors (not per port)
950 * QIB_E_SDMA_BUF_DUP needs no special handling, because we will also get
951 * the SDMAHALT error immediately, so we just print the dup error via the
952 * E_AUTO mechanism. This is true of most of the per-port fatal errors
953 * as well, but since this is port-independent, by definition, it's
954 * handled a bit differently. SDMA_VL15 and SDMA_WRONG_PORT are per
955 * packet send errors, and so are handled in the same manner as other
958 #define QIB_E_SDMA_VL15 ERR_MASK(SDmaVL15Err)
959 #define QIB_E_SDMA_WRONG_PORT ERR_MASK(SDmaWrongPortErr)
960 #define QIB_E_SDMA_BUF_DUP ERR_MASK(SDmaBufMaskDuplicateErr)
963 * Below functionally equivalent to legacy QLOGIC_IB_E_PKTERRS
964 * it is used to print "common" packet errors.
966 #define QIB_E_P_PKTERRS (QIB_E_P_SPKTLEN |\
967 QIB_E_P_SDROP_DATA | QIB_E_P_RVCRC |\
968 QIB_E_P_RICRC | QIB_E_P_RSHORTPKTLEN |\
969 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \
972 /* Error Bits that Packet-related (Receive, per-port) */
973 #define QIB_E_P_RPKTERRS (\
974 QIB_E_P_RHDRLEN | QIB_E_P_RBADTID | \
975 QIB_E_P_RBADVERSION | QIB_E_P_RHDR | \
976 QIB_E_P_RLONGPKTLEN | QIB_E_P_RSHORTPKTLEN |\
977 QIB_E_P_RMAXPKTLEN | QIB_E_P_RMINPKTLEN | \
978 QIB_E_P_RFORMATERR | QIB_E_P_RUNSUPVL | \
979 QIB_E_P_RUNEXPCHAR | QIB_E_P_RIBFLOW | QIB_E_P_REBP)
982 * Error bits that are Send-related (per port)
983 * (ARMLAUNCH excluded from E_SPKTERRS because it gets special handling).
984 * All of these potentially need to have a buffer disarmed
986 #define QIB_E_P_SPKTERRS (\
987 QIB_E_P_SUNEXP_PKTNUM |\
988 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\
989 QIB_E_P_SMAXPKTLEN |\
990 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \
991 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN | \
992 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNSUPVL)
994 #define QIB_E_SPKTERRS ( \
995 QIB_E_SBUF_VL15_MISUSE | QIB_E_VLMISMATCH | \
996 ERR_MASK_N(SendUnsupportedVLErr) | \
997 QIB_E_SPCLTRIG | QIB_E_SDMA_VL15 | QIB_E_SDMA_WRONG_PORT)
999 #define QIB_E_P_SDMAERRS ( \
1000 QIB_E_P_SDMAHALT | \
1001 QIB_E_P_SDMADESCADDRMISALIGN | \
1002 QIB_E_P_SDMAUNEXPDATA | \
1003 QIB_E_P_SDMAMISSINGDW | \
1004 QIB_E_P_SDMADWEN | \
1005 QIB_E_P_SDMARPYTAG | \
1006 QIB_E_P_SDMA1STDESC | \
1007 QIB_E_P_SDMABASE | \
1008 QIB_E_P_SDMATAILOUTOFBOUND | \
1009 QIB_E_P_SDMAOUTOFBOUND | \
1010 QIB_E_P_SDMAGENMISMATCH)
1013 * This sets some bits more than once, but makes it more obvious which
1014 * bits are not handled under other categories, and the repeat definition
1017 #define QIB_E_P_BITSEXTANT ( \
1018 QIB_E_P_SPKTERRS | QIB_E_P_PKTERRS | QIB_E_P_RPKTERRS | \
1019 QIB_E_P_RIBLOSTLINK | QIB_E_P_IBSTATUSCHANGED | \
1020 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNDERRUN | \
1021 QIB_E_P_SHDR | QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SDMAERRS \
1025 * These are errors that can occur when the link
1026 * changes state while a packet is being sent or received. This doesn't
1027 * cover things like EBP or VCRC that can be the result of a sending
1028 * having the link change state, so we receive a "known bad" packet.
1029 * All of these are "per port", so renamed:
1031 #define QIB_E_P_LINK_PKTERRS (\
1032 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\
1033 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN |\
1034 QIB_E_P_RSHORTPKTLEN | QIB_E_P_RMINPKTLEN |\
1038 * This sets some bits more than once, but makes it more obvious which
1039 * bits are not handled under other categories (such as QIB_E_SPKTERRS),
1040 * and the repeat definition is not a problem.
1042 #define QIB_E_C_BITSEXTANT (\
1043 QIB_E_HARDWARE | QIB_E_INVALIDADDR | QIB_E_BADEEP |\
1044 QIB_E_ARMLAUNCH | QIB_E_VLMISMATCH | QIB_E_RRCVHDRFULL |\
1045 QIB_E_RRCVEGRFULL | QIB_E_RESET | QIB_E_SBUF_VL15_MISUSE)
1047 /* Likewise Neuter E_SPKT_ERRS_IGNORE */
1048 #define E_SPKT_ERRS_IGNORE 0
1050 #define QIB_EXTS_MEMBIST_DISABLED \
1051 SYM_MASK(EXTStatus, MemBISTDisabled)
1052 #define QIB_EXTS_MEMBIST_ENDTEST \
1053 SYM_MASK(EXTStatus, MemBISTEndTest)
1055 #define QIB_E_SPIOARMLAUNCH \
1056 ERR_MASK(SendArmLaunchErr)
1058 #define IBA7322_IBCC_LINKINITCMD_MASK SYM_RMASK(IBCCtrlA_0, LinkInitCmd)
1059 #define IBA7322_IBCC_LINKCMD_SHIFT SYM_LSB(IBCCtrlA_0, LinkCmd)
1062 * IBTA_1_2 is set when multiple speeds are enabled (normal),
1063 * and also if forced QDR (only QDR enabled). It's enabled for the
1064 * forced QDR case so that scrambling will be enabled by the TS3
1065 * exchange, when supported by both sides of the link.
1067 #define IBA7322_IBC_IBTA_1_2_MASK SYM_MASK(IBCCtrlB_0, IB_ENHANCED_MODE)
1068 #define IBA7322_IBC_MAX_SPEED_MASK SYM_MASK(IBCCtrlB_0, SD_SPEED)
1069 #define IBA7322_IBC_SPEED_QDR SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR)
1070 #define IBA7322_IBC_SPEED_DDR SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR)
1071 #define IBA7322_IBC_SPEED_SDR SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR)
1072 #define IBA7322_IBC_SPEED_MASK (SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR) | \
1073 SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR) | SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR))
1074 #define IBA7322_IBC_SPEED_LSB SYM_LSB(IBCCtrlB_0, SD_SPEED_SDR)
1076 #define IBA7322_LEDBLINK_OFF_SHIFT SYM_LSB(RcvPktLEDCnt_0, OFFperiod)
1077 #define IBA7322_LEDBLINK_ON_SHIFT SYM_LSB(RcvPktLEDCnt_0, ONperiod)
1079 #define IBA7322_IBC_WIDTH_AUTONEG SYM_MASK(IBCCtrlB_0, IB_NUM_CHANNELS)
1080 #define IBA7322_IBC_WIDTH_4X_ONLY (1<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1081 #define IBA7322_IBC_WIDTH_1X_ONLY (0<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1083 #define IBA7322_IBC_RXPOL_MASK SYM_MASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1084 #define IBA7322_IBC_RXPOL_LSB SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1085 #define IBA7322_IBC_HRTBT_MASK (SYM_MASK(IBCCtrlB_0, HRTBT_AUTO) | \
1086 SYM_MASK(IBCCtrlB_0, HRTBT_ENB))
1087 #define IBA7322_IBC_HRTBT_RMASK (IBA7322_IBC_HRTBT_MASK >> \
1088 SYM_LSB(IBCCtrlB_0, HRTBT_ENB))
1089 #define IBA7322_IBC_HRTBT_LSB SYM_LSB(IBCCtrlB_0, HRTBT_ENB)
1091 #define IBA7322_REDIRECT_VEC_PER_REG 12
1093 #define IBA7322_SENDCHK_PKEY SYM_MASK(SendCheckControl_0, PKey_En)
1094 #define IBA7322_SENDCHK_BTHQP SYM_MASK(SendCheckControl_0, BTHQP_En)
1095 #define IBA7322_SENDCHK_SLID SYM_MASK(SendCheckControl_0, SLID_En)
1096 #define IBA7322_SENDCHK_RAW_IPV6 SYM_MASK(SendCheckControl_0, RawIPV6_En)
1097 #define IBA7322_SENDCHK_MINSZ SYM_MASK(SendCheckControl_0, PacketTooSmall_En)
1099 #define AUTONEG_TRIES 3 /* sequential retries to negotiate DDR */
1101 #define HWE_AUTO(fldname) { .mask = SYM_MASK(HwErrMask, fldname##Mask), \
1103 #define HWE_AUTO_P(fldname, port) { .mask = SYM_MASK(HwErrMask, \
1104 fldname##Mask##_##port), .msg = #fldname }
1105 static const struct qib_hwerror_msgs qib_7322_hwerror_msgs[] = {
1106 HWE_AUTO_P(IBSerdesPClkNotDetect, 1),
1107 HWE_AUTO_P(IBSerdesPClkNotDetect, 0),
1108 HWE_AUTO(PCIESerdesPClkNotDetect),
1109 HWE_AUTO(PowerOnBISTFailed),
1110 HWE_AUTO(TempsenseTholdReached),
1111 HWE_AUTO(MemoryErr),
1112 HWE_AUTO(PCIeBusParityErr),
1113 HWE_AUTO(PcieCplTimeout),
1114 HWE_AUTO(PciePoisonedTLP),
1115 HWE_AUTO_P(SDmaMemReadErr, 1),
1116 HWE_AUTO_P(SDmaMemReadErr, 0),
1117 HWE_AUTO_P(IBCBusFromSPCParityErr, 1),
1118 HWE_AUTO_P(IBCBusToSPCParityErr, 1),
1119 HWE_AUTO_P(IBCBusFromSPCParityErr, 0),
1120 HWE_AUTO(statusValidNoEop),
1121 HWE_AUTO(LATriggered),
1125 #define E_AUTO(fldname) { .mask = SYM_MASK(ErrMask, fldname##Mask), \
1127 #define E_P_AUTO(fldname) { .mask = SYM_MASK(ErrMask_0, fldname##Mask), \
1129 static const struct qib_hwerror_msgs qib_7322error_msgs[] = {
1130 E_AUTO(ResetNegated),
1131 E_AUTO(HardwareErr),
1132 E_AUTO(InvalidAddrErr),
1133 E_AUTO(SDmaVL15Err),
1134 E_AUTO(SBufVL15MisUseErr),
1135 E_AUTO(InvalidEEPCmd),
1136 E_AUTO(RcvContextShareErr),
1137 E_AUTO(SendVLMismatchErr),
1138 E_AUTO(SendArmLaunchErr),
1139 E_AUTO(SendSpecialTriggerErr),
1140 E_AUTO(SDmaWrongPortErr),
1141 E_AUTO(SDmaBufMaskDuplicateErr),
1142 E_AUTO(RcvHdrFullErr),
1143 E_AUTO(RcvEgrFullErr),
1147 static const struct qib_hwerror_msgs qib_7322p_error_msgs[] = {
1148 E_P_AUTO(IBStatusChanged),
1149 E_P_AUTO(SHeadersErr),
1150 E_P_AUTO(VL15BufMisuseErr),
1152 * SDmaHaltErr is not really an error, make it clearer;
1154 {.mask = SYM_MASK(ErrMask_0, SDmaHaltErrMask), .msg = "SDmaHalted"},
1155 E_P_AUTO(SDmaDescAddrMisalignErr),
1156 E_P_AUTO(SDmaUnexpDataErr),
1157 E_P_AUTO(SDmaMissingDwErr),
1158 E_P_AUTO(SDmaDwEnErr),
1159 E_P_AUTO(SDmaRpyTagErr),
1160 E_P_AUTO(SDma1stDescErr),
1161 E_P_AUTO(SDmaBaseErr),
1162 E_P_AUTO(SDmaTailOutOfBoundErr),
1163 E_P_AUTO(SDmaOutOfBoundErr),
1164 E_P_AUTO(SDmaGenMismatchErr),
1165 E_P_AUTO(SendBufMisuseErr),
1166 E_P_AUTO(SendUnsupportedVLErr),
1167 E_P_AUTO(SendUnexpectedPktNumErr),
1168 E_P_AUTO(SendDroppedDataPktErr),
1169 E_P_AUTO(SendDroppedSmpPktErr),
1170 E_P_AUTO(SendPktLenErr),
1171 E_P_AUTO(SendUnderRunErr),
1172 E_P_AUTO(SendMaxPktLenErr),
1173 E_P_AUTO(SendMinPktLenErr),
1174 E_P_AUTO(RcvIBLostLinkErr),
1175 E_P_AUTO(RcvHdrErr),
1176 E_P_AUTO(RcvHdrLenErr),
1177 E_P_AUTO(RcvBadTidErr),
1178 E_P_AUTO(RcvBadVersionErr),
1179 E_P_AUTO(RcvIBFlowErr),
1180 E_P_AUTO(RcvEBPErr),
1181 E_P_AUTO(RcvUnsupportedVLErr),
1182 E_P_AUTO(RcvUnexpectedCharErr),
1183 E_P_AUTO(RcvShortPktLenErr),
1184 E_P_AUTO(RcvLongPktLenErr),
1185 E_P_AUTO(RcvMaxPktLenErr),
1186 E_P_AUTO(RcvMinPktLenErr),
1187 E_P_AUTO(RcvICRCErr),
1188 E_P_AUTO(RcvVCRCErr),
1189 E_P_AUTO(RcvFormatErr),
1194 * Below generates "auto-message" for interrupts not specific to any port or
1197 #define INTR_AUTO(fldname) { .mask = SYM_MASK(IntMask, fldname##Mask), \
1199 /* Below generates "auto-message" for interrupts specific to a port */
1200 #define INTR_AUTO_P(fldname) { .mask = MASK_ACROSS(\
1201 SYM_LSB(IntMask, fldname##Mask##_0), \
1202 SYM_LSB(IntMask, fldname##Mask##_1)), \
1203 .msg = #fldname "_P" }
1204 /* For some reason, the SerDesTrimDone bits are reversed */
1205 #define INTR_AUTO_PI(fldname) { .mask = MASK_ACROSS(\
1206 SYM_LSB(IntMask, fldname##Mask##_1), \
1207 SYM_LSB(IntMask, fldname##Mask##_0)), \
1208 .msg = #fldname "_P" }
1210 * Below generates "auto-message" for interrupts specific to a context,
1211 * with ctxt-number appended
1213 #define INTR_AUTO_C(fldname) { .mask = MASK_ACROSS(\
1214 SYM_LSB(IntMask, fldname##0IntMask), \
1215 SYM_LSB(IntMask, fldname##17IntMask)), \
1216 .msg = #fldname "_C"}
1218 static const struct qib_hwerror_msgs qib_7322_intr_msgs[] = {
1219 INTR_AUTO_P(SDmaInt),
1220 INTR_AUTO_P(SDmaProgressInt),
1221 INTR_AUTO_P(SDmaIdleInt),
1222 INTR_AUTO_P(SDmaCleanupDone),
1223 INTR_AUTO_C(RcvUrg),
1224 INTR_AUTO_P(ErrInt),
1225 INTR_AUTO(ErrInt), /* non-port-specific errs */
1226 INTR_AUTO(AssertGPIOInt),
1227 INTR_AUTO_P(SendDoneInt),
1228 INTR_AUTO(SendBufAvailInt),
1229 INTR_AUTO_C(RcvAvail),
1233 #define TXSYMPTOM_AUTO_P(fldname) \
1234 { .mask = SYM_MASK(SendHdrErrSymptom_0, fldname), .msg = #fldname }
1235 static const struct qib_hwerror_msgs hdrchk_msgs[] = {
1236 TXSYMPTOM_AUTO_P(NonKeyPacket),
1237 TXSYMPTOM_AUTO_P(GRHFail),
1238 TXSYMPTOM_AUTO_P(PkeyFail),
1239 TXSYMPTOM_AUTO_P(QPFail),
1240 TXSYMPTOM_AUTO_P(SLIDFail),
1241 TXSYMPTOM_AUTO_P(RawIPV6),
1242 TXSYMPTOM_AUTO_P(PacketTooSmall),
1246 #define IBA7322_HDRHEAD_PKTINT_SHIFT 32 /* interrupt cnt in upper 32 bits */
1249 * Called when we might have an error that is specific to a particular
1250 * PIO buffer, and may need to cancel that buffer, so it can be re-used,
1251 * because we don't need to force the update of pioavail
1253 static void qib_disarm_7322_senderrbufs(struct qib_pportdata *ppd)
1255 struct qib_devdata *dd = ppd->dd;
1258 u32 piobcnt = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
1259 u32 regcnt = (piobcnt + BITS_PER_LONG - 1) / BITS_PER_LONG;
1260 unsigned long sbuf[4];
1263 * It's possible that sendbuffererror could have bits set; might
1264 * have already done this as a result of hardware error handling.
1267 for (i = 0; i < regcnt; ++i) {
1268 sbuf[i] = qib_read_kreg64(dd, kr_sendbuffererror + i);
1271 qib_write_kreg(dd, kr_sendbuffererror + i, sbuf[i]);
1276 qib_disarm_piobufs_set(dd, sbuf, piobcnt);
1279 /* No txe_recover yet, if ever */
1281 /* No decode__errors yet */
1282 static void err_decode(char *msg, size_t len, u64 errs,
1283 const struct qib_hwerror_msgs *msp)
1286 int took, multi, n = 0;
1288 while (msp && msp->mask) {
1289 multi = (msp->mask & (msp->mask - 1));
1290 while (errs & msp->mask) {
1291 these = (errs & msp->mask);
1292 lmask = (these & (these - 1)) ^ these;
1295 /* separate the strings */
1299 took = scnprintf(msg, len, "%s", msp->msg);
1305 /* More than one bit this mask */
1308 while (lmask & msp->mask) {
1312 took = scnprintf(msg, len, "_%d", idx);
1319 /* If some bits are left, show in hex. */
1321 snprintf(msg, len, "%sMORE:%llX", n ? "," : "",
1322 (unsigned long long) errs);
1325 /* only called if r1 set */
1326 static void flush_fifo(struct qib_pportdata *ppd)
1328 struct qib_devdata *dd = ppd->dd;
1329 u32 __iomem *piobuf;
1333 const unsigned hdrwords = 7;
1334 static struct qib_ib_header ibhdr = {
1335 .lrh[0] = cpu_to_be16(0xF000 | QIB_LRH_BTH),
1336 .lrh[1] = IB_LID_PERMISSIVE,
1337 .lrh[2] = cpu_to_be16(hdrwords + SIZE_OF_CRC),
1338 .lrh[3] = IB_LID_PERMISSIVE,
1339 .u.oth.bth[0] = cpu_to_be32(
1340 (IB_OPCODE_UD_SEND_ONLY << 24) | QIB_DEFAULT_P_KEY),
1341 .u.oth.bth[1] = cpu_to_be32(0),
1342 .u.oth.bth[2] = cpu_to_be32(0),
1343 .u.oth.u.ud.deth[0] = cpu_to_be32(0),
1344 .u.oth.u.ud.deth[1] = cpu_to_be32(0),
1348 * Send a dummy VL15 packet to flush the launch FIFO.
1349 * This will not actually be sent since the TxeBypassIbc bit is set.
1351 pbc = PBC_7322_VL15_SEND |
1352 (((u64)ppd->hw_pidx) << (PBC_PORT_SEL_LSB + 32)) |
1353 (hdrwords + SIZE_OF_CRC);
1354 piobuf = qib_7322_getsendbuf(ppd, pbc, &bufn);
1357 writeq(pbc, piobuf);
1358 hdr = (u32 *) &ibhdr;
1359 if (dd->flags & QIB_PIO_FLUSH_WC) {
1361 qib_pio_copy(piobuf + 2, hdr, hdrwords - 1);
1363 __raw_writel(hdr[hdrwords - 1], piobuf + hdrwords + 1);
1366 qib_pio_copy(piobuf + 2, hdr, hdrwords);
1367 qib_sendbuf_done(dd, bufn);
1371 * This is called with interrupts disabled and sdma_lock held.
1373 static void qib_7322_sdma_sendctrl(struct qib_pportdata *ppd, unsigned op)
1375 struct qib_devdata *dd = ppd->dd;
1376 u64 set_sendctrl = 0;
1377 u64 clr_sendctrl = 0;
1379 if (op & QIB_SDMA_SENDCTRL_OP_ENABLE)
1380 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable);
1382 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable);
1384 if (op & QIB_SDMA_SENDCTRL_OP_INTENABLE)
1385 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable);
1387 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable);
1389 if (op & QIB_SDMA_SENDCTRL_OP_HALT)
1390 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt);
1392 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt);
1394 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN)
1395 set_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) |
1396 SYM_MASK(SendCtrl_0, TxeAbortIbc) |
1397 SYM_MASK(SendCtrl_0, TxeDrainRmFifo);
1399 clr_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) |
1400 SYM_MASK(SendCtrl_0, TxeAbortIbc) |
1401 SYM_MASK(SendCtrl_0, TxeDrainRmFifo);
1403 spin_lock(&dd->sendctrl_lock);
1405 /* If we are draining everything, block sends first */
1406 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) {
1407 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable);
1408 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1409 qib_write_kreg(dd, kr_scratch, 0);
1412 ppd->p_sendctrl |= set_sendctrl;
1413 ppd->p_sendctrl &= ~clr_sendctrl;
1415 if (op & QIB_SDMA_SENDCTRL_OP_CLEANUP)
1416 qib_write_kreg_port(ppd, krp_sendctrl,
1418 SYM_MASK(SendCtrl_0, SDmaCleanup));
1420 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1421 qib_write_kreg(dd, kr_scratch, 0);
1423 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) {
1424 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable);
1425 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1426 qib_write_kreg(dd, kr_scratch, 0);
1429 spin_unlock(&dd->sendctrl_lock);
1431 if ((op & QIB_SDMA_SENDCTRL_OP_DRAIN) && ppd->dd->cspec->r1)
1435 static void qib_7322_sdma_hw_clean_up(struct qib_pportdata *ppd)
1437 __qib_sdma_process_event(ppd, qib_sdma_event_e50_hw_cleaned);
1440 static void qib_sdma_7322_setlengen(struct qib_pportdata *ppd)
1443 * Set SendDmaLenGen and clear and set
1444 * the MSB of the generation count to enable generation checking
1445 * and load the internal generation counter.
1447 qib_write_kreg_port(ppd, krp_senddmalengen, ppd->sdma_descq_cnt);
1448 qib_write_kreg_port(ppd, krp_senddmalengen,
1449 ppd->sdma_descq_cnt |
1450 (1ULL << QIB_7322_SendDmaLenGen_0_Generation_MSB));
1454 * Must be called with sdma_lock held, or before init finished.
1456 static void qib_sdma_update_7322_tail(struct qib_pportdata *ppd, u16 tail)
1458 /* Commit writes to memory and advance the tail on the chip */
1460 ppd->sdma_descq_tail = tail;
1461 qib_write_kreg_port(ppd, krp_senddmatail, tail);
1465 * This is called with interrupts disabled and sdma_lock held.
1467 static void qib_7322_sdma_hw_start_up(struct qib_pportdata *ppd)
1471 * The hardware doesn't require this but we do it so that verbs
1472 * and user applications don't wait for link active to send stale
1475 sendctrl_7322_mod(ppd, QIB_SENDCTRL_FLUSH);
1477 qib_sdma_7322_setlengen(ppd);
1478 qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */
1479 ppd->sdma_head_dma[0] = 0;
1480 qib_7322_sdma_sendctrl(ppd,
1481 ppd->sdma_state.current_op | QIB_SDMA_SENDCTRL_OP_CLEANUP);
1484 #define DISABLES_SDMA ( \
1485 QIB_E_P_SDMAHALT | \
1486 QIB_E_P_SDMADESCADDRMISALIGN | \
1487 QIB_E_P_SDMAMISSINGDW | \
1488 QIB_E_P_SDMADWEN | \
1489 QIB_E_P_SDMARPYTAG | \
1490 QIB_E_P_SDMA1STDESC | \
1491 QIB_E_P_SDMABASE | \
1492 QIB_E_P_SDMATAILOUTOFBOUND | \
1493 QIB_E_P_SDMAOUTOFBOUND | \
1494 QIB_E_P_SDMAGENMISMATCH)
1496 static void sdma_7322_p_errors(struct qib_pportdata *ppd, u64 errs)
1498 unsigned long flags;
1499 struct qib_devdata *dd = ppd->dd;
1501 errs &= QIB_E_P_SDMAERRS;
1503 if (errs & QIB_E_P_SDMAUNEXPDATA)
1504 qib_dev_err(dd, "IB%u:%u SDmaUnexpData\n", dd->unit,
1507 spin_lock_irqsave(&ppd->sdma_lock, flags);
1509 switch (ppd->sdma_state.current_state) {
1510 case qib_sdma_state_s00_hw_down:
1513 case qib_sdma_state_s10_hw_start_up_wait:
1514 if (errs & QIB_E_P_SDMAHALT)
1515 __qib_sdma_process_event(ppd,
1516 qib_sdma_event_e20_hw_started);
1519 case qib_sdma_state_s20_idle:
1522 case qib_sdma_state_s30_sw_clean_up_wait:
1525 case qib_sdma_state_s40_hw_clean_up_wait:
1526 if (errs & QIB_E_P_SDMAHALT)
1527 __qib_sdma_process_event(ppd,
1528 qib_sdma_event_e50_hw_cleaned);
1531 case qib_sdma_state_s50_hw_halt_wait:
1532 if (errs & QIB_E_P_SDMAHALT)
1533 __qib_sdma_process_event(ppd,
1534 qib_sdma_event_e60_hw_halted);
1537 case qib_sdma_state_s99_running:
1538 __qib_sdma_process_event(ppd, qib_sdma_event_e7322_err_halted);
1539 __qib_sdma_process_event(ppd, qib_sdma_event_e60_hw_halted);
1543 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
1547 * handle per-device errors (not per-port errors)
1549 static noinline void handle_7322_errors(struct qib_devdata *dd)
1557 qib_stats.sps_errints++;
1558 errs = qib_read_kreg64(dd, kr_errstatus);
1560 qib_devinfo(dd->pcidev, "device error interrupt, "
1561 "but no error bits set!\n");
1565 /* don't report errors that are masked */
1566 errs &= dd->cspec->errormask;
1567 msg = dd->cspec->emsgbuf;
1569 /* do these first, they are most important */
1570 if (errs & QIB_E_HARDWARE) {
1572 qib_7322_handle_hwerrors(dd, msg, sizeof dd->cspec->emsgbuf);
1574 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx)
1575 if (errs & dd->eep_st_masks[log_idx].errs_to_log)
1576 qib_inc_eeprom_err(dd, log_idx, 1);
1578 if (errs & QIB_E_SPKTERRS) {
1579 qib_disarm_7322_senderrbufs(dd->pport);
1580 qib_stats.sps_txerrs++;
1581 } else if (errs & QIB_E_INVALIDADDR)
1582 qib_stats.sps_txerrs++;
1583 else if (errs & QIB_E_ARMLAUNCH) {
1584 qib_stats.sps_txerrs++;
1585 qib_disarm_7322_senderrbufs(dd->pport);
1587 qib_write_kreg(dd, kr_errclear, errs);
1590 * The ones we mask off are handled specially below
1591 * or above. Also mask SDMADISABLED by default as it
1594 mask = QIB_E_HARDWARE;
1597 err_decode(msg, sizeof dd->cspec->emsgbuf, errs & ~mask,
1598 qib_7322error_msgs);
1601 * Getting reset is a tragedy for all ports. Mark the device
1602 * _and_ the ports as "offline" in way meaningful to each.
1604 if (errs & QIB_E_RESET) {
1607 qib_dev_err(dd, "Got reset, requires re-init "
1608 "(unload and reload driver)\n");
1609 dd->flags &= ~QIB_INITTED; /* needs re-init */
1610 /* mark as having had error */
1611 *dd->devstatusp |= QIB_STATUS_HWERROR;
1612 for (pidx = 0; pidx < dd->num_pports; ++pidx)
1613 if (dd->pport[pidx].link_speed_supported)
1614 *dd->pport[pidx].statusp &= ~QIB_STATUS_IB_CONF;
1618 qib_dev_err(dd, "%s error\n", msg);
1621 * If there were hdrq or egrfull errors, wake up any processes
1622 * waiting in poll. We used to try to check which contexts had
1623 * the overflow, but given the cost of that and the chip reads
1624 * to support it, it's better to just wake everybody up if we
1625 * get an overflow; waiters can poll again if it's not them.
1627 if (errs & (ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr))) {
1628 qib_handle_urcv(dd, ~0U);
1629 if (errs & ERR_MASK(RcvEgrFullErr))
1630 qib_stats.sps_buffull++;
1632 qib_stats.sps_hdrfull++;
1639 static void reenable_chase(unsigned long opaque)
1641 struct qib_pportdata *ppd = (struct qib_pportdata *)opaque;
1643 ppd->cpspec->chase_timer.expires = 0;
1644 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
1645 QLOGIC_IB_IBCC_LINKINITCMD_POLL);
1648 static void disable_chase(struct qib_pportdata *ppd, u64 tnow, u8 ibclt)
1650 ppd->cpspec->chase_end = 0;
1655 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
1656 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1657 ppd->cpspec->chase_timer.expires = jiffies + QIB_CHASE_DIS_TIME;
1658 add_timer(&ppd->cpspec->chase_timer);
1661 static void handle_serdes_issues(struct qib_pportdata *ppd, u64 ibcst)
1666 ibclt = (u8)SYM_FIELD(ibcst, IBCStatusA_0, LinkTrainingState);
1669 * Detect and handle the state chase issue, where we can
1670 * get stuck if we are unlucky on timing on both sides of
1671 * the link. If we are, we disable, set a timer, and
1675 case IB_7322_LT_STATE_CFGRCVFCFG:
1676 case IB_7322_LT_STATE_CFGWAITRMT:
1677 case IB_7322_LT_STATE_TXREVLANES:
1678 case IB_7322_LT_STATE_CFGENH:
1679 tnow = get_jiffies_64();
1680 if (ppd->cpspec->chase_end &&
1681 time_after64(tnow, ppd->cpspec->chase_end))
1682 disable_chase(ppd, tnow, ibclt);
1683 else if (!ppd->cpspec->chase_end)
1684 ppd->cpspec->chase_end = tnow + QIB_CHASE_TIME;
1687 ppd->cpspec->chase_end = 0;
1691 if (ibclt == IB_7322_LT_STATE_CFGTEST &&
1692 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR))) {
1694 ppd->cpspec->qdr_reforce = 1;
1695 } else if (ppd->cpspec->qdr_reforce &&
1696 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) &&
1697 (ibclt == IB_7322_LT_STATE_CFGENH ||
1698 ibclt == IB_7322_LT_STATE_CFGIDLE ||
1699 ibclt == IB_7322_LT_STATE_LINKUP))
1702 if ((IS_QMH(ppd->dd) || IS_QME(ppd->dd)) &&
1703 ppd->link_speed_enabled == QIB_IB_QDR &&
1704 (ibclt == IB_7322_LT_STATE_CFGTEST ||
1705 ibclt == IB_7322_LT_STATE_CFGENH ||
1706 (ibclt >= IB_7322_LT_STATE_POLLACTIVE &&
1707 ibclt <= IB_7322_LT_STATE_SLEEPQUIET)))
1710 if (!ppd->cpspec->qdr_dfe_on && ibclt != IB_7322_LT_STATE_LINKUP &&
1711 ibclt <= IB_7322_LT_STATE_SLEEPQUIET) {
1712 ppd->cpspec->qdr_dfe_on = 1;
1713 ppd->cpspec->qdr_dfe_time = 0;
1714 /* On link down, reenable QDR adaptation */
1715 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
1716 ppd->dd->cspec->r1 ?
1717 QDR_STATIC_ADAPT_DOWN_R1 :
1718 QDR_STATIC_ADAPT_DOWN);
1723 * This is per-pport error handling.
1724 * will likely get it's own MSIx interrupt (one for each port,
1725 * although just a single handler).
1727 static noinline void handle_7322_p_errors(struct qib_pportdata *ppd)
1730 u64 ignore_this_time = 0, iserr = 0, errs, fmask;
1731 struct qib_devdata *dd = ppd->dd;
1733 /* do this as soon as possible */
1734 fmask = qib_read_kreg64(dd, kr_act_fmask);
1736 check_7322_rxe_status(ppd);
1738 errs = qib_read_kreg_port(ppd, krp_errstatus);
1740 qib_devinfo(dd->pcidev,
1741 "Port%d error interrupt, but no error bits set!\n",
1744 errs &= ~QIB_E_P_IBSTATUSCHANGED;
1748 msg = ppd->cpspec->epmsgbuf;
1751 if (errs & ~QIB_E_P_BITSEXTANT) {
1752 err_decode(msg, sizeof ppd->cpspec->epmsgbuf,
1753 errs & ~QIB_E_P_BITSEXTANT, qib_7322p_error_msgs);
1755 snprintf(msg, sizeof ppd->cpspec->epmsgbuf,
1757 qib_dev_porterr(dd, ppd->port, "error interrupt with unknown"
1758 " errors 0x%016Lx set (and %s)\n",
1759 (errs & ~QIB_E_P_BITSEXTANT), msg);
1763 if (errs & QIB_E_P_SHDR) {
1766 /* determine cause, then write to clear */
1767 symptom = qib_read_kreg_port(ppd, krp_sendhdrsymptom);
1768 qib_write_kreg_port(ppd, krp_sendhdrsymptom, 0);
1769 err_decode(msg, sizeof ppd->cpspec->epmsgbuf, symptom,
1772 /* senderrbuf cleared in SPKTERRS below */
1775 if (errs & QIB_E_P_SPKTERRS) {
1776 if ((errs & QIB_E_P_LINK_PKTERRS) &&
1777 !(ppd->lflags & QIBL_LINKACTIVE)) {
1779 * This can happen when trying to bring the link
1780 * up, but the IB link changes state at the "wrong"
1781 * time. The IB logic then complains that the packet
1782 * isn't valid. We don't want to confuse people, so
1783 * we just don't print them, except at debug
1785 err_decode(msg, sizeof ppd->cpspec->epmsgbuf,
1786 (errs & QIB_E_P_LINK_PKTERRS),
1787 qib_7322p_error_msgs);
1789 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS;
1791 qib_disarm_7322_senderrbufs(ppd);
1792 } else if ((errs & QIB_E_P_LINK_PKTERRS) &&
1793 !(ppd->lflags & QIBL_LINKACTIVE)) {
1795 * This can happen when SMA is trying to bring the link
1796 * up, but the IB link changes state at the "wrong" time.
1797 * The IB logic then complains that the packet isn't
1798 * valid. We don't want to confuse people, so we just
1799 * don't print them, except at debug
1801 err_decode(msg, sizeof ppd->cpspec->epmsgbuf, errs,
1802 qib_7322p_error_msgs);
1803 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS;
1807 qib_write_kreg_port(ppd, krp_errclear, errs);
1809 errs &= ~ignore_this_time;
1813 if (errs & QIB_E_P_RPKTERRS)
1814 qib_stats.sps_rcverrs++;
1815 if (errs & QIB_E_P_SPKTERRS)
1816 qib_stats.sps_txerrs++;
1818 iserr = errs & ~(QIB_E_P_RPKTERRS | QIB_E_P_PKTERRS);
1820 if (errs & QIB_E_P_SDMAERRS)
1821 sdma_7322_p_errors(ppd, errs);
1823 if (errs & QIB_E_P_IBSTATUSCHANGED) {
1827 ibcs = qib_read_kreg_port(ppd, krp_ibcstatus_a);
1828 ltstate = qib_7322_phys_portstate(ibcs);
1830 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
1831 handle_serdes_issues(ppd, ibcs);
1832 if (!(ppd->cpspec->ibcctrl_a &
1833 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn))) {
1835 * We got our interrupt, so init code should be
1836 * happy and not try alternatives. Now squelch
1837 * other "chatter" from link-negotiation (pre Init)
1839 ppd->cpspec->ibcctrl_a |=
1840 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
1841 qib_write_kreg_port(ppd, krp_ibcctrl_a,
1842 ppd->cpspec->ibcctrl_a);
1845 /* Update our picture of width and speed from chip */
1846 ppd->link_width_active =
1847 (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) ?
1848 IB_WIDTH_4X : IB_WIDTH_1X;
1849 ppd->link_speed_active = (ibcs & SYM_MASK(IBCStatusA_0,
1850 LinkSpeedQDR)) ? QIB_IB_QDR : (ibcs &
1851 SYM_MASK(IBCStatusA_0, LinkSpeedActive)) ?
1852 QIB_IB_DDR : QIB_IB_SDR;
1854 if ((ppd->lflags & QIBL_IB_LINK_DISABLED) && ltstate !=
1855 IB_PHYSPORTSTATE_DISABLED)
1856 qib_set_ib_7322_lstate(ppd, 0,
1857 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1860 * Since going into a recovery state causes the link
1861 * state to go down and since recovery is transitory,
1862 * it is better if we "miss" ever seeing the link
1863 * training state go into recovery (i.e., ignore this
1864 * transition for link state special handling purposes)
1865 * without updating lastibcstat.
1867 if (ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER &&
1868 ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN &&
1869 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT &&
1870 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE)
1871 qib_handle_e_ibstatuschanged(ppd, ibcs);
1874 qib_dev_porterr(dd, ppd->port, "%s error\n", msg);
1876 if (ppd->state_wanted & ppd->lflags)
1877 wake_up_interruptible(&ppd->state_wait);
1882 /* enable/disable chip from delivering interrupts */
1883 static void qib_7322_set_intr_state(struct qib_devdata *dd, u32 enable)
1886 if (dd->flags & QIB_BADINTR)
1888 qib_write_kreg(dd, kr_intmask, dd->cspec->int_enable_mask);
1889 /* cause any pending enabled interrupts to be re-delivered */
1890 qib_write_kreg(dd, kr_intclear, 0ULL);
1891 if (dd->cspec->num_msix_entries) {
1892 /* and same for MSIx */
1893 u64 val = qib_read_kreg64(dd, kr_intgranted);
1895 qib_write_kreg(dd, kr_intgranted, val);
1898 qib_write_kreg(dd, kr_intmask, 0ULL);
1902 * Try to cleanup as much as possible for anything that might have gone
1903 * wrong while in freeze mode, such as pio buffers being written by user
1904 * processes (causing armlaunch), send errors due to going into freeze mode,
1905 * etc., and try to avoid causing extra interrupts while doing so.
1906 * Forcibly update the in-memory pioavail register copies after cleanup
1907 * because the chip won't do it while in freeze mode (the register values
1908 * themselves are kept correct).
1909 * Make sure that we don't lose any important interrupts by using the chip
1910 * feature that says that writing 0 to a bit in *clear that is set in
1911 * *status will cause an interrupt to be generated again (if allowed by
1913 * This is in chip-specific code because of all of the register accesses,
1914 * even though the details are similar on most chips.
1916 static void qib_7322_clear_freeze(struct qib_devdata *dd)
1920 /* disable error interrupts, to avoid confusion */
1921 qib_write_kreg(dd, kr_errmask, 0ULL);
1923 for (pidx = 0; pidx < dd->num_pports; ++pidx)
1924 if (dd->pport[pidx].link_speed_supported)
1925 qib_write_kreg_port(dd->pport + pidx, krp_errmask,
1928 /* also disable interrupts; errormask is sometimes overwriten */
1929 qib_7322_set_intr_state(dd, 0);
1931 /* clear the freeze, and be sure chip saw it */
1932 qib_write_kreg(dd, kr_control, dd->control);
1933 qib_read_kreg32(dd, kr_scratch);
1936 * Force new interrupt if any hwerr, error or interrupt bits are
1937 * still set, and clear "safe" send packet errors related to freeze
1938 * and cancelling sends. Re-enable error interrupts before possible
1939 * force of re-interrupt on pending interrupts.
1941 qib_write_kreg(dd, kr_hwerrclear, 0ULL);
1942 qib_write_kreg(dd, kr_errclear, E_SPKT_ERRS_IGNORE);
1943 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1944 /* We need to purge per-port errs and reset mask, too */
1945 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1946 if (!dd->pport[pidx].link_speed_supported)
1948 qib_write_kreg_port(dd->pport + pidx, krp_errclear, ~0Ull);
1949 qib_write_kreg_port(dd->pport + pidx, krp_errmask, ~0Ull);
1951 qib_7322_set_intr_state(dd, 1);
1954 /* no error handling to speak of */
1956 * qib_7322_handle_hwerrors - display hardware errors.
1957 * @dd: the qlogic_ib device
1958 * @msg: the output buffer
1959 * @msgl: the size of the output buffer
1961 * Use same msg buffer as regular errors to avoid excessive stack
1962 * use. Most hardware errors are catastrophic, but for right now,
1963 * we'll print them and continue. We reuse the same message buffer as
1964 * qib_handle_errors() to avoid excessive stack usage.
1966 static void qib_7322_handle_hwerrors(struct qib_devdata *dd, char *msg,
1973 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
1976 if (hwerrs == ~0ULL) {
1977 qib_dev_err(dd, "Read of hardware error status failed "
1978 "(all bits set); ignoring\n");
1981 qib_stats.sps_hwerrs++;
1983 /* Always clear the error status register, except BIST fail */
1984 qib_write_kreg(dd, kr_hwerrclear, hwerrs &
1985 ~HWE_MASK(PowerOnBISTFailed));
1987 hwerrs &= dd->cspec->hwerrmask;
1989 /* no EEPROM logging, yet */
1992 qib_devinfo(dd->pcidev, "Hardware error: hwerr=0x%llx "
1993 "(cleared)\n", (unsigned long long) hwerrs);
1995 ctrl = qib_read_kreg32(dd, kr_control);
1996 if ((ctrl & SYM_MASK(Control, FreezeMode)) && !dd->diag_client) {
1998 * No recovery yet...
2000 if ((hwerrs & ~HWE_MASK(LATriggered)) ||
2001 dd->cspec->stay_in_freeze) {
2003 * If any set that we aren't ignoring only make the
2004 * complaint once, in case it's stuck or recurring,
2005 * and we get here multiple times
2006 * Force link down, so switch knows, and
2007 * LEDs are turned off.
2009 if (dd->flags & QIB_INITTED)
2012 qib_7322_clear_freeze(dd);
2015 if (hwerrs & HWE_MASK(PowerOnBISTFailed)) {
2017 strlcpy(msg, "[Memory BIST test failed, "
2018 "InfiniPath hardware unusable]", msgl);
2019 /* ignore from now on, so disable until driver reloaded */
2020 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed);
2021 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2024 err_decode(msg, msgl, hwerrs, qib_7322_hwerror_msgs);
2026 /* Ignore esoteric PLL failures et al. */
2028 qib_dev_err(dd, "%s hardware error\n", msg);
2030 if (isfatal && !dd->diag_client) {
2031 qib_dev_err(dd, "Fatal Hardware Error, no longer"
2032 " usable, SN %.16s\n", dd->serial);
2034 * for /sys status file and user programs to print; if no
2035 * trailing brace is copied, we'll know it was truncated.
2038 snprintf(dd->freezemsg, dd->freezelen,
2040 qib_disable_after_error(dd);
2046 * qib_7322_init_hwerrors - enable hardware errors
2047 * @dd: the qlogic_ib device
2049 * now that we have finished initializing everything that might reasonably
2050 * cause a hardware error, and cleared those errors bits as they occur,
2051 * we can enable hardware errors in the mask (potentially enabling
2052 * freeze mode), and enable hardware errors as errors (along with
2053 * everything else) in errormask
2055 static void qib_7322_init_hwerrors(struct qib_devdata *dd)
2060 extsval = qib_read_kreg64(dd, kr_extstatus);
2061 if (!(extsval & (QIB_EXTS_MEMBIST_DISABLED |
2062 QIB_EXTS_MEMBIST_ENDTEST)))
2063 qib_dev_err(dd, "MemBIST did not complete!\n");
2065 /* never clear BIST failure, so reported on each driver load */
2066 qib_write_kreg(dd, kr_hwerrclear, ~HWE_MASK(PowerOnBISTFailed));
2067 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2070 qib_write_kreg(dd, kr_errclear, ~0ULL);
2071 /* enable errors that are masked, at least this first time. */
2072 qib_write_kreg(dd, kr_errmask, ~0ULL);
2073 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask);
2074 for (pidx = 0; pidx < dd->num_pports; ++pidx)
2075 if (dd->pport[pidx].link_speed_supported)
2076 qib_write_kreg_port(dd->pport + pidx, krp_errmask,
2081 * Disable and enable the armlaunch error. Used for PIO bandwidth testing
2082 * on chips that are count-based, rather than trigger-based. There is no
2083 * reference counting, but that's also fine, given the intended use.
2084 * Only chip-specific because it's all register accesses
2086 static void qib_set_7322_armlaunch(struct qib_devdata *dd, u32 enable)
2089 qib_write_kreg(dd, kr_errclear, QIB_E_SPIOARMLAUNCH);
2090 dd->cspec->errormask |= QIB_E_SPIOARMLAUNCH;
2092 dd->cspec->errormask &= ~QIB_E_SPIOARMLAUNCH;
2093 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
2097 * Formerly took parameter <which> in pre-shifted,
2098 * pre-merged form with LinkCmd and LinkInitCmd
2099 * together, and assuming the zero was NOP.
2101 static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd,
2105 struct qib_devdata *dd = ppd->dd;
2106 unsigned long flags;
2108 if (linitcmd == QLOGIC_IB_IBCC_LINKINITCMD_DISABLE) {
2110 * If we are told to disable, note that so link-recovery
2111 * code does not attempt to bring us back up.
2112 * Also reset everything that we can, so we start
2113 * completely clean when re-enabled (before we
2114 * actually issue the disable to the IBC)
2116 qib_7322_mini_pcs_reset(ppd);
2117 spin_lock_irqsave(&ppd->lflags_lock, flags);
2118 ppd->lflags |= QIBL_IB_LINK_DISABLED;
2119 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2120 } else if (linitcmd || linkcmd == QLOGIC_IB_IBCC_LINKCMD_DOWN) {
2122 * Any other linkinitcmd will lead to LINKDOWN and then
2123 * to INIT (if all is well), so clear flag to let
2124 * link-recovery code attempt to bring us back up.
2126 spin_lock_irqsave(&ppd->lflags_lock, flags);
2127 ppd->lflags &= ~QIBL_IB_LINK_DISABLED;
2128 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2130 * Clear status change interrupt reduction so the
2131 * new state is seen.
2133 ppd->cpspec->ibcctrl_a &=
2134 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
2137 mod_wd = (linkcmd << IBA7322_IBCC_LINKCMD_SHIFT) |
2138 (linitcmd << QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
2140 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a |
2142 /* write to chip to prevent back-to-back writes of ibc reg */
2143 qib_write_kreg(dd, kr_scratch, 0);
2148 * The total RCV buffer memory is 64KB, used for both ports, and is
2149 * in units of 64 bytes (same as IB flow control credit unit).
2150 * The consumedVL unit in the same registers are in 32 byte units!
2151 * So, a VL15 packet needs 4.50 IB credits, and 9 rx buffer chunks,
2152 * and we can therefore allocate just 9 IB credits for 2 VL15 packets
2153 * in krp_rxcreditvl15, rather than 10.
2155 #define RCV_BUF_UNITSZ 64
2156 #define NUM_RCV_BUF_UNITS(dd) ((64 * 1024) / (RCV_BUF_UNITSZ * dd->num_pports))
2158 static void set_vls(struct qib_pportdata *ppd)
2160 int i, numvls, totcred, cred_vl, vl0extra;
2161 struct qib_devdata *dd = ppd->dd;
2164 numvls = qib_num_vls(ppd->vls_operational);
2167 * Set up per-VL credits. Below is kluge based on these assumptions:
2168 * 1) port is disabled at the time early_init is called.
2169 * 2) give VL15 17 credits, for two max-plausible packets.
2170 * 3) Give VL0-N the rest, with any rounding excess used for VL0
2172 /* 2 VL15 packets @ 288 bytes each (including IB headers) */
2173 totcred = NUM_RCV_BUF_UNITS(dd);
2174 cred_vl = (2 * 288 + RCV_BUF_UNITSZ - 1) / RCV_BUF_UNITSZ;
2176 qib_write_kreg_port(ppd, krp_rxcreditvl15, (u64) cred_vl);
2177 cred_vl = totcred / numvls;
2178 vl0extra = totcred - cred_vl * numvls;
2179 qib_write_kreg_port(ppd, krp_rxcreditvl0, cred_vl + vl0extra);
2180 for (i = 1; i < numvls; i++)
2181 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, cred_vl);
2182 for (; i < 8; i++) /* no buffer space for other VLs */
2183 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0);
2185 /* Notify IBC that credits need to be recalculated */
2186 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx);
2187 val |= SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
2188 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
2189 qib_write_kreg(dd, kr_scratch, 0ULL);
2190 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
2191 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
2193 for (i = 0; i < numvls; i++)
2194 val = qib_read_kreg_port(ppd, krp_rxcreditvl0 + i);
2195 val = qib_read_kreg_port(ppd, krp_rxcreditvl15);
2197 /* Change the number of operational VLs */
2198 ppd->cpspec->ibcctrl_a = (ppd->cpspec->ibcctrl_a &
2199 ~SYM_MASK(IBCCtrlA_0, NumVLane)) |
2200 ((u64)(numvls - 1) << SYM_LSB(IBCCtrlA_0, NumVLane));
2201 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
2202 qib_write_kreg(dd, kr_scratch, 0ULL);
2206 * The code that deals with actual SerDes is in serdes_7322_init().
2207 * Compared to the code for iba7220, it is minimal.
2209 static int serdes_7322_init(struct qib_pportdata *ppd);
2212 * qib_7322_bringup_serdes - bring up the serdes
2213 * @ppd: physical port on the qlogic_ib device
2215 static int qib_7322_bringup_serdes(struct qib_pportdata *ppd)
2217 struct qib_devdata *dd = ppd->dd;
2219 unsigned long flags;
2223 * SerDes model not in Pd, but still need to
2224 * set up much of IBCCtrl and IBCDDRCtrl; move elsewhere
2227 /* Put IBC in reset, sends disabled (should be in reset already) */
2228 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn);
2229 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
2230 qib_write_kreg(dd, kr_scratch, 0ULL);
2232 if (qib_compat_ddr_negotiate) {
2233 ppd->cpspec->ibdeltainprog = 1;
2234 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd,
2236 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd,
2237 crp_iblinkerrrecov);
2240 /* flowcontrolwatermark is in units of KBytes */
2241 ibc = 0x5ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlWaterMark);
2243 * Flow control is sent this often, even if no changes in
2244 * buffer space occur. Units are 128ns for this chip.
2247 ibc |= 24ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlPeriod);
2248 /* max error tolerance */
2249 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, PhyerrThreshold);
2250 /* IB credit flow control. */
2251 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, OverrunThreshold);
2253 * set initial max size pkt IBC will send, including ICRC; it's the
2254 * PIO buffer size in dwords, less 1; also see qib_set_mtu()
2256 ibc |= ((u64)(ppd->ibmaxlen >> 2) + 1) <<
2257 SYM_LSB(IBCCtrlA_0, MaxPktLen);
2258 ppd->cpspec->ibcctrl_a = ibc; /* without linkcmd or linkinitcmd! */
2260 /* initially come up waiting for TS1, without sending anything. */
2261 val = ppd->cpspec->ibcctrl_a | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE <<
2262 QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
2265 * Reset the PCS interface to the serdes (and also ibc, which is still
2266 * in reset from above). Writes new value of ibcctrl_a as last step.
2268 qib_7322_mini_pcs_reset(ppd);
2269 qib_write_kreg(dd, kr_scratch, 0ULL);
2271 if (!ppd->cpspec->ibcctrl_b) {
2272 unsigned lse = ppd->link_speed_enabled;
2275 * Not on re-init after reset, establish shadow
2276 * and force initial config.
2278 ppd->cpspec->ibcctrl_b = qib_read_kreg_port(ppd,
2280 ppd->cpspec->ibcctrl_b &= ~(IBA7322_IBC_SPEED_QDR |
2281 IBA7322_IBC_SPEED_DDR |
2282 IBA7322_IBC_SPEED_SDR |
2283 IBA7322_IBC_WIDTH_AUTONEG |
2284 SYM_MASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED));
2285 if (lse & (lse - 1)) /* Muliple speeds enabled */
2286 ppd->cpspec->ibcctrl_b |=
2287 (lse << IBA7322_IBC_SPEED_LSB) |
2288 IBA7322_IBC_IBTA_1_2_MASK |
2289 IBA7322_IBC_MAX_SPEED_MASK;
2291 ppd->cpspec->ibcctrl_b |= (lse == QIB_IB_QDR) ?
2292 IBA7322_IBC_SPEED_QDR |
2293 IBA7322_IBC_IBTA_1_2_MASK :
2294 (lse == QIB_IB_DDR) ?
2295 IBA7322_IBC_SPEED_DDR :
2296 IBA7322_IBC_SPEED_SDR;
2297 if ((ppd->link_width_enabled & (IB_WIDTH_1X | IB_WIDTH_4X)) ==
2298 (IB_WIDTH_1X | IB_WIDTH_4X))
2299 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_WIDTH_AUTONEG;
2301 ppd->cpspec->ibcctrl_b |=
2302 ppd->link_width_enabled == IB_WIDTH_4X ?
2303 IBA7322_IBC_WIDTH_4X_ONLY :
2304 IBA7322_IBC_WIDTH_1X_ONLY;
2306 /* always enable these on driver reload, not sticky */
2307 ppd->cpspec->ibcctrl_b |= (IBA7322_IBC_RXPOL_MASK |
2308 IBA7322_IBC_HRTBT_MASK);
2310 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
2312 /* setup so we have more time at CFGTEST to change H1 */
2313 val = qib_read_kreg_port(ppd, krp_ibcctrl_c);
2314 val &= ~SYM_MASK(IBCCtrlC_0, IB_FRONT_PORCH);
2315 val |= 0xfULL << SYM_LSB(IBCCtrlC_0, IB_FRONT_PORCH);
2316 qib_write_kreg_port(ppd, krp_ibcctrl_c, val);
2318 serdes_7322_init(ppd);
2320 guid = be64_to_cpu(ppd->guid);
2323 guid = be64_to_cpu(dd->base_guid) + ppd->port - 1;
2324 ppd->guid = cpu_to_be64(guid);
2327 qib_write_kreg_port(ppd, krp_hrtbt_guid, guid);
2328 /* write to chip to prevent back-to-back writes of ibc reg */
2329 qib_write_kreg(dd, kr_scratch, 0);
2332 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0, IBLinkEn);
2335 /* be paranoid against later code motion, etc. */
2336 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
2337 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvIBPortEnable);
2338 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl);
2339 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
2341 /* Also enable IBSTATUSCHG interrupt. */
2342 val = qib_read_kreg_port(ppd, krp_errmask);
2343 qib_write_kreg_port(ppd, krp_errmask,
2344 val | ERR_MASK_N(IBStatusChanged));
2346 /* Always zero until we start messing with SerDes for real */
2351 * qib_7322_quiet_serdes - set serdes to txidle
2352 * @dd: the qlogic_ib device
2353 * Called when driver is being unloaded
2355 static void qib_7322_mini_quiet_serdes(struct qib_pportdata *ppd)
2358 unsigned long flags;
2360 qib_set_ib_7322_lstate(ppd, 0, QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
2362 spin_lock_irqsave(&ppd->lflags_lock, flags);
2363 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
2364 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2365 wake_up(&ppd->cpspec->autoneg_wait);
2366 cancel_delayed_work(&ppd->cpspec->autoneg_work);
2367 if (ppd->dd->cspec->r1)
2368 cancel_delayed_work(&ppd->cpspec->ipg_work);
2369 flush_scheduled_work();
2371 ppd->cpspec->chase_end = 0;
2372 if (ppd->cpspec->chase_timer.data) /* if initted */
2373 del_timer_sync(&ppd->cpspec->chase_timer);
2376 * Despite the name, actually disables IBC as well. Do it when
2377 * we are as sure as possible that no more packets can be
2378 * received, following the down and the PCS reset.
2379 * The actual disabling happens in qib_7322_mini_pci_reset(),
2380 * along with the PCS being reset.
2382 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn);
2383 qib_7322_mini_pcs_reset(ppd);
2386 * Update the adjusted counters so the adjustment persists
2387 * across driver reload.
2389 if (ppd->cpspec->ibsymdelta || ppd->cpspec->iblnkerrdelta ||
2390 ppd->cpspec->ibdeltainprog || ppd->cpspec->iblnkdowndelta) {
2391 struct qib_devdata *dd = ppd->dd;
2394 /* enable counter writes */
2395 diagc = qib_read_kreg64(dd, kr_hwdiagctrl);
2396 qib_write_kreg(dd, kr_hwdiagctrl,
2397 diagc | SYM_MASK(HwDiagCtrl, CounterWrEnable));
2399 if (ppd->cpspec->ibsymdelta || ppd->cpspec->ibdeltainprog) {
2400 val = read_7322_creg32_port(ppd, crp_ibsymbolerr);
2401 if (ppd->cpspec->ibdeltainprog)
2402 val -= val - ppd->cpspec->ibsymsnap;
2403 val -= ppd->cpspec->ibsymdelta;
2404 write_7322_creg_port(ppd, crp_ibsymbolerr, val);
2406 if (ppd->cpspec->iblnkerrdelta || ppd->cpspec->ibdeltainprog) {
2407 val = read_7322_creg32_port(ppd, crp_iblinkerrrecov);
2408 if (ppd->cpspec->ibdeltainprog)
2409 val -= val - ppd->cpspec->iblnkerrsnap;
2410 val -= ppd->cpspec->iblnkerrdelta;
2411 write_7322_creg_port(ppd, crp_iblinkerrrecov, val);
2413 if (ppd->cpspec->iblnkdowndelta) {
2414 val = read_7322_creg32_port(ppd, crp_iblinkdown);
2415 val += ppd->cpspec->iblnkdowndelta;
2416 write_7322_creg_port(ppd, crp_iblinkdown, val);
2419 * No need to save ibmalfdelta since IB perfcounters
2420 * are cleared on driver reload.
2423 /* and disable counter writes */
2424 qib_write_kreg(dd, kr_hwdiagctrl, diagc);
2429 * qib_setup_7322_setextled - set the state of the two external LEDs
2430 * @ppd: physical port on the qlogic_ib device
2431 * @on: whether the link is up or not
2433 * The exact combo of LEDs if on is true is determined by looking
2436 * These LEDs indicate the physical and logical state of IB link.
2437 * For this chip (at least with recommended board pinouts), LED1
2438 * is Yellow (logical state) and LED2 is Green (physical state),
2440 * Note: We try to match the Mellanox HCA LED behavior as best
2441 * we can. Green indicates physical link state is OK (something is
2442 * plugged in, and we can train).
2443 * Amber indicates the link is logically up (ACTIVE).
2444 * Mellanox further blinks the amber LED to indicate data packet
2445 * activity, but we have no hardware support for that, so it would
2446 * require waking up every 10-20 msecs and checking the counters
2447 * on the chip, and then turning the LED off if appropriate. That's
2448 * visible overhead, so not something we will do.
2450 static void qib_setup_7322_setextled(struct qib_pportdata *ppd, u32 on)
2452 struct qib_devdata *dd = ppd->dd;
2453 u64 extctl, ledblink = 0, val;
2454 unsigned long flags;
2458 * The diags use the LED to indicate diag info, so we leave
2459 * the external LED alone when the diags are running.
2461 if (dd->diag_client)
2464 /* Allow override of LED display for, e.g. Locating system in rack */
2465 if (ppd->led_override) {
2466 grn = (ppd->led_override & QIB_LED_PHYS);
2467 yel = (ppd->led_override & QIB_LED_LOG);
2469 val = qib_read_kreg_port(ppd, krp_ibcstatus_a);
2470 grn = qib_7322_phys_portstate(val) ==
2471 IB_PHYSPORTSTATE_LINKUP;
2472 yel = qib_7322_iblink_state(val) == IB_PORT_ACTIVE;
2478 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2479 extctl = dd->cspec->extctrl & (ppd->port == 1 ?
2480 ~ExtLED_IB1_MASK : ~ExtLED_IB2_MASK);
2482 extctl |= ppd->port == 1 ? ExtLED_IB1_GRN : ExtLED_IB2_GRN;
2484 * Counts are in chip clock (4ns) periods.
2485 * This is 1/16 sec (66.6ms) on,
2486 * 3/16 sec (187.5 ms) off, with packets rcvd.
2488 ledblink = ((66600 * 1000UL / 4) << IBA7322_LEDBLINK_ON_SHIFT) |
2489 ((187500 * 1000UL / 4) << IBA7322_LEDBLINK_OFF_SHIFT);
2492 extctl |= ppd->port == 1 ? ExtLED_IB1_YEL : ExtLED_IB2_YEL;
2493 dd->cspec->extctrl = extctl;
2494 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
2495 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2497 if (ledblink) /* blink the LED on packet receive */
2498 qib_write_kreg_port(ppd, krp_rcvpktledcnt, ledblink);
2502 * Disable MSIx interrupt if enabled, call generic MSIx code
2503 * to cleanup, and clear pending MSIx interrupts.
2504 * Used for fallback to INTx, after reset, and when MSIx setup fails.
2506 static void qib_7322_nomsix(struct qib_devdata *dd)
2511 dd->cspec->main_int_mask = ~0ULL;
2512 n = dd->cspec->num_msix_entries;
2516 dd->cspec->num_msix_entries = 0;
2517 for (i = 0; i < n; i++)
2518 free_irq(dd->cspec->msix_entries[i].vector,
2519 dd->cspec->msix_arg[i]);
2522 /* make sure no MSIx interrupts are left pending */
2523 intgranted = qib_read_kreg64(dd, kr_intgranted);
2525 qib_write_kreg(dd, kr_intgranted, intgranted);
2528 static void qib_7322_free_irq(struct qib_devdata *dd)
2530 if (dd->cspec->irq) {
2531 free_irq(dd->cspec->irq, dd);
2534 qib_7322_nomsix(dd);
2537 static void qib_setup_7322_cleanup(struct qib_devdata *dd)
2541 qib_7322_free_irq(dd);
2542 kfree(dd->cspec->cntrs);
2543 kfree(dd->cspec->sendchkenable);
2544 kfree(dd->cspec->sendgrhchk);
2545 kfree(dd->cspec->sendibchk);
2546 kfree(dd->cspec->msix_entries);
2547 kfree(dd->cspec->msix_arg);
2548 for (i = 0; i < dd->num_pports; i++) {
2549 unsigned long flags;
2550 u32 mask = QSFP_GPIO_MOD_PRS_N |
2551 (QSFP_GPIO_MOD_PRS_N << QSFP_GPIO_PORT2_SHIFT);
2553 kfree(dd->pport[i].cpspec->portcntrs);
2554 if (dd->flags & QIB_HAS_QSFP) {
2555 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2556 dd->cspec->gpio_mask &= ~mask;
2557 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
2558 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2559 qib_qsfp_deinit(&dd->pport[i].cpspec->qsfp_data);
2561 if (dd->pport[i].ibport_data.smi_ah)
2562 ib_destroy_ah(&dd->pport[i].ibport_data.smi_ah->ibah);
2566 /* handle SDMA interrupts */
2567 static void sdma_7322_intr(struct qib_devdata *dd, u64 istat)
2569 struct qib_pportdata *ppd0 = &dd->pport[0];
2570 struct qib_pportdata *ppd1 = &dd->pport[1];
2571 u64 intr0 = istat & (INT_MASK_P(SDma, 0) |
2572 INT_MASK_P(SDmaIdle, 0) | INT_MASK_P(SDmaProgress, 0));
2573 u64 intr1 = istat & (INT_MASK_P(SDma, 1) |
2574 INT_MASK_P(SDmaIdle, 1) | INT_MASK_P(SDmaProgress, 1));
2577 qib_sdma_intr(ppd0);
2579 qib_sdma_intr(ppd1);
2581 if (istat & INT_MASK_PM(SDmaCleanupDone, 0))
2582 qib_sdma_process_event(ppd0, qib_sdma_event_e20_hw_started);
2583 if (istat & INT_MASK_PM(SDmaCleanupDone, 1))
2584 qib_sdma_process_event(ppd1, qib_sdma_event_e20_hw_started);
2588 * Set or clear the Send buffer available interrupt enable bit.
2590 static void qib_wantpiobuf_7322_intr(struct qib_devdata *dd, u32 needint)
2592 unsigned long flags;
2594 spin_lock_irqsave(&dd->sendctrl_lock, flags);
2596 dd->sendctrl |= SYM_MASK(SendCtrl, SendIntBufAvail);
2598 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendIntBufAvail);
2599 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
2600 qib_write_kreg(dd, kr_scratch, 0ULL);
2601 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
2605 * Somehow got an interrupt with reserved bits set in interrupt status.
2606 * Print a message so we know it happened, then clear them.
2607 * keep mainline interrupt handler cache-friendly
2609 static noinline void unknown_7322_ibits(struct qib_devdata *dd, u64 istat)
2614 kills = istat & ~QIB_I_BITSEXTANT;
2615 qib_dev_err(dd, "Clearing reserved interrupt(s) 0x%016llx:"
2616 " %s\n", (unsigned long long) kills, msg);
2617 qib_write_kreg(dd, kr_intmask, (dd->cspec->int_enable_mask & ~kills));
2620 /* keep mainline interrupt handler cache-friendly */
2621 static noinline void unknown_7322_gpio_intr(struct qib_devdata *dd)
2628 * Boards for this chip currently don't use GPIO interrupts,
2629 * so clear by writing GPIOstatus to GPIOclear, and complain
2630 * to developer. To avoid endless repeats, clear
2631 * the bits in the mask, since there is some kind of
2632 * programming error or chip problem.
2634 gpiostatus = qib_read_kreg32(dd, kr_gpio_status);
2636 * In theory, writing GPIOstatus to GPIOclear could
2637 * have a bad side-effect on some diagnostic that wanted
2638 * to poll for a status-change, but the various shadows
2639 * make that problematic at best. Diags will just suppress
2640 * all GPIO interrupts during such tests.
2642 qib_write_kreg(dd, kr_gpio_clear, gpiostatus);
2644 * Check for QSFP MOD_PRS changes
2645 * only works for single port if IB1 != pidx1
2647 for (pidx = 0; pidx < dd->num_pports && (dd->flags & QIB_HAS_QSFP);
2649 struct qib_pportdata *ppd;
2650 struct qib_qsfp_data *qd;
2652 if (!dd->pport[pidx].link_speed_supported)
2654 mask = QSFP_GPIO_MOD_PRS_N;
2655 ppd = dd->pport + pidx;
2656 mask <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx);
2657 if (gpiostatus & dd->cspec->gpio_mask & mask) {
2659 qd = &ppd->cpspec->qsfp_data;
2660 gpiostatus &= ~mask;
2661 pins = qib_read_kreg64(dd, kr_extstatus);
2662 pins >>= SYM_LSB(EXTStatus, GPIOIn);
2663 if (!(pins & mask)) {
2665 qd->t_insert = get_jiffies_64();
2666 schedule_work(&qd->work);
2671 if (gpiostatus && !handled) {
2672 const u32 mask = qib_read_kreg32(dd, kr_gpio_mask);
2673 u32 gpio_irq = mask & gpiostatus;
2676 * Clear any troublemakers, and update chip from shadow
2678 dd->cspec->gpio_mask &= ~gpio_irq;
2679 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
2684 * Handle errors and unusual events first, separate function
2685 * to improve cache hits for fast path interrupt handling.
2687 static noinline void unlikely_7322_intr(struct qib_devdata *dd, u64 istat)
2689 if (istat & ~QIB_I_BITSEXTANT)
2690 unknown_7322_ibits(dd, istat);
2691 if (istat & QIB_I_GPIO)
2692 unknown_7322_gpio_intr(dd);
2693 if (istat & QIB_I_C_ERROR)
2694 handle_7322_errors(dd);
2695 if (istat & INT_MASK_P(Err, 0) && dd->rcd[0])
2696 handle_7322_p_errors(dd->rcd[0]->ppd);
2697 if (istat & INT_MASK_P(Err, 1) && dd->rcd[1])
2698 handle_7322_p_errors(dd->rcd[1]->ppd);
2702 * Dynamically adjust the rcv int timeout for a context based on incoming
2705 static void adjust_rcv_timeout(struct qib_ctxtdata *rcd, int npkts)
2707 struct qib_devdata *dd = rcd->dd;
2708 u32 timeout = dd->cspec->rcvavail_timeout[rcd->ctxt];
2711 * Dynamically adjust idle timeout on chip
2712 * based on number of packets processed.
2714 if (npkts < rcv_int_count && timeout > 2)
2716 else if (npkts >= rcv_int_count && timeout < rcv_int_timeout)
2717 timeout = min(timeout << 1, rcv_int_timeout);
2721 dd->cspec->rcvavail_timeout[rcd->ctxt] = timeout;
2722 qib_write_kreg(dd, kr_rcvavailtimeout + rcd->ctxt, timeout);
2726 * This is the main interrupt handler.
2727 * It will normally only be used for low frequency interrupts but may
2728 * have to handle all interrupts if INTx is enabled or fewer than normal
2729 * MSIx interrupts were allocated.
2730 * This routine should ignore the interrupt bits for any of the
2731 * dedicated MSIx handlers.
2733 static irqreturn_t qib_7322intr(int irq, void *data)
2735 struct qib_devdata *dd = data;
2743 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) {
2745 * This return value is not great, but we do not want the
2746 * interrupt core code to remove our interrupt handler
2747 * because we don't appear to be handling an interrupt
2748 * during a chip reset.
2754 istat = qib_read_kreg64(dd, kr_intstatus);
2756 if (unlikely(istat == ~0ULL)) {
2757 qib_bad_intrstatus(dd);
2758 qib_dev_err(dd, "Interrupt status all f's, skipping\n");
2759 /* don't know if it was our interrupt or not */
2764 istat &= dd->cspec->main_int_mask;
2765 if (unlikely(!istat)) {
2766 /* already handled, or shared and not us */
2771 qib_stats.sps_ints++;
2772 if (dd->int_counter != (u32) -1)
2775 /* handle "errors" of various kinds first, device ahead of port */
2776 if (unlikely(istat & (~QIB_I_BITSEXTANT | QIB_I_GPIO |
2777 QIB_I_C_ERROR | INT_MASK_P(Err, 0) |
2778 INT_MASK_P(Err, 1))))
2779 unlikely_7322_intr(dd, istat);
2782 * Clear the interrupt bits we found set, relatively early, so we
2783 * "know" know the chip will have seen this by the time we process
2784 * the queue, and will re-interrupt if necessary. The processor
2785 * itself won't take the interrupt again until we return.
2787 qib_write_kreg(dd, kr_intclear, istat);
2790 * Handle kernel receive queues before checking for pio buffers
2791 * available since receives can overflow; piobuf waiters can afford
2792 * a few extra cycles, since they were waiting anyway.
2794 ctxtrbits = istat & (QIB_I_RCVAVAIL_MASK | QIB_I_RCVURG_MASK);
2796 rmask = (1ULL << QIB_I_RCVAVAIL_LSB) |
2797 (1ULL << QIB_I_RCVURG_LSB);
2798 for (i = 0; i < dd->first_user_ctxt; i++) {
2799 if (ctxtrbits & rmask) {
2800 ctxtrbits &= ~rmask;
2802 qib_kreceive(dd->rcd[i], NULL, &npkts);
2803 adjust_rcv_timeout(dd->rcd[i], npkts);
2809 ctxtrbits = (ctxtrbits >> QIB_I_RCVAVAIL_LSB) |
2810 (ctxtrbits >> QIB_I_RCVURG_LSB);
2811 qib_handle_urcv(dd, ctxtrbits);
2815 if (istat & (QIB_I_P_SDMAINT(0) | QIB_I_P_SDMAINT(1)))
2816 sdma_7322_intr(dd, istat);
2818 if ((istat & QIB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED))
2819 qib_ib_piobufavail(dd);
2827 * Dedicated receive packet available interrupt handler.
2829 static irqreturn_t qib_7322pintr(int irq, void *data)
2831 struct qib_ctxtdata *rcd = data;
2832 struct qib_devdata *dd = rcd->dd;
2835 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2837 * This return value is not great, but we do not want the
2838 * interrupt core code to remove our interrupt handler
2839 * because we don't appear to be handling an interrupt
2840 * during a chip reset.
2844 qib_stats.sps_ints++;
2845 if (dd->int_counter != (u32) -1)
2848 /* Clear the interrupt bit we expect to be set. */
2849 qib_write_kreg(dd, kr_intclear, ((1ULL << QIB_I_RCVAVAIL_LSB) |
2850 (1ULL << QIB_I_RCVURG_LSB)) << rcd->ctxt);
2852 qib_kreceive(rcd, NULL, &npkts);
2853 adjust_rcv_timeout(rcd, npkts);
2859 * Dedicated Send buffer available interrupt handler.
2861 static irqreturn_t qib_7322bufavail(int irq, void *data)
2863 struct qib_devdata *dd = data;
2865 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2867 * This return value is not great, but we do not want the
2868 * interrupt core code to remove our interrupt handler
2869 * because we don't appear to be handling an interrupt
2870 * during a chip reset.
2874 qib_stats.sps_ints++;
2875 if (dd->int_counter != (u32) -1)
2878 /* Clear the interrupt bit we expect to be set. */
2879 qib_write_kreg(dd, kr_intclear, QIB_I_SPIOBUFAVAIL);
2881 /* qib_ib_piobufavail() will clear the want PIO interrupt if needed */
2882 if (dd->flags & QIB_INITTED)
2883 qib_ib_piobufavail(dd);
2885 qib_wantpiobuf_7322_intr(dd, 0);
2891 * Dedicated Send DMA interrupt handler.
2893 static irqreturn_t sdma_intr(int irq, void *data)
2895 struct qib_pportdata *ppd = data;
2896 struct qib_devdata *dd = ppd->dd;
2898 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2900 * This return value is not great, but we do not want the
2901 * interrupt core code to remove our interrupt handler
2902 * because we don't appear to be handling an interrupt
2903 * during a chip reset.
2907 qib_stats.sps_ints++;
2908 if (dd->int_counter != (u32) -1)
2911 /* Clear the interrupt bit we expect to be set. */
2912 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
2913 INT_MASK_P(SDma, 1) : INT_MASK_P(SDma, 0));
2920 * Dedicated Send DMA idle interrupt handler.
2922 static irqreturn_t sdma_idle_intr(int irq, void *data)
2924 struct qib_pportdata *ppd = data;
2925 struct qib_devdata *dd = ppd->dd;
2927 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2929 * This return value is not great, but we do not want the
2930 * interrupt core code to remove our interrupt handler
2931 * because we don't appear to be handling an interrupt
2932 * during a chip reset.
2936 qib_stats.sps_ints++;
2937 if (dd->int_counter != (u32) -1)
2940 /* Clear the interrupt bit we expect to be set. */
2941 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
2942 INT_MASK_P(SDmaIdle, 1) : INT_MASK_P(SDmaIdle, 0));
2949 * Dedicated Send DMA progress interrupt handler.
2951 static irqreturn_t sdma_progress_intr(int irq, void *data)
2953 struct qib_pportdata *ppd = data;
2954 struct qib_devdata *dd = ppd->dd;
2956 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2958 * This return value is not great, but we do not want the
2959 * interrupt core code to remove our interrupt handler
2960 * because we don't appear to be handling an interrupt
2961 * during a chip reset.
2965 qib_stats.sps_ints++;
2966 if (dd->int_counter != (u32) -1)
2969 /* Clear the interrupt bit we expect to be set. */
2970 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
2971 INT_MASK_P(SDmaProgress, 1) :
2972 INT_MASK_P(SDmaProgress, 0));
2979 * Dedicated Send DMA cleanup interrupt handler.
2981 static irqreturn_t sdma_cleanup_intr(int irq, void *data)
2983 struct qib_pportdata *ppd = data;
2984 struct qib_devdata *dd = ppd->dd;
2986 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2988 * This return value is not great, but we do not want the
2989 * interrupt core code to remove our interrupt handler
2990 * because we don't appear to be handling an interrupt
2991 * during a chip reset.
2995 qib_stats.sps_ints++;
2996 if (dd->int_counter != (u32) -1)
2999 /* Clear the interrupt bit we expect to be set. */
3000 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3001 INT_MASK_PM(SDmaCleanupDone, 1) :
3002 INT_MASK_PM(SDmaCleanupDone, 0));
3003 qib_sdma_process_event(ppd, qib_sdma_event_e20_hw_started);
3009 * Set up our chip-specific interrupt handler.
3010 * The interrupt type has already been setup, so
3011 * we just need to do the registration and error checking.
3012 * If we are using MSIx interrupts, we may fall back to
3013 * INTx later, if the interrupt handler doesn't get called
3014 * within 1/2 second (see verify_interrupt()).
3016 static void qib_setup_7322_interrupt(struct qib_devdata *dd, int clearpend)
3018 int ret, i, msixnum;
3022 if (!dd->num_pports)
3027 * if not switching interrupt types, be sure interrupts are
3028 * disabled, and then clear anything pending at this point,
3029 * because we are starting clean.
3031 qib_7322_set_intr_state(dd, 0);
3033 /* clear the reset error, init error/hwerror mask */
3034 qib_7322_init_hwerrors(dd);
3036 /* clear any interrupt bits that might be set */
3037 qib_write_kreg(dd, kr_intclear, ~0ULL);
3039 /* make sure no pending MSIx intr, and clear diag reg */
3040 qib_write_kreg(dd, kr_intgranted, ~0ULL);
3041 qib_write_kreg(dd, kr_vecclr_wo_int, ~0ULL);
3044 if (!dd->cspec->num_msix_entries) {
3045 /* Try to get INTx interrupt */
3047 if (!dd->pcidev->irq) {
3048 qib_dev_err(dd, "irq is 0, BIOS error? "
3049 "Interrupts won't work\n");
3052 ret = request_irq(dd->pcidev->irq, qib_7322intr,
3053 IRQF_SHARED, QIB_DRV_NAME, dd);
3055 qib_dev_err(dd, "Couldn't setup INTx "
3056 "interrupt (irq=%d): %d\n",
3057 dd->pcidev->irq, ret);
3060 dd->cspec->irq = dd->pcidev->irq;
3061 dd->cspec->main_int_mask = ~0ULL;
3065 /* Try to get MSIx interrupts */
3066 memset(redirect, 0, sizeof redirect);
3069 for (i = 0; msixnum < dd->cspec->num_msix_entries; i++) {
3070 irq_handler_t handler;
3076 if (i < ARRAY_SIZE(irq_table)) {
3077 if (irq_table[i].port) {
3078 /* skip if for a non-configured port */
3079 if (irq_table[i].port > dd->num_pports)
3081 arg = dd->pport + irq_table[i].port - 1;
3084 lsb = irq_table[i].lsb;
3085 handler = irq_table[i].handler;
3086 name = irq_table[i].name;
3090 ctxt = i - ARRAY_SIZE(irq_table);
3091 /* per krcvq context receive interrupt */
3092 arg = dd->rcd[ctxt];
3095 lsb = QIB_I_RCVAVAIL_LSB + ctxt;
3096 handler = qib_7322pintr;
3097 name = QIB_DRV_NAME " (kctx)";
3099 ret = request_irq(dd->cspec->msix_entries[msixnum].vector,
3100 handler, 0, name, arg);
3103 * Shouldn't happen since the enable said we could
3104 * have as many as we are trying to setup here.
3106 qib_dev_err(dd, "Couldn't setup MSIx "
3107 "interrupt (vec=%d, irq=%d): %d\n", msixnum,
3108 dd->cspec->msix_entries[msixnum].vector,
3110 qib_7322_nomsix(dd);
3113 dd->cspec->msix_arg[msixnum] = arg;
3115 reg = lsb / IBA7322_REDIRECT_VEC_PER_REG;
3116 sh = (lsb % IBA7322_REDIRECT_VEC_PER_REG) *
3117 SYM_LSB(IntRedirect0, vec1);
3118 mask &= ~(1ULL << lsb);
3119 redirect[reg] |= ((u64) msixnum) << sh;
3121 val = qib_read_kreg64(dd, 2 * msixnum + 1 +
3122 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3125 /* Initialize the vector mapping */
3126 for (i = 0; i < ARRAY_SIZE(redirect); i++)
3127 qib_write_kreg(dd, kr_intredirect + i, redirect[i]);
3128 dd->cspec->main_int_mask = mask;
3133 * qib_7322_boardname - fill in the board name and note features
3134 * @dd: the qlogic_ib device
3136 * info will be based on the board revision register
3138 static unsigned qib_7322_boardname(struct qib_devdata *dd)
3140 /* Will need enumeration of board-types here */
3142 u32 boardid, namelen;
3143 unsigned features = DUAL_PORT_CAP;
3145 boardid = SYM_FIELD(dd->revision, Revision, BoardID);
3149 n = "InfiniPath_QLE7342_Emulation";
3152 n = "InfiniPath_QLE7340";
3153 dd->flags |= QIB_HAS_QSFP;
3154 features = PORT_SPD_CAP;
3157 n = "InfiniPath_QLE7342";
3158 dd->flags |= QIB_HAS_QSFP;
3161 n = "InfiniPath_QMI7342";
3164 n = "InfiniPath_Unsupported7342";
3165 qib_dev_err(dd, "Unsupported version of QMH7342\n");
3169 n = "InfiniPath_QMH7342";
3173 n = "InfiniPath_QME7342";
3176 n = "InfiniPath_QME7362";
3177 dd->flags |= QIB_HAS_QSFP;
3180 n = "InfiniPath_QLE7342_TEST";
3181 dd->flags |= QIB_HAS_QSFP;
3184 n = "InfiniPath_QLE73xy_UNKNOWN";
3185 qib_dev_err(dd, "Unknown 7322 board type %u\n", boardid);
3188 dd->board_atten = 1; /* index into txdds_Xdr */
3190 namelen = strlen(n) + 1;
3191 dd->boardname = kmalloc(namelen, GFP_KERNEL);
3193 qib_dev_err(dd, "Failed allocation for board name: %s\n", n);
3195 snprintf(dd->boardname, namelen, "%s", n);
3197 snprintf(dd->boardversion, sizeof(dd->boardversion),
3198 "ChipABI %u.%u, %s, InfiniPath%u %u.%u, SW Compat %u\n",
3199 QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname,
3200 (unsigned)SYM_FIELD(dd->revision, Revision_R, Arch),
3201 dd->majrev, dd->minrev,
3202 (unsigned)SYM_FIELD(dd->revision, Revision_R, SW));
3204 if (qib_singleport && (features >> PORT_SPD_CAP_SHIFT) & PORT_SPD_CAP) {
3205 qib_devinfo(dd->pcidev, "IB%u: Forced to single port mode"
3206 " by module parameter\n", dd->unit);
3207 features &= PORT_SPD_CAP;
3214 * This routine sleeps, so it can only be called from user context, not
3215 * from interrupt context.
3217 static int qib_do_7322_reset(struct qib_devdata *dd)
3221 int i, msix_entries, ret = 1;
3223 u8 int_line, clinesz;
3224 unsigned long flags;
3226 /* Use dev_err so it shows up in logs, etc. */
3227 qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit);
3229 qib_pcie_getcmd(dd, &cmdval, &int_line, &clinesz);
3231 msix_entries = dd->cspec->num_msix_entries;
3233 /* no interrupts till re-initted */
3234 qib_7322_set_intr_state(dd, 0);
3237 qib_7322_nomsix(dd);
3238 /* can be up to 512 bytes, too big for stack */
3239 msix_vecsave = kmalloc(2 * dd->cspec->num_msix_entries *
3240 sizeof(u64), GFP_KERNEL);
3242 qib_dev_err(dd, "No mem to save MSIx data\n");
3244 msix_vecsave = NULL;
3247 * Core PCI (as of 2.6.18) doesn't save or rewrite the full vector
3248 * info that is set up by the BIOS, so we have to save and restore
3249 * it ourselves. There is some risk something could change it,
3250 * after we save it, but since we have disabled the MSIx, it
3251 * shouldn't be touched...
3253 for (i = 0; i < msix_entries; i++) {
3254 u64 vecaddr, vecdata;
3255 vecaddr = qib_read_kreg64(dd, 2 * i +
3256 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3257 vecdata = qib_read_kreg64(dd, 1 + 2 * i +
3258 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3260 msix_vecsave[2 * i] = vecaddr;
3261 /* save it without the masked bit set */
3262 msix_vecsave[1 + 2 * i] = vecdata & ~0x100000000ULL;
3266 dd->pport->cpspec->ibdeltainprog = 0;
3267 dd->pport->cpspec->ibsymdelta = 0;
3268 dd->pport->cpspec->iblnkerrdelta = 0;
3269 dd->pport->cpspec->ibmalfdelta = 0;
3270 dd->int_counter = 0; /* so we check interrupts work again */
3273 * Keep chip from being accessed until we are ready. Use
3274 * writeq() directly, to allow the write even though QIB_PRESENT
3277 dd->flags &= ~(QIB_INITTED | QIB_PRESENT | QIB_BADINTR);
3278 dd->flags |= QIB_DOING_RESET;
3279 val = dd->control | QLOGIC_IB_C_RESET;
3280 writeq(val, &dd->kregbase[kr_control]);
3282 for (i = 1; i <= 5; i++) {
3284 * Allow MBIST, etc. to complete; longer on each retry.
3285 * We sometimes get machine checks from bus timeout if no
3286 * response, so for now, make it *really* long.
3288 msleep(1000 + (1 + i) * 3000);
3290 qib_pcie_reenable(dd, cmdval, int_line, clinesz);
3293 * Use readq directly, so we don't need to mark it as PRESENT
3294 * until we get a successful indication that all is well.
3296 val = readq(&dd->kregbase[kr_revision]);
3297 if (val == dd->revision)
3300 qib_dev_err(dd, "Failed to initialize after reset, "
3307 dd->flags |= QIB_PRESENT; /* it's back */
3310 /* restore the MSIx vector address and data if saved above */
3311 for (i = 0; i < msix_entries; i++) {
3312 dd->cspec->msix_entries[i].entry = i;
3313 if (!msix_vecsave || !msix_vecsave[2 * i])
3315 qib_write_kreg(dd, 2 * i +
3316 (QIB_7322_MsixTable_OFFS / sizeof(u64)),
3317 msix_vecsave[2 * i]);
3318 qib_write_kreg(dd, 1 + 2 * i +
3319 (QIB_7322_MsixTable_OFFS / sizeof(u64)),
3320 msix_vecsave[1 + 2 * i]);
3324 /* initialize the remaining registers. */
3325 for (i = 0; i < dd->num_pports; ++i)
3326 write_7322_init_portregs(&dd->pport[i]);
3327 write_7322_initregs(dd);
3329 if (qib_pcie_params(dd, dd->lbus_width,
3330 &dd->cspec->num_msix_entries,
3331 dd->cspec->msix_entries))
3332 qib_dev_err(dd, "Reset failed to setup PCIe or interrupts; "
3333 "continuing anyway\n");
3335 qib_setup_7322_interrupt(dd, 1);
3337 for (i = 0; i < dd->num_pports; ++i) {
3338 struct qib_pportdata *ppd = &dd->pport[i];
3340 spin_lock_irqsave(&ppd->lflags_lock, flags);
3341 ppd->lflags |= QIBL_IB_FORCE_NOTIFY;
3342 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
3343 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3347 dd->flags &= ~QIB_DOING_RESET; /* OK or not, no longer resetting */
3348 kfree(msix_vecsave);
3353 * qib_7322_put_tid - write a TID to the chip
3354 * @dd: the qlogic_ib device
3355 * @tidptr: pointer to the expected TID (in chip) to update
3356 * @tidtype: 0 for eager, 1 for expected
3357 * @pa: physical address of in memory buffer; tidinvalid if freeing
3359 static void qib_7322_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr,
3360 u32 type, unsigned long pa)
3362 if (!(dd->flags & QIB_PRESENT))
3364 if (pa != dd->tidinvalid) {
3365 u64 chippa = pa >> IBA7322_TID_PA_SHIFT;
3367 /* paranoia checks */
3368 if (pa != (chippa << IBA7322_TID_PA_SHIFT)) {
3369 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n",
3373 if (chippa >= (1UL << IBA7322_TID_SZ_SHIFT)) {
3374 qib_dev_err(dd, "Physical page address 0x%lx "
3375 "larger than supported\n", pa);
3379 if (type == RCVHQ_RCV_TYPE_EAGER)
3380 chippa |= dd->tidtemplate;
3381 else /* for now, always full 4KB page */
3382 chippa |= IBA7322_TID_SZ_4K;
3390 * qib_7322_clear_tids - clear all TID entries for a ctxt, expected and eager
3391 * @dd: the qlogic_ib device
3394 * clear all TID entries for a ctxt, expected and eager.
3395 * Used from qib_close().
3397 static void qib_7322_clear_tids(struct qib_devdata *dd,
3398 struct qib_ctxtdata *rcd)
3400 u64 __iomem *tidbase;
3401 unsigned long tidinv;
3405 if (!dd->kregbase || !rcd)
3410 tidinv = dd->tidinvalid;
3411 tidbase = (u64 __iomem *)
3412 ((char __iomem *) dd->kregbase +
3414 ctxt * dd->rcvtidcnt * sizeof(*tidbase));
3416 for (i = 0; i < dd->rcvtidcnt; i++)
3417 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
3420 tidbase = (u64 __iomem *)
3421 ((char __iomem *) dd->kregbase +
3423 rcd->rcvegr_tid_base * sizeof(*tidbase));
3425 for (i = 0; i < rcd->rcvegrcnt; i++)
3426 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
3431 * qib_7322_tidtemplate - setup constants for TID updates
3432 * @dd: the qlogic_ib device
3434 * We setup stuff that we use a lot, to avoid calculating each time
3436 static void qib_7322_tidtemplate(struct qib_devdata *dd)
3439 * For now, we always allocate 4KB buffers (at init) so we can
3440 * receive max size packets. We may want a module parameter to
3441 * specify 2KB or 4KB and/or make it per port instead of per device
3442 * for those who want to reduce memory footprint. Note that the
3443 * rcvhdrentsize size must be large enough to hold the largest
3444 * IB header (currently 96 bytes) that we expect to handle (plus of
3445 * course the 2 dwords of RHF).
3447 if (dd->rcvegrbufsize == 2048)
3448 dd->tidtemplate = IBA7322_TID_SZ_2K;
3449 else if (dd->rcvegrbufsize == 4096)
3450 dd->tidtemplate = IBA7322_TID_SZ_4K;
3455 * qib_init_7322_get_base_info - set chip-specific flags for user code
3456 * @rcd: the qlogic_ib ctxt
3457 * @kbase: qib_base_info pointer
3459 * We set the PCIE flag because the lower bandwidth on PCIe vs
3460 * HyperTransport can affect some user packet algorithims.
3463 static int qib_7322_get_base_info(struct qib_ctxtdata *rcd,
3464 struct qib_base_info *kinfo)
3466 kinfo->spi_runtime_flags |= QIB_RUNTIME_CTXT_MSB_IN_QP |
3467 QIB_RUNTIME_PCIE | QIB_RUNTIME_NODMA_RTAIL |
3468 QIB_RUNTIME_HDRSUPP | QIB_RUNTIME_SDMA;
3469 if (rcd->dd->cspec->r1)
3470 kinfo->spi_runtime_flags |= QIB_RUNTIME_RCHK;
3471 if (rcd->dd->flags & QIB_USE_SPCL_TRIG)
3472 kinfo->spi_runtime_flags |= QIB_RUNTIME_SPECIAL_TRIGGER;
3477 static struct qib_message_header *
3478 qib_7322_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr)
3480 u32 offset = qib_hdrget_offset(rhf_addr);
3482 return (struct qib_message_header *)
3483 (rhf_addr - dd->rhf_offset + offset);
3487 * Configure number of contexts.
3489 static void qib_7322_config_ctxts(struct qib_devdata *dd)
3491 unsigned long flags;
3494 nchipctxts = qib_read_kreg32(dd, kr_contextcnt);
3495 dd->cspec->numctxts = nchipctxts;
3496 if (qib_n_krcv_queues > 1 && dd->num_pports) {
3498 * Set the mask for which bits from the QPN are used
3499 * to select a context number.
3501 dd->qpn_mask = 0x3f;
3502 dd->first_user_ctxt = NUM_IB_PORTS +
3503 (qib_n_krcv_queues - 1) * dd->num_pports;
3504 if (dd->first_user_ctxt > nchipctxts)
3505 dd->first_user_ctxt = nchipctxts;
3506 dd->n_krcv_queues = dd->first_user_ctxt / dd->num_pports;
3508 dd->first_user_ctxt = NUM_IB_PORTS;
3509 dd->n_krcv_queues = 1;
3512 if (!qib_cfgctxts) {
3513 int nctxts = dd->first_user_ctxt + num_online_cpus();
3517 else if (nctxts <= 10)
3519 else if (nctxts <= nchipctxts)
3520 dd->ctxtcnt = nchipctxts;
3521 } else if (qib_cfgctxts < dd->num_pports)
3522 dd->ctxtcnt = dd->num_pports;
3523 else if (qib_cfgctxts <= nchipctxts)
3524 dd->ctxtcnt = qib_cfgctxts;
3525 if (!dd->ctxtcnt) /* none of the above, set to max */
3526 dd->ctxtcnt = nchipctxts;
3529 * Chip can be configured for 6, 10, or 18 ctxts, and choice
3530 * affects number of eager TIDs per ctxt (1K, 2K, 4K).
3531 * Lock to be paranoid about later motion, etc.
3533 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
3534 if (dd->ctxtcnt > 10)
3535 dd->rcvctrl |= 2ULL << SYM_LSB(RcvCtrl, ContextCfg);
3536 else if (dd->ctxtcnt > 6)
3537 dd->rcvctrl |= 1ULL << SYM_LSB(RcvCtrl, ContextCfg);
3538 /* else configure for default 6 receive ctxts */
3540 /* The XRC opcode is 5. */
3541 dd->rcvctrl |= 5ULL << SYM_LSB(RcvCtrl, XrcTypeCode);
3544 * RcvCtrl *must* be written here so that the
3545 * chip understands how to change rcvegrcnt below.
3547 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
3548 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
3550 /* kr_rcvegrcnt changes based on the number of contexts enabled */
3551 dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt);
3553 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, qib_rcvhdrcnt);
3555 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt,
3556 dd->num_pports > 1 ? 1024U : 2048U);
3559 static int qib_7322_get_ib_cfg(struct qib_pportdata *ppd, int which)
3563 u64 maskr; /* right-justified mask */
3567 case QIB_IB_CFG_LWID_ENB: /* Get allowed Link-width */
3568 ret = ppd->link_width_enabled;
3571 case QIB_IB_CFG_LWID: /* Get currently active Link-width */
3572 ret = ppd->link_width_active;
3575 case QIB_IB_CFG_SPD_ENB: /* Get allowed Link speeds */
3576 ret = ppd->link_speed_enabled;
3579 case QIB_IB_CFG_SPD: /* Get current Link spd */
3580 ret = ppd->link_speed_active;
3583 case QIB_IB_CFG_RXPOL_ENB: /* Get Auto-RX-polarity enable */
3584 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3585 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3588 case QIB_IB_CFG_LREV_ENB: /* Get Auto-Lane-reversal enable */
3589 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3590 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3593 case QIB_IB_CFG_LINKLATENCY:
3594 ret = qib_read_kreg_port(ppd, krp_ibcstatus_b) &
3595 SYM_MASK(IBCStatusB_0, LinkRoundTripLatency);
3598 case QIB_IB_CFG_OP_VLS:
3599 ret = ppd->vls_operational;
3602 case QIB_IB_CFG_VL_HIGH_CAP:
3606 case QIB_IB_CFG_VL_LOW_CAP:
3610 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
3611 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3615 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
3616 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3620 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
3621 /* will only take effect when the link state changes */
3622 ret = (ppd->cpspec->ibcctrl_a &
3623 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState)) ?
3624 IB_LINKINITCMD_SLEEP : IB_LINKINITCMD_POLL;
3627 case QIB_IB_CFG_HRTBT: /* Get Heartbeat off/enable/auto */
3628 lsb = IBA7322_IBC_HRTBT_LSB;
3629 maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */
3632 case QIB_IB_CFG_PMA_TICKS:
3634 * 0x00 = 10x link transfer rate or 4 nsec. for 2.5Gbs
3635 * Since the clock is always 250MHz, the value is 3, 1 or 0.
3637 if (ppd->link_speed_active == QIB_IB_QDR)
3639 else if (ppd->link_speed_active == QIB_IB_DDR)
3649 ret = (int)((ppd->cpspec->ibcctrl_b >> lsb) & maskr);
3655 * Below again cribbed liberally from older version. Do not lean
3658 #define IBA7322_IBC_DLIDLMC_SHIFT QIB_7322_IBCCtrlB_0_IB_DLID_LSB
3659 #define IBA7322_IBC_DLIDLMC_MASK (QIB_7322_IBCCtrlB_0_IB_DLID_RMASK \
3660 | (QIB_7322_IBCCtrlB_0_IB_DLID_MASK_RMASK << 16))
3662 static int qib_7322_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val)
3664 struct qib_devdata *dd = ppd->dd;
3665 u64 maskr; /* right-justified mask */
3668 unsigned long flags;
3671 case QIB_IB_CFG_LIDLMC:
3673 * Set LID and LMC. Combined to avoid possible hazard
3674 * caller puts LMC in 16MSbits, DLID in 16LSbits of val
3676 lsb = IBA7322_IBC_DLIDLMC_SHIFT;
3677 maskr = IBA7322_IBC_DLIDLMC_MASK;
3679 * For header-checking, the SLID in the packet will
3680 * be masked with SendIBSLMCMask, and compared
3681 * with SendIBSLIDAssignMask. Make sure we do not
3682 * set any bits not covered by the mask, or we get
3685 qib_write_kreg_port(ppd, krp_sendslid,
3686 val & (val >> 16) & SendIBSLIDAssignMask);
3687 qib_write_kreg_port(ppd, krp_sendslidmask,
3688 (val >> 16) & SendIBSLMCMask);
3691 case QIB_IB_CFG_LWID_ENB: /* set allowed Link-width */
3692 ppd->link_width_enabled = val;
3693 /* convert IB value to chip register value */
3694 if (val == IB_WIDTH_1X)
3696 else if (val == IB_WIDTH_4X)
3700 maskr = SYM_RMASK(IBCCtrlB_0, IB_NUM_CHANNELS);
3701 lsb = SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS);
3704 case QIB_IB_CFG_SPD_ENB: /* set allowed Link speeds */
3706 * As with width, only write the actual register if the
3707 * link is currently down, otherwise takes effect on next
3708 * link change. Since setting is being explictly requested
3709 * (via MAD or sysfs), clear autoneg failure status if speed
3710 * autoneg is enabled.
3712 ppd->link_speed_enabled = val;
3713 val <<= IBA7322_IBC_SPEED_LSB;
3714 maskr = IBA7322_IBC_SPEED_MASK | IBA7322_IBC_IBTA_1_2_MASK |
3715 IBA7322_IBC_MAX_SPEED_MASK;
3716 if (val & (val - 1)) {
3717 /* Muliple speeds enabled */
3718 val |= IBA7322_IBC_IBTA_1_2_MASK |
3719 IBA7322_IBC_MAX_SPEED_MASK;
3720 spin_lock_irqsave(&ppd->lflags_lock, flags);
3721 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
3722 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3723 } else if (val & IBA7322_IBC_SPEED_QDR)
3724 val |= IBA7322_IBC_IBTA_1_2_MASK;
3725 /* IBTA 1.2 mode + min/max + speed bits are contiguous */
3726 lsb = SYM_LSB(IBCCtrlB_0, IB_ENHANCED_MODE);
3729 case QIB_IB_CFG_RXPOL_ENB: /* set Auto-RX-polarity enable */
3730 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3731 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3734 case QIB_IB_CFG_LREV_ENB: /* set Auto-Lane-reversal enable */
3735 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3736 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3739 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
3740 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3743 ppd->cpspec->ibcctrl_a &=
3744 ~SYM_MASK(IBCCtrlA_0, OverrunThreshold);
3745 ppd->cpspec->ibcctrl_a |= (u64) val <<
3746 SYM_LSB(IBCCtrlA_0, OverrunThreshold);
3747 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3748 ppd->cpspec->ibcctrl_a);
3749 qib_write_kreg(dd, kr_scratch, 0ULL);
3753 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
3754 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3757 ppd->cpspec->ibcctrl_a &=
3758 ~SYM_MASK(IBCCtrlA_0, PhyerrThreshold);
3759 ppd->cpspec->ibcctrl_a |= (u64) val <<
3760 SYM_LSB(IBCCtrlA_0, PhyerrThreshold);
3761 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3762 ppd->cpspec->ibcctrl_a);
3763 qib_write_kreg(dd, kr_scratch, 0ULL);
3767 case QIB_IB_CFG_PKEYS: /* update pkeys */
3768 maskr = (u64) ppd->pkeys[0] | ((u64) ppd->pkeys[1] << 16) |
3769 ((u64) ppd->pkeys[2] << 32) |
3770 ((u64) ppd->pkeys[3] << 48);
3771 qib_write_kreg_port(ppd, krp_partitionkey, maskr);
3774 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
3775 /* will only take effect when the link state changes */
3776 if (val == IB_LINKINITCMD_POLL)
3777 ppd->cpspec->ibcctrl_a &=
3778 ~SYM_MASK(IBCCtrlA_0, LinkDownDefaultState);
3780 ppd->cpspec->ibcctrl_a |=
3781 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState);
3782 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
3783 qib_write_kreg(dd, kr_scratch, 0ULL);
3786 case QIB_IB_CFG_MTU: /* update the MTU in IBC */
3788 * Update our housekeeping variables, and set IBC max
3789 * size, same as init code; max IBC is max we allow in
3790 * buffer, less the qword pbc, plus 1 for ICRC, in dwords
3791 * Set even if it's unchanged, print debug message only
3794 val = (ppd->ibmaxlen >> 2) + 1;
3795 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, MaxPktLen);
3796 ppd->cpspec->ibcctrl_a |= (u64)val <<
3797 SYM_LSB(IBCCtrlA_0, MaxPktLen);
3798 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3799 ppd->cpspec->ibcctrl_a);
3800 qib_write_kreg(dd, kr_scratch, 0ULL);
3803 case QIB_IB_CFG_LSTATE: /* set the IB link state */
3804 switch (val & 0xffff0000) {
3805 case IB_LINKCMD_DOWN:
3806 lcmd = QLOGIC_IB_IBCC_LINKCMD_DOWN;
3807 ppd->cpspec->ibmalfusesnap = 1;
3808 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd,
3810 if (!ppd->cpspec->ibdeltainprog &&
3811 qib_compat_ddr_negotiate) {
3812 ppd->cpspec->ibdeltainprog = 1;
3813 ppd->cpspec->ibsymsnap =
3814 read_7322_creg32_port(ppd,
3816 ppd->cpspec->iblnkerrsnap =
3817 read_7322_creg32_port(ppd,
3818 crp_iblinkerrrecov);
3822 case IB_LINKCMD_ARMED:
3823 lcmd = QLOGIC_IB_IBCC_LINKCMD_ARMED;
3824 if (ppd->cpspec->ibmalfusesnap) {
3825 ppd->cpspec->ibmalfusesnap = 0;
3826 ppd->cpspec->ibmalfdelta +=
3827 read_7322_creg32_port(ppd,
3829 ppd->cpspec->ibmalfsnap;
3833 case IB_LINKCMD_ACTIVE:
3834 lcmd = QLOGIC_IB_IBCC_LINKCMD_ACTIVE;
3839 qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16);
3842 switch (val & 0xffff) {
3843 case IB_LINKINITCMD_NOP:
3847 case IB_LINKINITCMD_POLL:
3848 licmd = QLOGIC_IB_IBCC_LINKINITCMD_POLL;
3851 case IB_LINKINITCMD_SLEEP:
3852 licmd = QLOGIC_IB_IBCC_LINKINITCMD_SLEEP;
3855 case IB_LINKINITCMD_DISABLE:
3856 licmd = QLOGIC_IB_IBCC_LINKINITCMD_DISABLE;
3857 ppd->cpspec->chase_end = 0;
3859 * stop state chase counter and timer, if running.
3860 * wait forpending timer, but don't clear .data (ppd)!
3862 if (ppd->cpspec->chase_timer.expires) {
3863 del_timer_sync(&ppd->cpspec->chase_timer);
3864 ppd->cpspec->chase_timer.expires = 0;
3870 qib_dev_err(dd, "bad linkinitcmd req 0x%x\n",
3874 qib_set_ib_7322_lstate(ppd, lcmd, licmd);
3877 case QIB_IB_CFG_OP_VLS:
3878 if (ppd->vls_operational != val) {
3879 ppd->vls_operational = val;
3884 case QIB_IB_CFG_VL_HIGH_LIMIT:
3885 qib_write_kreg_port(ppd, krp_highprio_limit, val);
3888 case QIB_IB_CFG_HRTBT: /* set Heartbeat off/enable/auto */
3893 lsb = IBA7322_IBC_HRTBT_LSB;
3894 maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */
3897 case QIB_IB_CFG_PORT:
3898 /* val is the port number of the switch we are connected to. */
3899 if (ppd->dd->cspec->r1) {
3900 cancel_delayed_work(&ppd->cpspec->ipg_work);
3901 ppd->cpspec->ipg_tries = 0;
3909 ppd->cpspec->ibcctrl_b &= ~(maskr << lsb);
3910 ppd->cpspec->ibcctrl_b |= (((u64) val & maskr) << lsb);
3911 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
3912 qib_write_kreg(dd, kr_scratch, 0);
3917 static int qib_7322_set_loopback(struct qib_pportdata *ppd, const char *what)
3922 /* only IBC loopback, may add serdes and xgxs loopbacks later */
3923 if (!strncmp(what, "ibc", 3)) {
3924 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0,
3926 val = 0; /* disable heart beat, so link will come up */
3927 qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n",
3928 ppd->dd->unit, ppd->port);
3929 } else if (!strncmp(what, "off", 3)) {
3930 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0,
3932 /* enable heart beat again */
3933 val = IBA7322_IBC_HRTBT_RMASK << IBA7322_IBC_HRTBT_LSB;
3934 qib_devinfo(ppd->dd->pcidev, "Disabling IB%u:%u IBC loopback "
3935 "(normal)\n", ppd->dd->unit, ppd->port);
3939 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3940 ppd->cpspec->ibcctrl_a);
3941 ctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_HRTBT_MASK
3942 << IBA7322_IBC_HRTBT_LSB);
3943 ppd->cpspec->ibcctrl_b = ctrlb | val;
3944 qib_write_kreg_port(ppd, krp_ibcctrl_b,
3945 ppd->cpspec->ibcctrl_b);
3946 qib_write_kreg(ppd->dd, kr_scratch, 0);
3951 static void get_vl_weights(struct qib_pportdata *ppd, unsigned regno,
3952 struct ib_vl_weight_elem *vl)
3956 for (i = 0; i < 16; i++, regno++, vl++) {
3957 u32 val = qib_read_kreg_port(ppd, regno);
3959 vl->vl = (val >> SYM_LSB(LowPriority0_0, VirtualLane)) &
3960 SYM_RMASK(LowPriority0_0, VirtualLane);
3961 vl->weight = (val >> SYM_LSB(LowPriority0_0, Weight)) &
3962 SYM_RMASK(LowPriority0_0, Weight);
3966 static void set_vl_weights(struct qib_pportdata *ppd, unsigned regno,
3967 struct ib_vl_weight_elem *vl)
3971 for (i = 0; i < 16; i++, regno++, vl++) {
3974 val = ((vl->vl & SYM_RMASK(LowPriority0_0, VirtualLane)) <<
3975 SYM_LSB(LowPriority0_0, VirtualLane)) |
3976 ((vl->weight & SYM_RMASK(LowPriority0_0, Weight)) <<
3977 SYM_LSB(LowPriority0_0, Weight));
3978 qib_write_kreg_port(ppd, regno, val);
3980 if (!(ppd->p_sendctrl & SYM_MASK(SendCtrl_0, IBVLArbiterEn))) {
3981 struct qib_devdata *dd = ppd->dd;
3982 unsigned long flags;
3984 spin_lock_irqsave(&dd->sendctrl_lock, flags);
3985 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, IBVLArbiterEn);
3986 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
3987 qib_write_kreg(dd, kr_scratch, 0);
3988 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
3992 static int qib_7322_get_ib_table(struct qib_pportdata *ppd, int which, void *t)
3995 case QIB_IB_TBL_VL_HIGH_ARB:
3996 get_vl_weights(ppd, krp_highprio_0, t);
3999 case QIB_IB_TBL_VL_LOW_ARB:
4000 get_vl_weights(ppd, krp_lowprio_0, t);
4009 static int qib_7322_set_ib_table(struct qib_pportdata *ppd, int which, void *t)
4012 case QIB_IB_TBL_VL_HIGH_ARB:
4013 set_vl_weights(ppd, krp_highprio_0, t);
4016 case QIB_IB_TBL_VL_LOW_ARB:
4017 set_vl_weights(ppd, krp_lowprio_0, t);
4026 static void qib_update_7322_usrhead(struct qib_ctxtdata *rcd, u64 hd,
4027 u32 updegr, u32 egrhd)
4029 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
4030 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
4032 qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt);
4035 static u32 qib_7322_hdrqempty(struct qib_ctxtdata *rcd)
4039 head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt);
4040 if (rcd->rcvhdrtail_kvaddr)
4041 tail = qib_get_rcvhdrtail(rcd);
4043 tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt);
4044 return head == tail;
4047 #define RCVCTRL_COMMON_MODS (QIB_RCVCTRL_CTXT_ENB | \
4048 QIB_RCVCTRL_CTXT_DIS | \
4049 QIB_RCVCTRL_TIDFLOW_ENB | \
4050 QIB_RCVCTRL_TIDFLOW_DIS | \
4051 QIB_RCVCTRL_TAILUPD_ENB | \
4052 QIB_RCVCTRL_TAILUPD_DIS | \
4053 QIB_RCVCTRL_INTRAVAIL_ENB | \
4054 QIB_RCVCTRL_INTRAVAIL_DIS | \
4055 QIB_RCVCTRL_BP_ENB | \
4058 #define RCVCTRL_PORT_MODS (QIB_RCVCTRL_CTXT_ENB | \
4059 QIB_RCVCTRL_CTXT_DIS | \
4060 QIB_RCVCTRL_PKEY_DIS | \
4061 QIB_RCVCTRL_PKEY_ENB)
4064 * Modify the RCVCTRL register in chip-specific way. This
4065 * is a function because bit positions and (future) register
4066 * location is chip-specifc, but the needed operations are
4067 * generic. <op> is a bit-mask because we often want to
4068 * do multiple modifications.
4070 static void rcvctrl_7322_mod(struct qib_pportdata *ppd, unsigned int op,
4073 struct qib_devdata *dd = ppd->dd;
4074 struct qib_ctxtdata *rcd;
4076 unsigned long flags;
4078 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
4080 if (op & QIB_RCVCTRL_TIDFLOW_ENB)
4081 dd->rcvctrl |= SYM_MASK(RcvCtrl, TidFlowEnable);
4082 if (op & QIB_RCVCTRL_TIDFLOW_DIS)
4083 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TidFlowEnable);
4084 if (op & QIB_RCVCTRL_TAILUPD_ENB)
4085 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd);
4086 if (op & QIB_RCVCTRL_TAILUPD_DIS)
4087 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TailUpd);
4088 if (op & QIB_RCVCTRL_PKEY_ENB)
4089 ppd->p_rcvctrl &= ~SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable);
4090 if (op & QIB_RCVCTRL_PKEY_DIS)
4091 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable);
4093 mask = (1ULL << dd->ctxtcnt) - 1;
4096 mask = (1ULL << ctxt);
4097 rcd = dd->rcd[ctxt];
4099 if ((op & QIB_RCVCTRL_CTXT_ENB) && rcd) {
4101 (mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel));
4102 if (!(dd->flags & QIB_NODMA_RTAIL)) {
4103 op |= QIB_RCVCTRL_TAILUPD_ENB; /* need reg write */
4104 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd);
4106 /* Write these registers before the context is enabled. */
4107 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt,
4108 rcd->rcvhdrqtailaddr_phys);
4109 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt,
4113 if (op & QIB_RCVCTRL_CTXT_DIS)
4115 ~(mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel));
4116 if (op & QIB_RCVCTRL_BP_ENB)
4117 dd->rcvctrl |= mask << SYM_LSB(RcvCtrl, dontDropRHQFull);
4118 if (op & QIB_RCVCTRL_BP_DIS)
4119 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, dontDropRHQFull));
4120 if (op & QIB_RCVCTRL_INTRAVAIL_ENB)
4121 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, IntrAvail));
4122 if (op & QIB_RCVCTRL_INTRAVAIL_DIS)
4123 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, IntrAvail));
4125 * Decide which registers to write depending on the ops enabled.
4126 * Special case is "flush" (no bits set at all)
4127 * which needs to write both.
4129 if (op == 0 || (op & RCVCTRL_COMMON_MODS))
4130 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
4131 if (op == 0 || (op & RCVCTRL_PORT_MODS))
4132 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl);
4133 if ((op & QIB_RCVCTRL_CTXT_ENB) && dd->rcd[ctxt]) {
4135 * Init the context registers also; if we were
4136 * disabled, tail and head should both be zero
4137 * already from the enable, but since we don't
4138 * know, we have to do it explictly.
4140 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt);
4141 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt);
4143 /* be sure enabling write seen; hd/tl should be 0 */
4144 (void) qib_read_kreg32(dd, kr_scratch);
4145 val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt);
4146 dd->rcd[ctxt]->head = val;
4147 /* If kctxt, interrupt on next receive. */
4148 if (ctxt < dd->first_user_ctxt)
4149 val |= dd->rhdrhead_intr_off;
4150 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
4151 } else if ((op & QIB_RCVCTRL_INTRAVAIL_ENB) &&
4152 dd->rcd[ctxt] && dd->rhdrhead_intr_off) {
4153 /* arm rcv interrupt */
4154 val = dd->rcd[ctxt]->head | dd->rhdrhead_intr_off;
4155 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
4157 if (op & QIB_RCVCTRL_CTXT_DIS) {
4160 /* Now that the context is disabled, clear these registers. */
4162 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt, 0);
4163 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt, 0);
4164 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++)
4165 qib_write_ureg(dd, ur_rcvflowtable + f,
4166 TIDFLOW_ERRBITS, ctxt);
4170 for (i = 0; i < dd->cfgctxts; i++) {
4171 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr,
4173 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, i, 0);
4174 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++)
4175 qib_write_ureg(dd, ur_rcvflowtable + f,
4176 TIDFLOW_ERRBITS, i);
4180 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
4184 * Modify the SENDCTRL register in chip-specific way. This
4185 * is a function where there are multiple such registers with
4186 * slightly different layouts.
4187 * The chip doesn't allow back-to-back sendctrl writes, so write
4188 * the scratch register after writing sendctrl.
4190 * Which register is written depends on the operation.
4191 * Most operate on the common register, while
4192 * SEND_ENB and SEND_DIS operate on the per-port ones.
4193 * SEND_ENB is included in common because it can change SPCL_TRIG
4195 #define SENDCTRL_COMMON_MODS (\
4196 QIB_SENDCTRL_CLEAR | \
4197 QIB_SENDCTRL_AVAIL_DIS | \
4198 QIB_SENDCTRL_AVAIL_ENB | \
4199 QIB_SENDCTRL_AVAIL_BLIP | \
4200 QIB_SENDCTRL_DISARM | \
4201 QIB_SENDCTRL_DISARM_ALL | \
4202 QIB_SENDCTRL_SEND_ENB)
4204 #define SENDCTRL_PORT_MODS (\
4205 QIB_SENDCTRL_CLEAR | \
4206 QIB_SENDCTRL_SEND_ENB | \
4207 QIB_SENDCTRL_SEND_DIS | \
4210 static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op)
4212 struct qib_devdata *dd = ppd->dd;
4213 u64 tmp_dd_sendctrl;
4214 unsigned long flags;
4216 spin_lock_irqsave(&dd->sendctrl_lock, flags);
4218 /* First the dd ones that are "sticky", saved in shadow */
4219 if (op & QIB_SENDCTRL_CLEAR)
4221 if (op & QIB_SENDCTRL_AVAIL_DIS)
4222 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4223 else if (op & QIB_SENDCTRL_AVAIL_ENB) {
4224 dd->sendctrl |= SYM_MASK(SendCtrl, SendBufAvailUpd);
4225 if (dd->flags & QIB_USE_SPCL_TRIG)
4226 dd->sendctrl |= SYM_MASK(SendCtrl, SpecialTriggerEn);
4229 /* Then the ppd ones that are "sticky", saved in shadow */
4230 if (op & QIB_SENDCTRL_SEND_DIS)
4231 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable);
4232 else if (op & QIB_SENDCTRL_SEND_ENB)
4233 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable);
4235 if (op & QIB_SENDCTRL_DISARM_ALL) {
4238 tmp_dd_sendctrl = dd->sendctrl;
4239 last = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
4241 * Disarm any buffers that are not yet launched,
4242 * disabling updates until done.
4244 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4245 for (i = 0; i < last; i++) {
4246 qib_write_kreg(dd, kr_sendctrl,
4248 SYM_MASK(SendCtrl, Disarm) | i);
4249 qib_write_kreg(dd, kr_scratch, 0);
4253 if (op & QIB_SENDCTRL_FLUSH) {
4254 u64 tmp_ppd_sendctrl = ppd->p_sendctrl;
4257 * Now drain all the fifos. The Abort bit should never be
4258 * needed, so for now, at least, we don't use it.
4261 SYM_MASK(SendCtrl_0, TxeDrainRmFifo) |
4262 SYM_MASK(SendCtrl_0, TxeDrainLaFifo) |
4263 SYM_MASK(SendCtrl_0, TxeBypassIbc);
4264 qib_write_kreg_port(ppd, krp_sendctrl, tmp_ppd_sendctrl);
4265 qib_write_kreg(dd, kr_scratch, 0);
4268 tmp_dd_sendctrl = dd->sendctrl;
4270 if (op & QIB_SENDCTRL_DISARM)
4271 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Disarm) |
4272 ((op & QIB_7322_SendCtrl_DisarmSendBuf_RMASK) <<
4273 SYM_LSB(SendCtrl, DisarmSendBuf));
4274 if ((op & QIB_SENDCTRL_AVAIL_BLIP) &&
4275 (dd->sendctrl & SYM_MASK(SendCtrl, SendBufAvailUpd)))
4276 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4278 if (op == 0 || (op & SENDCTRL_COMMON_MODS)) {
4279 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl);
4280 qib_write_kreg(dd, kr_scratch, 0);
4283 if (op == 0 || (op & SENDCTRL_PORT_MODS)) {
4284 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
4285 qib_write_kreg(dd, kr_scratch, 0);
4288 if (op & QIB_SENDCTRL_AVAIL_BLIP) {
4289 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
4290 qib_write_kreg(dd, kr_scratch, 0);
4293 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4295 if (op & QIB_SENDCTRL_FLUSH) {
4298 * ensure writes have hit chip, then do a few
4299 * more reads, to allow DMA of pioavail registers
4300 * to occur, so in-memory copy is in sync with
4301 * the chip. Not always safe to sleep.
4303 v = qib_read_kreg32(dd, kr_scratch);
4304 qib_write_kreg(dd, kr_scratch, v);
4305 v = qib_read_kreg32(dd, kr_scratch);
4306 qib_write_kreg(dd, kr_scratch, v);
4307 qib_read_kreg32(dd, kr_scratch);
4311 #define _PORT_VIRT_FLAG 0x8000U /* "virtual", need adjustments */
4312 #define _PORT_64BIT_FLAG 0x10000U /* not "virtual", but 64bit */
4313 #define _PORT_CNTR_IDXMASK 0x7fffU /* mask off flags above */
4316 * qib_portcntr_7322 - read a per-port chip counter
4317 * @ppd: the qlogic_ib pport
4318 * @creg: the counter to read (not a chip offset)
4320 static u64 qib_portcntr_7322(struct qib_pportdata *ppd, u32 reg)
4322 struct qib_devdata *dd = ppd->dd;
4325 /* 0xffff for unimplemented or synthesized counters */
4326 static const u32 xlator[] = {
4327 [QIBPORTCNTR_PKTSEND] = crp_pktsend | _PORT_64BIT_FLAG,
4328 [QIBPORTCNTR_WORDSEND] = crp_wordsend | _PORT_64BIT_FLAG,
4329 [QIBPORTCNTR_PSXMITDATA] = crp_psxmitdatacount,
4330 [QIBPORTCNTR_PSXMITPKTS] = crp_psxmitpktscount,
4331 [QIBPORTCNTR_PSXMITWAIT] = crp_psxmitwaitcount,
4332 [QIBPORTCNTR_SENDSTALL] = crp_sendstall,
4333 [QIBPORTCNTR_PKTRCV] = crp_pktrcv | _PORT_64BIT_FLAG,
4334 [QIBPORTCNTR_PSRCVDATA] = crp_psrcvdatacount,
4335 [QIBPORTCNTR_PSRCVPKTS] = crp_psrcvpktscount,
4336 [QIBPORTCNTR_RCVEBP] = crp_rcvebp,
4337 [QIBPORTCNTR_RCVOVFL] = crp_rcvovfl,
4338 [QIBPORTCNTR_WORDRCV] = crp_wordrcv | _PORT_64BIT_FLAG,
4339 [QIBPORTCNTR_RXDROPPKT] = 0xffff, /* not needed for 7322 */
4340 [QIBPORTCNTR_RXLOCALPHYERR] = crp_rxotherlocalphyerr,
4341 [QIBPORTCNTR_RXVLERR] = crp_rxvlerr,
4342 [QIBPORTCNTR_ERRICRC] = crp_erricrc,
4343 [QIBPORTCNTR_ERRVCRC] = crp_errvcrc,
4344 [QIBPORTCNTR_ERRLPCRC] = crp_errlpcrc,
4345 [QIBPORTCNTR_BADFORMAT] = crp_badformat,
4346 [QIBPORTCNTR_ERR_RLEN] = crp_err_rlen,
4347 [QIBPORTCNTR_IBSYMBOLERR] = crp_ibsymbolerr,
4348 [QIBPORTCNTR_INVALIDRLEN] = crp_invalidrlen,
4349 [QIBPORTCNTR_UNSUPVL] = crp_txunsupvl,
4350 [QIBPORTCNTR_EXCESSBUFOVFL] = crp_excessbufferovfl,
4351 [QIBPORTCNTR_ERRLINK] = crp_errlink,
4352 [QIBPORTCNTR_IBLINKDOWN] = crp_iblinkdown,
4353 [QIBPORTCNTR_IBLINKERRRECOV] = crp_iblinkerrrecov,
4354 [QIBPORTCNTR_LLI] = crp_locallinkintegrityerr,
4355 [QIBPORTCNTR_VL15PKTDROP] = crp_vl15droppedpkt,
4356 [QIBPORTCNTR_ERRPKEY] = crp_errpkey,
4358 * the next 3 aren't really counters, but were implemented
4359 * as counters in older chips, so still get accessed as
4360 * though they were counters from this code.
4362 [QIBPORTCNTR_PSINTERVAL] = krp_psinterval,
4363 [QIBPORTCNTR_PSSTART] = krp_psstart,
4364 [QIBPORTCNTR_PSSTAT] = krp_psstat,
4365 /* pseudo-counter, summed for all ports */
4366 [QIBPORTCNTR_KHDROVFL] = 0xffff,
4369 if (reg >= ARRAY_SIZE(xlator)) {
4370 qib_devinfo(ppd->dd->pcidev,
4371 "Unimplemented portcounter %u\n", reg);
4374 creg = xlator[reg] & _PORT_CNTR_IDXMASK;
4376 /* handle non-counters and special cases first */
4377 if (reg == QIBPORTCNTR_KHDROVFL) {
4380 /* sum over all kernel contexts (skip if mini_init) */
4381 for (i = 0; dd->rcd && i < dd->first_user_ctxt; i++) {
4382 struct qib_ctxtdata *rcd = dd->rcd[i];
4384 if (!rcd || rcd->ppd != ppd)
4386 ret += read_7322_creg32(dd, cr_base_egrovfl + i);
4389 } else if (reg == QIBPORTCNTR_RXDROPPKT) {
4391 * Used as part of the synthesis of port_rcv_errors
4392 * in the verbs code for IBTA counters. Not needed for 7322,
4393 * because all the errors are already counted by other cntrs.
4396 } else if (reg == QIBPORTCNTR_PSINTERVAL ||
4397 reg == QIBPORTCNTR_PSSTART || reg == QIBPORTCNTR_PSSTAT) {
4398 /* were counters in older chips, now per-port kernel regs */
4399 ret = qib_read_kreg_port(ppd, creg);
4404 * Only fast increment counters are 64 bits; use 32 bit reads to
4405 * avoid two independent reads when on Opteron.
4407 if (xlator[reg] & _PORT_64BIT_FLAG)
4408 ret = read_7322_creg_port(ppd, creg);
4410 ret = read_7322_creg32_port(ppd, creg);
4411 if (creg == crp_ibsymbolerr) {
4412 if (ppd->cpspec->ibdeltainprog)
4413 ret -= ret - ppd->cpspec->ibsymsnap;
4414 ret -= ppd->cpspec->ibsymdelta;
4415 } else if (creg == crp_iblinkerrrecov) {
4416 if (ppd->cpspec->ibdeltainprog)
4417 ret -= ret - ppd->cpspec->iblnkerrsnap;
4418 ret -= ppd->cpspec->iblnkerrdelta;
4419 } else if (creg == crp_errlink)
4420 ret -= ppd->cpspec->ibmalfdelta;
4421 else if (creg == crp_iblinkdown)
4422 ret += ppd->cpspec->iblnkdowndelta;
4428 * Device counter names (not port-specific), one line per stat,
4429 * single string. Used by utilities like ipathstats to print the stats
4430 * in a way which works for different versions of drivers, without changing
4431 * the utility. Names need to be 12 chars or less (w/o newline), for proper
4432 * display by utility.
4433 * Non-error counters are first.
4434 * Start of "error" conters is indicated by a leading "E " on the first
4435 * "error" counter, and doesn't count in label length.
4436 * The EgrOvfl list needs to be last so we truncate them at the configured
4437 * context count for the device.
4438 * cntr7322indices contains the corresponding register indices.
4440 static const char cntr7322names[] =
4445 "RxTIDFloDrop\n" /* 7322 only */
4466 static const u32 cntr7322indices[] = {
4467 cr_lbint | _PORT_64BIT_FLAG,
4468 cr_lbstall | _PORT_64BIT_FLAG,
4472 cr_base_egrovfl + 0,
4473 cr_base_egrovfl + 1,
4474 cr_base_egrovfl + 2,
4475 cr_base_egrovfl + 3,
4476 cr_base_egrovfl + 4,
4477 cr_base_egrovfl + 5,
4478 cr_base_egrovfl + 6,
4479 cr_base_egrovfl + 7,
4480 cr_base_egrovfl + 8,
4481 cr_base_egrovfl + 9,
4482 cr_base_egrovfl + 10,
4483 cr_base_egrovfl + 11,
4484 cr_base_egrovfl + 12,
4485 cr_base_egrovfl + 13,
4486 cr_base_egrovfl + 14,
4487 cr_base_egrovfl + 15,
4488 cr_base_egrovfl + 16,
4489 cr_base_egrovfl + 17,
4493 * same as cntr7322names and cntr7322indices, but for port-specific counters.
4494 * portcntr7322indices is somewhat complicated by some registers needing
4495 * adjustments of various kinds, and those are ORed with _PORT_VIRT_FLAG
4497 static const char portcntr7322names[] =
4505 "TxDmaDesc\n" /* 7220 and 7322-only */
4506 "E RxDlidFltr\n" /* 7220 and 7322-only */
4529 "RxLclPhyErr\n" /* 7220 and 7322-only from here down */
4533 "RxQPBadCtxt\n" /* 7322-only from here down */
4537 static const u32 portcntr7322indices[] = {
4538 QIBPORTCNTR_PKTSEND | _PORT_VIRT_FLAG,
4540 QIBPORTCNTR_WORDSEND | _PORT_VIRT_FLAG,
4541 QIBPORTCNTR_PKTRCV | _PORT_VIRT_FLAG,
4543 QIBPORTCNTR_WORDRCV | _PORT_VIRT_FLAG,
4544 QIBPORTCNTR_SENDSTALL | _PORT_VIRT_FLAG,
4545 crp_txsdmadesc | _PORT_64BIT_FLAG,
4548 QIBPORTCNTR_IBLINKDOWN | _PORT_VIRT_FLAG,
4549 QIBPORTCNTR_IBLINKERRRECOV | _PORT_VIRT_FLAG,
4550 QIBPORTCNTR_ERRLINK | _PORT_VIRT_FLAG,
4551 QIBPORTCNTR_IBSYMBOLERR | _PORT_VIRT_FLAG,
4552 QIBPORTCNTR_LLI | _PORT_VIRT_FLAG,
4553 QIBPORTCNTR_BADFORMAT | _PORT_VIRT_FLAG,
4554 QIBPORTCNTR_ERR_RLEN | _PORT_VIRT_FLAG,
4555 QIBPORTCNTR_RCVOVFL | _PORT_VIRT_FLAG,
4556 QIBPORTCNTR_RCVEBP | _PORT_VIRT_FLAG,
4557 crp_rcvflowctrlviol,
4558 QIBPORTCNTR_ERRICRC | _PORT_VIRT_FLAG,
4559 QIBPORTCNTR_ERRLPCRC | _PORT_VIRT_FLAG,
4560 QIBPORTCNTR_ERRVCRC | _PORT_VIRT_FLAG,
4561 QIBPORTCNTR_INVALIDRLEN | _PORT_VIRT_FLAG,
4562 QIBPORTCNTR_ERRPKEY | _PORT_VIRT_FLAG,
4563 QIBPORTCNTR_RXDROPPKT | _PORT_VIRT_FLAG,
4569 QIBPORTCNTR_RXLOCALPHYERR | _PORT_VIRT_FLAG,
4570 QIBPORTCNTR_VL15PKTDROP | _PORT_VIRT_FLAG,
4571 QIBPORTCNTR_RXVLERR | _PORT_VIRT_FLAG,
4572 QIBPORTCNTR_EXCESSBUFOVFL | _PORT_VIRT_FLAG,
4573 crp_rxqpinvalidctxt,
4577 /* do all the setup to make the counter reads efficient later */
4578 static void init_7322_cntrnames(struct qib_devdata *dd)
4583 for (i = 0, s = (char *)cntr7322names; s && j <= dd->cfgctxts;
4585 /* we always have at least one counter before the egrovfl */
4586 if (!j && !strncmp("Ctxt0EgrOvfl", s + 1, 12))
4588 s = strchr(s + 1, '\n');
4592 dd->cspec->ncntrs = i;
4594 /* full list; size is without terminating null */
4595 dd->cspec->cntrnamelen = sizeof(cntr7322names) - 1;
4597 dd->cspec->cntrnamelen = 1 + s - cntr7322names;
4598 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs
4599 * sizeof(u64), GFP_KERNEL);
4600 if (!dd->cspec->cntrs)
4601 qib_dev_err(dd, "Failed allocation for counters\n");
4603 for (i = 0, s = (char *)portcntr7322names; s; i++)
4604 s = strchr(s + 1, '\n');
4605 dd->cspec->nportcntrs = i - 1;
4606 dd->cspec->portcntrnamelen = sizeof(portcntr7322names) - 1;
4607 for (i = 0; i < dd->num_pports; ++i) {
4608 dd->pport[i].cpspec->portcntrs = kmalloc(dd->cspec->nportcntrs
4609 * sizeof(u64), GFP_KERNEL);
4610 if (!dd->pport[i].cpspec->portcntrs)
4611 qib_dev_err(dd, "Failed allocation for"
4616 static u32 qib_read_7322cntrs(struct qib_devdata *dd, loff_t pos, char **namep,
4622 ret = dd->cspec->cntrnamelen;
4624 ret = 0; /* final read after getting everything */
4626 *namep = (char *) cntr7322names;
4628 u64 *cntr = dd->cspec->cntrs;
4631 ret = dd->cspec->ncntrs * sizeof(u64);
4632 if (!cntr || pos >= ret) {
4633 /* everything read, or couldn't get memory */
4638 for (i = 0; i < dd->cspec->ncntrs; i++)
4639 if (cntr7322indices[i] & _PORT_64BIT_FLAG)
4640 *cntr++ = read_7322_creg(dd,
4641 cntr7322indices[i] &
4642 _PORT_CNTR_IDXMASK);
4644 *cntr++ = read_7322_creg32(dd,
4645 cntr7322indices[i]);
4651 static u32 qib_read_7322portcntrs(struct qib_devdata *dd, loff_t pos, u32 port,
4652 char **namep, u64 **cntrp)
4657 ret = dd->cspec->portcntrnamelen;
4659 ret = 0; /* final read after getting everything */
4661 *namep = (char *)portcntr7322names;
4663 struct qib_pportdata *ppd = &dd->pport[port];
4664 u64 *cntr = ppd->cpspec->portcntrs;
4667 ret = dd->cspec->nportcntrs * sizeof(u64);
4668 if (!cntr || pos >= ret) {
4669 /* everything read, or couldn't get memory */
4674 for (i = 0; i < dd->cspec->nportcntrs; i++) {
4675 if (portcntr7322indices[i] & _PORT_VIRT_FLAG)
4676 *cntr++ = qib_portcntr_7322(ppd,
4677 portcntr7322indices[i] &
4678 _PORT_CNTR_IDXMASK);
4679 else if (portcntr7322indices[i] & _PORT_64BIT_FLAG)
4680 *cntr++ = read_7322_creg_port(ppd,
4681 portcntr7322indices[i] &
4682 _PORT_CNTR_IDXMASK);
4684 *cntr++ = read_7322_creg32_port(ppd,
4685 portcntr7322indices[i]);
4693 * qib_get_7322_faststats - get word counters from chip before they overflow
4694 * @opaque - contains a pointer to the qlogic_ib device qib_devdata
4696 * VESTIGIAL IBA7322 has no "small fast counters", so the only
4697 * real purpose of this function is to maintain the notion of
4698 * "active time", which in turn is only logged into the eeprom,
4699 * which we don;t have, yet, for 7322-based boards.
4701 * called from add_timer
4703 static void qib_get_7322_faststats(unsigned long opaque)
4705 struct qib_devdata *dd = (struct qib_devdata *) opaque;
4706 struct qib_pportdata *ppd;
4707 unsigned long flags;
4711 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
4712 ppd = dd->pport + pidx;
4715 * If port isn't enabled or not operational ports, or
4716 * diags is running (can cause memory diags to fail)
4717 * skip this port this time.
4719 if (!ppd->link_speed_supported || !(dd->flags & QIB_INITTED)
4724 * Maintain an activity timer, based on traffic
4725 * exceeding a threshold, so we need to check the word-counts
4726 * even if they are 64-bit.
4728 traffic_wds = qib_portcntr_7322(ppd, QIBPORTCNTR_WORDRCV) +
4729 qib_portcntr_7322(ppd, QIBPORTCNTR_WORDSEND);
4730 spin_lock_irqsave(&ppd->dd->eep_st_lock, flags);
4731 traffic_wds -= ppd->dd->traffic_wds;
4732 ppd->dd->traffic_wds += traffic_wds;
4733 if (traffic_wds >= QIB_TRAFFIC_ACTIVE_THRESHOLD)
4734 atomic_add(ACTIVITY_TIMER, &ppd->dd->active_time);
4735 spin_unlock_irqrestore(&ppd->dd->eep_st_lock, flags);
4736 if (ppd->cpspec->qdr_dfe_on && (ppd->link_speed_active &
4738 (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED |
4739 QIBL_LINKACTIVE)) &&
4740 ppd->cpspec->qdr_dfe_time &&
4741 time_after64(get_jiffies_64(), ppd->cpspec->qdr_dfe_time)) {
4742 ppd->cpspec->qdr_dfe_on = 0;
4744 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
4745 ppd->dd->cspec->r1 ?
4746 QDR_STATIC_ADAPT_INIT_R1 :
4747 QDR_STATIC_ADAPT_INIT);
4751 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER);
4755 * If we were using MSIx, try to fallback to INTx.
4757 static int qib_7322_intr_fallback(struct qib_devdata *dd)
4759 if (!dd->cspec->num_msix_entries)
4760 return 0; /* already using INTx */
4762 qib_devinfo(dd->pcidev, "MSIx interrupt not detected,"
4763 " trying INTx interrupts\n");
4764 qib_7322_nomsix(dd);
4765 qib_enable_intx(dd->pcidev);
4766 qib_setup_7322_interrupt(dd, 0);
4771 * Reset the XGXS (between serdes and IBC). Slightly less intrusive
4772 * than resetting the IBC or external link state, and useful in some
4773 * cases to cause some retraining. To do this right, we reset IBC
4774 * as well, then return to previous state (which may be still in reset)
4775 * NOTE: some callers of this "know" this writes the current value
4776 * of cpspec->ibcctrl_a as part of it's operation, so if that changes,
4777 * check all callers.
4779 static void qib_7322_mini_pcs_reset(struct qib_pportdata *ppd)
4782 struct qib_devdata *dd = ppd->dd;
4783 const u64 reset_bits = SYM_MASK(IBPCSConfig_0, xcv_rreset) |
4784 SYM_MASK(IBPCSConfig_0, xcv_treset) |
4785 SYM_MASK(IBPCSConfig_0, tx_rx_reset);
4787 val = qib_read_kreg_port(ppd, krp_ib_pcsconfig);
4788 qib_write_kreg(dd, kr_hwerrmask,
4789 dd->cspec->hwerrmask & ~HWE_MASK(statusValidNoEop));
4790 qib_write_kreg_port(ppd, krp_ibcctrl_a,
4791 ppd->cpspec->ibcctrl_a &
4792 ~SYM_MASK(IBCCtrlA_0, IBLinkEn));
4794 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val | reset_bits);
4795 qib_read_kreg32(dd, kr_scratch);
4796 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val & ~reset_bits);
4797 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
4798 qib_write_kreg(dd, kr_scratch, 0ULL);
4799 qib_write_kreg(dd, kr_hwerrclear,
4800 SYM_MASK(HwErrClear, statusValidNoEopClear));
4801 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
4805 * This code for non-IBTA-compliant IB speed negotiation is only known to
4806 * work for the SDR to DDR transition, and only between an HCA and a switch
4807 * with recent firmware. It is based on observed heuristics, rather than
4808 * actual knowledge of the non-compliant speed negotiation.
4809 * It has a number of hard-coded fields, since the hope is to rewrite this
4810 * when a spec is available on how the negoation is intended to work.
4812 static void autoneg_7322_sendpkt(struct qib_pportdata *ppd, u32 *hdr,
4813 u32 dcnt, u32 *data)
4817 u32 __iomem *piobuf;
4818 u32 pnum, control, len;
4819 struct qib_devdata *dd = ppd->dd;
4822 len = 7 + dcnt + 1; /* 7 dword header, dword data, icrc */
4823 control = qib_7322_setpbc_control(ppd, len, 0, 15);
4824 pbc = ((u64) control << 32) | len;
4825 while (!(piobuf = qib_7322_getsendbuf(ppd, pbc, &pnum))) {
4830 /* disable header check on this packet, since it can't be valid */
4831 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_DIS1, NULL);
4832 writeq(pbc, piobuf);
4834 qib_pio_copy(piobuf + 2, hdr, 7);
4835 qib_pio_copy(piobuf + 9, data, dcnt);
4836 if (dd->flags & QIB_USE_SPCL_TRIG) {
4837 u32 spcl_off = (pnum >= dd->piobcnt2k) ? 2047 : 1023;
4840 __raw_writel(0xaebecede, piobuf + spcl_off);
4843 qib_sendbuf_done(dd, pnum);
4844 /* and re-enable hdr check */
4845 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_ENAB1, NULL);
4849 * _start packet gets sent twice at start, _done gets sent twice at end
4851 static void qib_autoneg_7322_send(struct qib_pportdata *ppd, int which)
4853 struct qib_devdata *dd = ppd->dd;
4855 u32 dw, i, hcnt, dcnt, *data;
4856 static u32 hdr[7] = { 0xf002ffff, 0x48ffff, 0x6400abba };
4857 static u32 madpayload_start[0x40] = {
4858 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
4859 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
4860 0x1, 0x1388, 0x15e, 0x1, /* rest 0's */
4862 static u32 madpayload_done[0x40] = {
4863 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
4864 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
4865 0x40000001, 0x1388, 0x15e, /* rest 0's */
4868 dcnt = ARRAY_SIZE(madpayload_start);
4869 hcnt = ARRAY_SIZE(hdr);
4871 /* for maintainability, do it at runtime */
4872 for (i = 0; i < hcnt; i++) {
4873 dw = (__force u32) cpu_to_be32(hdr[i]);
4876 for (i = 0; i < dcnt; i++) {
4877 dw = (__force u32) cpu_to_be32(madpayload_start[i]);
4878 madpayload_start[i] = dw;
4879 dw = (__force u32) cpu_to_be32(madpayload_done[i]);
4880 madpayload_done[i] = dw;
4885 data = which ? madpayload_done : madpayload_start;
4887 autoneg_7322_sendpkt(ppd, hdr, dcnt, data);
4888 qib_read_kreg64(dd, kr_scratch);
4890 autoneg_7322_sendpkt(ppd, hdr, dcnt, data);
4891 qib_read_kreg64(dd, kr_scratch);
4896 * Do the absolute minimum to cause an IB speed change, and make it
4897 * ready, but don't actually trigger the change. The caller will
4898 * do that when ready (if link is in Polling training state, it will
4899 * happen immediately, otherwise when link next goes down)
4901 * This routine should only be used as part of the DDR autonegotation
4902 * code for devices that are not compliant with IB 1.2 (or code that
4903 * fixes things up for same).
4905 * When link has gone down, and autoneg enabled, or autoneg has
4906 * failed and we give up until next time we set both speeds, and
4907 * then we want IBTA enabled as well as "use max enabled speed.
4909 static void set_7322_ibspeed_fast(struct qib_pportdata *ppd, u32 speed)
4912 newctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_SPEED_MASK |
4913 IBA7322_IBC_IBTA_1_2_MASK |
4914 IBA7322_IBC_MAX_SPEED_MASK);
4916 if (speed & (speed - 1)) /* multiple speeds */
4917 newctrlb |= (speed << IBA7322_IBC_SPEED_LSB) |
4918 IBA7322_IBC_IBTA_1_2_MASK |
4919 IBA7322_IBC_MAX_SPEED_MASK;
4921 newctrlb |= speed == QIB_IB_QDR ?
4922 IBA7322_IBC_SPEED_QDR | IBA7322_IBC_IBTA_1_2_MASK :
4923 ((speed == QIB_IB_DDR ?
4924 IBA7322_IBC_SPEED_DDR : IBA7322_IBC_SPEED_SDR));
4926 if (newctrlb == ppd->cpspec->ibcctrl_b)
4929 ppd->cpspec->ibcctrl_b = newctrlb;
4930 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
4931 qib_write_kreg(ppd->dd, kr_scratch, 0);
4935 * This routine is only used when we are not talking to another
4936 * IB 1.2-compliant device that we think can do DDR.
4937 * (This includes all existing switch chips as of Oct 2007.)
4938 * 1.2-compliant devices go directly to DDR prior to reaching INIT
4940 static void try_7322_autoneg(struct qib_pportdata *ppd)
4942 unsigned long flags;
4944 spin_lock_irqsave(&ppd->lflags_lock, flags);
4945 ppd->lflags |= QIBL_IB_AUTONEG_INPROG;
4946 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
4947 qib_autoneg_7322_send(ppd, 0);
4948 set_7322_ibspeed_fast(ppd, QIB_IB_DDR);
4949 qib_7322_mini_pcs_reset(ppd);
4950 /* 2 msec is minimum length of a poll cycle */
4951 schedule_delayed_work(&ppd->cpspec->autoneg_work,
4952 msecs_to_jiffies(2));
4956 * Handle the empirically determined mechanism for auto-negotiation
4957 * of DDR speed with switches.
4959 static void autoneg_7322_work(struct work_struct *work)
4961 struct qib_pportdata *ppd;
4962 struct qib_devdata *dd;
4965 unsigned long flags;
4967 ppd = container_of(work, struct qib_chippport_specific,
4968 autoneg_work.work)->ppd;
4971 startms = jiffies_to_msecs(jiffies);
4974 * Busy wait for this first part, it should be at most a
4975 * few hundred usec, since we scheduled ourselves for 2msec.
4977 for (i = 0; i < 25; i++) {
4978 if (SYM_FIELD(ppd->lastibcstat, IBCStatusA_0, LinkState)
4979 == IB_7322_LT_STATE_POLLQUIET) {
4980 qib_set_linkstate(ppd, QIB_IB_LINKDOWN_DISABLE);
4986 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
4987 goto done; /* we got there early or told to stop */
4989 /* we expect this to timeout */
4990 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
4991 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
4992 msecs_to_jiffies(90)))
4994 qib_7322_mini_pcs_reset(ppd);
4996 /* we expect this to timeout */
4997 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
4998 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
4999 msecs_to_jiffies(1700)))
5001 qib_7322_mini_pcs_reset(ppd);
5003 set_7322_ibspeed_fast(ppd, QIB_IB_SDR);
5006 * Wait up to 250 msec for link to train and get to INIT at DDR;
5007 * this should terminate early.
5009 wait_event_timeout(ppd->cpspec->autoneg_wait,
5010 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5011 msecs_to_jiffies(250));
5013 if (ppd->lflags & QIBL_IB_AUTONEG_INPROG) {
5014 spin_lock_irqsave(&ppd->lflags_lock, flags);
5015 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
5016 if (ppd->cpspec->autoneg_tries == AUTONEG_TRIES) {
5017 ppd->lflags |= QIBL_IB_AUTONEG_FAILED;
5018 ppd->cpspec->autoneg_tries = 0;
5020 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5021 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5026 * This routine is used to request IPG set in the QLogic switch.
5027 * Only called if r1.
5029 static void try_7322_ipg(struct qib_pportdata *ppd)
5031 struct qib_ibport *ibp = &ppd->ibport_data;
5032 struct ib_mad_send_buf *send_buf;
5033 struct ib_mad_agent *agent;
5038 agent = ibp->send_agent;
5042 send_buf = ib_create_send_mad(agent, 0, 0, 0, IB_MGMT_MAD_HDR,
5043 IB_MGMT_MAD_DATA, GFP_ATOMIC);
5044 if (IS_ERR(send_buf))
5048 struct ib_ah_attr attr;
5051 memset(&attr, 0, sizeof attr);
5052 attr.dlid = be16_to_cpu(IB_LID_PERMISSIVE);
5053 attr.port_num = ppd->port;
5054 ah = ib_create_ah(ibp->qp0->ibqp.pd, &attr);
5059 ibp->smi_ah = to_iah(ah);
5063 send_buf->ah = &ibp->smi_ah->ibah;
5067 smp = send_buf->mad;
5068 smp->base_version = IB_MGMT_BASE_VERSION;
5069 smp->mgmt_class = IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE;
5070 smp->class_version = 1;
5071 smp->method = IB_MGMT_METHOD_SEND;
5073 smp->attr_id = QIB_VENDOR_IPG;
5077 ret = ib_post_send_mad(send_buf, NULL);
5079 ib_free_send_mad(send_buf);
5081 delay = 2 << ppd->cpspec->ipg_tries;
5082 schedule_delayed_work(&ppd->cpspec->ipg_work, msecs_to_jiffies(delay));
5086 * Timeout handler for setting IPG.
5087 * Only called if r1.
5089 static void ipg_7322_work(struct work_struct *work)
5091 struct qib_pportdata *ppd;
5093 ppd = container_of(work, struct qib_chippport_specific,
5094 ipg_work.work)->ppd;
5095 if ((ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED | QIBL_LINKACTIVE))
5096 && ++ppd->cpspec->ipg_tries <= 10)
5100 static u32 qib_7322_iblink_state(u64 ibcs)
5102 u32 state = (u32)SYM_FIELD(ibcs, IBCStatusA_0, LinkState);
5105 case IB_7322_L_STATE_INIT:
5106 state = IB_PORT_INIT;
5108 case IB_7322_L_STATE_ARM:
5109 state = IB_PORT_ARMED;
5111 case IB_7322_L_STATE_ACTIVE:
5113 case IB_7322_L_STATE_ACT_DEFER:
5114 state = IB_PORT_ACTIVE;
5116 default: /* fall through */
5117 case IB_7322_L_STATE_DOWN:
5118 state = IB_PORT_DOWN;
5124 /* returns the IBTA port state, rather than the IBC link training state */
5125 static u8 qib_7322_phys_portstate(u64 ibcs)
5127 u8 state = (u8)SYM_FIELD(ibcs, IBCStatusA_0, LinkTrainingState);
5128 return qib_7322_physportstate[state];
5131 static int qib_7322_ib_updown(struct qib_pportdata *ppd, int ibup, u64 ibcs)
5133 int ret = 0, symadj = 0;
5134 unsigned long flags;
5137 spin_lock_irqsave(&ppd->lflags_lock, flags);
5138 ppd->lflags &= ~QIBL_IB_FORCE_NOTIFY;
5139 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5141 /* Update our picture of width and speed from chip */
5142 if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) {
5143 ppd->link_speed_active = QIB_IB_QDR;
5145 } else if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedActive)) {
5146 ppd->link_speed_active = QIB_IB_DDR;
5149 ppd->link_speed_active = QIB_IB_SDR;
5152 if (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) {
5153 ppd->link_width_active = IB_WIDTH_4X;
5156 ppd->link_width_active = IB_WIDTH_1X;
5157 ppd->delay_mult = ib_rate_to_delay[mult_to_ib_rate(mult)];
5162 /* Link went down. */
5163 /* do IPG MAD again after linkdown, even if last time failed */
5164 ppd->cpspec->ipg_tries = 0;
5165 clr = qib_read_kreg_port(ppd, krp_ibcstatus_b) &
5166 (SYM_MASK(IBCStatusB_0, heartbeat_timed_out) |
5167 SYM_MASK(IBCStatusB_0, heartbeat_crosstalk));
5169 qib_write_kreg_port(ppd, krp_ibcstatus_b, clr);
5170 if (!(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
5171 QIBL_IB_AUTONEG_INPROG)))
5172 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5173 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5174 /* unlock the Tx settings, speed may change */
5175 qib_write_kreg_port(ppd, krp_tx_deemph_override,
5176 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
5177 reset_tx_deemphasis_override));
5178 qib_cancel_sends(ppd);
5179 /* on link down, ensure sane pcs state */
5180 qib_7322_mini_pcs_reset(ppd);
5181 spin_lock_irqsave(&ppd->sdma_lock, flags);
5182 if (__qib_sdma_running(ppd))
5183 __qib_sdma_process_event(ppd,
5184 qib_sdma_event_e70_go_idle);
5185 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
5187 clr = read_7322_creg32_port(ppd, crp_iblinkdown);
5188 if (clr == ppd->cpspec->iblnkdownsnap)
5189 ppd->cpspec->iblnkdowndelta++;
5191 if (qib_compat_ddr_negotiate &&
5192 !(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
5193 QIBL_IB_AUTONEG_INPROG)) &&
5194 ppd->link_speed_active == QIB_IB_SDR &&
5195 (ppd->link_speed_enabled & QIB_IB_DDR)
5196 && ppd->cpspec->autoneg_tries < AUTONEG_TRIES) {
5197 /* we are SDR, and auto-negotiation enabled */
5198 ++ppd->cpspec->autoneg_tries;
5199 if (!ppd->cpspec->ibdeltainprog) {
5200 ppd->cpspec->ibdeltainprog = 1;
5201 ppd->cpspec->ibsymdelta +=
5202 read_7322_creg32_port(ppd,
5204 ppd->cpspec->ibsymsnap;
5205 ppd->cpspec->iblnkerrdelta +=
5206 read_7322_creg32_port(ppd,
5207 crp_iblinkerrrecov) -
5208 ppd->cpspec->iblnkerrsnap;
5210 try_7322_autoneg(ppd);
5211 ret = 1; /* no other IB status change processing */
5212 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
5213 ppd->link_speed_active == QIB_IB_SDR) {
5214 qib_autoneg_7322_send(ppd, 1);
5215 set_7322_ibspeed_fast(ppd, QIB_IB_DDR);
5216 qib_7322_mini_pcs_reset(ppd);
5218 ret = 1; /* no other IB status change processing */
5219 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
5220 (ppd->link_speed_active & QIB_IB_DDR)) {
5221 spin_lock_irqsave(&ppd->lflags_lock, flags);
5222 ppd->lflags &= ~(QIBL_IB_AUTONEG_INPROG |
5223 QIBL_IB_AUTONEG_FAILED);
5224 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5225 ppd->cpspec->autoneg_tries = 0;
5226 /* re-enable SDR, for next link down */
5227 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5228 wake_up(&ppd->cpspec->autoneg_wait);
5230 } else if (ppd->lflags & QIBL_IB_AUTONEG_FAILED) {
5232 * Clear autoneg failure flag, and do setup
5233 * so we'll try next time link goes down and
5234 * back to INIT (possibly connected to a
5235 * different device).
5237 spin_lock_irqsave(&ppd->lflags_lock, flags);
5238 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
5239 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5240 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_IBTA_1_2_MASK;
5243 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5245 if (ppd->dd->cspec->r1 && ppd->cpspec->ipg_tries <= 10)
5247 if (!ppd->cpspec->recovery_init)
5248 setup_7322_link_recovery(ppd, 0);
5249 ppd->cpspec->qdr_dfe_time = jiffies +
5250 msecs_to_jiffies(QDR_DFE_DISABLE_DELAY);
5252 ppd->cpspec->ibmalfusesnap = 0;
5253 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd,
5257 ppd->cpspec->iblnkdownsnap =
5258 read_7322_creg32_port(ppd, crp_iblinkdown);
5259 if (ppd->cpspec->ibdeltainprog) {
5260 ppd->cpspec->ibdeltainprog = 0;
5261 ppd->cpspec->ibsymdelta += read_7322_creg32_port(ppd,
5262 crp_ibsymbolerr) - ppd->cpspec->ibsymsnap;
5263 ppd->cpspec->iblnkerrdelta += read_7322_creg32_port(ppd,
5264 crp_iblinkerrrecov) - ppd->cpspec->iblnkerrsnap;
5266 } else if (!ibup && qib_compat_ddr_negotiate &&
5267 !ppd->cpspec->ibdeltainprog &&
5268 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5269 ppd->cpspec->ibdeltainprog = 1;
5270 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd,
5272 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd,
5273 crp_iblinkerrrecov);
5277 qib_setup_7322_setextled(ppd, ibup);
5282 * Does read/modify/write to appropriate registers to
5283 * set output and direction bits selected by mask.
5284 * these are in their canonical postions (e.g. lsb of
5285 * dir will end up in D48 of extctrl on existing chips).
5286 * returns contents of GP Inputs.
5288 static int gpio_7322_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask)
5290 u64 read_val, new_out;
5291 unsigned long flags;
5294 /* some bits being written, lock access to GPIO */
5297 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
5298 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe));
5299 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe));
5300 new_out = (dd->cspec->gpio_out & ~mask) | out;
5302 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
5303 qib_write_kreg(dd, kr_gpio_out, new_out);
5304 dd->cspec->gpio_out = new_out;
5305 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
5308 * It is unlikely that a read at this time would get valid
5309 * data on a pin whose direction line was set in the same
5310 * call to this function. We include the read here because
5311 * that allows us to potentially combine a change on one pin with
5312 * a read on another, and because the old code did something like
5315 read_val = qib_read_kreg64(dd, kr_extstatus);
5316 return SYM_FIELD(read_val, EXTStatus, GPIOIn);
5319 /* Enable writes to config EEPROM, if possible. Returns previous state */
5320 static int qib_7322_eeprom_wen(struct qib_devdata *dd, int wen)
5325 mask = 1 << QIB_EEPROM_WEN_NUM;
5326 prev_wen = ~gpio_7322_mod(dd, 0, 0, 0) >> QIB_EEPROM_WEN_NUM;
5327 gpio_7322_mod(dd, wen ? 0 : mask, mask, mask);
5329 return prev_wen & 1;
5333 * Read fundamental info we need to use the chip. These are
5334 * the registers that describe chip capabilities, and are
5335 * saved in shadow registers.
5337 static void get_7322_chip_params(struct qib_devdata *dd)
5343 dd->palign = qib_read_kreg32(dd, kr_pagealign);
5345 dd->uregbase = qib_read_kreg32(dd, kr_userregbase);
5347 dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt);
5348 dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase);
5349 dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase);
5350 dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase);
5351 dd->pio2k_bufbase = dd->piobufbase & 0xffffffff;
5353 val = qib_read_kreg64(dd, kr_sendpiobufcnt);
5354 dd->piobcnt2k = val & ~0U;
5355 dd->piobcnt4k = val >> 32;
5356 val = qib_read_kreg64(dd, kr_sendpiosize);
5357 dd->piosize2k = val & ~0U;
5358 dd->piosize4k = val >> 32;
5360 mtu = ib_mtu_enum_to_int(qib_ibmtu);
5362 mtu = QIB_DEFAULT_MTU;
5363 dd->pport[0].ibmtu = (u32)mtu;
5364 dd->pport[1].ibmtu = (u32)mtu;
5366 /* these may be adjusted in init_chip_wc_pat() */
5367 dd->pio2kbase = (u32 __iomem *)
5368 ((char __iomem *) dd->kregbase + dd->pio2k_bufbase);
5369 dd->pio4kbase = (u32 __iomem *)
5370 ((char __iomem *) dd->kregbase +
5371 (dd->piobufbase >> 32));
5373 * 4K buffers take 2 pages; we use roundup just to be
5374 * paranoid; we calculate it once here, rather than on
5377 dd->align4k = ALIGN(dd->piosize4k, dd->palign);
5379 piobufs = dd->piobcnt4k + dd->piobcnt2k + NUM_VL15_BUFS;
5381 dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) /
5382 (sizeof(u64) * BITS_PER_BYTE / 2);
5386 * The chip base addresses in cspec and cpspec have to be set
5387 * after possible init_chip_wc_pat(), rather than in
5388 * get_7322_chip_params(), so split out as separate function
5390 static void qib_7322_set_baseaddrs(struct qib_devdata *dd)
5393 cregbase = qib_read_kreg32(dd, kr_counterregbase);
5395 dd->cspec->cregbase = (u64 __iomem *)(cregbase +
5396 (char __iomem *)dd->kregbase);
5398 dd->egrtidbase = (u64 __iomem *)
5399 ((char __iomem *) dd->kregbase + dd->rcvegrbase);
5401 /* port registers are defined as relative to base of chip */
5402 dd->pport[0].cpspec->kpregbase =
5403 (u64 __iomem *)((char __iomem *)dd->kregbase);
5404 dd->pport[1].cpspec->kpregbase =
5405 (u64 __iomem *)(dd->palign +
5406 (char __iomem *)dd->kregbase);
5407 dd->pport[0].cpspec->cpregbase =
5408 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[0],
5409 kr_counterregbase) + (char __iomem *)dd->kregbase);
5410 dd->pport[1].cpspec->cpregbase =
5411 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[1],
5412 kr_counterregbase) + (char __iomem *)dd->kregbase);
5416 * This is a fairly special-purpose observer, so we only support
5417 * the port-specific parts of SendCtrl
5420 #define SENDCTRL_SHADOWED (SYM_MASK(SendCtrl_0, SendEnable) | \
5421 SYM_MASK(SendCtrl_0, SDmaEnable) | \
5422 SYM_MASK(SendCtrl_0, SDmaIntEnable) | \
5423 SYM_MASK(SendCtrl_0, SDmaSingleDescriptor) | \
5424 SYM_MASK(SendCtrl_0, SDmaHalt) | \
5425 SYM_MASK(SendCtrl_0, IBVLArbiterEn) | \
5426 SYM_MASK(SendCtrl_0, ForceCreditUpToDate))
5428 static int sendctrl_hook(struct qib_devdata *dd,
5429 const struct diag_observer *op, u32 offs,
5430 u64 *data, u64 mask, int only_32)
5432 unsigned long flags;
5435 struct qib_pportdata *ppd = NULL;
5436 u64 local_data, all_bits;
5439 * The fixed correspondence between Physical ports and pports is
5440 * severed. We need to hunt for the ppd that corresponds
5441 * to the offset we got. And we have to do that without admitting
5442 * we know the stride, apparently.
5444 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
5448 ppd = dd->pport + pidx;
5449 if (!ppd->cpspec->kpregbase)
5452 psptr = ppd->cpspec->kpregbase + krp_sendctrl;
5453 psoffs = (u32) (psptr - dd->kregbase) * sizeof(*psptr);
5458 /* If pport is not being managed by driver, just avoid shadows. */
5459 if (pidx >= dd->num_pports)
5462 /* In any case, "idx" is flat index in kreg space */
5463 idx = offs / sizeof(u64);
5469 spin_lock_irqsave(&dd->sendctrl_lock, flags);
5470 if (!ppd || (mask & all_bits) != all_bits) {
5472 * At least some mask bits are zero, so we need
5473 * to read. The judgement call is whether from
5474 * reg or shadow. First-cut: read reg, and complain
5475 * if any bits which should be shadowed are different
5476 * from their shadowed value.
5479 local_data = (u64)qib_read_kreg32(dd, idx);
5481 local_data = qib_read_kreg64(dd, idx);
5482 *data = (local_data & ~mask) | (*data & mask);
5486 * At least some mask bits are one, so we need
5487 * to write, but only shadow some bits.
5489 u64 sval, tval; /* Shadowed, transient */
5492 * New shadow val is bits we don't want to touch,
5493 * ORed with bits we do, that are intended for shadow.
5496 sval = ppd->p_sendctrl & ~mask;
5497 sval |= *data & SENDCTRL_SHADOWED & mask;
5498 ppd->p_sendctrl = sval;
5500 sval = *data & SENDCTRL_SHADOWED & mask;
5501 tval = sval | (*data & ~SENDCTRL_SHADOWED & mask);
5502 qib_write_kreg(dd, idx, tval);
5503 qib_write_kreg(dd, kr_scratch, 0Ull);
5505 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
5506 return only_32 ? 4 : 8;
5509 static const struct diag_observer sendctrl_0_observer = {
5510 sendctrl_hook, KREG_IDX(SendCtrl_0) * sizeof(u64),
5511 KREG_IDX(SendCtrl_0) * sizeof(u64)
5514 static const struct diag_observer sendctrl_1_observer = {
5515 sendctrl_hook, KREG_IDX(SendCtrl_1) * sizeof(u64),
5516 KREG_IDX(SendCtrl_1) * sizeof(u64)
5519 static ushort sdma_fetch_prio = 8;
5520 module_param_named(sdma_fetch_prio, sdma_fetch_prio, ushort, S_IRUGO);
5521 MODULE_PARM_DESC(sdma_fetch_prio, "SDMA descriptor fetch priority");
5523 /* Besides logging QSFP events, we set appropriate TxDDS values */
5524 static void init_txdds_table(struct qib_pportdata *ppd, int override);
5526 static void qsfp_7322_event(struct work_struct *work)
5528 struct qib_qsfp_data *qd;
5529 struct qib_pportdata *ppd;
5534 qd = container_of(work, struct qib_qsfp_data, work);
5536 pwrup = qd->t_insert + msecs_to_jiffies(QSFP_PWR_LAG_MSEC);
5539 * Some QSFP's not only do not respond until the full power-up
5540 * time, but may behave badly if we try. So hold off responding
5544 u64 now = get_jiffies_64();
5545 if (time_after64(now, pwrup))
5549 ret = qib_refresh_qsfp_cache(ppd, &qd->cache);
5551 * Need to change LE2 back to defaults if we couldn't
5552 * read the cable type (to handle cable swaps), so do this
5553 * even on failure to read cable information. We don't
5554 * get here for QME, so IS_QME check not needed here.
5556 le2 = (!ret && qd->cache.atten[1] >= qib_long_atten &&
5557 !ppd->dd->cspec->r1 && QSFP_IS_CU(qd->cache.tech)) ?
5558 LE2_5m : LE2_DEFAULT;
5559 ibsd_wr_allchans(ppd, 13, (le2 << 7), BMASK(9, 7));
5560 init_txdds_table(ppd, 0);
5564 * There is little we can do but complain to the user if QSFP
5565 * initialization fails.
5567 static void qib_init_7322_qsfp(struct qib_pportdata *ppd)
5569 unsigned long flags;
5570 struct qib_qsfp_data *qd = &ppd->cpspec->qsfp_data;
5571 struct qib_devdata *dd = ppd->dd;
5572 u64 mod_prs_bit = QSFP_GPIO_MOD_PRS_N;
5574 mod_prs_bit <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx);
5576 qib_qsfp_init(qd, qsfp_7322_event);
5577 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
5578 dd->cspec->extctrl |= (mod_prs_bit << SYM_LSB(EXTCtrl, GPIOInvert));
5579 dd->cspec->gpio_mask |= mod_prs_bit;
5580 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
5581 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
5582 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
5586 * called at device initialization time, and also if the txselect
5587 * module parameter is changed. This is used for cables that don't
5588 * have valid QSFP EEPROMs (not present, or attenuation is zero).
5589 * We initialize to the default, then if there is a specific
5590 * unit,port match, we use that (and set it immediately, for the
5591 * current speed, if the link is at INIT or better).
5592 * String format is "default# unit#,port#=# ... u,p=#", separators must
5593 * be a SPACE character. A newline terminates. The u,p=# tuples may
5594 * optionally have "u,p=#,#", where the final # is the H1 value
5595 * The last specific match is used (actually, all are used, but last
5596 * one is the one that winds up set); if none at all, fall back on default.
5598 static void set_no_qsfp_atten(struct qib_devdata *dd, int change)
5601 u32 pidx, unit, port, deflt, h1;
5605 str = txselect_list;
5607 /* default number is validated in setup_txselect() */
5608 deflt = simple_strtoul(str, &nxt, 0);
5609 for (pidx = 0; pidx < dd->num_pports; ++pidx)
5610 dd->pport[pidx].cpspec->no_eep = deflt;
5612 while (*nxt && nxt[1]) {
5614 unit = simple_strtoul(str, &nxt, 0);
5615 if (nxt == str || !*nxt || *nxt != ',') {
5616 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
5621 port = simple_strtoul(str, &nxt, 0);
5622 if (nxt == str || *nxt != '=') {
5623 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
5628 val = simple_strtoul(str, &nxt, 0);
5630 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
5634 if (val >= TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ)
5637 h1 = 0; /* gcc thinks it might be used uninitted */
5638 if (*nxt == ',' && nxt[1]) {
5640 h1 = (u32)simple_strtoul(str, &nxt, 0);
5642 while (*nxt && *nxt++ != ' ') /* skip */
5647 for (pidx = 0; dd->unit == unit && pidx < dd->num_pports;
5649 struct qib_pportdata *ppd = &dd->pport[pidx];
5651 if (ppd->port != port || !ppd->link_speed_supported)
5653 ppd->cpspec->no_eep = val;
5655 ppd->cpspec->h1_val = h1;
5656 /* now change the IBC and serdes, overriding generic */
5657 init_txdds_table(ppd, 1);
5663 if (change && !any) {
5664 /* no specific setting, use the default.
5665 * Change the IBC and serdes, but since it's
5666 * general, don't override specific settings.
5668 for (pidx = 0; pidx < dd->num_pports; ++pidx)
5669 if (dd->pport[pidx].link_speed_supported)
5670 init_txdds_table(&dd->pport[pidx], 0);
5674 /* handle the txselect parameter changing */
5675 static int setup_txselect(const char *str, struct kernel_param *kp)
5677 struct qib_devdata *dd;
5680 if (strlen(str) >= MAX_ATTEN_LEN) {
5681 printk(KERN_INFO QIB_DRV_NAME " txselect_values string "
5685 val = simple_strtoul(str, &n, 0);
5686 if (n == str || val >= (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ)) {
5687 printk(KERN_INFO QIB_DRV_NAME
5688 "txselect_values must start with a number < %d\n",
5689 TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ);
5692 strcpy(txselect_list, str);
5694 list_for_each_entry(dd, &qib_dev_list, list)
5695 if (dd->deviceid == PCI_DEVICE_ID_QLOGIC_IB_7322)
5696 set_no_qsfp_atten(dd, 1);
5701 * Write the final few registers that depend on some of the
5702 * init setup. Done late in init, just before bringing up
5705 static int qib_late_7322_initreg(struct qib_devdata *dd)
5710 qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize);
5711 qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize);
5712 qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt);
5713 qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys);
5714 val = qib_read_kreg64(dd, kr_sendpioavailaddr);
5715 if (val != dd->pioavailregs_phys) {
5716 qib_dev_err(dd, "Catastrophic software error, "
5717 "SendPIOAvailAddr written as %lx, "
5718 "read back as %llx\n",
5719 (unsigned long) dd->pioavailregs_phys,
5720 (unsigned long long) val);
5724 n = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
5725 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_KERN, NULL);
5726 /* driver sends get pkey, lid, etc. checking also, to catch bugs */
5727 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_ENAB1, NULL);
5729 qib_register_observer(dd, &sendctrl_0_observer);
5730 qib_register_observer(dd, &sendctrl_1_observer);
5732 dd->control &= ~QLOGIC_IB_C_SDMAFETCHPRIOEN;
5733 qib_write_kreg(dd, kr_control, dd->control);
5735 * Set SendDmaFetchPriority and init Tx params, including
5736 * QSFP handler on boards that have QSFP.
5737 * First set our default attenuation entry for cables that
5738 * don't have valid attenuation.
5740 set_no_qsfp_atten(dd, 0);
5741 for (n = 0; n < dd->num_pports; ++n) {
5742 struct qib_pportdata *ppd = dd->pport + n;
5744 qib_write_kreg_port(ppd, krp_senddmaprioritythld,
5745 sdma_fetch_prio & 0xf);
5746 /* Initialize qsfp if present on board. */
5747 if (dd->flags & QIB_HAS_QSFP)
5748 qib_init_7322_qsfp(ppd);
5750 dd->control |= QLOGIC_IB_C_SDMAFETCHPRIOEN;
5751 qib_write_kreg(dd, kr_control, dd->control);
5756 /* per IB port errors. */
5757 #define SENDCTRL_PIBP (MASK_ACROSS(0, 1) | MASK_ACROSS(3, 3) | \
5759 #define RCVCTRL_PIBP (MASK_ACROSS(0, 17) | MASK_ACROSS(39, 41))
5760 #define ERRS_PIBP (MASK_ACROSS(57, 58) | MASK_ACROSS(54, 54) | \
5761 MASK_ACROSS(36, 49) | MASK_ACROSS(29, 34) | MASK_ACROSS(14, 17) | \
5765 * Write the initialization per-port registers that need to be done at
5766 * driver load and after reset completes (i.e., that aren't done as part
5767 * of other init procedures called from qib_init.c).
5768 * Some of these should be redundant on reset, but play safe.
5770 static void write_7322_init_portregs(struct qib_pportdata *ppd)
5775 if (!ppd->link_speed_supported) {
5776 /* no buffer credits for this port */
5777 for (i = 1; i < 8; i++)
5778 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0);
5779 qib_write_kreg_port(ppd, krp_ibcctrl_b, 0);
5780 qib_write_kreg(ppd->dd, kr_scratch, 0);
5785 * Set the number of supported virtual lanes in IBC,
5786 * for flow control packet handling on unsupported VLs
5788 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx);
5789 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, VL_CAP);
5790 val |= (u64)(ppd->vls_supported - 1) <<
5791 SYM_LSB(IB_SDTEST_IF_TX_0, VL_CAP);
5792 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
5794 qib_write_kreg_port(ppd, krp_rcvbthqp, QIB_KD_QP);
5796 /* enable tx header checking */
5797 qib_write_kreg_port(ppd, krp_sendcheckcontrol, IBA7322_SENDCHK_PKEY |
5798 IBA7322_SENDCHK_BTHQP | IBA7322_SENDCHK_SLID |
5799 IBA7322_SENDCHK_RAW_IPV6 | IBA7322_SENDCHK_MINSZ);
5801 qib_write_kreg_port(ppd, krp_ncmodectrl,
5802 SYM_MASK(IBNCModeCtrl_0, ScrambleCapLocal));
5805 * Unconditionally clear the bufmask bits. If SDMA is
5806 * enabled, we'll set them appropriately later.
5808 qib_write_kreg_port(ppd, krp_senddmabufmask0, 0);
5809 qib_write_kreg_port(ppd, krp_senddmabufmask1, 0);
5810 qib_write_kreg_port(ppd, krp_senddmabufmask2, 0);
5811 if (ppd->dd->cspec->r1)
5812 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, ForceCreditUpToDate);
5816 * Write the initialization per-device registers that need to be done at
5817 * driver load and after reset completes (i.e., that aren't done as part
5818 * of other init procedures called from qib_init.c). Also write per-port
5819 * registers that are affected by overall device config, such as QP mapping
5820 * Some of these should be redundant on reset, but play safe.
5822 static void write_7322_initregs(struct qib_devdata *dd)
5824 struct qib_pportdata *ppd;
5828 /* Set Multicast QPs received by port 2 to map to context one. */
5829 qib_write_kreg(dd, KREG_IDX(RcvQPMulticastContext_1), 1);
5831 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
5833 unsigned long flags;
5835 if (!dd->qpn_mask || !dd->pport[pidx].link_speed_supported)
5838 ppd = &dd->pport[pidx];
5840 /* be paranoid against later code motion, etc. */
5841 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
5842 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvQPMapEnable);
5843 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
5845 /* Initialize QP to context mapping */
5846 regno = krp_rcvqpmaptable;
5848 if (dd->num_pports > 1)
5849 n = dd->first_user_ctxt / dd->num_pports;
5851 n = dd->first_user_ctxt - 1;
5852 for (i = 0; i < 32; ) {
5855 if (dd->num_pports > 1)
5856 ctxt = (i % n) * dd->num_pports + pidx;
5860 ctxt = ppd->hw_pidx;
5861 val |= ctxt << (5 * (i % 6));
5864 qib_write_kreg_port(ppd, regno, val);
5869 qib_write_kreg_port(ppd, regno, val);
5873 * Setup up interrupt mitigation for kernel contexts, but
5874 * not user contexts (user contexts use interrupts when
5875 * stalled waiting for any packet, so want those interrupts
5878 for (i = 0; i < dd->first_user_ctxt; i++) {
5879 dd->cspec->rcvavail_timeout[i] = rcv_int_timeout;
5880 qib_write_kreg(dd, kr_rcvavailtimeout + i, rcv_int_timeout);
5884 * Initialize as (disabled) rcvflow tables. Application code
5885 * will setup each flow as it uses the flow.
5886 * Doesn't clear any of the error bits that might be set.
5888 val = TIDFLOW_ERRBITS; /* these are W1C */
5889 for (i = 0; i < dd->cfgctxts; i++) {
5891 for (flow = 0; flow < NUM_TIDFLOWS_CTXT; flow++)
5892 qib_write_ureg(dd, ur_rcvflowtable+flow, val, i);
5896 * dual cards init to dual port recovery, single port cards to
5897 * the one port. Dual port cards may later adjust to 1 port,
5898 * and then back to dual port if both ports are connected
5901 setup_7322_link_recovery(dd->pport, dd->num_pports > 1);
5904 static int qib_init_7322_variables(struct qib_devdata *dd)
5906 struct qib_pportdata *ppd;
5907 unsigned features, pidx, sbufcnt;
5909 u32 sbufs, updthresh;
5911 /* pport structs are contiguous, allocated after devdata */
5912 ppd = (struct qib_pportdata *)(dd + 1);
5917 dd->cspec = (struct qib_chip_specific *)(ppd + 2);
5919 ppd[0].cpspec = (struct qib_chippport_specific *)(dd->cspec + 1);
5920 ppd[1].cpspec = &ppd[0].cpspec[1];
5921 ppd[0].cpspec->ppd = &ppd[0]; /* for autoneg_7322_work() */
5922 ppd[1].cpspec->ppd = &ppd[1]; /* for autoneg_7322_work() */
5924 spin_lock_init(&dd->cspec->rcvmod_lock);
5925 spin_lock_init(&dd->cspec->gpio_lock);
5927 /* we haven't yet set QIB_PRESENT, so use read directly */
5928 dd->revision = readq(&dd->kregbase[kr_revision]);
5930 if ((dd->revision & 0xffffffffU) == 0xffffffffU) {
5931 qib_dev_err(dd, "Revision register read failure, "
5932 "giving up initialization\n");
5936 dd->flags |= QIB_PRESENT; /* now register routines work */
5938 dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMajor);
5939 dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMinor);
5940 dd->cspec->r1 = dd->minrev == 1;
5942 get_7322_chip_params(dd);
5943 features = qib_7322_boardname(dd);
5945 /* now that piobcnt2k and 4k set, we can allocate these */
5946 sbufcnt = dd->piobcnt2k + dd->piobcnt4k +
5947 NUM_VL15_BUFS + BITS_PER_LONG - 1;
5948 sbufcnt /= BITS_PER_LONG;
5949 dd->cspec->sendchkenable = kmalloc(sbufcnt *
5950 sizeof(*dd->cspec->sendchkenable), GFP_KERNEL);
5951 dd->cspec->sendgrhchk = kmalloc(sbufcnt *
5952 sizeof(*dd->cspec->sendgrhchk), GFP_KERNEL);
5953 dd->cspec->sendibchk = kmalloc(sbufcnt *
5954 sizeof(*dd->cspec->sendibchk), GFP_KERNEL);
5955 if (!dd->cspec->sendchkenable || !dd->cspec->sendgrhchk ||
5956 !dd->cspec->sendibchk) {
5957 qib_dev_err(dd, "Failed allocation for hdrchk bitmaps\n");
5965 * GPIO bits for TWSI data and clock,
5966 * used for serial EEPROM.
5968 dd->gpio_sda_num = _QIB_GPIO_SDA_NUM;
5969 dd->gpio_scl_num = _QIB_GPIO_SCL_NUM;
5970 dd->twsi_eeprom_dev = QIB_TWSI_EEPROM_DEV;
5972 dd->flags |= QIB_HAS_INTX | QIB_HAS_LINK_LATENCY |
5973 QIB_NODMA_RTAIL | QIB_HAS_VLSUPP | QIB_HAS_HDRSUPP |
5974 QIB_HAS_THRESH_UPDATE |
5975 (sdma_idle_cnt ? QIB_HAS_SDMA_TIMEOUT : 0);
5976 dd->flags |= qib_special_trigger ?
5977 QIB_USE_SPCL_TRIG : QIB_HAS_SEND_DMA;
5980 * Setup initial values. These may change when PAT is enabled, but
5981 * we need these to do initial chip register accesses.
5983 qib_7322_set_baseaddrs(dd);
5985 mtu = ib_mtu_enum_to_int(qib_ibmtu);
5987 mtu = QIB_DEFAULT_MTU;
5989 dd->cspec->int_enable_mask = QIB_I_BITSEXTANT;
5990 /* all hwerrors become interrupts, unless special purposed */
5991 dd->cspec->hwerrmask = ~0ULL;
5992 /* link_recovery setup causes these errors, so ignore them,
5993 * other than clearing them when they occur */
5994 dd->cspec->hwerrmask &=
5995 ~(SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_0) |
5996 SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_1) |
5997 HWE_MASK(LATriggered));
5999 for (pidx = 0; pidx < NUM_IB_PORTS; ++pidx) {
6000 struct qib_chippport_specific *cp = ppd->cpspec;
6001 ppd->link_speed_supported = features & PORT_SPD_CAP;
6002 features >>= PORT_SPD_CAP_SHIFT;
6003 if (!ppd->link_speed_supported) {
6004 /* single port mode (7340, or configured) */
6005 dd->skip_kctxt_mask |= 1 << pidx;
6007 /* Make sure port is disabled. */
6008 qib_write_kreg_port(ppd, krp_rcvctrl, 0);
6009 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0);
6011 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6012 IBSerdesPClkNotDetectMask_0)
6013 | SYM_MASK(HwErrMask,
6014 SDmaMemReadErrMask_0));
6015 dd->cspec->int_enable_mask &= ~(
6016 SYM_MASK(IntMask, SDmaCleanupDoneMask_0) |
6017 SYM_MASK(IntMask, SDmaIdleIntMask_0) |
6018 SYM_MASK(IntMask, SDmaProgressIntMask_0) |
6019 SYM_MASK(IntMask, SDmaIntMask_0) |
6020 SYM_MASK(IntMask, ErrIntMask_0) |
6021 SYM_MASK(IntMask, SendDoneIntMask_0));
6023 /* Make sure port is disabled. */
6024 qib_write_kreg_port(ppd, krp_rcvctrl, 0);
6025 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0);
6026 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6027 IBSerdesPClkNotDetectMask_1)
6028 | SYM_MASK(HwErrMask,
6029 SDmaMemReadErrMask_1));
6030 dd->cspec->int_enable_mask &= ~(
6031 SYM_MASK(IntMask, SDmaCleanupDoneMask_1) |
6032 SYM_MASK(IntMask, SDmaIdleIntMask_1) |
6033 SYM_MASK(IntMask, SDmaProgressIntMask_1) |
6034 SYM_MASK(IntMask, SDmaIntMask_1) |
6035 SYM_MASK(IntMask, ErrIntMask_1) |
6036 SYM_MASK(IntMask, SendDoneIntMask_1));
6042 qib_init_pportdata(ppd, dd, pidx, dd->num_pports);
6044 ppd->link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
6045 ppd->link_width_enabled = IB_WIDTH_4X;
6046 ppd->link_speed_enabled = ppd->link_speed_supported;
6048 * Set the initial values to reasonable default, will be set
6049 * for real when link is up.
6051 ppd->link_width_active = IB_WIDTH_4X;
6052 ppd->link_speed_active = QIB_IB_SDR;
6053 ppd->delay_mult = ib_rate_to_delay[IB_RATE_10_GBPS];
6054 switch (qib_num_cfg_vls) {
6056 ppd->vls_supported = IB_VL_VL0;
6059 ppd->vls_supported = IB_VL_VL0_1;
6062 qib_devinfo(dd->pcidev,
6063 "Invalid num_vls %u, using 4 VLs\n",
6065 qib_num_cfg_vls = 4;
6068 ppd->vls_supported = IB_VL_VL0_3;
6072 ppd->vls_supported = IB_VL_VL0_7;
6074 qib_devinfo(dd->pcidev,
6075 "Invalid num_vls %u for MTU %d "
6077 qib_num_cfg_vls, mtu);
6078 ppd->vls_supported = IB_VL_VL0_3;
6079 qib_num_cfg_vls = 4;
6083 ppd->vls_operational = ppd->vls_supported;
6085 init_waitqueue_head(&cp->autoneg_wait);
6086 INIT_DELAYED_WORK(&cp->autoneg_work,
6088 if (ppd->dd->cspec->r1)
6089 INIT_DELAYED_WORK(&cp->ipg_work, ipg_7322_work);
6092 * For Mez and similar cards, no qsfp info, so do
6093 * the "cable info" setup here. Can be overridden
6094 * in adapter-specific routines.
6096 if (!(dd->flags & QIB_HAS_QSFP)) {
6097 if (!IS_QMH(dd) && !IS_QME(dd))
6098 qib_devinfo(dd->pcidev, "IB%u:%u: "
6099 "Unknown mezzanine card type\n",
6100 dd->unit, ppd->port);
6101 cp->h1_val = IS_QMH(dd) ? H1_FORCE_QMH : H1_FORCE_QME;
6103 * Choose center value as default tx serdes setting
6104 * until changed through module parameter.
6106 ppd->cpspec->no_eep = IS_QMH(dd) ?
6107 TXDDS_TABLE_SZ + 2 : TXDDS_TABLE_SZ + 4;
6109 cp->h1_val = H1_FORCE_VAL;
6111 /* Avoid writes to chip for mini_init */
6113 write_7322_init_portregs(ppd);
6115 init_timer(&cp->chase_timer);
6116 cp->chase_timer.function = reenable_chase;
6117 cp->chase_timer.data = (unsigned long)ppd;
6122 dd->rcvhdrentsize = qib_rcvhdrentsize ?
6123 qib_rcvhdrentsize : QIB_RCVHDR_ENTSIZE;
6124 dd->rcvhdrsize = qib_rcvhdrsize ?
6125 qib_rcvhdrsize : QIB_DFLT_RCVHDRSIZE;
6126 dd->rhf_offset = dd->rcvhdrentsize - sizeof(u64) / sizeof(u32);
6128 /* we always allocate at least 2048 bytes for eager buffers */
6129 dd->rcvegrbufsize = max(mtu, 2048);
6131 qib_7322_tidtemplate(dd);
6134 * We can request a receive interrupt for 1 or
6135 * more packets from current offset.
6137 dd->rhdrhead_intr_off =
6138 (u64) rcv_int_count << IBA7322_HDRHEAD_PKTINT_SHIFT;
6140 /* setup the stats timer; the add_timer is done at end of init */
6141 init_timer(&dd->stats_timer);
6142 dd->stats_timer.function = qib_get_7322_faststats;
6143 dd->stats_timer.data = (unsigned long) dd;
6145 dd->ureg_align = 0x10000; /* 64KB alignment */
6147 dd->piosize2kmax_dwords = dd->piosize2k >> 2;
6149 qib_7322_config_ctxts(dd);
6150 qib_set_ctxtcnt(dd);
6153 resource_size_t vl15off;
6155 * We do not set WC on the VL15 buffers to avoid
6156 * a rare problem with unaligned writes from
6157 * interrupt-flushed store buffers, so we need
6158 * to map those separately here. We can't solve
6159 * this for the rarely used mtrr case.
6161 ret = init_chip_wc_pat(dd, 0);
6165 /* vl15 buffers start just after the 4k buffers */
6166 vl15off = dd->physaddr + (dd->piobufbase >> 32) +
6167 dd->piobcnt4k * dd->align4k;
6168 dd->piovl15base = ioremap_nocache(vl15off,
6169 NUM_VL15_BUFS * dd->align4k);
6170 if (!dd->piovl15base)
6173 qib_7322_set_baseaddrs(dd); /* set chip access pointers now */
6178 if (!dd->num_pports) {
6179 qib_dev_err(dd, "No ports enabled, giving up initialization\n");
6180 goto bail; /* no error, so can still figure out why err */
6183 write_7322_initregs(dd);
6184 ret = qib_create_ctxts(dd);
6185 init_7322_cntrnames(dd);
6187 updthresh = 8U; /* update threshold */
6189 /* use all of 4KB buffers for the kernel SDMA, zero if !SDMA.
6190 * reserve the update threshold amount for other kernel use, such
6191 * as sending SMI, MAD, and ACKs, or 3, whichever is greater,
6192 * unless we aren't enabling SDMA, in which case we want to use
6193 * all the 4k bufs for the kernel.
6194 * if this was less than the update threshold, we could wait
6195 * a long time for an update. Coded this way because we
6196 * sometimes change the update threshold for various reasons,
6197 * and we want this to remain robust.
6199 if (dd->flags & QIB_HAS_SEND_DMA) {
6200 dd->cspec->sdmabufcnt = dd->piobcnt4k;
6201 sbufs = updthresh > 3 ? updthresh : 3;
6203 dd->cspec->sdmabufcnt = 0;
6204 sbufs = dd->piobcnt4k;
6206 dd->cspec->lastbuf_for_pio = dd->piobcnt2k + dd->piobcnt4k -
6207 dd->cspec->sdmabufcnt;
6208 dd->lastctxt_piobuf = dd->cspec->lastbuf_for_pio - sbufs;
6209 dd->cspec->lastbuf_for_pio--; /* range is <= , not < */
6210 dd->pbufsctxt = (dd->cfgctxts > dd->first_user_ctxt) ?
6211 dd->lastctxt_piobuf / (dd->cfgctxts - dd->first_user_ctxt) : 0;
6214 * If we have 16 user contexts, we will have 7 sbufs
6215 * per context, so reduce the update threshold to match. We
6216 * want to update before we actually run out, at low pbufs/ctxt
6217 * so give ourselves some margin.
6219 if (dd->pbufsctxt >= 2 && dd->pbufsctxt - 2 < updthresh)
6220 updthresh = dd->pbufsctxt - 2;
6221 dd->cspec->updthresh_dflt = updthresh;
6222 dd->cspec->updthresh = updthresh;
6224 /* before full enable, no interrupts, no locking needed */
6225 dd->sendctrl |= ((updthresh & SYM_RMASK(SendCtrl, AvailUpdThld))
6226 << SYM_LSB(SendCtrl, AvailUpdThld)) |
6227 SYM_MASK(SendCtrl, SendBufAvailPad64Byte);
6229 dd->psxmitwait_supported = 1;
6230 dd->psxmitwait_check_rate = QIB_7322_PSXMITWAIT_CHECK_RATE;
6233 dd->ctxtcnt = 1; /* for other initialization code */
6238 static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *ppd, u64 pbc,
6241 u32 first, last, plen = pbc & QIB_PBC_LENGTH_MASK;
6242 struct qib_devdata *dd = ppd->dd;
6244 /* last is same for 2k and 4k, because we use 4k if all 2k busy */
6245 if (pbc & PBC_7322_VL15_SEND) {
6246 first = dd->piobcnt2k + dd->piobcnt4k + ppd->hw_pidx;
6249 if ((plen + 1) > dd->piosize2kmax_dwords)
6250 first = dd->piobcnt2k;
6253 last = dd->cspec->lastbuf_for_pio;
6255 return qib_getsendbuf_range(dd, pbufnum, first, last);
6258 static void qib_set_cntr_7322_sample(struct qib_pportdata *ppd, u32 intv,
6261 qib_write_kreg_port(ppd, krp_psinterval, intv);
6262 qib_write_kreg_port(ppd, krp_psstart, start);
6266 * Must be called with sdma_lock held, or before init finished.
6268 static void qib_sdma_set_7322_desc_cnt(struct qib_pportdata *ppd, unsigned cnt)
6270 qib_write_kreg_port(ppd, krp_senddmadesccnt, cnt);
6273 static struct sdma_set_state_action sdma_7322_action_table[] = {
6274 [qib_sdma_state_s00_hw_down] = {
6275 .go_s99_running_tofalse = 1,
6281 [qib_sdma_state_s10_hw_start_up_wait] = {
6287 [qib_sdma_state_s20_idle] = {
6293 [qib_sdma_state_s30_sw_clean_up_wait] = {
6299 [qib_sdma_state_s40_hw_clean_up_wait] = {
6305 [qib_sdma_state_s50_hw_halt_wait] = {
6311 [qib_sdma_state_s99_running] = {
6316 .go_s99_running_totrue = 1,
6320 static void qib_7322_sdma_init_early(struct qib_pportdata *ppd)
6322 ppd->sdma_state.set_state_action = sdma_7322_action_table;
6325 static int init_sdma_7322_regs(struct qib_pportdata *ppd)
6327 struct qib_devdata *dd = ppd->dd;
6328 unsigned lastbuf, erstbuf;
6329 u64 senddmabufmask[3] = { 0 };
6332 qib_write_kreg_port(ppd, krp_senddmabase, ppd->sdma_descq_phys);
6333 qib_sdma_7322_setlengen(ppd);
6334 qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */
6335 qib_write_kreg_port(ppd, krp_senddmareloadcnt, sdma_idle_cnt);
6336 qib_write_kreg_port(ppd, krp_senddmadesccnt, 0);
6337 qib_write_kreg_port(ppd, krp_senddmaheadaddr, ppd->sdma_head_phys);
6340 n = dd->cspec->sdmabufcnt / dd->num_pports; /* no remainder */
6342 n = dd->cspec->sdmabufcnt; /* failsafe for init */
6343 erstbuf = (dd->piobcnt2k + dd->piobcnt4k) -
6344 ((dd->num_pports == 1 || ppd->port == 2) ? n :
6345 dd->cspec->sdmabufcnt);
6346 lastbuf = erstbuf + n;
6348 ppd->sdma_state.first_sendbuf = erstbuf;
6349 ppd->sdma_state.last_sendbuf = lastbuf;
6350 for (; erstbuf < lastbuf; ++erstbuf) {
6351 unsigned word = erstbuf / BITS_PER_LONG;
6352 unsigned bit = erstbuf & (BITS_PER_LONG - 1);
6355 senddmabufmask[word] |= 1ULL << bit;
6357 qib_write_kreg_port(ppd, krp_senddmabufmask0, senddmabufmask[0]);
6358 qib_write_kreg_port(ppd, krp_senddmabufmask1, senddmabufmask[1]);
6359 qib_write_kreg_port(ppd, krp_senddmabufmask2, senddmabufmask[2]);
6363 /* sdma_lock must be held */
6364 static u16 qib_sdma_7322_gethead(struct qib_pportdata *ppd)
6366 struct qib_devdata *dd = ppd->dd;
6374 use_dmahead = __qib_sdma_running(ppd) &&
6375 (dd->flags & QIB_HAS_SDMA_TIMEOUT);
6377 hwhead = use_dmahead ?
6378 (u16) le64_to_cpu(*ppd->sdma_head_dma) :
6379 (u16) qib_read_kreg_port(ppd, krp_senddmahead);
6381 swhead = ppd->sdma_descq_head;
6382 swtail = ppd->sdma_descq_tail;
6383 cnt = ppd->sdma_descq_cnt;
6385 if (swhead < swtail)
6387 sane = (hwhead >= swhead) & (hwhead <= swtail);
6388 else if (swhead > swtail)
6389 /* wrapped around */
6390 sane = ((hwhead >= swhead) && (hwhead < cnt)) ||
6394 sane = (hwhead == swhead);
6396 if (unlikely(!sane)) {
6398 /* try one more time, directly from the register */
6402 /* proceed as if no progress */
6409 static int qib_sdma_7322_busy(struct qib_pportdata *ppd)
6411 u64 hwstatus = qib_read_kreg_port(ppd, krp_senddmastatus);
6413 return (hwstatus & SYM_MASK(SendDmaStatus_0, ScoreBoardDrainInProg)) ||
6414 (hwstatus & SYM_MASK(SendDmaStatus_0, HaltInProg)) ||
6415 !(hwstatus & SYM_MASK(SendDmaStatus_0, InternalSDmaHalt)) ||
6416 !(hwstatus & SYM_MASK(SendDmaStatus_0, ScbEmpty));
6420 * Compute the amount of delay before sending the next packet if the
6421 * port's send rate differs from the static rate set for the QP.
6422 * The delay affects the next packet and the amount of the delay is
6423 * based on the length of the this packet.
6425 static u32 qib_7322_setpbc_control(struct qib_pportdata *ppd, u32 plen,
6428 u8 snd_mult = ppd->delay_mult;
6429 u8 rcv_mult = ib_rate_to_delay[srate];
6432 ret = rcv_mult > snd_mult ? ((plen + 1) >> 1) * snd_mult : 0;
6434 /* Indicate VL15, else set the VL in the control word */
6436 ret |= PBC_7322_VL15_SEND_CTRL;
6438 ret |= vl << PBC_VL_NUM_LSB;
6439 ret |= ((u32)(ppd->hw_pidx)) << PBC_PORT_SEL_LSB;
6445 * Enable the per-port VL15 send buffers for use.
6446 * They follow the rest of the buffers, without a config parameter.
6447 * This was in initregs, but that is done before the shadow
6448 * is set up, and this has to be done after the shadow is
6451 static void qib_7322_initvl15_bufs(struct qib_devdata *dd)
6455 vl15bufs = dd->piobcnt2k + dd->piobcnt4k;
6456 qib_chg_pioavailkernel(dd, vl15bufs, NUM_VL15_BUFS,
6457 TXCHK_CHG_TYPE_KERN, NULL);
6460 static void qib_7322_init_ctxt(struct qib_ctxtdata *rcd)
6462 if (rcd->ctxt < NUM_IB_PORTS) {
6463 if (rcd->dd->num_pports > 1) {
6464 rcd->rcvegrcnt = KCTXT0_EGRCNT / 2;
6465 rcd->rcvegr_tid_base = rcd->ctxt ? rcd->rcvegrcnt : 0;
6467 rcd->rcvegrcnt = KCTXT0_EGRCNT;
6468 rcd->rcvegr_tid_base = 0;
6471 rcd->rcvegrcnt = rcd->dd->cspec->rcvegrcnt;
6472 rcd->rcvegr_tid_base = KCTXT0_EGRCNT +
6473 (rcd->ctxt - NUM_IB_PORTS) * rcd->rcvegrcnt;
6477 #define QTXSLEEPS 5000
6478 static void qib_7322_txchk_change(struct qib_devdata *dd, u32 start,
6479 u32 len, u32 which, struct qib_ctxtdata *rcd)
6482 const int last = start + len - 1;
6483 const int lastr = last / BITS_PER_LONG;
6485 int wait = rcd != NULL;
6486 unsigned long flags;
6489 unsigned long shadow;
6490 int cstart, previ = -1;
6493 * when flipping from kernel to user, we can't change
6494 * the checking type if the buffer is allocated to the
6495 * driver. It's OK the other direction, because it's
6496 * from close, and we have just disarm'ed all the
6497 * buffers. All the kernel to kernel changes are also
6500 for (cstart = start; cstart <= last; cstart++) {
6501 i = ((2 * cstart) + QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT)
6504 shadow = (unsigned long)
6505 le64_to_cpu(dd->pioavailregs_dma[i]);
6508 if (test_bit(((2 * cstart) +
6509 QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT)
6510 % BITS_PER_LONG, &shadow))
6517 if (sleeps == QTXSLEEPS)
6519 /* make sure we see an updated copy next time around */
6520 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
6526 case TXCHK_CHG_TYPE_DIS1:
6528 * disable checking on a range; used by diags; just
6529 * one buffer, but still written generically
6531 for (i = start; i <= last; i++)
6532 clear_bit(i, dd->cspec->sendchkenable);
6535 case TXCHK_CHG_TYPE_ENAB1:
6537 * (re)enable checking on a range; used by diags; just
6538 * one buffer, but still written generically; read
6539 * scratch to be sure buffer actually triggered, not
6540 * just flushed from processor.
6542 qib_read_kreg32(dd, kr_scratch);
6543 for (i = start; i <= last; i++)
6544 set_bit(i, dd->cspec->sendchkenable);
6547 case TXCHK_CHG_TYPE_KERN:
6548 /* usable by kernel */
6549 for (i = start; i <= last; i++) {
6550 set_bit(i, dd->cspec->sendibchk);
6551 clear_bit(i, dd->cspec->sendgrhchk);
6553 spin_lock_irqsave(&dd->uctxt_lock, flags);
6554 /* see if we need to raise avail update threshold */
6555 for (i = dd->first_user_ctxt;
6556 dd->cspec->updthresh != dd->cspec->updthresh_dflt
6557 && i < dd->cfgctxts; i++)
6558 if (dd->rcd[i] && dd->rcd[i]->subctxt_cnt &&
6559 ((dd->rcd[i]->piocnt / dd->rcd[i]->subctxt_cnt) - 1)
6560 < dd->cspec->updthresh_dflt)
6562 spin_unlock_irqrestore(&dd->uctxt_lock, flags);
6563 if (i == dd->cfgctxts) {
6564 spin_lock_irqsave(&dd->sendctrl_lock, flags);
6565 dd->cspec->updthresh = dd->cspec->updthresh_dflt;
6566 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
6567 dd->sendctrl |= (dd->cspec->updthresh &
6568 SYM_RMASK(SendCtrl, AvailUpdThld)) <<
6569 SYM_LSB(SendCtrl, AvailUpdThld);
6570 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
6571 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
6575 case TXCHK_CHG_TYPE_USER:
6576 /* for user process */
6577 for (i = start; i <= last; i++) {
6578 clear_bit(i, dd->cspec->sendibchk);
6579 set_bit(i, dd->cspec->sendgrhchk);
6581 spin_lock_irqsave(&dd->sendctrl_lock, flags);
6582 if (rcd && rcd->subctxt_cnt && ((rcd->piocnt
6583 / rcd->subctxt_cnt) - 1) < dd->cspec->updthresh) {
6584 dd->cspec->updthresh = (rcd->piocnt /
6585 rcd->subctxt_cnt) - 1;
6586 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
6587 dd->sendctrl |= (dd->cspec->updthresh &
6588 SYM_RMASK(SendCtrl, AvailUpdThld))
6589 << SYM_LSB(SendCtrl, AvailUpdThld);
6590 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
6591 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
6593 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
6600 for (i = start / BITS_PER_LONG; which >= 2 && i <= lastr; ++i)
6601 qib_write_kreg(dd, kr_sendcheckmask + i,
6602 dd->cspec->sendchkenable[i]);
6604 for (i = start / BITS_PER_LONG; which < 2 && i <= lastr; ++i) {
6605 qib_write_kreg(dd, kr_sendgrhcheckmask + i,
6606 dd->cspec->sendgrhchk[i]);
6607 qib_write_kreg(dd, kr_sendibpktmask + i,
6608 dd->cspec->sendibchk[i]);
6612 * Be sure whatever we did was seen by the chip and acted upon,
6613 * before we return. Mostly important for which >= 2.
6615 qib_read_kreg32(dd, kr_scratch);
6619 /* useful for trigger analyzers, etc. */
6620 static void writescratch(struct qib_devdata *dd, u32 val)
6622 qib_write_kreg(dd, kr_scratch, val);
6625 /* Dummy for now, use chip regs soon */
6626 static int qib_7322_tempsense_rd(struct qib_devdata *dd, int regnum)
6632 * qib_init_iba7322_funcs - set up the chip-specific function pointers
6633 * @dev: the pci_dev for qlogic_ib device
6634 * @ent: pci_device_id struct for this dev
6636 * Also allocates, inits, and returns the devdata struct for this
6639 * This is global, and is called directly at init to set up the
6640 * chip-specific function pointers for later use.
6642 struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *pdev,
6643 const struct pci_device_id *ent)
6645 struct qib_devdata *dd;
6647 u32 tabsize, actual_cnt = 0;
6649 dd = qib_alloc_devdata(pdev,
6650 NUM_IB_PORTS * sizeof(struct qib_pportdata) +
6651 sizeof(struct qib_chip_specific) +
6652 NUM_IB_PORTS * sizeof(struct qib_chippport_specific));
6656 dd->f_bringup_serdes = qib_7322_bringup_serdes;
6657 dd->f_cleanup = qib_setup_7322_cleanup;
6658 dd->f_clear_tids = qib_7322_clear_tids;
6659 dd->f_free_irq = qib_7322_free_irq;
6660 dd->f_get_base_info = qib_7322_get_base_info;
6661 dd->f_get_msgheader = qib_7322_get_msgheader;
6662 dd->f_getsendbuf = qib_7322_getsendbuf;
6663 dd->f_gpio_mod = gpio_7322_mod;
6664 dd->f_eeprom_wen = qib_7322_eeprom_wen;
6665 dd->f_hdrqempty = qib_7322_hdrqempty;
6666 dd->f_ib_updown = qib_7322_ib_updown;
6667 dd->f_init_ctxt = qib_7322_init_ctxt;
6668 dd->f_initvl15_bufs = qib_7322_initvl15_bufs;
6669 dd->f_intr_fallback = qib_7322_intr_fallback;
6670 dd->f_late_initreg = qib_late_7322_initreg;
6671 dd->f_setpbc_control = qib_7322_setpbc_control;
6672 dd->f_portcntr = qib_portcntr_7322;
6673 dd->f_put_tid = qib_7322_put_tid;
6674 dd->f_quiet_serdes = qib_7322_mini_quiet_serdes;
6675 dd->f_rcvctrl = rcvctrl_7322_mod;
6676 dd->f_read_cntrs = qib_read_7322cntrs;
6677 dd->f_read_portcntrs = qib_read_7322portcntrs;
6678 dd->f_reset = qib_do_7322_reset;
6679 dd->f_init_sdma_regs = init_sdma_7322_regs;
6680 dd->f_sdma_busy = qib_sdma_7322_busy;
6681 dd->f_sdma_gethead = qib_sdma_7322_gethead;
6682 dd->f_sdma_sendctrl = qib_7322_sdma_sendctrl;
6683 dd->f_sdma_set_desc_cnt = qib_sdma_set_7322_desc_cnt;
6684 dd->f_sdma_update_tail = qib_sdma_update_7322_tail;
6685 dd->f_sendctrl = sendctrl_7322_mod;
6686 dd->f_set_armlaunch = qib_set_7322_armlaunch;
6687 dd->f_set_cntr_sample = qib_set_cntr_7322_sample;
6688 dd->f_iblink_state = qib_7322_iblink_state;
6689 dd->f_ibphys_portstate = qib_7322_phys_portstate;
6690 dd->f_get_ib_cfg = qib_7322_get_ib_cfg;
6691 dd->f_set_ib_cfg = qib_7322_set_ib_cfg;
6692 dd->f_set_ib_loopback = qib_7322_set_loopback;
6693 dd->f_get_ib_table = qib_7322_get_ib_table;
6694 dd->f_set_ib_table = qib_7322_set_ib_table;
6695 dd->f_set_intr_state = qib_7322_set_intr_state;
6696 dd->f_setextled = qib_setup_7322_setextled;
6697 dd->f_txchk_change = qib_7322_txchk_change;
6698 dd->f_update_usrhead = qib_update_7322_usrhead;
6699 dd->f_wantpiobuf_intr = qib_wantpiobuf_7322_intr;
6700 dd->f_xgxs_reset = qib_7322_mini_pcs_reset;
6701 dd->f_sdma_hw_clean_up = qib_7322_sdma_hw_clean_up;
6702 dd->f_sdma_hw_start_up = qib_7322_sdma_hw_start_up;
6703 dd->f_sdma_init_early = qib_7322_sdma_init_early;
6704 dd->f_writescratch = writescratch;
6705 dd->f_tempsense_rd = qib_7322_tempsense_rd;
6707 * Do remaining PCIe setup and save PCIe values in dd.
6708 * Any error printing is already done by the init code.
6709 * On return, we have the chip mapped, but chip registers
6710 * are not set up until start of qib_init_7322_variables.
6712 ret = qib_pcie_ddinit(dd, pdev, ent);
6716 /* initialize chip-specific variables */
6717 ret = qib_init_7322_variables(dd);
6721 if (qib_mini_init || !dd->num_pports)
6725 * Determine number of vectors we want; depends on port count
6726 * and number of configured kernel receive queues actually used.
6727 * Should also depend on whether sdma is enabled or not, but
6728 * that's such a rare testing case it's not worth worrying about.
6730 tabsize = dd->first_user_ctxt + ARRAY_SIZE(irq_table);
6731 for (i = 0; i < tabsize; i++)
6732 if ((i < ARRAY_SIZE(irq_table) &&
6733 irq_table[i].port <= dd->num_pports) ||
6734 (i >= ARRAY_SIZE(irq_table) &&
6735 dd->rcd[i - ARRAY_SIZE(irq_table)]))
6737 tabsize = actual_cnt;
6738 dd->cspec->msix_entries = kmalloc(tabsize *
6739 sizeof(struct msix_entry), GFP_KERNEL);
6740 dd->cspec->msix_arg = kmalloc(tabsize *
6741 sizeof(void *), GFP_KERNEL);
6742 if (!dd->cspec->msix_entries || !dd->cspec->msix_arg) {
6743 qib_dev_err(dd, "No memory for MSIx table\n");
6746 for (i = 0; i < tabsize; i++)
6747 dd->cspec->msix_entries[i].entry = i;
6749 if (qib_pcie_params(dd, 8, &tabsize, dd->cspec->msix_entries))
6750 qib_dev_err(dd, "Failed to setup PCIe or interrupts; "
6751 "continuing anyway\n");
6752 /* may be less than we wanted, if not enough available */
6753 dd->cspec->num_msix_entries = tabsize;
6755 /* setup interrupt handler */
6756 qib_setup_7322_interrupt(dd, 1);
6758 /* clear diagctrl register, in case diags were running and crashed */
6759 qib_write_kreg(dd, kr_hwdiagctrl, 0);
6764 qib_pcie_ddcleanup(dd);
6766 qib_free_devdata(dd);
6773 * Set the table entry at the specified index from the table specifed.
6774 * There are 3 * TXDDS_TABLE_SZ entries in all per port, with the first
6775 * TXDDS_TABLE_SZ for SDR, the next for DDR, and the last for QDR.
6776 * 'idx' below addresses the correct entry, while its 4 LSBs select the
6777 * corresponding entry (one of TXDDS_TABLE_SZ) from the selected table.
6779 #define DDS_ENT_AMP_LSB 14
6780 #define DDS_ENT_MAIN_LSB 9
6781 #define DDS_ENT_POST_LSB 5
6782 #define DDS_ENT_PRE_XTRA_LSB 3
6783 #define DDS_ENT_PRE_LSB 0
6786 * Set one entry in the TxDDS table for spec'd port
6787 * ridx picks one of the entries, while tp points
6788 * to the appropriate table entry.
6790 static void set_txdds(struct qib_pportdata *ppd, int ridx,
6791 const struct txdds_ent *tp)
6793 struct qib_devdata *dd = ppd->dd;
6797 /* Get correct offset in chip-space, and in source table */
6798 regidx = KREG_IBPORT_IDX(IBSD_DDS_MAP_TABLE) + ridx;
6800 * We do not use qib_write_kreg_port() because it was intended
6801 * only for registers in the lower "port specific" pages.
6802 * So do index calculation by hand.
6805 regidx += (dd->palign / sizeof(u64));
6807 pack_ent = tp->amp << DDS_ENT_AMP_LSB;
6808 pack_ent |= tp->main << DDS_ENT_MAIN_LSB;
6809 pack_ent |= tp->pre << DDS_ENT_PRE_LSB;
6810 pack_ent |= tp->post << DDS_ENT_POST_LSB;
6811 qib_write_kreg(dd, regidx, pack_ent);
6812 /* Prevent back-to-back writes by hitting scratch */
6813 qib_write_kreg(ppd->dd, kr_scratch, 0);
6816 static const struct vendor_txdds_ent vendor_txdds[] = {
6817 { /* Amphenol 1m 30awg NoEq */
6818 { 0x41, 0x50, 0x48 }, "584470002 ",
6819 { 10, 0, 0, 5 }, { 10, 0, 0, 9 }, { 7, 1, 0, 13 },
6821 { /* Amphenol 3m 28awg NoEq */
6822 { 0x41, 0x50, 0x48 }, "584470004 ",
6823 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 7, 15 },
6825 { /* Finisar 3m OM2 Optical */
6826 { 0x00, 0x90, 0x65 }, "FCBG410QB1C03-QL",
6827 { 0, 0, 0, 3 }, { 0, 0, 0, 4 }, { 0, 0, 0, 13 },
6829 { /* Finisar 30m OM2 Optical */
6830 { 0x00, 0x90, 0x65 }, "FCBG410QB1C30-QL",
6831 { 0, 0, 0, 1 }, { 0, 0, 0, 5 }, { 0, 0, 0, 11 },
6833 { /* Finisar Default OM2 Optical */
6834 { 0x00, 0x90, 0x65 }, NULL,
6835 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 0, 0, 12 },
6837 { /* Gore 1m 30awg NoEq */
6838 { 0x00, 0x21, 0x77 }, "QSN3300-1 ",
6839 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 0, 15 },
6841 { /* Gore 2m 30awg NoEq */
6842 { 0x00, 0x21, 0x77 }, "QSN3300-2 ",
6843 { 0, 0, 0, 8 }, { 0, 0, 0, 10 }, { 0, 1, 7, 15 },
6845 { /* Gore 1m 28awg NoEq */
6846 { 0x00, 0x21, 0x77 }, "QSN3800-1 ",
6847 { 0, 0, 0, 6 }, { 0, 0, 0, 8 }, { 0, 1, 0, 15 },
6849 { /* Gore 3m 28awg NoEq */
6850 { 0x00, 0x21, 0x77 }, "QSN3800-3 ",
6851 { 0, 0, 0, 9 }, { 0, 0, 0, 13 }, { 0, 1, 7, 15 },
6853 { /* Gore 5m 24awg Eq */
6854 { 0x00, 0x21, 0x77 }, "QSN7000-5 ",
6855 { 0, 0, 0, 7 }, { 0, 0, 0, 9 }, { 0, 1, 3, 15 },
6857 { /* Gore 7m 24awg Eq */
6858 { 0x00, 0x21, 0x77 }, "QSN7000-7 ",
6859 { 0, 0, 0, 9 }, { 0, 0, 0, 11 }, { 0, 2, 6, 15 },
6861 { /* Gore 5m 26awg Eq */
6862 { 0x00, 0x21, 0x77 }, "QSN7600-5 ",
6863 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 9, 13 },
6865 { /* Gore 7m 26awg Eq */
6866 { 0x00, 0x21, 0x77 }, "QSN7600-7 ",
6867 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 10, 1, 8, 15 },
6869 { /* Intersil 12m 24awg Active */
6870 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1224",
6871 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 3, 0, 9 },
6873 { /* Intersil 10m 28awg Active */
6874 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1028",
6875 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 2, 0, 2 },
6877 { /* Intersil 7m 30awg Active */
6878 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0730",
6879 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 1, 0, 3 },
6881 { /* Intersil 5m 32awg Active */
6882 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0532",
6883 { 0, 0, 0, 6 }, { 0, 0, 0, 6 }, { 0, 2, 0, 8 },
6885 { /* Intersil Default Active */
6886 { 0x00, 0x30, 0xB4 }, NULL,
6887 { 0, 0, 0, 6 }, { 0, 0, 0, 5 }, { 0, 2, 0, 5 },
6889 { /* Luxtera 20m Active Optical */
6890 { 0x00, 0x25, 0x63 }, NULL,
6891 { 0, 0, 0, 5 }, { 0, 0, 0, 8 }, { 0, 2, 0, 12 },
6893 { /* Molex 1M Cu loopback */
6894 { 0x00, 0x09, 0x3A }, "74763-0025 ",
6895 { 2, 2, 6, 15 }, { 2, 2, 6, 15 }, { 2, 2, 6, 15 },
6897 { /* Molex 2m 28awg NoEq */
6898 { 0x00, 0x09, 0x3A }, "74757-2201 ",
6899 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 1, 15 },
6903 static const struct txdds_ent txdds_sdr[TXDDS_TABLE_SZ] = {
6904 /* amp, pre, main, post */
6905 { 2, 2, 15, 6 }, /* Loopback */
6906 { 0, 0, 0, 1 }, /* 2 dB */
6907 { 0, 0, 0, 2 }, /* 3 dB */
6908 { 0, 0, 0, 3 }, /* 4 dB */
6909 { 0, 0, 0, 4 }, /* 5 dB */
6910 { 0, 0, 0, 5 }, /* 6 dB */
6911 { 0, 0, 0, 6 }, /* 7 dB */
6912 { 0, 0, 0, 7 }, /* 8 dB */
6913 { 0, 0, 0, 8 }, /* 9 dB */
6914 { 0, 0, 0, 9 }, /* 10 dB */
6915 { 0, 0, 0, 10 }, /* 11 dB */
6916 { 0, 0, 0, 11 }, /* 12 dB */
6917 { 0, 0, 0, 12 }, /* 13 dB */
6918 { 0, 0, 0, 13 }, /* 14 dB */
6919 { 0, 0, 0, 14 }, /* 15 dB */
6920 { 0, 0, 0, 15 }, /* 16 dB */
6923 static const struct txdds_ent txdds_ddr[TXDDS_TABLE_SZ] = {
6924 /* amp, pre, main, post */
6925 { 2, 2, 15, 6 }, /* Loopback */
6926 { 0, 0, 0, 8 }, /* 2 dB */
6927 { 0, 0, 0, 8 }, /* 3 dB */
6928 { 0, 0, 0, 9 }, /* 4 dB */
6929 { 0, 0, 0, 9 }, /* 5 dB */
6930 { 0, 0, 0, 10 }, /* 6 dB */
6931 { 0, 0, 0, 10 }, /* 7 dB */
6932 { 0, 0, 0, 11 }, /* 8 dB */
6933 { 0, 0, 0, 11 }, /* 9 dB */
6934 { 0, 0, 0, 12 }, /* 10 dB */
6935 { 0, 0, 0, 12 }, /* 11 dB */
6936 { 0, 0, 0, 13 }, /* 12 dB */
6937 { 0, 0, 0, 13 }, /* 13 dB */
6938 { 0, 0, 0, 14 }, /* 14 dB */
6939 { 0, 0, 0, 14 }, /* 15 dB */
6940 { 0, 0, 0, 15 }, /* 16 dB */
6943 static const struct txdds_ent txdds_qdr[TXDDS_TABLE_SZ] = {
6944 /* amp, pre, main, post */
6945 { 2, 2, 15, 6 }, /* Loopback */
6946 { 0, 1, 0, 7 }, /* 2 dB (also QMH7342) */
6947 { 0, 1, 0, 9 }, /* 3 dB (also QMH7342) */
6948 { 0, 1, 0, 11 }, /* 4 dB */
6949 { 0, 1, 0, 13 }, /* 5 dB */
6950 { 0, 1, 0, 15 }, /* 6 dB */
6951 { 0, 1, 3, 15 }, /* 7 dB */
6952 { 0, 1, 7, 15 }, /* 8 dB */
6953 { 0, 1, 7, 15 }, /* 9 dB */
6954 { 0, 1, 8, 15 }, /* 10 dB */
6955 { 0, 1, 9, 15 }, /* 11 dB */
6956 { 0, 1, 10, 15 }, /* 12 dB */
6957 { 0, 2, 6, 15 }, /* 13 dB */
6958 { 0, 2, 7, 15 }, /* 14 dB */
6959 { 0, 2, 8, 15 }, /* 15 dB */
6960 { 0, 2, 9, 15 }, /* 16 dB */
6964 * extra entries for use with txselect, for indices >= TXDDS_TABLE_SZ.
6965 * These are mostly used for mez cards going through connectors
6966 * and backplane traces, but can be used to add other "unusual"
6967 * table values as well.
6969 static const struct txdds_ent txdds_extra_sdr[TXDDS_EXTRA_SZ] = {
6970 /* amp, pre, main, post */
6971 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */
6972 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */
6973 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */
6974 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */
6975 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
6976 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
6977 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
6978 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
6979 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
6980 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
6981 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
6982 { 0, 0, 0, 3 }, /* QMH7342 backplane settings */
6983 { 0, 0, 0, 4 }, /* QMH7342 backplane settings */
6986 static const struct txdds_ent txdds_extra_ddr[TXDDS_EXTRA_SZ] = {
6987 /* amp, pre, main, post */
6988 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */
6989 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */
6990 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */
6991 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */
6992 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
6993 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
6994 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
6995 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
6996 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
6997 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
6998 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
6999 { 0, 0, 0, 9 }, /* QMH7342 backplane settings */
7000 { 0, 0, 0, 10 }, /* QMH7342 backplane settings */
7003 static const struct txdds_ent txdds_extra_qdr[TXDDS_EXTRA_SZ] = {
7004 /* amp, pre, main, post */
7005 { 0, 1, 0, 4 }, /* QMH7342 backplane settings */
7006 { 0, 1, 0, 5 }, /* QMH7342 backplane settings */
7007 { 0, 1, 0, 6 }, /* QMH7342 backplane settings */
7008 { 0, 1, 0, 8 }, /* QMH7342 backplane settings */
7009 { 0, 1, 12, 10 }, /* QME7342 backplane setting */
7010 { 0, 1, 12, 11 }, /* QME7342 backplane setting */
7011 { 0, 1, 12, 12 }, /* QME7342 backplane setting */
7012 { 0, 1, 12, 14 }, /* QME7342 backplane setting */
7013 { 0, 1, 12, 6 }, /* QME7342 backplane setting */
7014 { 0, 1, 12, 7 }, /* QME7342 backplane setting */
7015 { 0, 1, 12, 8 }, /* QME7342 backplane setting */
7016 { 0, 1, 0, 10 }, /* QMH7342 backplane settings */
7017 { 0, 1, 0, 12 }, /* QMH7342 backplane settings */
7020 static const struct txdds_ent *get_atten_table(const struct txdds_ent *txdds,
7024 * The attenuation table starts at 2dB for entry 1,
7025 * with entry 0 being the loopback entry.
7029 else if (atten > TXDDS_TABLE_SZ)
7030 atten = TXDDS_TABLE_SZ - 1;
7033 return txdds + atten;
7037 * if override is set, the module parameter txselect has a value
7038 * for this specific port, so use it, rather than our normal mechanism.
7040 static void find_best_ent(struct qib_pportdata *ppd,
7041 const struct txdds_ent **sdr_dds,
7042 const struct txdds_ent **ddr_dds,
7043 const struct txdds_ent **qdr_dds, int override)
7045 struct qib_qsfp_cache *qd = &ppd->cpspec->qsfp_data.cache;
7048 /* Search table of known cables */
7049 for (idx = 0; !override && idx < ARRAY_SIZE(vendor_txdds); ++idx) {
7050 const struct vendor_txdds_ent *v = vendor_txdds + idx;
7052 if (!memcmp(v->oui, qd->oui, QSFP_VOUI_LEN) &&
7054 !memcmp(v->partnum, qd->partnum, QSFP_PN_LEN))) {
7062 /* Lookup serdes setting by cable type and attenuation */
7063 if (!override && QSFP_IS_ACTIVE(qd->tech)) {
7064 *sdr_dds = txdds_sdr + ppd->dd->board_atten;
7065 *ddr_dds = txdds_ddr + ppd->dd->board_atten;
7066 *qdr_dds = txdds_qdr + ppd->dd->board_atten;
7070 if (!override && QSFP_HAS_ATTEN(qd->tech) && (qd->atten[0] ||
7072 *sdr_dds = get_atten_table(txdds_sdr, qd->atten[0]);
7073 *ddr_dds = get_atten_table(txdds_ddr, qd->atten[0]);
7074 *qdr_dds = get_atten_table(txdds_qdr, qd->atten[1]);
7076 } else if (ppd->cpspec->no_eep < TXDDS_TABLE_SZ) {
7078 * If we have no (or incomplete) data from the cable
7079 * EEPROM, or no QSFP, or override is set, use the
7080 * module parameter value to index into the attentuation
7083 idx = ppd->cpspec->no_eep;
7084 *sdr_dds = &txdds_sdr[idx];
7085 *ddr_dds = &txdds_ddr[idx];
7086 *qdr_dds = &txdds_qdr[idx];
7087 } else if (ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ)) {
7088 /* similar to above, but index into the "extra" table. */
7089 idx = ppd->cpspec->no_eep - TXDDS_TABLE_SZ;
7090 *sdr_dds = &txdds_extra_sdr[idx];
7091 *ddr_dds = &txdds_extra_ddr[idx];
7092 *qdr_dds = &txdds_extra_qdr[idx];
7094 /* this shouldn't happen, it's range checked */
7095 *sdr_dds = txdds_sdr + qib_long_atten;
7096 *ddr_dds = txdds_ddr + qib_long_atten;
7097 *qdr_dds = txdds_qdr + qib_long_atten;
7101 static void init_txdds_table(struct qib_pportdata *ppd, int override)
7103 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds;
7104 struct txdds_ent *dds;
7108 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, override);
7110 /* for mez cards or override, use the selected value for all entries */
7111 if (!(ppd->dd->flags & QIB_HAS_QSFP) || override)
7114 /* Fill in the first entry with the best entry found. */
7115 set_txdds(ppd, 0, sdr_dds);
7116 set_txdds(ppd, TXDDS_TABLE_SZ, ddr_dds);
7117 set_txdds(ppd, 2 * TXDDS_TABLE_SZ, qdr_dds);
7118 if (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED |
7120 dds = (struct txdds_ent *)(ppd->link_speed_active ==
7121 QIB_IB_QDR ? qdr_dds :
7122 (ppd->link_speed_active ==
7123 QIB_IB_DDR ? ddr_dds : sdr_dds));
7124 write_tx_serdes_param(ppd, dds);
7127 /* Fill in the remaining entries with the default table values. */
7128 for (idx = 1; idx < ARRAY_SIZE(txdds_sdr); ++idx) {
7129 set_txdds(ppd, idx, single_ent ? sdr_dds : txdds_sdr + idx);
7130 set_txdds(ppd, idx + TXDDS_TABLE_SZ,
7131 single_ent ? ddr_dds : txdds_ddr + idx);
7132 set_txdds(ppd, idx + 2 * TXDDS_TABLE_SZ,
7133 single_ent ? qdr_dds : txdds_qdr + idx);
7137 #define KR_AHB_ACC KREG_IDX(ahb_access_ctrl)
7138 #define KR_AHB_TRANS KREG_IDX(ahb_transaction_reg)
7139 #define AHB_TRANS_RDY SYM_MASK(ahb_transaction_reg, ahb_rdy)
7140 #define AHB_ADDR_LSB SYM_LSB(ahb_transaction_reg, ahb_address)
7141 #define AHB_DATA_LSB SYM_LSB(ahb_transaction_reg, ahb_data)
7142 #define AHB_WR SYM_MASK(ahb_transaction_reg, write_not_read)
7143 #define AHB_TRANS_TRIES 10
7146 * The chan argument is 0=chan0, 1=chan1, 2=pll, 3=chan2, 4=chan4,
7147 * 5=subsystem which is why most calls have "chan + chan >> 1"
7148 * for the channel argument.
7150 static u32 ahb_mod(struct qib_devdata *dd, int quad, int chan, int addr,
7153 u32 rd_data, wr_data, sz_mask;
7154 u64 trans, acc, prev_acc;
7155 u32 ret = 0xBAD0BAD;
7158 prev_acc = qib_read_kreg64(dd, KR_AHB_ACC);
7159 /* From this point on, make sure we return access */
7160 acc = (quad << 1) | 1;
7161 qib_write_kreg(dd, KR_AHB_ACC, acc);
7163 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7164 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7165 if (trans & AHB_TRANS_RDY)
7168 if (tries >= AHB_TRANS_TRIES) {
7169 qib_dev_err(dd, "No ahb_rdy in %d tries\n", AHB_TRANS_TRIES);
7173 /* If mask is not all 1s, we need to read, but different SerDes
7174 * entities have different sizes
7176 sz_mask = (1UL << ((quad == 1) ? 32 : 16)) - 1;
7177 wr_data = data & mask & sz_mask;
7178 if ((~mask & sz_mask) != 0) {
7179 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1);
7180 qib_write_kreg(dd, KR_AHB_TRANS, trans);
7182 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7183 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7184 if (trans & AHB_TRANS_RDY)
7187 if (tries >= AHB_TRANS_TRIES) {
7188 qib_dev_err(dd, "No Rd ahb_rdy in %d tries\n",
7192 /* Re-read in case host split reads and read data first */
7193 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7194 rd_data = (uint32_t)(trans >> AHB_DATA_LSB);
7195 wr_data |= (rd_data & ~mask & sz_mask);
7198 /* If mask is not zero, we need to write. */
7199 if (mask & sz_mask) {
7200 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1);
7201 trans |= ((uint64_t)wr_data << AHB_DATA_LSB);
7203 qib_write_kreg(dd, KR_AHB_TRANS, trans);
7205 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7206 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7207 if (trans & AHB_TRANS_RDY)
7210 if (tries >= AHB_TRANS_TRIES) {
7211 qib_dev_err(dd, "No Wr ahb_rdy in %d tries\n",
7218 qib_write_kreg(dd, KR_AHB_ACC, prev_acc);
7222 static void ibsd_wr_allchans(struct qib_pportdata *ppd, int addr, unsigned data,
7225 struct qib_devdata *dd = ppd->dd;
7229 for (chan = 0; chan < SERDES_CHANS; ++chan) {
7230 ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), addr,
7232 rbc = ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7237 static int serdes_7322_init(struct qib_pportdata *ppd)
7243 * Initialize the Tx DDS tables. Also done every QSFP event,
7244 * for adapters with QSFP
7246 init_txdds_table(ppd, 0);
7248 /* ensure no tx overrides from earlier driver loads */
7249 qib_write_kreg_port(ppd, krp_tx_deemph_override,
7250 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7251 reset_tx_deemphasis_override));
7253 /* Patch some SerDes defaults to "Better for IB" */
7254 /* Timing Loop Bandwidth: cdr_timing[11:9] = 0 */
7255 ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9));
7257 /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */
7258 ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11));
7259 /* Enable LE2: rxle2en_r2a addr 13 bit [6] = 1 */
7260 ibsd_wr_allchans(ppd, 13, (1 << 6), (1 << 6));
7262 /* May be overridden in qsfp_7322_event */
7263 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT;
7264 ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7));
7266 /* enable LE1 adaptation for all but QME, which is disabled */
7267 le_val = IS_QME(ppd->dd) ? 0 : 1;
7268 ibsd_wr_allchans(ppd, 13, (le_val << 5), (1 << 5));
7270 /* Clear cmode-override, may be set from older driver */
7271 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14);
7273 /* Timing Recovery: rxtapsel addr 5 bits [9:8] = 0 */
7274 ibsd_wr_allchans(ppd, 5, (0 << 8), BMASK(9, 8));
7276 /* setup LoS params; these are subsystem, so chan == 5 */
7277 /* LoS filter threshold_count on, ch 0-3, set to 8 */
7278 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11));
7279 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4));
7280 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11));
7281 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4));
7283 /* LoS filter threshold_count off, ch 0-3, set to 4 */
7284 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0));
7285 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8));
7286 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0));
7287 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8));
7289 /* LoS filter select enabled */
7290 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15);
7292 /* LoS target data: SDR=4, DDR=2, QDR=1 */
7293 ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */
7294 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */
7295 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */
7297 data = qib_read_kreg_port(ppd, krp_serdesctrl);
7298 qib_write_kreg_port(ppd, krp_serdesctrl, data |
7299 SYM_MASK(IBSerdesCtrl_0, RXLOSEN));
7301 /* rxbistena; set 0 to avoid effects of it switch later */
7302 ibsd_wr_allchans(ppd, 9, 0 << 15, 1 << 15);
7304 /* Configure 4 DFE taps, and only they adapt */
7305 ibsd_wr_allchans(ppd, 16, 0 << 0, BMASK(1, 0));
7307 /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */
7308 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac;
7309 ibsd_wr_allchans(ppd, 21, le_val, 0xfffe);
7312 * Set receive adaptation mode. SDR and DDR adaptation are
7313 * always on, and QDR is initially enabled; later disabled.
7315 qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL);
7316 qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL);
7317 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
7318 ppd->dd->cspec->r1 ?
7319 QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN);
7320 ppd->cpspec->qdr_dfe_on = 1;
7322 /* FLoop LOS gate: PPM filter enabled */
7323 ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10);
7325 /* rx offset center enabled */
7326 ibsd_wr_allchans(ppd, 12, 1 << 4, 1 << 4);
7328 if (!ppd->dd->cspec->r1) {
7329 ibsd_wr_allchans(ppd, 12, 1 << 12, 1 << 12);
7330 ibsd_wr_allchans(ppd, 12, 2 << 8, 0x0f << 8);
7333 /* Set the frequency loop bandwidth to 15 */
7334 ibsd_wr_allchans(ppd, 2, 15 << 5, BMASK(8, 5));
7339 /* start adjust QMH serdes parameters */
7341 static void set_man_code(struct qib_pportdata *ppd, int chan, int code)
7343 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7344 9, code << 9, 0x3f << 9);
7347 static void set_man_mode_h1(struct qib_pportdata *ppd, int chan,
7348 int enable, u32 tapenable)
7351 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7352 1, 3 << 10, 0x1f << 10);
7354 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7358 /* Set clock to 1, 0, 1, 0 */
7359 static void clock_man(struct qib_pportdata *ppd, int chan)
7361 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7363 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7365 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7367 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7372 * write the current Tx serdes pre,post,main,amp settings into the serdes.
7373 * The caller must pass the settings appropriate for the current speed,
7374 * or not care if they are correct for the current speed.
7376 static void write_tx_serdes_param(struct qib_pportdata *ppd,
7377 struct txdds_ent *txdds)
7381 deemph = qib_read_kreg_port(ppd, krp_tx_deemph_override);
7382 /* field names for amp, main, post, pre, respectively */
7383 deemph &= ~(SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txampcntl_d2a) |
7384 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txc0_ena) |
7385 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcp1_ena) |
7386 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcn1_ena));
7388 deemph |= SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7389 tx_override_deemphasis_select);
7390 deemph |= (txdds->amp & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7391 txampcntl_d2a)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7393 deemph |= (txdds->main & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7394 txc0_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7396 deemph |= (txdds->post & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7397 txcp1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7399 deemph |= (txdds->pre & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7400 txcn1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7402 qib_write_kreg_port(ppd, krp_tx_deemph_override, deemph);
7406 * Set the parameters for mez cards on link bounce, so they are
7407 * always exactly what was requested. Similar logic to init_txdds
7408 * but does just the serdes.
7410 static void adj_tx_serdes(struct qib_pportdata *ppd)
7412 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds;
7413 struct txdds_ent *dds;
7415 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, 1);
7416 dds = (struct txdds_ent *)(ppd->link_speed_active == QIB_IB_QDR ?
7417 qdr_dds : (ppd->link_speed_active == QIB_IB_DDR ?
7418 ddr_dds : sdr_dds));
7419 write_tx_serdes_param(ppd, dds);
7422 /* set QDR forced value for H1, if needed */
7423 static void force_h1(struct qib_pportdata *ppd)
7427 ppd->cpspec->qdr_reforce = 0;
7428 if (!ppd->dd->cspec->r1)
7431 for (chan = 0; chan < SERDES_CHANS; chan++) {
7432 set_man_mode_h1(ppd, chan, 1, 0);
7433 set_man_code(ppd, chan, ppd->cpspec->h1_val);
7434 clock_man(ppd, chan);
7435 set_man_mode_h1(ppd, chan, 0, 0);
7439 #define SJA_EN SYM_MASK(SPC_JTAG_ACCESS_REG, SPC_JTAG_ACCESS_EN)
7440 #define BISTEN_LSB SYM_LSB(SPC_JTAG_ACCESS_REG, bist_en)
7442 #define R_OPCODE_LSB 3
7444 #define R_OP_SHIFT 2
7445 #define R_OP_UPDATE 3
7450 static int qib_r_grab(struct qib_devdata *dd)
7454 qib_write_kreg(dd, kr_r_access, val);
7455 qib_read_kreg32(dd, kr_scratch);
7459 /* qib_r_wait_for_rdy() not only waits for the ready bit, it
7460 * returns the current state of R_TDO
7462 static int qib_r_wait_for_rdy(struct qib_devdata *dd)
7466 for (timeout = 0; timeout < 100 ; ++timeout) {
7467 val = qib_read_kreg32(dd, kr_r_access);
7469 return (val >> R_TDO_LSB) & 1;
7474 static int qib_r_shift(struct qib_devdata *dd, int bisten,
7475 int len, u8 *inp, u8 *outp)
7480 valbase = SJA_EN | (bisten << BISTEN_LSB) |
7481 (R_OP_SHIFT << R_OPCODE_LSB);
7482 ret = qib_r_wait_for_rdy(dd);
7485 for (pos = 0; pos < len; ++pos) {
7488 outp[pos >> 3] &= ~(1 << (pos & 7));
7489 outp[pos >> 3] |= (ret << (pos & 7));
7492 int tdi = inp[pos >> 3] >> (pos & 7);
7493 val |= ((tdi & 1) << R_TDI_LSB);
7495 qib_write_kreg(dd, kr_r_access, val);
7496 qib_read_kreg32(dd, kr_scratch);
7497 ret = qib_r_wait_for_rdy(dd);
7501 /* Restore to NOP between operations. */
7502 val = SJA_EN | (bisten << BISTEN_LSB);
7503 qib_write_kreg(dd, kr_r_access, val);
7504 qib_read_kreg32(dd, kr_scratch);
7505 ret = qib_r_wait_for_rdy(dd);
7513 static int qib_r_update(struct qib_devdata *dd, int bisten)
7518 val = SJA_EN | (bisten << BISTEN_LSB) | (R_OP_UPDATE << R_OPCODE_LSB);
7519 ret = qib_r_wait_for_rdy(dd);
7521 qib_write_kreg(dd, kr_r_access, val);
7522 qib_read_kreg32(dd, kr_scratch);
7527 #define BISTEN_PORT_SEL 15
7528 #define LEN_PORT_SEL 625
7529 #define BISTEN_AT 17
7531 #define BISTEN_ETM 16
7534 #define BIT2BYTE(x) (((x) + BITS_PER_BYTE - 1) / BITS_PER_BYTE)
7536 /* these are common for all IB port use cases. */
7537 static u8 reset_at[BIT2BYTE(LEN_AT)] = {
7538 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7539 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
7541 static u8 reset_atetm[BIT2BYTE(LEN_ETM)] = {
7542 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7543 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7544 0x00, 0x00, 0x00, 0x80, 0xe3, 0x81, 0x73, 0x3c, 0x70, 0x8e,
7545 0x07, 0xce, 0xf1, 0xc0, 0x39, 0x1e, 0x38, 0xc7, 0x03, 0xe7,
7546 0x78, 0xe0, 0x1c, 0x0f, 0x9c, 0x7f, 0x80, 0x73, 0x0f, 0x70,
7547 0xde, 0x01, 0xce, 0x39, 0xc0, 0xf9, 0x06, 0x38, 0xd7, 0x00,
7548 0xe7, 0x19, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7549 0x00, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00,
7551 static u8 at[BIT2BYTE(LEN_AT)] = {
7552 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00,
7553 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
7556 /* used for IB1 or IB2, only one in use */
7557 static u8 atetm_1port[BIT2BYTE(LEN_ETM)] = {
7558 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7559 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7560 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7561 0x00, 0x10, 0xf2, 0x80, 0x83, 0x1e, 0x38, 0x00, 0x00, 0x00,
7562 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7563 0x00, 0x00, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xc8, 0x03,
7564 0x07, 0x7b, 0xa0, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x18, 0x00,
7565 0x18, 0x00, 0x00, 0x00, 0x00, 0x4b, 0x00, 0x00, 0x00,
7568 /* used when both IB1 and IB2 are in use */
7569 static u8 atetm_2port[BIT2BYTE(LEN_ETM)] = {
7570 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7571 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x79,
7572 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7573 0x00, 0x00, 0xf8, 0x80, 0x83, 0x1e, 0x38, 0xe0, 0x03, 0x05,
7574 0x7b, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
7575 0xa2, 0x0f, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xd1, 0x07,
7576 0x02, 0x7c, 0x80, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x3e, 0x00,
7577 0x02, 0x00, 0x00, 0x00, 0x00, 0x64, 0x00, 0x00, 0x00,
7580 /* used when only IB1 is in use */
7581 static u8 portsel_port1[BIT2BYTE(LEN_PORT_SEL)] = {
7582 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13,
7583 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c,
7584 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7585 0x13, 0x78, 0x78, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7586 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32,
7587 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
7588 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
7589 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
7592 /* used when only IB2 is in use */
7593 static u8 portsel_port2[BIT2BYTE(LEN_PORT_SEL)] = {
7594 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x39, 0x39,
7595 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x73, 0x32, 0x32, 0x32,
7596 0x32, 0x32, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39,
7597 0x39, 0x78, 0x78, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39,
7598 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x74, 0x32,
7599 0x32, 0x32, 0x32, 0x32, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a,
7600 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a,
7601 0x3a, 0x3a, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01,
7604 /* used when both IB1 and IB2 are in use */
7605 static u8 portsel_2port[BIT2BYTE(LEN_PORT_SEL)] = {
7606 0x32, 0xba, 0x54, 0x76, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13,
7607 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c,
7608 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7609 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7610 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32,
7611 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x3a,
7612 0x3a, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
7613 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
7617 * Do setup to properly handle IB link recovery; if port is zero, we
7618 * are initializing to cover both ports; otherwise we are initializing
7619 * to cover a single port card, or the port has reached INIT and we may
7620 * need to switch coverage types.
7622 static void setup_7322_link_recovery(struct qib_pportdata *ppd, u32 both)
7625 struct qib_devdata *dd = ppd->dd;
7627 if (!ppd->dd->cspec->r1)
7630 dd->cspec->recovery_ports_initted++;
7631 ppd->cpspec->recovery_init = 1;
7633 if (!both && dd->cspec->recovery_ports_initted == 1) {
7634 portsel = ppd->port == 1 ? portsel_port1 : portsel_port2;
7637 portsel = portsel_2port;
7641 if (qib_r_grab(dd) < 0 ||
7642 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, reset_atetm, NULL) < 0 ||
7643 qib_r_update(dd, BISTEN_ETM) < 0 ||
7644 qib_r_shift(dd, BISTEN_AT, LEN_AT, reset_at, NULL) < 0 ||
7645 qib_r_update(dd, BISTEN_AT) < 0 ||
7646 qib_r_shift(dd, BISTEN_PORT_SEL, LEN_PORT_SEL,
7647 portsel, NULL) < 0 ||
7648 qib_r_update(dd, BISTEN_PORT_SEL) < 0 ||
7649 qib_r_shift(dd, BISTEN_AT, LEN_AT, at, NULL) < 0 ||
7650 qib_r_update(dd, BISTEN_AT) < 0 ||
7651 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, etm, NULL) < 0 ||
7652 qib_r_update(dd, BISTEN_ETM) < 0)
7653 qib_dev_err(dd, "Failed IB link recovery setup\n");
7656 static void check_7322_rxe_status(struct qib_pportdata *ppd)
7658 struct qib_devdata *dd = ppd->dd;
7661 if (dd->cspec->recovery_ports_initted != 1)
7662 return; /* rest doesn't apply to dualport */
7663 qib_write_kreg(dd, kr_control, dd->control |
7664 SYM_MASK(Control, FreezeMode));
7665 (void)qib_read_kreg64(dd, kr_scratch);
7666 udelay(3); /* ibcreset asserted 400ns, be sure that's over */
7667 fmask = qib_read_kreg64(dd, kr_act_fmask);
7670 * require a powercycle before we'll work again, and make
7671 * sure we get no more interrupts, and don't turn off
7674 ppd->dd->cspec->stay_in_freeze = 1;
7675 qib_7322_set_intr_state(ppd->dd, 0);
7676 qib_write_kreg(dd, kr_fmask, 0ULL);
7677 qib_dev_err(dd, "HCA unusable until powercycled\n");
7678 return; /* eventually reset */
7681 qib_write_kreg(ppd->dd, kr_hwerrclear,
7682 SYM_MASK(HwErrClear, IBSerdesPClkNotDetectClear_1));
7684 /* don't do the full clear_freeze(), not needed for this */
7685 qib_write_kreg(dd, kr_control, dd->control);
7686 qib_read_kreg32(dd, kr_scratch);
7687 /* take IBC out of reset */
7688 if (ppd->link_speed_supported) {
7689 ppd->cpspec->ibcctrl_a &=
7690 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
7691 qib_write_kreg_port(ppd, krp_ibcctrl_a,
7692 ppd->cpspec->ibcctrl_a);
7693 qib_read_kreg32(dd, kr_scratch);
7694 if (ppd->lflags & QIBL_IB_LINK_DISABLED)
7695 qib_set_ib_7322_lstate(ppd, 0,
7696 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);