2 * Copyright (c) 2012, 2013 Intel Corporation. All rights reserved.
3 * Copyright (c) 2006 - 2012 QLogic Corporation. All rights reserved.
4 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/pci.h>
36 #include <linux/poll.h>
37 #include <linux/cdev.h>
38 #include <linux/swap.h>
39 #include <linux/vmalloc.h>
40 #include <linux/highmem.h>
42 #include <linux/jiffies.h>
43 #include <asm/pgtable.h>
44 #include <linux/delay.h>
45 #include <linux/export.h>
46 #include <linux/uio.h>
51 #include "qib_common.h"
52 #include "qib_user_sdma.h"
55 #define pr_fmt(fmt) QIB_DRV_NAME ": " fmt
57 static int qib_open(struct inode *, struct file *);
58 static int qib_close(struct inode *, struct file *);
59 static ssize_t qib_write(struct file *, const char __user *, size_t, loff_t *);
60 static ssize_t qib_write_iter(struct kiocb *, struct iov_iter *);
61 static unsigned int qib_poll(struct file *, struct poll_table_struct *);
62 static int qib_mmapf(struct file *, struct vm_area_struct *);
65 * This is really, really weird shit - write() and writev() here
66 * have completely unrelated semantics. Sucky userland ABI,
69 static const struct file_operations qib_file_ops = {
72 .write_iter = qib_write_iter,
77 .llseek = noop_llseek,
81 * Convert kernel virtual addresses to physical addresses so they don't
82 * potentially conflict with the chip addresses used as mmap offsets.
83 * It doesn't really matter what mmap offset we use as long as we can
84 * interpret it correctly.
86 static u64 cvt_kvaddr(void *p)
91 page = vmalloc_to_page(p);
93 paddr = page_to_pfn(page) << PAGE_SHIFT;
98 static int qib_get_base_info(struct file *fp, void __user *ubase,
101 struct qib_ctxtdata *rcd = ctxt_fp(fp);
103 struct qib_base_info *kinfo = NULL;
104 struct qib_devdata *dd = rcd->dd;
105 struct qib_pportdata *ppd = rcd->ppd;
106 unsigned subctxt_cnt;
110 subctxt_cnt = rcd->subctxt_cnt;
117 master = !subctxt_fp(fp);
121 /* If context sharing is not requested, allow the old size structure */
123 sz -= 7 * sizeof(u64);
124 if (ubase_size < sz) {
129 kinfo = kzalloc(sizeof(*kinfo), GFP_KERNEL);
135 ret = dd->f_get_base_info(rcd, kinfo);
139 kinfo->spi_rcvhdr_cnt = dd->rcvhdrcnt;
140 kinfo->spi_rcvhdrent_size = dd->rcvhdrentsize;
141 kinfo->spi_tidegrcnt = rcd->rcvegrcnt;
142 kinfo->spi_rcv_egrbufsize = dd->rcvegrbufsize;
144 * have to mmap whole thing
146 kinfo->spi_rcv_egrbuftotlen =
147 rcd->rcvegrbuf_chunks * rcd->rcvegrbuf_size;
148 kinfo->spi_rcv_egrperchunk = rcd->rcvegrbufs_perchunk;
149 kinfo->spi_rcv_egrchunksize = kinfo->spi_rcv_egrbuftotlen /
150 rcd->rcvegrbuf_chunks;
151 kinfo->spi_tidcnt = dd->rcvtidcnt / subctxt_cnt;
153 kinfo->spi_tidcnt += dd->rcvtidcnt % subctxt_cnt;
155 * for this use, may be cfgctxts summed over all chips that
156 * are are configured and present
158 kinfo->spi_nctxts = dd->cfgctxts;
159 /* unit (chip/board) our context is on */
160 kinfo->spi_unit = dd->unit;
161 kinfo->spi_port = ppd->port;
162 /* for now, only a single page */
163 kinfo->spi_tid_maxsize = PAGE_SIZE;
166 * Doing this per context, and based on the skip value, etc. This has
167 * to be the actual buffer size, since the protocol code treats it
170 * These have to be set to user addresses in the user code via mmap.
171 * These values are used on return to user code for the mmap target
172 * addresses only. For 32 bit, same 44 bit address problem, so use
173 * the physical address, not virtual. Before 2.6.11, using the
174 * page_address() macro worked, but in 2.6.11, even that returns the
175 * full 64 bit address (upper bits all 1's). So far, using the
176 * physical addresses (or chip offsets, for chip mapping) works, but
177 * no doubt some future kernel release will change that, and we'll be
178 * on to yet another method of dealing with this.
179 * Normally only one of rcvhdr_tailaddr or rhf_offset is useful
180 * since the chips with non-zero rhf_offset don't normally
181 * enable tail register updates to host memory, but for testing,
182 * both can be enabled and used.
184 kinfo->spi_rcvhdr_base = (u64) rcd->rcvhdrq_phys;
185 kinfo->spi_rcvhdr_tailaddr = (u64) rcd->rcvhdrqtailaddr_phys;
186 kinfo->spi_rhf_offset = dd->rhf_offset;
187 kinfo->spi_rcv_egrbufs = (u64) rcd->rcvegr_phys;
188 kinfo->spi_pioavailaddr = (u64) dd->pioavailregs_phys;
189 /* setup per-unit (not port) status area for user programs */
190 kinfo->spi_status = (u64) kinfo->spi_pioavailaddr +
191 (char *) ppd->statusp -
192 (char *) dd->pioavailregs_dma;
193 kinfo->spi_uregbase = (u64) dd->uregbase + dd->ureg_align * rcd->ctxt;
195 kinfo->spi_piocnt = rcd->piocnt;
196 kinfo->spi_piobufbase = (u64) rcd->piobufs;
197 kinfo->spi_sendbuf_status = cvt_kvaddr(rcd->user_event_mask);
199 kinfo->spi_piocnt = (rcd->piocnt / subctxt_cnt) +
200 (rcd->piocnt % subctxt_cnt);
201 /* Master's PIO buffers are after all the slave's */
202 kinfo->spi_piobufbase = (u64) rcd->piobufs +
204 (rcd->piocnt - kinfo->spi_piocnt);
206 unsigned slave = subctxt_fp(fp) - 1;
208 kinfo->spi_piocnt = rcd->piocnt / subctxt_cnt;
209 kinfo->spi_piobufbase = (u64) rcd->piobufs +
210 dd->palign * kinfo->spi_piocnt * slave;
214 kinfo->spi_sendbuf_status =
215 cvt_kvaddr(&rcd->user_event_mask[subctxt_fp(fp)]);
216 /* only spi_subctxt_* fields should be set in this block! */
217 kinfo->spi_subctxt_uregbase = cvt_kvaddr(rcd->subctxt_uregbase);
219 kinfo->spi_subctxt_rcvegrbuf =
220 cvt_kvaddr(rcd->subctxt_rcvegrbuf);
221 kinfo->spi_subctxt_rcvhdr_base =
222 cvt_kvaddr(rcd->subctxt_rcvhdr_base);
226 * All user buffers are 2KB buffers. If we ever support
227 * giving 4KB buffers to user processes, this will need some
228 * work. Can't use piobufbase directly, because it has
229 * both 2K and 4K buffer base values.
231 kinfo->spi_pioindex = (kinfo->spi_piobufbase - dd->pio2k_bufbase) /
233 kinfo->spi_pioalign = dd->palign;
234 kinfo->spi_qpair = QIB_KD_QP;
236 * user mode PIO buffers are always 2KB, even when 4KB can
237 * be received, and sent via the kernel; this is ibmaxlen
240 kinfo->spi_piosize = dd->piosize2k - 2 * sizeof(u32);
241 kinfo->spi_mtu = ppd->ibmaxlen; /* maxlen, not ibmtu */
242 kinfo->spi_ctxt = rcd->ctxt;
243 kinfo->spi_subctxt = subctxt_fp(fp);
244 kinfo->spi_sw_version = QIB_KERN_SWVERSION;
245 kinfo->spi_sw_version |= 1U << 31; /* QLogic-built, not kernel.org */
246 kinfo->spi_hw_version = dd->revision;
249 kinfo->spi_runtime_flags |= QIB_RUNTIME_MASTER;
251 sz = (ubase_size < sizeof(*kinfo)) ? ubase_size : sizeof(*kinfo);
252 if (copy_to_user(ubase, kinfo, sz))
260 * qib_tid_update - update a context TID
262 * @fp: the qib device file
263 * @ti: the TID information
265 * The new implementation as of Oct 2004 is that the driver assigns
266 * the tid and returns it to the caller. To reduce search time, we
267 * keep a cursor for each context, walking the shadow tid array to find
268 * one that's not in use.
270 * For now, if we can't allocate the full list, we fail, although
271 * in the long run, we'll allocate as many as we can, and the
272 * caller will deal with that by trying the remaining pages later.
273 * That means that when we fail, we have to mark the tids as not in
274 * use again, in our shadow copy.
276 * It's up to the caller to free the tids when they are done.
277 * We'll unlock the pages as they free them.
279 * Also, right now we are locking one page at a time, but since
280 * the intended use of this routine is for a single group of
281 * virtually contiguous pages, that should change to improve
284 static int qib_tid_update(struct qib_ctxtdata *rcd, struct file *fp,
285 const struct qib_tid_info *ti)
288 u32 tid, ctxttid, cnt, i, tidcnt, tidoff;
290 struct qib_devdata *dd = rcd->dd;
293 u64 __iomem *tidbase;
294 unsigned long tidmap[8];
295 struct page **pagep = NULL;
296 unsigned subctxt = subctxt_fp(fp);
298 if (!dd->pageshadow) {
308 ctxttid = rcd->ctxt * dd->rcvtidcnt;
309 if (!rcd->subctxt_cnt) {
310 tidcnt = dd->rcvtidcnt;
311 tid = rcd->tidcursor;
313 } else if (!subctxt) {
314 tidcnt = (dd->rcvtidcnt / rcd->subctxt_cnt) +
315 (dd->rcvtidcnt % rcd->subctxt_cnt);
316 tidoff = dd->rcvtidcnt - tidcnt;
318 tid = tidcursor_fp(fp);
320 tidcnt = dd->rcvtidcnt / rcd->subctxt_cnt;
321 tidoff = tidcnt * (subctxt - 1);
323 tid = tidcursor_fp(fp);
326 /* make sure it all fits in tid_pg_list */
327 qib_devinfo(dd->pcidev,
328 "Process tried to allocate %u TIDs, only trying max (%u)\n",
332 pagep = (struct page **) rcd->tid_pg_list;
333 tidlist = (u16 *) &pagep[dd->rcvtidcnt];
337 memset(tidmap, 0, sizeof(tidmap));
338 /* before decrement; chip actual # */
340 tidbase = (u64 __iomem *) (((char __iomem *) dd->kregbase) +
342 ctxttid * sizeof(*tidbase));
344 /* virtual address of first page in transfer */
345 vaddr = ti->tidvaddr;
346 if (!access_ok(VERIFY_WRITE, (void __user *) vaddr,
351 ret = qib_get_user_pages(vaddr, cnt, pagep);
355 * We can't continue because the pagep array won't be
356 * initialized. This should never happen,
357 * unless perhaps the user has mpin'ed the pages
362 "Failed to lock addr %p, %u pages: errno %d\n",
363 (void *) vaddr, cnt, -ret);
366 for (i = 0; i < cnt; i++, vaddr += PAGE_SIZE) {
367 for (; ntids--; tid++) {
370 if (!dd->pageshadow[ctxttid + tid])
375 * Oops, wrapped all the way through their TIDs,
376 * and didn't have enough free; see comments at
379 i--; /* last tidlist[i] not filled in */
383 tidlist[i] = tid + tidoff;
384 /* we "know" system pages and TID pages are same size */
385 dd->pageshadow[ctxttid + tid] = pagep[i];
386 dd->physshadow[ctxttid + tid] =
387 qib_map_page(dd->pcidev, pagep[i], 0, PAGE_SIZE,
390 * don't need atomic or it's overhead
392 __set_bit(tid, tidmap);
393 physaddr = dd->physshadow[ctxttid + tid];
394 /* PERFORMANCE: below should almost certainly be cached */
395 dd->f_put_tid(dd, &tidbase[tid],
396 RCVHQ_RCV_TYPE_EXPECTED, physaddr);
398 * don't check this tid in qib_ctxtshadow, since we
399 * just filled it in; start with the next one.
407 /* jump here if copy out of updated info failed... */
408 /* same code that's in qib_free_tid() */
409 limit = sizeof(tidmap) * BITS_PER_BYTE;
411 /* just in case size changes in future */
413 tid = find_first_bit((const unsigned long *)tidmap, limit);
414 for (; tid < limit; tid++) {
415 if (!test_bit(tid, tidmap))
417 if (dd->pageshadow[ctxttid + tid]) {
420 phys = dd->physshadow[ctxttid + tid];
421 dd->physshadow[ctxttid + tid] = dd->tidinvalid;
422 /* PERFORMANCE: below should almost certainly
425 dd->f_put_tid(dd, &tidbase[tid],
426 RCVHQ_RCV_TYPE_EXPECTED,
428 pci_unmap_page(dd->pcidev, phys, PAGE_SIZE,
430 dd->pageshadow[ctxttid + tid] = NULL;
433 qib_release_user_pages(pagep, cnt);
436 * Copy the updated array, with qib_tid's filled in, back
437 * to user. Since we did the copy in already, this "should
438 * never fail" If it does, we have to clean up...
440 if (copy_to_user((void __user *)
441 (unsigned long) ti->tidlist,
442 tidlist, cnt * sizeof(*tidlist))) {
446 if (copy_to_user((void __user *) (unsigned long) ti->tidmap,
447 tidmap, sizeof(tidmap))) {
453 if (!rcd->subctxt_cnt)
454 rcd->tidcursor = tid;
456 tidcursor_fp(fp) = tid;
464 * qib_tid_free - free a context TID
466 * @subctxt: the subcontext
469 * right now we are unlocking one page at a time, but since
470 * the intended use of this routine is for a single group of
471 * virtually contiguous pages, that should change to improve
472 * performance. We check that the TID is in range for this context
473 * but otherwise don't check validity; if user has an error and
474 * frees the wrong tid, it's only their own data that can thereby
475 * be corrupted. We do check that the TID was in use, for sanity
476 * We always use our idea of the saved address, not the address that
477 * they pass in to us.
479 static int qib_tid_free(struct qib_ctxtdata *rcd, unsigned subctxt,
480 const struct qib_tid_info *ti)
483 u32 tid, ctxttid, cnt, limit, tidcnt;
484 struct qib_devdata *dd = rcd->dd;
485 u64 __iomem *tidbase;
486 unsigned long tidmap[8];
488 if (!dd->pageshadow) {
493 if (copy_from_user(tidmap, (void __user *)(unsigned long)ti->tidmap,
499 ctxttid = rcd->ctxt * dd->rcvtidcnt;
500 if (!rcd->subctxt_cnt)
501 tidcnt = dd->rcvtidcnt;
503 tidcnt = (dd->rcvtidcnt / rcd->subctxt_cnt) +
504 (dd->rcvtidcnt % rcd->subctxt_cnt);
505 ctxttid += dd->rcvtidcnt - tidcnt;
507 tidcnt = dd->rcvtidcnt / rcd->subctxt_cnt;
508 ctxttid += tidcnt * (subctxt - 1);
510 tidbase = (u64 __iomem *) ((char __iomem *)(dd->kregbase) +
512 ctxttid * sizeof(*tidbase));
514 limit = sizeof(tidmap) * BITS_PER_BYTE;
516 /* just in case size changes in future */
518 tid = find_first_bit(tidmap, limit);
519 for (cnt = 0; tid < limit; tid++) {
521 * small optimization; if we detect a run of 3 or so without
522 * any set, use find_first_bit again. That's mainly to
523 * accelerate the case where we wrapped, so we have some at
524 * the beginning, and some at the end, and a big gap
527 if (!test_bit(tid, tidmap))
530 if (dd->pageshadow[ctxttid + tid]) {
534 p = dd->pageshadow[ctxttid + tid];
535 dd->pageshadow[ctxttid + tid] = NULL;
536 phys = dd->physshadow[ctxttid + tid];
537 dd->physshadow[ctxttid + tid] = dd->tidinvalid;
538 /* PERFORMANCE: below should almost certainly be
541 dd->f_put_tid(dd, &tidbase[tid],
542 RCVHQ_RCV_TYPE_EXPECTED, dd->tidinvalid);
543 pci_unmap_page(dd->pcidev, phys, PAGE_SIZE,
545 qib_release_user_pages(&p, 1);
553 * qib_set_part_key - set a partition key
557 * We can have up to 4 active at a time (other than the default, which is
558 * always allowed). This is somewhat tricky, since multiple contexts may set
559 * the same key, so we reference count them, and clean up at exit. All 4
560 * partition keys are packed into a single qlogic_ib register. It's an
561 * error for a process to set the same pkey multiple times. We provide no
562 * mechanism to de-allocate a pkey at this time, we may eventually need to
563 * do that. I've used the atomic operations, and no locking, and only make
564 * a single pass through what's available. This should be more than
565 * adequate for some time. I'll think about spinlocks or the like if and as
568 static int qib_set_part_key(struct qib_ctxtdata *rcd, u16 key)
570 struct qib_pportdata *ppd = rcd->ppd;
571 int i, any = 0, pidx = -1;
572 u16 lkey = key & 0x7FFF;
575 if (lkey == (QIB_DEFAULT_P_KEY & 0x7FFF)) {
576 /* nothing to do; this key always valid */
587 * Set the full membership bit, because it has to be
588 * set in the register or the packet, and it seems
589 * cleaner to set in the register than to force all
594 for (i = 0; i < ARRAY_SIZE(rcd->pkeys); i++) {
595 if (!rcd->pkeys[i] && pidx == -1)
597 if (rcd->pkeys[i] == key) {
606 for (any = i = 0; i < ARRAY_SIZE(ppd->pkeys); i++) {
607 if (!ppd->pkeys[i]) {
611 if (ppd->pkeys[i] == key) {
612 atomic_t *pkrefs = &ppd->pkeyrefs[i];
614 if (atomic_inc_return(pkrefs) > 1) {
615 rcd->pkeys[pidx] = key;
620 * lost race, decrement count, catch below
626 if ((ppd->pkeys[i] & 0x7FFF) == lkey) {
628 * It makes no sense to have both the limited and
629 * full membership PKEY set at the same time since
630 * the unlimited one will disable the limited one.
640 for (any = i = 0; i < ARRAY_SIZE(ppd->pkeys); i++) {
641 if (!ppd->pkeys[i] &&
642 atomic_inc_return(&ppd->pkeyrefs[i]) == 1) {
643 rcd->pkeys[pidx] = key;
645 (void) ppd->dd->f_set_ib_cfg(ppd, QIB_IB_CFG_PKEYS, 0);
657 * qib_manage_rcvq - manage a context's receive queue
659 * @subctxt: the subcontext
660 * @start_stop: action to carry out
662 * start_stop == 0 disables receive on the context, for use in queue
663 * overflow conditions. start_stop==1 re-enables, to be used to
664 * re-init the software copy of the head register
666 static int qib_manage_rcvq(struct qib_ctxtdata *rcd, unsigned subctxt,
669 struct qib_devdata *dd = rcd->dd;
670 unsigned int rcvctrl_op;
674 /* atomically clear receive enable ctxt. */
677 * On enable, force in-memory copy of the tail register to
678 * 0, so that protocol code doesn't have to worry about
679 * whether or not the chip has yet updated the in-memory
680 * copy or not on return from the system call. The chip
681 * always resets it's tail register back to 0 on a
682 * transition from disabled to enabled.
684 if (rcd->rcvhdrtail_kvaddr)
685 qib_clear_rcvhdrtail(rcd);
686 rcvctrl_op = QIB_RCVCTRL_CTXT_ENB;
688 rcvctrl_op = QIB_RCVCTRL_CTXT_DIS;
689 dd->f_rcvctrl(rcd->ppd, rcvctrl_op, rcd->ctxt);
690 /* always; new head should be equal to new tail; see above */
695 static void qib_clean_part_key(struct qib_ctxtdata *rcd,
696 struct qib_devdata *dd)
698 int i, j, pchanged = 0;
700 struct qib_pportdata *ppd = rcd->ppd;
702 /* for debugging only */
703 oldpkey = (u64) ppd->pkeys[0] |
704 ((u64) ppd->pkeys[1] << 16) |
705 ((u64) ppd->pkeys[2] << 32) |
706 ((u64) ppd->pkeys[3] << 48);
708 for (i = 0; i < ARRAY_SIZE(rcd->pkeys); i++) {
711 for (j = 0; j < ARRAY_SIZE(ppd->pkeys); j++) {
712 /* check for match independent of the global bit */
713 if ((ppd->pkeys[j] & 0x7fff) !=
714 (rcd->pkeys[i] & 0x7fff))
716 if (atomic_dec_and_test(&ppd->pkeyrefs[j])) {
725 (void) ppd->dd->f_set_ib_cfg(ppd, QIB_IB_CFG_PKEYS, 0);
728 /* common code for the mappings on dma_alloc_coherent mem */
729 static int qib_mmap_mem(struct vm_area_struct *vma, struct qib_ctxtdata *rcd,
730 unsigned len, void *kvaddr, u32 write_ok, char *what)
732 struct qib_devdata *dd = rcd->dd;
736 if ((vma->vm_end - vma->vm_start) > len) {
737 qib_devinfo(dd->pcidev,
738 "FAIL on %s: len %lx > %x\n", what,
739 vma->vm_end - vma->vm_start, len);
745 * shared context user code requires rcvhdrq mapped r/w, others
746 * only allowed readonly mapping.
749 if (vma->vm_flags & VM_WRITE) {
750 qib_devinfo(dd->pcidev,
751 "%s must be mapped readonly\n", what);
756 /* don't allow them to later change with mprotect */
757 vma->vm_flags &= ~VM_MAYWRITE;
760 pfn = virt_to_phys(kvaddr) >> PAGE_SHIFT;
761 ret = remap_pfn_range(vma, vma->vm_start, pfn,
762 len, vma->vm_page_prot);
764 qib_devinfo(dd->pcidev,
765 "%s ctxt%u mmap of %lx, %x bytes failed: %d\n",
766 what, rcd->ctxt, pfn, len, ret);
771 static int mmap_ureg(struct vm_area_struct *vma, struct qib_devdata *dd,
779 * This is real hardware, so use io_remap. This is the mechanism
780 * for the user process to update the head registers for their ctxt
783 sz = dd->flags & QIB_HAS_HDRSUPP ? 2 * PAGE_SIZE : PAGE_SIZE;
784 if ((vma->vm_end - vma->vm_start) > sz) {
785 qib_devinfo(dd->pcidev,
786 "FAIL mmap userreg: reqlen %lx > PAGE\n",
787 vma->vm_end - vma->vm_start);
790 phys = dd->physaddr + ureg;
791 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
793 vma->vm_flags |= VM_DONTCOPY | VM_DONTEXPAND;
794 ret = io_remap_pfn_range(vma, vma->vm_start,
796 vma->vm_end - vma->vm_start,
802 static int mmap_piobufs(struct vm_area_struct *vma,
803 struct qib_devdata *dd,
804 struct qib_ctxtdata *rcd,
805 unsigned piobufs, unsigned piocnt)
811 * When we map the PIO buffers in the chip, we want to map them as
812 * writeonly, no read possible; unfortunately, x86 doesn't allow
813 * for this in hardware, but we still prevent users from asking
816 if ((vma->vm_end - vma->vm_start) > (piocnt * dd->palign)) {
817 qib_devinfo(dd->pcidev,
818 "FAIL mmap piobufs: reqlen %lx > PAGE\n",
819 vma->vm_end - vma->vm_start);
824 phys = dd->physaddr + piobufs;
826 #if defined(__powerpc__)
827 /* There isn't a generic way to specify writethrough mappings */
828 pgprot_val(vma->vm_page_prot) |= _PAGE_NO_CACHE;
829 pgprot_val(vma->vm_page_prot) |= _PAGE_WRITETHRU;
830 pgprot_val(vma->vm_page_prot) &= ~_PAGE_GUARDED;
834 * don't allow them to later change to readable with mprotect (for when
835 * not initially mapped readable, as is normally the case)
837 vma->vm_flags &= ~VM_MAYREAD;
838 vma->vm_flags |= VM_DONTCOPY | VM_DONTEXPAND;
840 /* We used PAT if wc_cookie == 0 */
842 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
844 ret = io_remap_pfn_range(vma, vma->vm_start, phys >> PAGE_SHIFT,
845 vma->vm_end - vma->vm_start,
851 static int mmap_rcvegrbufs(struct vm_area_struct *vma,
852 struct qib_ctxtdata *rcd)
854 struct qib_devdata *dd = rcd->dd;
855 unsigned long start, size;
856 size_t total_size, i;
860 size = rcd->rcvegrbuf_size;
861 total_size = rcd->rcvegrbuf_chunks * size;
862 if ((vma->vm_end - vma->vm_start) > total_size) {
863 qib_devinfo(dd->pcidev,
864 "FAIL on egr bufs: reqlen %lx > actual %lx\n",
865 vma->vm_end - vma->vm_start,
866 (unsigned long) total_size);
871 if (vma->vm_flags & VM_WRITE) {
872 qib_devinfo(dd->pcidev,
873 "Can't map eager buffers as writable (flags=%lx)\n",
878 /* don't allow them to later change to writeable with mprotect */
879 vma->vm_flags &= ~VM_MAYWRITE;
881 start = vma->vm_start;
883 for (i = 0; i < rcd->rcvegrbuf_chunks; i++, start += size) {
884 pfn = virt_to_phys(rcd->rcvegrbuf[i]) >> PAGE_SHIFT;
885 ret = remap_pfn_range(vma, start, pfn, size,
897 * qib_file_vma_fault - handle a VMA page fault.
899 static int qib_file_vma_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
903 page = vmalloc_to_page((void *)(vmf->pgoff << PAGE_SHIFT));
905 return VM_FAULT_SIGBUS;
913 static const struct vm_operations_struct qib_file_vm_ops = {
914 .fault = qib_file_vma_fault,
917 static int mmap_kvaddr(struct vm_area_struct *vma, u64 pgaddr,
918 struct qib_ctxtdata *rcd, unsigned subctxt)
920 struct qib_devdata *dd = rcd->dd;
921 unsigned subctxt_cnt;
927 subctxt_cnt = rcd->subctxt_cnt;
928 size = rcd->rcvegrbuf_chunks * rcd->rcvegrbuf_size;
931 * Each process has all the subctxt uregbase, rcvhdrq, and
932 * rcvegrbufs mmapped - as an array for all the processes,
933 * and also separately for this process.
935 if (pgaddr == cvt_kvaddr(rcd->subctxt_uregbase)) {
936 addr = rcd->subctxt_uregbase;
937 size = PAGE_SIZE * subctxt_cnt;
938 } else if (pgaddr == cvt_kvaddr(rcd->subctxt_rcvhdr_base)) {
939 addr = rcd->subctxt_rcvhdr_base;
940 size = rcd->rcvhdrq_size * subctxt_cnt;
941 } else if (pgaddr == cvt_kvaddr(rcd->subctxt_rcvegrbuf)) {
942 addr = rcd->subctxt_rcvegrbuf;
944 } else if (pgaddr == cvt_kvaddr(rcd->subctxt_uregbase +
945 PAGE_SIZE * subctxt)) {
946 addr = rcd->subctxt_uregbase + PAGE_SIZE * subctxt;
948 } else if (pgaddr == cvt_kvaddr(rcd->subctxt_rcvhdr_base +
949 rcd->rcvhdrq_size * subctxt)) {
950 addr = rcd->subctxt_rcvhdr_base +
951 rcd->rcvhdrq_size * subctxt;
952 size = rcd->rcvhdrq_size;
953 } else if (pgaddr == cvt_kvaddr(&rcd->user_event_mask[subctxt])) {
954 addr = rcd->user_event_mask;
956 } else if (pgaddr == cvt_kvaddr(rcd->subctxt_rcvegrbuf +
958 addr = rcd->subctxt_rcvegrbuf + size * subctxt;
959 /* rcvegrbufs are read-only on the slave */
960 if (vma->vm_flags & VM_WRITE) {
961 qib_devinfo(dd->pcidev,
962 "Can't map eager buffers as writable (flags=%lx)\n",
968 * Don't allow permission to later change to writeable
971 vma->vm_flags &= ~VM_MAYWRITE;
974 len = vma->vm_end - vma->vm_start;
980 vma->vm_pgoff = (unsigned long) addr >> PAGE_SHIFT;
981 vma->vm_ops = &qib_file_vm_ops;
982 vma->vm_flags |= VM_DONTEXPAND | VM_DONTDUMP;
990 * qib_mmapf - mmap various structures into user space
991 * @fp: the file pointer
994 * We use this to have a shared buffer between the kernel and the user code
995 * for the rcvhdr queue, egr buffers, and the per-context user regs and pio
996 * buffers in the chip. We have the open and close entries so we can bump
997 * the ref count and keep the driver from being unloaded while still mapped.
999 static int qib_mmapf(struct file *fp, struct vm_area_struct *vma)
1001 struct qib_ctxtdata *rcd;
1002 struct qib_devdata *dd;
1004 unsigned piobufs, piocnt;
1008 if (!rcd || !(vma->vm_flags & VM_SHARED)) {
1015 * This is the qib_do_user_init() code, mapping the shared buffers
1016 * and per-context user registers into the user process. The address
1017 * referred to by vm_pgoff is the file offset passed via mmap().
1018 * For shared contexts, this is the kernel vmalloc() address of the
1019 * pages to share with the master.
1020 * For non-shared or master ctxts, this is a physical address.
1021 * We only do one mmap for each space mapped.
1023 pgaddr = vma->vm_pgoff << PAGE_SHIFT;
1026 * Check for 0 in case one of the allocations failed, but user
1027 * called mmap anyway.
1035 * Physical addresses must fit in 40 bits for our hardware.
1036 * Check for kernel virtual addresses first, anything else must
1037 * match a HW or memory address.
1039 ret = mmap_kvaddr(vma, pgaddr, rcd, subctxt_fp(fp));
1046 ureg = dd->uregbase + dd->ureg_align * rcd->ctxt;
1047 if (!rcd->subctxt_cnt) {
1048 /* ctxt is not shared */
1049 piocnt = rcd->piocnt;
1050 piobufs = rcd->piobufs;
1051 } else if (!subctxt_fp(fp)) {
1052 /* caller is the master */
1053 piocnt = (rcd->piocnt / rcd->subctxt_cnt) +
1054 (rcd->piocnt % rcd->subctxt_cnt);
1055 piobufs = rcd->piobufs +
1056 dd->palign * (rcd->piocnt - piocnt);
1058 unsigned slave = subctxt_fp(fp) - 1;
1060 /* caller is a slave */
1061 piocnt = rcd->piocnt / rcd->subctxt_cnt;
1062 piobufs = rcd->piobufs + dd->palign * piocnt * slave;
1066 ret = mmap_ureg(vma, dd, ureg);
1067 else if (pgaddr == piobufs)
1068 ret = mmap_piobufs(vma, dd, rcd, piobufs, piocnt);
1069 else if (pgaddr == dd->pioavailregs_phys)
1070 /* in-memory copy of pioavail registers */
1071 ret = qib_mmap_mem(vma, rcd, PAGE_SIZE,
1072 (void *) dd->pioavailregs_dma, 0,
1073 "pioavail registers");
1074 else if (pgaddr == rcd->rcvegr_phys)
1075 ret = mmap_rcvegrbufs(vma, rcd);
1076 else if (pgaddr == (u64) rcd->rcvhdrq_phys)
1078 * The rcvhdrq itself; multiple pages, contiguous
1079 * from an i/o perspective. Shared contexts need
1080 * to map r/w, so we allow writing.
1082 ret = qib_mmap_mem(vma, rcd, rcd->rcvhdrq_size,
1083 rcd->rcvhdrq, 1, "rcvhdrq");
1084 else if (pgaddr == (u64) rcd->rcvhdrqtailaddr_phys)
1085 /* in-memory copy of rcvhdrq tail register */
1086 ret = qib_mmap_mem(vma, rcd, PAGE_SIZE,
1087 rcd->rcvhdrtail_kvaddr, 0,
1094 vma->vm_private_data = NULL;
1097 qib_devinfo(dd->pcidev,
1098 "mmap Failure %d: off %llx len %lx\n",
1099 -ret, (unsigned long long)pgaddr,
1100 vma->vm_end - vma->vm_start);
1105 static unsigned int qib_poll_urgent(struct qib_ctxtdata *rcd,
1107 struct poll_table_struct *pt)
1109 struct qib_devdata *dd = rcd->dd;
1112 poll_wait(fp, &rcd->wait, pt);
1114 spin_lock_irq(&dd->uctxt_lock);
1115 if (rcd->urgent != rcd->urgent_poll) {
1116 pollflag = POLLIN | POLLRDNORM;
1117 rcd->urgent_poll = rcd->urgent;
1120 set_bit(QIB_CTXT_WAITING_URG, &rcd->flag);
1122 spin_unlock_irq(&dd->uctxt_lock);
1127 static unsigned int qib_poll_next(struct qib_ctxtdata *rcd,
1129 struct poll_table_struct *pt)
1131 struct qib_devdata *dd = rcd->dd;
1134 poll_wait(fp, &rcd->wait, pt);
1136 spin_lock_irq(&dd->uctxt_lock);
1137 if (dd->f_hdrqempty(rcd)) {
1138 set_bit(QIB_CTXT_WAITING_RCV, &rcd->flag);
1139 dd->f_rcvctrl(rcd->ppd, QIB_RCVCTRL_INTRAVAIL_ENB, rcd->ctxt);
1142 pollflag = POLLIN | POLLRDNORM;
1143 spin_unlock_irq(&dd->uctxt_lock);
1148 static unsigned int qib_poll(struct file *fp, struct poll_table_struct *pt)
1150 struct qib_ctxtdata *rcd;
1156 else if (rcd->poll_type == QIB_POLL_TYPE_URGENT)
1157 pollflag = qib_poll_urgent(rcd, fp, pt);
1158 else if (rcd->poll_type == QIB_POLL_TYPE_ANYRCV)
1159 pollflag = qib_poll_next(rcd, fp, pt);
1166 static void assign_ctxt_affinity(struct file *fp, struct qib_devdata *dd)
1168 struct qib_filedata *fd = fp->private_data;
1169 const unsigned int weight = cpumask_weight(¤t->cpus_allowed);
1170 const struct cpumask *local_mask = cpumask_of_pcibus(dd->pcidev->bus);
1174 * If process has NOT already set it's affinity, select and
1175 * reserve a processor for it on the local NUMA node.
1177 if ((weight >= qib_cpulist_count) &&
1178 (cpumask_weight(local_mask) <= qib_cpulist_count)) {
1179 for_each_cpu(local_cpu, local_mask)
1180 if (!test_and_set_bit(local_cpu, qib_cpulist)) {
1181 fd->rec_cpu_num = local_cpu;
1187 * If process has NOT already set it's affinity, select and
1188 * reserve a processor for it, as a rendevous for all
1189 * users of the driver. If they don't actually later
1190 * set affinity to this cpu, or set it to some other cpu,
1191 * it just means that sooner or later we don't recommend
1192 * a cpu, and let the scheduler do it's best.
1194 if (weight >= qib_cpulist_count) {
1197 cpu = find_first_zero_bit(qib_cpulist,
1199 if (cpu == qib_cpulist_count)
1201 "no cpus avail for affinity PID %u\n",
1204 __set_bit(cpu, qib_cpulist);
1205 fd->rec_cpu_num = cpu;
1211 * Check that userland and driver are compatible for subcontexts.
1213 static int qib_compatible_subctxts(int user_swmajor, int user_swminor)
1215 /* this code is written long-hand for clarity */
1216 if (QIB_USER_SWMAJOR != user_swmajor) {
1217 /* no promise of compatibility if major mismatch */
1220 if (QIB_USER_SWMAJOR == 1) {
1221 switch (QIB_USER_SWMINOR) {
1225 /* no subctxt implementation so cannot be compatible */
1228 /* 3 is only compatible with itself */
1229 return user_swminor == 3;
1231 /* >= 4 are compatible (or are expected to be) */
1232 return user_swminor <= QIB_USER_SWMINOR;
1235 /* make no promises yet for future major versions */
1239 static int init_subctxts(struct qib_devdata *dd,
1240 struct qib_ctxtdata *rcd,
1241 const struct qib_user_info *uinfo)
1244 unsigned num_subctxts;
1248 * If the user is requesting zero subctxts,
1249 * skip the subctxt allocation.
1251 if (uinfo->spu_subctxt_cnt <= 0)
1253 num_subctxts = uinfo->spu_subctxt_cnt;
1255 /* Check for subctxt compatibility */
1256 if (!qib_compatible_subctxts(uinfo->spu_userversion >> 16,
1257 uinfo->spu_userversion & 0xffff)) {
1258 qib_devinfo(dd->pcidev,
1259 "Mismatched user version (%d.%d) and driver version (%d.%d) while context sharing. Ensure that driver and library are from the same release.\n",
1260 (int) (uinfo->spu_userversion >> 16),
1261 (int) (uinfo->spu_userversion & 0xffff),
1262 QIB_USER_SWMAJOR, QIB_USER_SWMINOR);
1265 if (num_subctxts > QLOGIC_IB_MAX_SUBCTXT) {
1270 rcd->subctxt_uregbase = vmalloc_user(PAGE_SIZE * num_subctxts);
1271 if (!rcd->subctxt_uregbase) {
1275 /* Note: rcd->rcvhdrq_size isn't initialized yet. */
1276 size = ALIGN(dd->rcvhdrcnt * dd->rcvhdrentsize *
1277 sizeof(u32), PAGE_SIZE) * num_subctxts;
1278 rcd->subctxt_rcvhdr_base = vmalloc_user(size);
1279 if (!rcd->subctxt_rcvhdr_base) {
1284 rcd->subctxt_rcvegrbuf = vmalloc_user(rcd->rcvegrbuf_chunks *
1285 rcd->rcvegrbuf_size *
1287 if (!rcd->subctxt_rcvegrbuf) {
1292 rcd->subctxt_cnt = uinfo->spu_subctxt_cnt;
1293 rcd->subctxt_id = uinfo->spu_subctxt_id;
1294 rcd->active_slaves = 1;
1295 rcd->redirect_seq_cnt = 1;
1296 set_bit(QIB_CTXT_MASTER_UNINIT, &rcd->flag);
1300 vfree(rcd->subctxt_rcvhdr_base);
1302 vfree(rcd->subctxt_uregbase);
1303 rcd->subctxt_uregbase = NULL;
1308 static int setup_ctxt(struct qib_pportdata *ppd, int ctxt,
1309 struct file *fp, const struct qib_user_info *uinfo)
1311 struct qib_filedata *fd = fp->private_data;
1312 struct qib_devdata *dd = ppd->dd;
1313 struct qib_ctxtdata *rcd;
1318 assign_ctxt_affinity(fp, dd);
1320 numa_id = qib_numa_aware ? ((fd->rec_cpu_num != -1) ?
1321 cpu_to_node(fd->rec_cpu_num) :
1322 numa_node_id()) : dd->assigned_node_id;
1324 rcd = qib_create_ctxtdata(ppd, ctxt, numa_id);
1327 * Allocate memory for use in qib_tid_update() at open to
1328 * reduce cost of expected send setup per message segment
1331 ptmp = kmalloc(dd->rcvtidcnt * sizeof(u16) +
1332 dd->rcvtidcnt * sizeof(struct page **),
1335 if (!rcd || !ptmp) {
1337 "Unable to allocate ctxtdata memory, failing open\n");
1341 rcd->userversion = uinfo->spu_userversion;
1342 ret = init_subctxts(dd, rcd, uinfo);
1345 rcd->tid_pg_list = ptmp;
1346 rcd->pid = current->pid;
1347 init_waitqueue_head(&dd->rcd[ctxt]->wait);
1348 strlcpy(rcd->comm, current->comm, sizeof(rcd->comm));
1350 qib_stats.sps_ctxts++;
1356 if (fd->rec_cpu_num != -1)
1357 __clear_bit(fd->rec_cpu_num, qib_cpulist);
1359 dd->rcd[ctxt] = NULL;
1366 static inline int usable(struct qib_pportdata *ppd)
1368 struct qib_devdata *dd = ppd->dd;
1370 return dd && (dd->flags & QIB_PRESENT) && dd->kregbase && ppd->lid &&
1371 (ppd->lflags & QIBL_LINKACTIVE);
1375 * Select a context on the given device, either using a requested port
1376 * or the port based on the context number.
1378 static int choose_port_ctxt(struct file *fp, struct qib_devdata *dd, u32 port,
1379 const struct qib_user_info *uinfo)
1381 struct qib_pportdata *ppd = NULL;
1385 if (!usable(dd->pport + port - 1)) {
1389 ppd = dd->pport + port - 1;
1391 for (ctxt = dd->first_user_ctxt; ctxt < dd->cfgctxts && dd->rcd[ctxt];
1394 if (ctxt == dd->cfgctxts) {
1399 u32 pidx = ctxt % dd->num_pports;
1401 if (usable(dd->pport + pidx))
1402 ppd = dd->pport + pidx;
1404 for (pidx = 0; pidx < dd->num_pports && !ppd;
1406 if (usable(dd->pport + pidx))
1407 ppd = dd->pport + pidx;
1410 ret = ppd ? setup_ctxt(ppd, ctxt, fp, uinfo) : -ENETDOWN;
1415 static int find_free_ctxt(int unit, struct file *fp,
1416 const struct qib_user_info *uinfo)
1418 struct qib_devdata *dd = qib_lookup(unit);
1421 if (!dd || (uinfo->spu_port && uinfo->spu_port > dd->num_pports))
1424 ret = choose_port_ctxt(fp, dd, uinfo->spu_port, uinfo);
1429 static int get_a_ctxt(struct file *fp, const struct qib_user_info *uinfo,
1432 struct qib_devdata *udd = NULL;
1433 int ret = 0, devmax, npresent, nup, ndev, dusable = 0, i;
1434 u32 port = uinfo->spu_port, ctxt;
1436 devmax = qib_count_units(&npresent, &nup);
1446 if (alg == QIB_PORT_ALG_ACROSS) {
1447 unsigned inuse = ~0U;
1449 /* find device (with ACTIVE ports) with fewest ctxts in use */
1450 for (ndev = 0; ndev < devmax; ndev++) {
1451 struct qib_devdata *dd = qib_lookup(ndev);
1452 unsigned cused = 0, cfree = 0, pusable = 0;
1456 if (port && port <= dd->num_pports &&
1457 usable(dd->pport + port - 1))
1460 for (i = 0; i < dd->num_pports; i++)
1461 if (usable(dd->pport + i))
1465 for (ctxt = dd->first_user_ctxt; ctxt < dd->cfgctxts;
1471 if (cfree && cused < inuse) {
1477 ret = choose_port_ctxt(fp, udd, port, uinfo);
1481 for (ndev = 0; ndev < devmax; ndev++) {
1482 struct qib_devdata *dd = qib_lookup(ndev);
1485 ret = choose_port_ctxt(fp, dd, port, uinfo);
1493 ret = dusable ? -EBUSY : -ENETDOWN;
1499 static int find_shared_ctxt(struct file *fp,
1500 const struct qib_user_info *uinfo)
1502 int devmax, ndev, i;
1505 devmax = qib_count_units(NULL, NULL);
1507 for (ndev = 0; ndev < devmax; ndev++) {
1508 struct qib_devdata *dd = qib_lookup(ndev);
1510 /* device portion of usable() */
1511 if (!(dd && (dd->flags & QIB_PRESENT) && dd->kregbase))
1513 for (i = dd->first_user_ctxt; i < dd->cfgctxts; i++) {
1514 struct qib_ctxtdata *rcd = dd->rcd[i];
1516 /* Skip ctxts which are not yet open */
1517 if (!rcd || !rcd->cnt)
1519 /* Skip ctxt if it doesn't match the requested one */
1520 if (rcd->subctxt_id != uinfo->spu_subctxt_id)
1522 /* Verify the sharing process matches the master */
1523 if (rcd->subctxt_cnt != uinfo->spu_subctxt_cnt ||
1524 rcd->userversion != uinfo->spu_userversion ||
1525 rcd->cnt >= rcd->subctxt_cnt) {
1530 subctxt_fp(fp) = rcd->cnt++;
1531 rcd->subpid[subctxt_fp(fp)] = current->pid;
1532 tidcursor_fp(fp) = 0;
1533 rcd->active_slaves |= 1 << subctxt_fp(fp);
1543 static int qib_open(struct inode *in, struct file *fp)
1545 /* The real work is performed later in qib_assign_ctxt() */
1546 fp->private_data = kzalloc(sizeof(struct qib_filedata), GFP_KERNEL);
1547 if (fp->private_data) /* no cpu affinity by default */
1548 ((struct qib_filedata *)fp->private_data)->rec_cpu_num = -1;
1549 return fp->private_data ? 0 : -ENOMEM;
1552 static int find_hca(unsigned int cpu, int *unit)
1554 int ret = 0, devmax, npresent, nup, ndev;
1558 devmax = qib_count_units(&npresent, &nup);
1567 for (ndev = 0; ndev < devmax; ndev++) {
1568 struct qib_devdata *dd = qib_lookup(ndev);
1571 if (pcibus_to_node(dd->pcidev->bus) < 0) {
1575 if (cpu_to_node(cpu) ==
1576 pcibus_to_node(dd->pcidev->bus)) {
1586 static int do_qib_user_sdma_queue_create(struct file *fp)
1588 struct qib_filedata *fd = fp->private_data;
1589 struct qib_ctxtdata *rcd = fd->rcd;
1590 struct qib_devdata *dd = rcd->dd;
1592 if (dd->flags & QIB_HAS_SEND_DMA) {
1594 fd->pq = qib_user_sdma_queue_create(&dd->pcidev->dev,
1606 * Get ctxt early, so can set affinity prior to memory allocation.
1608 static int qib_assign_ctxt(struct file *fp, const struct qib_user_info *uinfo)
1612 unsigned swmajor, swminor, alg = QIB_PORT_ALG_ACROSS;
1614 /* Check to be sure we haven't already initialized this file */
1620 /* for now, if major version is different, bail */
1621 swmajor = uinfo->spu_userversion >> 16;
1622 if (swmajor != QIB_USER_SWMAJOR) {
1627 swminor = uinfo->spu_userversion & 0xffff;
1629 if (swminor >= 11 && uinfo->spu_port_alg < QIB_PORT_ALG_COUNT)
1630 alg = uinfo->spu_port_alg;
1632 mutex_lock(&qib_mutex);
1634 if (qib_compatible_subctxts(swmajor, swminor) &&
1635 uinfo->spu_subctxt_cnt) {
1636 ret = find_shared_ctxt(fp, uinfo);
1638 ret = do_qib_user_sdma_queue_create(fp);
1640 assign_ctxt_affinity(fp, (ctxt_fp(fp))->dd);
1645 i_minor = iminor(file_inode(fp)) - QIB_USER_MINOR_BASE;
1647 ret = find_free_ctxt(i_minor - 1, fp, uinfo);
1650 const unsigned int cpu = cpumask_first(¤t->cpus_allowed);
1651 const unsigned int weight =
1652 cpumask_weight(¤t->cpus_allowed);
1654 if (weight == 1 && !test_bit(cpu, qib_cpulist))
1655 if (!find_hca(cpu, &unit) && unit >= 0)
1656 if (!find_free_ctxt(unit, fp, uinfo)) {
1660 ret = get_a_ctxt(fp, uinfo, alg);
1665 ret = do_qib_user_sdma_queue_create(fp);
1667 mutex_unlock(&qib_mutex);
1674 static int qib_do_user_init(struct file *fp,
1675 const struct qib_user_info *uinfo)
1678 struct qib_ctxtdata *rcd = ctxt_fp(fp);
1679 struct qib_devdata *dd;
1682 /* Subctxts don't need to initialize anything since master did it. */
1683 if (subctxt_fp(fp)) {
1684 ret = wait_event_interruptible(rcd->wait,
1685 !test_bit(QIB_CTXT_MASTER_UNINIT, &rcd->flag));
1691 /* some ctxts may get extra buffers, calculate that here */
1692 uctxt = rcd->ctxt - dd->first_user_ctxt;
1693 if (uctxt < dd->ctxts_extrabuf) {
1694 rcd->piocnt = dd->pbufsctxt + 1;
1695 rcd->pio_base = rcd->piocnt * uctxt;
1697 rcd->piocnt = dd->pbufsctxt;
1698 rcd->pio_base = rcd->piocnt * uctxt +
1703 * All user buffers are 2KB buffers. If we ever support
1704 * giving 4KB buffers to user processes, this will need some
1705 * work. Can't use piobufbase directly, because it has
1706 * both 2K and 4K buffer base values. So check and handle.
1708 if ((rcd->pio_base + rcd->piocnt) > dd->piobcnt2k) {
1709 if (rcd->pio_base >= dd->piobcnt2k) {
1711 "%u:ctxt%u: no 2KB buffers available\n",
1712 dd->unit, rcd->ctxt);
1716 rcd->piocnt = dd->piobcnt2k - rcd->pio_base;
1717 qib_dev_err(dd, "Ctxt%u: would use 4KB bufs, using %u\n",
1718 rcd->ctxt, rcd->piocnt);
1721 rcd->piobufs = dd->pio2k_bufbase + rcd->pio_base * dd->palign;
1722 qib_chg_pioavailkernel(dd, rcd->pio_base, rcd->piocnt,
1723 TXCHK_CHG_TYPE_USER, rcd);
1725 * try to ensure that processes start up with consistent avail update
1726 * for their own range, at least. If system very quiet, it might
1727 * have the in-memory copy out of date at startup for this range of
1728 * buffers, when a context gets re-used. Do after the chg_pioavail
1729 * and before the rest of setup, so it's "almost certain" the dma
1730 * will have occurred (can't 100% guarantee, but should be many
1731 * decimals of 9s, with this ordering), given how much else happens
1734 dd->f_sendctrl(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
1737 * Now allocate the rcvhdr Q and eager TIDs; skip the TID
1738 * array for time being. If rcd->ctxt > chip-supported,
1739 * we need to do extra stuff here to handle by handling overflow
1740 * through ctxt 0, someday
1742 ret = qib_create_rcvhdrq(dd, rcd);
1744 ret = qib_setup_eagerbufs(rcd);
1748 rcd->tidcursor = 0; /* start at beginning after open */
1750 /* initialize poll variables... */
1752 rcd->urgent_poll = 0;
1755 * Now enable the ctxt for receive.
1756 * For chips that are set to DMA the tail register to memory
1757 * when they change (and when the update bit transitions from
1758 * 0 to 1. So for those chips, we turn it off and then back on.
1759 * This will (very briefly) affect any other open ctxts, but the
1760 * duration is very short, and therefore isn't an issue. We
1761 * explicitly set the in-memory tail copy to 0 beforehand, so we
1762 * don't have to wait to be sure the DMA update has happened
1763 * (chip resets head/tail to 0 on transition to enable).
1765 if (rcd->rcvhdrtail_kvaddr)
1766 qib_clear_rcvhdrtail(rcd);
1768 dd->f_rcvctrl(rcd->ppd, QIB_RCVCTRL_CTXT_ENB | QIB_RCVCTRL_TIDFLOW_ENB,
1771 /* Notify any waiting slaves */
1772 if (rcd->subctxt_cnt) {
1773 clear_bit(QIB_CTXT_MASTER_UNINIT, &rcd->flag);
1774 wake_up(&rcd->wait);
1779 qib_chg_pioavailkernel(dd, rcd->pio_base, rcd->piocnt,
1780 TXCHK_CHG_TYPE_KERN, rcd);
1786 * unlock_exptid - unlock any expected TID entries context still had in use
1789 * We don't actually update the chip here, because we do a bulk update
1790 * below, using f_clear_tids.
1792 static void unlock_expected_tids(struct qib_ctxtdata *rcd)
1794 struct qib_devdata *dd = rcd->dd;
1795 int ctxt_tidbase = rcd->ctxt * dd->rcvtidcnt;
1796 int i, cnt = 0, maxtid = ctxt_tidbase + dd->rcvtidcnt;
1798 for (i = ctxt_tidbase; i < maxtid; i++) {
1799 struct page *p = dd->pageshadow[i];
1805 phys = dd->physshadow[i];
1806 dd->physshadow[i] = dd->tidinvalid;
1807 dd->pageshadow[i] = NULL;
1808 pci_unmap_page(dd->pcidev, phys, PAGE_SIZE,
1809 PCI_DMA_FROMDEVICE);
1810 qib_release_user_pages(&p, 1);
1815 static int qib_close(struct inode *in, struct file *fp)
1818 struct qib_filedata *fd;
1819 struct qib_ctxtdata *rcd;
1820 struct qib_devdata *dd;
1821 unsigned long flags;
1825 mutex_lock(&qib_mutex);
1827 fd = fp->private_data;
1828 fp->private_data = NULL;
1831 mutex_unlock(&qib_mutex);
1837 /* ensure all pio buffer writes in progress are flushed */
1840 /* drain user sdma queue */
1842 qib_user_sdma_queue_drain(rcd->ppd, fd->pq);
1843 qib_user_sdma_queue_destroy(fd->pq);
1846 if (fd->rec_cpu_num != -1)
1847 __clear_bit(fd->rec_cpu_num, qib_cpulist);
1851 * XXX If the master closes the context before the slave(s),
1852 * revoke the mmap for the eager receive queue so
1853 * the slave(s) don't wait for receive data forever.
1855 rcd->active_slaves &= ~(1 << fd->subctxt);
1856 rcd->subpid[fd->subctxt] = 0;
1857 mutex_unlock(&qib_mutex);
1861 /* early; no interrupt users after this */
1862 spin_lock_irqsave(&dd->uctxt_lock, flags);
1864 dd->rcd[ctxt] = NULL;
1867 spin_unlock_irqrestore(&dd->uctxt_lock, flags);
1869 if (rcd->rcvwait_to || rcd->piowait_to ||
1870 rcd->rcvnowait || rcd->pionowait) {
1871 rcd->rcvwait_to = 0;
1872 rcd->piowait_to = 0;
1880 /* atomically clear receive enable ctxt and intr avail. */
1881 dd->f_rcvctrl(rcd->ppd, QIB_RCVCTRL_CTXT_DIS |
1882 QIB_RCVCTRL_INTRAVAIL_DIS, ctxt);
1884 /* clean up the pkeys for this ctxt user */
1885 qib_clean_part_key(rcd, dd);
1886 qib_disarm_piobufs(dd, rcd->pio_base, rcd->piocnt);
1887 qib_chg_pioavailkernel(dd, rcd->pio_base,
1888 rcd->piocnt, TXCHK_CHG_TYPE_KERN, NULL);
1890 dd->f_clear_tids(dd, rcd);
1893 unlock_expected_tids(rcd);
1894 qib_stats.sps_ctxts--;
1898 mutex_unlock(&qib_mutex);
1899 qib_free_ctxtdata(dd, rcd); /* after releasing the mutex */
1906 static int qib_ctxt_info(struct file *fp, struct qib_ctxt_info __user *uinfo)
1908 struct qib_ctxt_info info;
1911 struct qib_ctxtdata *rcd = ctxt_fp(fp);
1912 struct qib_filedata *fd;
1914 fd = fp->private_data;
1916 info.num_active = qib_count_active_units();
1917 info.unit = rcd->dd->unit;
1918 info.port = rcd->ppd->port;
1919 info.ctxt = rcd->ctxt;
1920 info.subctxt = subctxt_fp(fp);
1921 /* Number of user ctxts available for this device. */
1922 info.num_ctxts = rcd->dd->cfgctxts - rcd->dd->first_user_ctxt;
1923 info.num_subctxts = rcd->subctxt_cnt;
1924 info.rec_cpu = fd->rec_cpu_num;
1927 if (copy_to_user(uinfo, &info, sz)) {
1937 static int qib_sdma_get_inflight(struct qib_user_sdma_queue *pq,
1938 u32 __user *inflightp)
1940 const u32 val = qib_user_sdma_inflight_counter(pq);
1942 if (put_user(val, inflightp))
1948 static int qib_sdma_get_complete(struct qib_pportdata *ppd,
1949 struct qib_user_sdma_queue *pq,
1950 u32 __user *completep)
1958 err = qib_user_sdma_make_progress(ppd, pq);
1962 val = qib_user_sdma_complete_counter(pq);
1963 if (put_user(val, completep))
1969 static int disarm_req_delay(struct qib_ctxtdata *rcd)
1973 if (!usable(rcd->ppd)) {
1976 * if link is down, or otherwise not usable, delay
1977 * the caller up to 30 seconds, so we don't thrash
1978 * in trying to get the chip back to ACTIVE, and
1979 * set flag so they make the call again.
1981 if (rcd->user_event_mask) {
1983 * subctxt_cnt is 0 if not shared, so do base
1984 * separately, first, then remaining subctxt, if any
1986 set_bit(_QIB_EVENT_DISARM_BUFS_BIT,
1987 &rcd->user_event_mask[0]);
1988 for (i = 1; i < rcd->subctxt_cnt; i++)
1989 set_bit(_QIB_EVENT_DISARM_BUFS_BIT,
1990 &rcd->user_event_mask[i]);
1992 for (i = 0; !usable(rcd->ppd) && i < 300; i++)
2000 * Find all user contexts in use, and set the specified bit in their
2002 * See also find_ctxt() for a similar use, that is specific to send buffers.
2004 int qib_set_uevent_bits(struct qib_pportdata *ppd, const int evtbit)
2006 struct qib_ctxtdata *rcd;
2009 unsigned long flags;
2011 spin_lock_irqsave(&ppd->dd->uctxt_lock, flags);
2012 for (ctxt = ppd->dd->first_user_ctxt; ctxt < ppd->dd->cfgctxts;
2014 rcd = ppd->dd->rcd[ctxt];
2017 if (rcd->user_event_mask) {
2020 * subctxt_cnt is 0 if not shared, so do base
2021 * separately, first, then remaining subctxt, if any
2023 set_bit(evtbit, &rcd->user_event_mask[0]);
2024 for (i = 1; i < rcd->subctxt_cnt; i++)
2025 set_bit(evtbit, &rcd->user_event_mask[i]);
2030 spin_unlock_irqrestore(&ppd->dd->uctxt_lock, flags);
2036 * clear the event notifier events for this context.
2037 * For the DISARM_BUFS case, we also take action (this obsoletes
2038 * the older QIB_CMD_DISARM_BUFS, but we keep it for backwards
2040 * Other bits don't currently require actions, just atomically clear.
2041 * User process then performs actions appropriate to bit having been
2042 * set, if desired, and checks again in future.
2044 static int qib_user_event_ack(struct qib_ctxtdata *rcd, int subctxt,
2045 unsigned long events)
2049 for (i = 0; i <= _QIB_MAX_EVENT_BIT; i++) {
2050 if (!test_bit(i, &events))
2052 if (i == _QIB_EVENT_DISARM_BUFS_BIT) {
2053 (void)qib_disarm_piobufs_ifneeded(rcd);
2054 ret = disarm_req_delay(rcd);
2056 clear_bit(i, &rcd->user_event_mask[subctxt]);
2061 static ssize_t qib_write(struct file *fp, const char __user *data,
2062 size_t count, loff_t *off)
2064 const struct qib_cmd __user *ucmd;
2065 struct qib_ctxtdata *rcd;
2066 const void __user *src;
2067 size_t consumed, copy = 0;
2072 if (WARN_ON_ONCE(!ib_safe_file_access(fp)))
2075 if (count < sizeof(cmd.type)) {
2080 ucmd = (const struct qib_cmd __user *) data;
2082 if (copy_from_user(&cmd.type, &ucmd->type, sizeof(cmd.type))) {
2087 consumed = sizeof(cmd.type);
2090 case QIB_CMD_ASSIGN_CTXT:
2091 case QIB_CMD_USER_INIT:
2092 copy = sizeof(cmd.cmd.user_info);
2093 dest = &cmd.cmd.user_info;
2094 src = &ucmd->cmd.user_info;
2097 case QIB_CMD_RECV_CTRL:
2098 copy = sizeof(cmd.cmd.recv_ctrl);
2099 dest = &cmd.cmd.recv_ctrl;
2100 src = &ucmd->cmd.recv_ctrl;
2103 case QIB_CMD_CTXT_INFO:
2104 copy = sizeof(cmd.cmd.ctxt_info);
2105 dest = &cmd.cmd.ctxt_info;
2106 src = &ucmd->cmd.ctxt_info;
2109 case QIB_CMD_TID_UPDATE:
2110 case QIB_CMD_TID_FREE:
2111 copy = sizeof(cmd.cmd.tid_info);
2112 dest = &cmd.cmd.tid_info;
2113 src = &ucmd->cmd.tid_info;
2116 case QIB_CMD_SET_PART_KEY:
2117 copy = sizeof(cmd.cmd.part_key);
2118 dest = &cmd.cmd.part_key;
2119 src = &ucmd->cmd.part_key;
2122 case QIB_CMD_DISARM_BUFS:
2123 case QIB_CMD_PIOAVAILUPD: /* force an update of PIOAvail reg */
2129 case QIB_CMD_POLL_TYPE:
2130 copy = sizeof(cmd.cmd.poll_type);
2131 dest = &cmd.cmd.poll_type;
2132 src = &ucmd->cmd.poll_type;
2135 case QIB_CMD_ARMLAUNCH_CTRL:
2136 copy = sizeof(cmd.cmd.armlaunch_ctrl);
2137 dest = &cmd.cmd.armlaunch_ctrl;
2138 src = &ucmd->cmd.armlaunch_ctrl;
2141 case QIB_CMD_SDMA_INFLIGHT:
2142 copy = sizeof(cmd.cmd.sdma_inflight);
2143 dest = &cmd.cmd.sdma_inflight;
2144 src = &ucmd->cmd.sdma_inflight;
2147 case QIB_CMD_SDMA_COMPLETE:
2148 copy = sizeof(cmd.cmd.sdma_complete);
2149 dest = &cmd.cmd.sdma_complete;
2150 src = &ucmd->cmd.sdma_complete;
2153 case QIB_CMD_ACK_EVENT:
2154 copy = sizeof(cmd.cmd.event_mask);
2155 dest = &cmd.cmd.event_mask;
2156 src = &ucmd->cmd.event_mask;
2165 if ((count - consumed) < copy) {
2169 if (copy_from_user(dest, src, copy)) {
2177 if (!rcd && cmd.type != QIB_CMD_ASSIGN_CTXT) {
2183 case QIB_CMD_ASSIGN_CTXT:
2184 ret = qib_assign_ctxt(fp, &cmd.cmd.user_info);
2189 case QIB_CMD_USER_INIT:
2190 ret = qib_do_user_init(fp, &cmd.cmd.user_info);
2193 ret = qib_get_base_info(fp, (void __user *) (unsigned long)
2194 cmd.cmd.user_info.spu_base_info,
2195 cmd.cmd.user_info.spu_base_info_size);
2198 case QIB_CMD_RECV_CTRL:
2199 ret = qib_manage_rcvq(rcd, subctxt_fp(fp), cmd.cmd.recv_ctrl);
2202 case QIB_CMD_CTXT_INFO:
2203 ret = qib_ctxt_info(fp, (struct qib_ctxt_info __user *)
2204 (unsigned long) cmd.cmd.ctxt_info);
2207 case QIB_CMD_TID_UPDATE:
2208 ret = qib_tid_update(rcd, fp, &cmd.cmd.tid_info);
2211 case QIB_CMD_TID_FREE:
2212 ret = qib_tid_free(rcd, subctxt_fp(fp), &cmd.cmd.tid_info);
2215 case QIB_CMD_SET_PART_KEY:
2216 ret = qib_set_part_key(rcd, cmd.cmd.part_key);
2219 case QIB_CMD_DISARM_BUFS:
2220 (void)qib_disarm_piobufs_ifneeded(rcd);
2221 ret = disarm_req_delay(rcd);
2224 case QIB_CMD_PIOAVAILUPD:
2225 qib_force_pio_avail_update(rcd->dd);
2228 case QIB_CMD_POLL_TYPE:
2229 rcd->poll_type = cmd.cmd.poll_type;
2232 case QIB_CMD_ARMLAUNCH_CTRL:
2233 rcd->dd->f_set_armlaunch(rcd->dd, cmd.cmd.armlaunch_ctrl);
2236 case QIB_CMD_SDMA_INFLIGHT:
2237 ret = qib_sdma_get_inflight(user_sdma_queue_fp(fp),
2238 (u32 __user *) (unsigned long)
2239 cmd.cmd.sdma_inflight);
2242 case QIB_CMD_SDMA_COMPLETE:
2243 ret = qib_sdma_get_complete(rcd->ppd,
2244 user_sdma_queue_fp(fp),
2245 (u32 __user *) (unsigned long)
2246 cmd.cmd.sdma_complete);
2249 case QIB_CMD_ACK_EVENT:
2250 ret = qib_user_event_ack(rcd, subctxt_fp(fp),
2251 cmd.cmd.event_mask);
2262 static ssize_t qib_write_iter(struct kiocb *iocb, struct iov_iter *from)
2264 struct qib_filedata *fp = iocb->ki_filp->private_data;
2265 struct qib_ctxtdata *rcd = ctxt_fp(iocb->ki_filp);
2266 struct qib_user_sdma_queue *pq = fp->pq;
2268 if (!iter_is_iovec(from) || !from->nr_segs || !pq)
2271 return qib_user_sdma_writev(rcd, pq, from->iov, from->nr_segs);
2274 static struct class *qib_class;
2275 static dev_t qib_dev;
2277 int qib_cdev_init(int minor, const char *name,
2278 const struct file_operations *fops,
2279 struct cdev **cdevp, struct device **devp)
2281 const dev_t dev = MKDEV(MAJOR(qib_dev), minor);
2283 struct device *device = NULL;
2286 cdev = cdev_alloc();
2288 pr_err("Could not allocate cdev for minor %d, %s\n",
2294 cdev->owner = THIS_MODULE;
2296 kobject_set_name(&cdev->kobj, name);
2298 ret = cdev_add(cdev, dev, 1);
2300 pr_err("Could not add cdev for minor %d, %s (err %d)\n",
2305 device = device_create(qib_class, NULL, dev, NULL, "%s", name);
2306 if (!IS_ERR(device))
2308 ret = PTR_ERR(device);
2310 pr_err("Could not create device for minor %d, %s (err %d)\n",
2321 void qib_cdev_cleanup(struct cdev **cdevp, struct device **devp)
2323 struct device *device = *devp;
2326 device_unregister(device);
2336 static struct cdev *wildcard_cdev;
2337 static struct device *wildcard_device;
2339 int __init qib_dev_init(void)
2343 ret = alloc_chrdev_region(&qib_dev, 0, QIB_NMINORS, QIB_DRV_NAME);
2345 pr_err("Could not allocate chrdev region (err %d)\n", -ret);
2349 qib_class = class_create(THIS_MODULE, "ipath");
2350 if (IS_ERR(qib_class)) {
2351 ret = PTR_ERR(qib_class);
2352 pr_err("Could not create device class (err %d)\n", -ret);
2353 unregister_chrdev_region(qib_dev, QIB_NMINORS);
2360 void qib_dev_cleanup(void)
2363 class_destroy(qib_class);
2367 unregister_chrdev_region(qib_dev, QIB_NMINORS);
2370 static atomic_t user_count = ATOMIC_INIT(0);
2372 static void qib_user_remove(struct qib_devdata *dd)
2374 if (atomic_dec_return(&user_count) == 0)
2375 qib_cdev_cleanup(&wildcard_cdev, &wildcard_device);
2377 qib_cdev_cleanup(&dd->user_cdev, &dd->user_device);
2380 static int qib_user_add(struct qib_devdata *dd)
2385 if (atomic_inc_return(&user_count) == 1) {
2386 ret = qib_cdev_init(0, "ipath", &qib_file_ops,
2387 &wildcard_cdev, &wildcard_device);
2392 snprintf(name, sizeof(name), "ipath%d", dd->unit);
2393 ret = qib_cdev_init(dd->unit + 1, name, &qib_file_ops,
2394 &dd->user_cdev, &dd->user_device);
2396 qib_user_remove(dd);
2402 * Create per-unit files in /dev
2404 int qib_device_create(struct qib_devdata *dd)
2408 r = qib_user_add(dd);
2409 ret = qib_diag_add(dd);
2416 * Remove per-unit files in /dev
2417 * void, core kernel returns no errors for this stuff
2419 void qib_device_remove(struct qib_devdata *dd)
2421 qib_user_remove(dd);
2422 qib_diag_remove(dd);