4 * Copyright (c) 2012, 2013 Intel Corporation. All rights reserved.
5 * Copyright (c) 2006 - 2012 QLogic Corporation. All rights reserved.
6 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
38 * This header file is the base header file for qlogic_ib kernel code
39 * qib_user.h serves a similar purpose for user code.
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/mutex.h>
46 #include <linux/list.h>
47 #include <linux/scatterlist.h>
48 #include <linux/slab.h>
51 #include <linux/completion.h>
52 #include <linux/kref.h>
53 #include <linux/sched.h>
54 #include <linux/kthread.h>
56 #include "qib_common.h"
57 #include "qib_verbs.h"
59 /* only s/w major version of QLogic_IB we can handle */
60 #define QIB_CHIP_VERS_MAJ 2U
62 /* don't care about this except printing */
63 #define QIB_CHIP_VERS_MIN 0U
65 /* The Organization Unique Identifier (Mfg code), and its position in GUID */
66 #define QIB_OUI 0x001175
67 #define QIB_OUI_LSB 40
70 * per driver stats, either not device nor port-specific, or
71 * summed over all of the devices and ports.
72 * They are described by name via ipathfs filesystem, so layout
73 * and number of elements can change without breaking compatibility.
74 * If members are added or deleted qib_statnames[] in qib_fs.c must
77 struct qlogic_ib_stats {
78 __u64 sps_ints; /* number of interrupts handled */
79 __u64 sps_errints; /* number of error interrupts */
80 __u64 sps_txerrs; /* tx-related packet errors */
81 __u64 sps_rcverrs; /* non-crc rcv packet errors */
82 __u64 sps_hwerrs; /* hardware errors reported (parity, etc.) */
83 __u64 sps_nopiobufs; /* no pio bufs avail from kernel */
84 __u64 sps_ctxts; /* number of contexts currently open */
85 __u64 sps_lenerrs; /* number of kernel packets where RHF != LRH len */
90 extern struct qlogic_ib_stats qib_stats;
91 extern const struct pci_error_handlers qib_pci_err_handler;
92 extern struct pci_driver qib_driver;
94 #define QIB_CHIP_SWVERSION QIB_CHIP_VERS_MAJ
96 * First-cut critierion for "device is active" is
97 * two thousand dwords combined Tx, Rx traffic per
98 * 5-second interval. SMA packets are 64 dwords,
99 * and occur "a few per second", presumably each way.
101 #define QIB_TRAFFIC_ACTIVE_THRESHOLD (2000)
104 * Struct used to indicate which errors are logged in each of the
105 * error-counters that are logged to EEPROM. A counter is incremented
106 * _once_ (saturating at 255) for each event with any bits set in
107 * the error or hwerror register masks below.
109 #define QIB_EEP_LOG_CNT (4)
110 struct qib_eep_log_mask {
116 * Below contains all data related to a single context (formerly called port).
118 struct qib_ctxtdata {
120 dma_addr_t *rcvegrbuf_phys;
121 /* rcvhdrq base, needs mmap before useful */
123 /* kernel virtual address where hdrqtail is updated */
124 void *rcvhdrtail_kvaddr;
126 * temp buffer for expected send setup, allocated at open, instead
131 * Shared page for kernel to signal user processes that send buffers
132 * need disarming. The process should call QIB_CMD_DISARM_BUFS
133 * or QIB_CMD_ACK_EVENT with IPATH_EVENT_DISARM_BUFS set.
135 unsigned long *user_event_mask;
136 /* when waiting for rcv or pioavail */
137 wait_queue_head_t wait;
139 * rcvegr bufs base, physical, must fit
140 * in 44 bits so 32 bit programs mmap64 44 bit works)
142 dma_addr_t rcvegr_phys;
143 /* mmap of hdrq, must fit in 44 bits */
144 dma_addr_t rcvhdrq_phys;
145 dma_addr_t rcvhdrqtailaddr_phys;
148 * number of opens (including slave sub-contexts) on this instance
149 * (ignoring forks, dup, etc. for now)
153 * how much space to leave at start of eager TID entries for
154 * protocol use, on each TID
156 /* instead of calculating it */
158 /* local node of context */
160 /* non-zero if ctxt is being shared. */
162 /* non-zero if ctxt is being shared. */
164 /* number of eager TID entries. */
166 /* index of first eager TID entry. */
168 /* number of pio bufs for this ctxt (all procs, if shared) */
170 /* first pio buffer for this ctxt */
172 /* chip offset of PIO buffers for this ctxt */
174 /* how many alloc_pages() chunks in rcvegrbuf_pages */
175 u32 rcvegrbuf_chunks;
176 /* how many egrbufs per chunk */
177 u16 rcvegrbufs_perchunk;
179 u16 rcvegrbufs_perchunk_shift;
180 /* order for rcvegrbuf_pages */
181 size_t rcvegrbuf_size;
182 /* rcvhdrq size (for freeing) */
184 /* per-context flags for fileops/intr communication */
186 /* next expected TID to check when looking for free */
188 /* WAIT_RCV that timed out, no interrupt */
190 /* WAIT_PIO that timed out, no interrupt */
192 /* WAIT_RCV already happened, no wait */
194 /* WAIT_PIO already happened, no wait */
196 /* total number of polled urgent packets */
198 /* saved total number of polled urgent packets for poll edge trigger */
200 /* pid of process using this ctxt */
202 pid_t subpid[QLOGIC_IB_MAX_SUBCTXT];
203 /* same size as task_struct .comm[], command that opened context */
205 /* pkeys set by this use of this ctxt */
207 /* so file ops can get at unit */
208 struct qib_devdata *dd;
209 /* so funcs that need physical port can get it easily */
210 struct qib_pportdata *ppd;
211 /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */
212 void *subctxt_uregbase;
213 /* An array of pages for the eager receive buffers * N */
214 void *subctxt_rcvegrbuf;
215 /* An array of pages for the eager header queue entries * N */
216 void *subctxt_rcvhdr_base;
217 /* The version of the library which opened this ctxt */
219 /* Bitmask of active slaves */
221 /* Type of packets or conditions we want to poll for */
223 /* receive packet sequence counter */
226 /* ctxt rcvhdrq head offset */
229 /* lookaside fields */
230 struct qib_qp *lookaside_qp;
232 /* QPs waiting for context processing */
233 struct list_head qp_wait_list;
236 struct qib_sge_state;
238 struct qib_sdma_txreq {
242 void (*callback)(struct qib_sdma_txreq *, int);
243 u16 start_idx; /* sdma private */
244 u16 next_descq_idx; /* sdma private */
245 struct list_head list; /* sdma private */
248 struct qib_sdma_desc {
252 struct qib_verbs_txreq {
253 struct qib_sdma_txreq txreq;
255 struct qib_swqe *wqe;
259 struct qib_pio_header *align_buf;
260 struct qib_mregion *mr;
261 struct qib_sge_state *ss;
264 #define QIB_SDMA_TXREQ_F_USELARGEBUF 0x1
265 #define QIB_SDMA_TXREQ_F_HEADTOHOST 0x2
266 #define QIB_SDMA_TXREQ_F_INTREQ 0x4
267 #define QIB_SDMA_TXREQ_F_FREEBUF 0x8
268 #define QIB_SDMA_TXREQ_F_FREEDESC 0x10
270 #define QIB_SDMA_TXREQ_S_OK 0
271 #define QIB_SDMA_TXREQ_S_SENDERROR 1
272 #define QIB_SDMA_TXREQ_S_ABORTED 2
273 #define QIB_SDMA_TXREQ_S_SHUTDOWN 3
276 * Get/Set IB link-level config parameters for f_get/set_ib_cfg()
277 * Mostly for MADs that set or query link parameters, also ipath
280 #define QIB_IB_CFG_LIDLMC 0 /* LID (LS16b) and Mask (MS16b) */
281 #define QIB_IB_CFG_LWID_ENB 2 /* allowed Link-width */
282 #define QIB_IB_CFG_LWID 3 /* currently active Link-width */
283 #define QIB_IB_CFG_SPD_ENB 4 /* allowed Link speeds */
284 #define QIB_IB_CFG_SPD 5 /* current Link spd */
285 #define QIB_IB_CFG_RXPOL_ENB 6 /* Auto-RX-polarity enable */
286 #define QIB_IB_CFG_LREV_ENB 7 /* Auto-Lane-reversal enable */
287 #define QIB_IB_CFG_LINKLATENCY 8 /* Link Latency (IB1.2 only) */
288 #define QIB_IB_CFG_HRTBT 9 /* IB heartbeat off/enable/auto; DDR/QDR only */
289 #define QIB_IB_CFG_OP_VLS 10 /* operational VLs */
290 #define QIB_IB_CFG_VL_HIGH_CAP 11 /* num of VL high priority weights */
291 #define QIB_IB_CFG_VL_LOW_CAP 12 /* num of VL low priority weights */
292 #define QIB_IB_CFG_OVERRUN_THRESH 13 /* IB overrun threshold */
293 #define QIB_IB_CFG_PHYERR_THRESH 14 /* IB PHY error threshold */
294 #define QIB_IB_CFG_LINKDEFAULT 15 /* IB link default (sleep/poll) */
295 #define QIB_IB_CFG_PKEYS 16 /* update partition keys */
296 #define QIB_IB_CFG_MTU 17 /* update MTU in IBC */
297 #define QIB_IB_CFG_LSTATE 18 /* update linkcmd and linkinitcmd in IBC */
298 #define QIB_IB_CFG_VL_HIGH_LIMIT 19
299 #define QIB_IB_CFG_PMA_TICKS 20 /* PMA sample tick resolution */
300 #define QIB_IB_CFG_PORT 21 /* switch port we are connected to */
303 * for CFG_LSTATE: LINKCMD in upper 16 bits, LINKINITCMD in lower 16
304 * IB_LINKINITCMD_POLL and SLEEP are also used as set/get values for
305 * QIB_IB_CFG_LINKDEFAULT cmd
307 #define IB_LINKCMD_DOWN (0 << 16)
308 #define IB_LINKCMD_ARMED (1 << 16)
309 #define IB_LINKCMD_ACTIVE (2 << 16)
310 #define IB_LINKINITCMD_NOP 0
311 #define IB_LINKINITCMD_POLL 1
312 #define IB_LINKINITCMD_SLEEP 2
313 #define IB_LINKINITCMD_DISABLE 3
316 * valid states passed to qib_set_linkstate() user call
318 #define QIB_IB_LINKDOWN 0
319 #define QIB_IB_LINKARM 1
320 #define QIB_IB_LINKACTIVE 2
321 #define QIB_IB_LINKDOWN_ONLY 3
322 #define QIB_IB_LINKDOWN_SLEEP 4
323 #define QIB_IB_LINKDOWN_DISABLE 5
326 * These 7 values (SDR, DDR, and QDR may be ORed for auto-speed
327 * negotiation) are used for the 3rd argument to path_f_set_ib_cfg
328 * with cmd QIB_IB_CFG_SPD_ENB, by direct calls or via sysfs. They
329 * are also the the possible values for qib_link_speed_enabled and active
330 * The values were chosen to match values used within the IB spec.
336 #define QIB_DEFAULT_MTU 4096
338 /* max number of IB ports supported per HCA */
339 #define QIB_MAX_IB_PORTS 2
342 * Possible IB config parameters for f_get/set_ib_table()
344 #define QIB_IB_TBL_VL_HIGH_ARB 1 /* Get/set VL high priority weights */
345 #define QIB_IB_TBL_VL_LOW_ARB 2 /* Get/set VL low priority weights */
348 * Possible "operations" for f_rcvctrl(ppd, op, ctxt)
349 * these are bits so they can be combined, e.g.
350 * QIB_RCVCTRL_INTRAVAIL_ENB | QIB_RCVCTRL_CTXT_ENB
352 #define QIB_RCVCTRL_TAILUPD_ENB 0x01
353 #define QIB_RCVCTRL_TAILUPD_DIS 0x02
354 #define QIB_RCVCTRL_CTXT_ENB 0x04
355 #define QIB_RCVCTRL_CTXT_DIS 0x08
356 #define QIB_RCVCTRL_INTRAVAIL_ENB 0x10
357 #define QIB_RCVCTRL_INTRAVAIL_DIS 0x20
358 #define QIB_RCVCTRL_PKEY_ENB 0x40 /* Note, default is enabled */
359 #define QIB_RCVCTRL_PKEY_DIS 0x80
360 #define QIB_RCVCTRL_BP_ENB 0x0100
361 #define QIB_RCVCTRL_BP_DIS 0x0200
362 #define QIB_RCVCTRL_TIDFLOW_ENB 0x0400
363 #define QIB_RCVCTRL_TIDFLOW_DIS 0x0800
366 * Possible "operations" for f_sendctrl(ppd, op, var)
367 * these are bits so they can be combined, e.g.
368 * QIB_SENDCTRL_BUFAVAIL_ENB | QIB_SENDCTRL_ENB
369 * Some operations (e.g. DISARM, ABORT) are known to
370 * be "one-shot", so do not modify shadow.
372 #define QIB_SENDCTRL_DISARM (0x1000)
373 #define QIB_SENDCTRL_DISARM_BUF(bufn) ((bufn) | QIB_SENDCTRL_DISARM)
374 /* available (0x2000) */
375 #define QIB_SENDCTRL_AVAIL_DIS (0x4000)
376 #define QIB_SENDCTRL_AVAIL_ENB (0x8000)
377 #define QIB_SENDCTRL_AVAIL_BLIP (0x10000)
378 #define QIB_SENDCTRL_SEND_DIS (0x20000)
379 #define QIB_SENDCTRL_SEND_ENB (0x40000)
380 #define QIB_SENDCTRL_FLUSH (0x80000)
381 #define QIB_SENDCTRL_CLEAR (0x100000)
382 #define QIB_SENDCTRL_DISARM_ALL (0x200000)
385 * These are the generic indices for requesting per-port
386 * counter values via the f_portcntr function. They
387 * are always returned as 64 bit values, although most
388 * are 32 bit counters.
390 /* send-related counters */
391 #define QIBPORTCNTR_PKTSEND 0U
392 #define QIBPORTCNTR_WORDSEND 1U
393 #define QIBPORTCNTR_PSXMITDATA 2U
394 #define QIBPORTCNTR_PSXMITPKTS 3U
395 #define QIBPORTCNTR_PSXMITWAIT 4U
396 #define QIBPORTCNTR_SENDSTALL 5U
397 /* receive-related counters */
398 #define QIBPORTCNTR_PKTRCV 6U
399 #define QIBPORTCNTR_PSRCVDATA 7U
400 #define QIBPORTCNTR_PSRCVPKTS 8U
401 #define QIBPORTCNTR_RCVEBP 9U
402 #define QIBPORTCNTR_RCVOVFL 10U
403 #define QIBPORTCNTR_WORDRCV 11U
404 /* IB link related error counters */
405 #define QIBPORTCNTR_RXLOCALPHYERR 12U
406 #define QIBPORTCNTR_RXVLERR 13U
407 #define QIBPORTCNTR_ERRICRC 14U
408 #define QIBPORTCNTR_ERRVCRC 15U
409 #define QIBPORTCNTR_ERRLPCRC 16U
410 #define QIBPORTCNTR_BADFORMAT 17U
411 #define QIBPORTCNTR_ERR_RLEN 18U
412 #define QIBPORTCNTR_IBSYMBOLERR 19U
413 #define QIBPORTCNTR_INVALIDRLEN 20U
414 #define QIBPORTCNTR_UNSUPVL 21U
415 #define QIBPORTCNTR_EXCESSBUFOVFL 22U
416 #define QIBPORTCNTR_ERRLINK 23U
417 #define QIBPORTCNTR_IBLINKDOWN 24U
418 #define QIBPORTCNTR_IBLINKERRRECOV 25U
419 #define QIBPORTCNTR_LLI 26U
420 /* other error counters */
421 #define QIBPORTCNTR_RXDROPPKT 27U
422 #define QIBPORTCNTR_VL15PKTDROP 28U
423 #define QIBPORTCNTR_ERRPKEY 29U
424 #define QIBPORTCNTR_KHDROVFL 30U
425 /* sampling counters (these are actually control registers) */
426 #define QIBPORTCNTR_PSINTERVAL 31U
427 #define QIBPORTCNTR_PSSTART 32U
428 #define QIBPORTCNTR_PSSTAT 33U
430 /* how often we check for packet activity for "power on hours (in seconds) */
431 #define ACTIVITY_TIMER 5
433 #define MAX_NAME_SIZE 64
435 #ifdef CONFIG_INFINIBAND_QIB_DCA
436 struct qib_irq_notify;
439 struct qib_msix_entry {
440 struct msix_entry msix;
442 #ifdef CONFIG_INFINIBAND_QIB_DCA
445 struct qib_irq_notify *notifier;
447 char name[MAX_NAME_SIZE];
451 /* Below is an opaque struct. Each chip (device) can maintain
452 * private data needed for its operation, but not germane to the
453 * rest of the driver. For convenience, we define another that
454 * is chip-specific, per-port
456 struct qib_chip_specific;
457 struct qib_chipport_specific;
459 enum qib_sdma_states {
460 qib_sdma_state_s00_hw_down,
461 qib_sdma_state_s10_hw_start_up_wait,
462 qib_sdma_state_s20_idle,
463 qib_sdma_state_s30_sw_clean_up_wait,
464 qib_sdma_state_s40_hw_clean_up_wait,
465 qib_sdma_state_s50_hw_halt_wait,
466 qib_sdma_state_s99_running,
469 enum qib_sdma_events {
470 qib_sdma_event_e00_go_hw_down,
471 qib_sdma_event_e10_go_hw_start,
472 qib_sdma_event_e20_hw_started,
473 qib_sdma_event_e30_go_running,
474 qib_sdma_event_e40_sw_cleaned,
475 qib_sdma_event_e50_hw_cleaned,
476 qib_sdma_event_e60_hw_halted,
477 qib_sdma_event_e70_go_idle,
478 qib_sdma_event_e7220_err_halted,
479 qib_sdma_event_e7322_err_halted,
480 qib_sdma_event_e90_timer_tick,
483 extern char *qib_sdma_state_names[];
484 extern char *qib_sdma_event_names[];
486 struct sdma_set_state_action {
487 unsigned op_enable:1;
488 unsigned op_intenable:1;
491 unsigned go_s99_running_tofalse:1;
492 unsigned go_s99_running_totrue:1;
495 struct qib_sdma_state {
497 struct completion comp;
498 enum qib_sdma_states current_state;
499 struct sdma_set_state_action *set_state_action;
501 unsigned go_s99_running;
502 unsigned first_sendbuf;
503 unsigned last_sendbuf; /* really last +1 */
504 /* debugging/devel */
505 enum qib_sdma_states previous_state;
506 unsigned previous_op;
507 enum qib_sdma_events last_event;
511 struct timer_list timer;
524 * The structure below encapsulates data relevant to a physical IB Port.
525 * Current chips support only one such port, but the separation
526 * clarifies things a bit. Note that to conform to IB conventions,
527 * port-numbers are one-based. The first or only port is port1.
529 struct qib_pportdata {
530 struct qib_ibport ibport_data;
532 struct qib_devdata *dd;
533 struct qib_chippport_specific *cpspec; /* chip-specific per-port */
534 struct kobject pport_kobj;
535 struct kobject pport_cc_kobj;
536 struct kobject sl2vl_kobj;
537 struct kobject diagc_kobj;
539 /* GUID for this interface, in network order */
542 /* QIB_POLL, etc. link-state specific flags, per port */
544 /* qib_lflags driver is waiting for */
546 spinlock_t lflags_lock;
548 /* ref count for each pkey */
549 atomic_t pkeyrefs[4];
552 * this address is mapped readonly into user processes so they can
553 * get status cheaply, whenever they want. One qword of status per port
557 /* SendDMA related entries */
560 struct qib_sdma_desc *sdma_descq;
561 struct workqueue_struct *qib_wq;
562 struct qib_sdma_state sdma_state;
563 dma_addr_t sdma_descq_phys;
564 volatile __le64 *sdma_head_dma; /* DMA'ed by chip */
565 dma_addr_t sdma_head_phys;
568 /* read/write using lock */
569 spinlock_t sdma_lock ____cacheline_aligned_in_smp;
570 struct list_head sdma_activelist;
571 u64 sdma_descq_added;
572 u64 sdma_descq_removed;
577 struct tasklet_struct sdma_sw_clean_up_task
578 ____cacheline_aligned_in_smp;
580 wait_queue_head_t state_wait; /* for state_wanted */
582 /* HoL blocking for SMP replies */
584 struct timer_list hol_timer;
587 * Shadow copies of registers; size indicates read access size.
588 * Most of them are readonly, but some are write-only register,
589 * where we manipulate the bits in the shadow copy, and then write
590 * the shadow copy to qlogic_ib.
592 * We deliberately make most of these 32 bits, since they have
593 * restricted range. For any that we read, we won't to generate 32
594 * bit accesses, since Opteron will generate 2 separate 32 bit HT
595 * transactions for a 64 bit read, and we want to avoid unnecessary
599 /* This is the 64 bit group */
600 /* last ibcstatus. opaque outside chip-specific code */
603 /* these are the "32 bit" regs */
606 * the following two are 32-bit bitmasks, but {test,clear,set}_bit
607 * all expect bit fields to be "unsigned long"
609 unsigned long p_rcvctrl; /* shadow per-port rcvctrl */
610 unsigned long p_sendctrl; /* shadow per-port sendctrl */
612 u32 ibmtu; /* The MTU programmed for this unit */
614 * Current max size IB packet (in bytes) including IB headers, that
615 * we can send. Changes when ibmtu changes.
619 * ibmaxlen at init time, limited by chip and by receive buffer
620 * size. Not changed after init.
623 /* LID programmed for this instance */
625 /* list of pkeys programmed; 0 if not set */
627 /* LID mask control */
629 u8 link_width_supported;
630 u8 link_speed_supported;
631 u8 link_width_enabled;
632 u8 link_speed_enabled;
633 u8 link_width_active;
634 u8 link_speed_active;
637 /* Rx Polarity inversion (compensate for ~tx on partner) */
640 u8 hw_pidx; /* physical port index */
641 u8 port; /* IB port number and index into dd->pports - 1 */
645 /* used to override LED behavior */
646 u8 led_override; /* Substituted for normal value, if non-zero */
647 u16 led_override_timeoff; /* delta to next timer event */
648 u8 led_override_vals[2]; /* Alternates per blink-frame */
649 u8 led_override_phase; /* Just counts, LSB picks from vals[] */
650 atomic_t led_override_timer_active;
651 /* Used to flash LEDs in override mode */
652 struct timer_list led_override_timer;
653 struct xmit_wait cong_stats;
654 struct timer_list symerr_clear_timer;
656 /* Synchronize access between driver writes and sysfs reads */
657 spinlock_t cc_shadow_lock
658 ____cacheline_aligned_in_smp;
660 /* Shadow copy of the congestion control table */
661 struct cc_table_shadow *ccti_entries_shadow;
663 /* Shadow copy of the congestion control entries */
664 struct ib_cc_congestion_setting_attr_shadow *congestion_entries_shadow;
666 /* List of congestion control table entries */
667 struct ib_cc_table_entry_shadow *ccti_entries;
669 /* 16 congestion entries with each entry corresponding to a SL */
670 struct ib_cc_congestion_entry_shadow *congestion_entries;
672 /* Maximum number of congestion control entries that the agent expects
673 * the manager to send.
675 u16 cc_supported_table_entries;
677 /* Total number of congestion control table entries */
680 /* Bit map identifying service level */
681 u16 cc_sl_control_map;
683 /* maximum congestion control table index */
686 /* CA's max number of 64 entry units in the congestion control table */
687 u8 cc_max_table_entries;
690 /* Observers. Not to be taken lightly, possibly not to ship. */
692 * If a diag read or write is to (bottom <= offset <= top),
693 * the "hoook" is called, allowing, e.g. shadows to be
694 * updated in sync with the driver. struct diag_observer
695 * is the "visible" part.
697 struct diag_observer;
699 typedef int (*diag_hook) (struct qib_devdata *dd,
700 const struct diag_observer *op,
701 u32 offs, u64 *data, u64 mask, int only_32);
703 struct diag_observer {
709 extern int qib_register_observer(struct qib_devdata *dd,
710 const struct diag_observer *op);
712 /* Only declared here, not defined. Private to diags */
713 struct diag_observer_list_elt;
715 /* device data struct now contains only "general per-device" info.
716 * fields related to a physical IB port are in a qib_pportdata struct,
717 * described above) while fields only used by a particular chip-type are in
718 * a qib_chipdata struct, whose contents are opaque to this file.
721 struct qib_ibdev verbs_dev; /* must be first */
722 struct list_head list;
723 /* pointers to related structs for this device */
724 /* pci access data structure */
725 struct pci_dev *pcidev;
726 struct cdev *user_cdev;
727 struct cdev *diag_cdev;
728 struct device *user_device;
729 struct device *diag_device;
731 /* mem-mapped pointer to base of chip regs */
732 u64 __iomem *kregbase;
733 /* end of mem-mapped chip space excluding sendbuf and user regs */
734 u64 __iomem *kregend;
735 /* physical address of chip for io_remap, etc. */
736 resource_size_t physaddr;
737 /* qib_cfgctxts pointers */
738 struct qib_ctxtdata **rcd; /* Receive Context Data */
740 /* qib_pportdata, points to array of (physical) port-specific
741 * data structs, indexed by pidx (0..n-1)
743 struct qib_pportdata *pport;
744 struct qib_chip_specific *cspec; /* chip-specific */
746 /* kvirt address of 1st 2k pio buffer */
747 void __iomem *pio2kbase;
748 /* kvirt address of 1st 4k pio buffer */
749 void __iomem *pio4kbase;
750 /* mem-mapped pointer to base of PIO buffers (if using WC PAT) */
751 void __iomem *piobase;
752 /* mem-mapped pointer to base of user chip regs (if using WC PAT) */
753 u64 __iomem *userbase;
754 void __iomem *piovl15base; /* base of VL15 buffers, if not WC */
756 * points to area where PIOavail registers will be DMA'ed.
757 * Has to be on a page of it's own, because the page will be
758 * mapped into user program space. This copy is *ONLY* ever
759 * written by DMA, not by the driver! Need a copy per device
760 * when we get to multiple devices
762 volatile __le64 *pioavailregs_dma; /* DMA'ed by chip */
763 /* physical address where updates occur */
764 dma_addr_t pioavailregs_phys;
766 /* device-specific implementations of functions needed by
767 * common code. Contrary to previous consensus, we can't
768 * really just point to a device-specific table, because we
769 * may need to "bend", e.g. *_f_put_tid
771 /* fallback to alternate interrupt type if possible */
772 int (*f_intr_fallback)(struct qib_devdata *);
773 /* hard reset chip */
774 int (*f_reset)(struct qib_devdata *);
775 void (*f_quiet_serdes)(struct qib_pportdata *);
776 int (*f_bringup_serdes)(struct qib_pportdata *);
777 int (*f_early_init)(struct qib_devdata *);
778 void (*f_clear_tids)(struct qib_devdata *, struct qib_ctxtdata *);
779 void (*f_put_tid)(struct qib_devdata *, u64 __iomem*,
781 void (*f_cleanup)(struct qib_devdata *);
782 void (*f_setextled)(struct qib_pportdata *, u32);
783 /* fill out chip-specific fields */
784 int (*f_get_base_info)(struct qib_ctxtdata *, struct qib_base_info *);
786 void (*f_free_irq)(struct qib_devdata *);
787 struct qib_message_header *(*f_get_msgheader)
788 (struct qib_devdata *, __le32 *);
789 void (*f_config_ctxts)(struct qib_devdata *);
790 int (*f_get_ib_cfg)(struct qib_pportdata *, int);
791 int (*f_set_ib_cfg)(struct qib_pportdata *, int, u32);
792 int (*f_set_ib_loopback)(struct qib_pportdata *, const char *);
793 int (*f_get_ib_table)(struct qib_pportdata *, int, void *);
794 int (*f_set_ib_table)(struct qib_pportdata *, int, void *);
795 u32 (*f_iblink_state)(u64);
796 u8 (*f_ibphys_portstate)(u64);
797 void (*f_xgxs_reset)(struct qib_pportdata *);
798 /* per chip actions needed for IB Link up/down changes */
799 int (*f_ib_updown)(struct qib_pportdata *, int, u64);
800 u32 __iomem *(*f_getsendbuf)(struct qib_pportdata *, u64, u32 *);
801 /* Read/modify/write of GPIO pins (potentially chip-specific */
802 int (*f_gpio_mod)(struct qib_devdata *dd, u32 out, u32 dir,
804 /* Enable writes to config EEPROM (if supported) */
805 int (*f_eeprom_wen)(struct qib_devdata *dd, int wen);
807 * modify rcvctrl shadow[s] and write to appropriate chip-regs.
808 * see above QIB_RCVCTRL_xxx_ENB/DIS for operations.
809 * (ctxt == -1) means "all contexts", only meaningful for
810 * clearing. Could remove if chip_spec shutdown properly done.
812 void (*f_rcvctrl)(struct qib_pportdata *, unsigned int op,
814 /* Read/modify/write sendctrl appropriately for op and port. */
815 void (*f_sendctrl)(struct qib_pportdata *, u32 op);
816 void (*f_set_intr_state)(struct qib_devdata *, u32);
817 void (*f_set_armlaunch)(struct qib_devdata *, u32);
818 void (*f_wantpiobuf_intr)(struct qib_devdata *, u32);
819 int (*f_late_initreg)(struct qib_devdata *);
820 int (*f_init_sdma_regs)(struct qib_pportdata *);
821 u16 (*f_sdma_gethead)(struct qib_pportdata *);
822 int (*f_sdma_busy)(struct qib_pportdata *);
823 void (*f_sdma_update_tail)(struct qib_pportdata *, u16);
824 void (*f_sdma_set_desc_cnt)(struct qib_pportdata *, unsigned);
825 void (*f_sdma_sendctrl)(struct qib_pportdata *, unsigned);
826 void (*f_sdma_hw_clean_up)(struct qib_pportdata *);
827 void (*f_sdma_hw_start_up)(struct qib_pportdata *);
828 void (*f_sdma_init_early)(struct qib_pportdata *);
829 void (*f_set_cntr_sample)(struct qib_pportdata *, u32, u32);
830 void (*f_update_usrhead)(struct qib_ctxtdata *, u64, u32, u32, u32);
831 u32 (*f_hdrqempty)(struct qib_ctxtdata *);
832 u64 (*f_portcntr)(struct qib_pportdata *, u32);
833 u32 (*f_read_cntrs)(struct qib_devdata *, loff_t, char **,
835 u32 (*f_read_portcntrs)(struct qib_devdata *, loff_t, u32,
837 u32 (*f_setpbc_control)(struct qib_pportdata *, u32, u8, u8);
838 void (*f_initvl15_bufs)(struct qib_devdata *);
839 void (*f_init_ctxt)(struct qib_ctxtdata *);
840 void (*f_txchk_change)(struct qib_devdata *, u32, u32, u32,
841 struct qib_ctxtdata *);
842 void (*f_writescratch)(struct qib_devdata *, u32);
843 int (*f_tempsense_rd)(struct qib_devdata *, int regnum);
844 #ifdef CONFIG_INFINIBAND_QIB_DCA
845 int (*f_notify_dca)(struct qib_devdata *, unsigned long event);
848 char *boardname; /* human readable board info */
850 /* template for writing TIDs */
852 /* value to write to free TIDs */
855 /* number of registers used for pioavail */
857 /* device (not port) flags, basically device capabilities */
859 /* last buffer for user use */
862 /* saturating counter of (non-port-specific) device interrupts */
865 /* pio bufs allocated per ctxt */
867 /* if remainder on bufs/ctxt, ctxts < extrabuf get 1 extra */
870 * number of ctxts configured as max; zero is set to number chip
871 * supports, less gives more pio bufs/ctxt, etc.
875 * number of ctxts available for PSM open
880 * hint that we should update pioavailshadow before
881 * looking for a PIO buffer
885 /* internal debugging stats */
890 /* PCI Vendor ID (here for NodeInfo) */
892 /* PCI Device ID (here for NodeInfo) */
894 /* for write combining settings */
895 unsigned long wc_cookie;
896 unsigned long wc_base;
897 unsigned long wc_len;
899 /* shadow copy of struct page *'s for exp tid pages */
900 struct page **pageshadow;
901 /* shadow copy of dma handles for exp tid pages */
902 dma_addr_t *physshadow;
903 u64 __iomem *egrtidbase;
904 spinlock_t sendctrl_lock; /* protect changes to sendctrl shadow */
905 /* around rcd and (user ctxts) ctxt_cnt use (intr vs free) */
906 spinlock_t uctxt_lock; /* rcd and user context changes */
908 * per unit status, see also portdata statusp
909 * mapped readonly into user processes so they can get unit and
910 * IB link status cheaply
913 char *freezemsg; /* freeze msg if hw error put chip in freeze */
914 u32 freezelen; /* max length of freezemsg */
915 /* timer used to prevent stats overflow, error throttling, etc. */
916 struct timer_list stats_timer;
918 /* timer to verify interrupts work, and fallback if possible */
919 struct timer_list intrchk_timer;
920 unsigned long ureg_align; /* user register alignment */
923 * Protects pioavailshadow, pioavailkernel, pio_need_disarm, and
926 spinlock_t pioavail_lock;
928 * index of last buffer to optimize search for next
932 * min kernel pio buffer to optimize search
936 * Shadow copies of registers; size indicates read access size.
937 * Most of them are readonly, but some are write-only register,
938 * where we manipulate the bits in the shadow copy, and then write
939 * the shadow copy to qlogic_ib.
941 * We deliberately make most of these 32 bits, since they have
942 * restricted range. For any that we read, we won't to generate 32
943 * bit accesses, since Opteron will generate 2 separate 32 bit HT
944 * transactions for a 64 bit read, and we want to avoid unnecessary
948 /* This is the 64 bit group */
950 unsigned long pioavailshadow[6];
951 /* bitmap of send buffers available for the kernel to use with PIO. */
952 unsigned long pioavailkernel[6];
953 /* bitmap of send buffers which need to be disarmed. */
954 unsigned long pio_need_disarm[3];
955 /* bitmap of send buffers which are being written to. */
956 unsigned long pio_writing[3];
957 /* kr_revision shadow */
959 /* Base GUID for device (from eeprom, network order) */
963 * kr_sendpiobufbase value (chip offset of pio buffers), and the
964 * base of the 2KB buffer s(user processes only use 2K)
969 /* these are the "32 bit" regs */
971 /* number of GUIDs in the flash for this interface */
974 * the following two are 32-bit bitmasks, but {test,clear,set}_bit
975 * all expect bit fields to be "unsigned long"
977 unsigned long rcvctrl; /* shadow per device rcvctrl */
978 unsigned long sendctrl; /* shadow per device sendctrl */
980 /* value we put in kr_rcvhdrcnt */
982 /* value we put in kr_rcvhdrsize */
984 /* value we put in kr_rcvhdrentsize */
986 /* kr_ctxtcnt value */
988 /* kr_pagealign value */
990 /* number of "2KB" PIO buffers */
992 /* size in bytes of "2KB" PIO buffers */
994 /* max usable size in dwords of a "2KB" PIO buffer before going "4KB" */
995 u32 piosize2kmax_dwords;
996 /* number of "4KB" PIO buffers */
998 /* size in bytes of "4KB" PIO buffers */
1000 /* kr_rcvegrbase value */
1002 /* kr_rcvtidbase value */
1004 /* kr_rcvtidcnt value */
1006 /* kr_userregbase */
1008 /* shadow the control register contents */
1011 /* chip address space used by 4k pio buffers */
1013 /* size of each rcvegrbuffer */
1016 u16 rcvegrbufsize_shift;
1017 /* localbus width (1, 2,4,8,16,32) from config space */
1019 /* localbus speed in MHz */
1021 int unit; /* unit # of this chip */
1023 /* start of CHIP_SPEC move to chipspec, but need code changes */
1024 /* low and high portions of MSI capability/vector */
1026 /* saved after PCIe init for restore after reset */
1028 /* MSI data (vector) saved for restore */
1030 /* so we can rewrite it after a chip reset */
1032 /* so we can rewrite it after a chip reset */
1034 u64 rhdrhead_intr_off;
1037 * ASCII serial number, from flash, large enough for original
1038 * all digit strings, and longer QLogic serial number format
1041 /* human readable board version */
1042 u8 boardversion[96];
1043 u8 lbus_info[32]; /* human readable localbus info */
1044 /* chip major rev, from qib_revision */
1046 /* chip minor rev, from qib_revision */
1049 /* Misc small ints */
1050 /* Number of physical ports available */
1052 /* Lowest context number which can be used by user processes */
1058 u16 rhf_offset; /* offset of RHF within receive header entry */
1061 * GPIO pins for twsi-connected devices, and device code for eeprom
1068 /* Support (including locks) for EEPROM logging of errors and time */
1069 /* control access to actual counters, timer */
1070 spinlock_t eep_st_lock;
1071 /* control high-level access to EEPROM */
1072 struct mutex eep_lock;
1073 uint64_t traffic_wds;
1074 /* active time is kept in seconds, but logged in hours */
1075 atomic_t active_time;
1076 /* Below are nominal shadow of EEPROM, new since last EEPROM update */
1077 uint8_t eep_st_errs[QIB_EEP_LOG_CNT];
1078 uint8_t eep_st_new_errs[QIB_EEP_LOG_CNT];
1081 * masks for which bits of errs, hwerrs that cause
1082 * each of the counters to increment.
1084 struct qib_eep_log_mask eep_st_masks[QIB_EEP_LOG_CNT];
1085 struct qib_diag_client *diag_client;
1086 spinlock_t qib_diag_trans_lock; /* protect diag observer ops */
1087 struct diag_observer_list_elt *diag_observer_list;
1089 u8 psxmitwait_supported;
1090 /* cycle length of PS* counters in HW (in picoseconds) */
1091 u16 psxmitwait_check_rate;
1092 /* high volume overflow errors defered to tasklet */
1093 struct tasklet_struct error_tasklet;
1094 /* per device cq worker */
1095 struct kthread_worker *worker;
1097 int assigned_node_id; /* NUMA node closest to HCA */
1100 /* hol_state values */
1101 #define QIB_HOL_UP 0
1102 #define QIB_HOL_INIT 1
1104 #define QIB_SDMA_SENDCTRL_OP_ENABLE (1U << 0)
1105 #define QIB_SDMA_SENDCTRL_OP_INTENABLE (1U << 1)
1106 #define QIB_SDMA_SENDCTRL_OP_HALT (1U << 2)
1107 #define QIB_SDMA_SENDCTRL_OP_CLEANUP (1U << 3)
1108 #define QIB_SDMA_SENDCTRL_OP_DRAIN (1U << 4)
1110 /* operation types for f_txchk_change() */
1111 #define TXCHK_CHG_TYPE_DIS1 3
1112 #define TXCHK_CHG_TYPE_ENAB1 2
1113 #define TXCHK_CHG_TYPE_KERN 1
1114 #define TXCHK_CHG_TYPE_USER 0
1116 #define QIB_CHASE_TIME msecs_to_jiffies(145)
1117 #define QIB_CHASE_DIS_TIME msecs_to_jiffies(160)
1119 /* Private data for file operations */
1120 struct qib_filedata {
1121 struct qib_ctxtdata *rcd;
1124 struct qib_user_sdma_queue *pq;
1125 int rec_cpu_num; /* for cpu affinity; -1 if none */
1128 extern struct list_head qib_dev_list;
1129 extern spinlock_t qib_devs_lock;
1130 extern struct qib_devdata *qib_lookup(int unit);
1131 extern u32 qib_cpulist_count;
1132 extern unsigned long *qib_cpulist;
1134 extern unsigned qib_wc_pat;
1135 extern unsigned qib_cc_table_size;
1136 int qib_init(struct qib_devdata *, int);
1137 int init_chip_wc_pat(struct qib_devdata *dd, u32);
1138 int qib_enable_wc(struct qib_devdata *dd);
1139 void qib_disable_wc(struct qib_devdata *dd);
1140 int qib_count_units(int *npresentp, int *nupp);
1141 int qib_count_active_units(void);
1143 int qib_cdev_init(int minor, const char *name,
1144 const struct file_operations *fops,
1145 struct cdev **cdevp, struct device **devp);
1146 void qib_cdev_cleanup(struct cdev **cdevp, struct device **devp);
1147 int qib_dev_init(void);
1148 void qib_dev_cleanup(void);
1150 int qib_diag_add(struct qib_devdata *);
1151 void qib_diag_remove(struct qib_devdata *);
1152 void qib_handle_e_ibstatuschanged(struct qib_pportdata *, u64);
1153 void qib_sdma_update_tail(struct qib_pportdata *, u16); /* hold sdma_lock */
1155 int qib_decode_err(struct qib_devdata *dd, char *buf, size_t blen, u64 err);
1156 void qib_bad_intrstatus(struct qib_devdata *);
1157 void qib_handle_urcv(struct qib_devdata *, u64);
1159 /* clean up any per-chip chip-specific stuff */
1160 void qib_chip_cleanup(struct qib_devdata *);
1161 /* clean up any chip type-specific stuff */
1162 void qib_chip_done(void);
1164 /* check to see if we have to force ordering for write combining */
1165 int qib_unordered_wc(void);
1166 void qib_pio_copy(void __iomem *to, const void *from, size_t count);
1168 void qib_disarm_piobufs(struct qib_devdata *, unsigned, unsigned);
1169 int qib_disarm_piobufs_ifneeded(struct qib_ctxtdata *);
1170 void qib_disarm_piobufs_set(struct qib_devdata *, unsigned long *, unsigned);
1171 void qib_cancel_sends(struct qib_pportdata *);
1173 int qib_create_rcvhdrq(struct qib_devdata *, struct qib_ctxtdata *);
1174 int qib_setup_eagerbufs(struct qib_ctxtdata *);
1175 void qib_set_ctxtcnt(struct qib_devdata *);
1176 int qib_create_ctxts(struct qib_devdata *dd);
1177 struct qib_ctxtdata *qib_create_ctxtdata(struct qib_pportdata *, u32, int);
1178 void qib_init_pportdata(struct qib_pportdata *, struct qib_devdata *, u8, u8);
1179 void qib_free_ctxtdata(struct qib_devdata *, struct qib_ctxtdata *);
1181 u32 qib_kreceive(struct qib_ctxtdata *, u32 *, u32 *);
1182 int qib_reset_device(int);
1183 int qib_wait_linkstate(struct qib_pportdata *, u32, int);
1184 int qib_set_linkstate(struct qib_pportdata *, u8);
1185 int qib_set_mtu(struct qib_pportdata *, u16);
1186 int qib_set_lid(struct qib_pportdata *, u32, u8);
1187 void qib_hol_down(struct qib_pportdata *);
1188 void qib_hol_init(struct qib_pportdata *);
1189 void qib_hol_up(struct qib_pportdata *);
1190 void qib_hol_event(unsigned long);
1191 void qib_disable_after_error(struct qib_devdata *);
1192 int qib_set_uevent_bits(struct qib_pportdata *, const int);
1194 /* for use in system calls, where we want to know device type, etc. */
1195 #define ctxt_fp(fp) \
1196 (((struct qib_filedata *)(fp)->private_data)->rcd)
1197 #define subctxt_fp(fp) \
1198 (((struct qib_filedata *)(fp)->private_data)->subctxt)
1199 #define tidcursor_fp(fp) \
1200 (((struct qib_filedata *)(fp)->private_data)->tidcursor)
1201 #define user_sdma_queue_fp(fp) \
1202 (((struct qib_filedata *)(fp)->private_data)->pq)
1204 static inline struct qib_devdata *dd_from_ppd(struct qib_pportdata *ppd)
1209 static inline struct qib_devdata *dd_from_dev(struct qib_ibdev *dev)
1211 return container_of(dev, struct qib_devdata, verbs_dev);
1214 static inline struct qib_devdata *dd_from_ibdev(struct ib_device *ibdev)
1216 return dd_from_dev(to_idev(ibdev));
1219 static inline struct qib_pportdata *ppd_from_ibp(struct qib_ibport *ibp)
1221 return container_of(ibp, struct qib_pportdata, ibport_data);
1224 static inline struct qib_ibport *to_iport(struct ib_device *ibdev, u8 port)
1226 struct qib_devdata *dd = dd_from_ibdev(ibdev);
1227 unsigned pidx = port - 1; /* IB number port from 1, hdw from 0 */
1229 WARN_ON(pidx >= dd->num_pports);
1230 return &dd->pport[pidx].ibport_data;
1234 * values for dd->flags (_device_ related flags) and
1236 #define QIB_HAS_LINK_LATENCY 0x1 /* supports link latency (IB 1.2) */
1237 #define QIB_INITTED 0x2 /* chip and driver up and initted */
1238 #define QIB_DOING_RESET 0x4 /* in the middle of doing chip reset */
1239 #define QIB_PRESENT 0x8 /* chip accesses can be done */
1240 #define QIB_PIO_FLUSH_WC 0x10 /* Needs Write combining flush for PIO */
1241 #define QIB_HAS_THRESH_UPDATE 0x40
1242 #define QIB_HAS_SDMA_TIMEOUT 0x80
1243 #define QIB_USE_SPCL_TRIG 0x100 /* SpecialTrigger launch enabled */
1244 #define QIB_NODMA_RTAIL 0x200 /* rcvhdrtail register DMA enabled */
1245 #define QIB_HAS_INTX 0x800 /* Supports INTx interrupts */
1246 #define QIB_HAS_SEND_DMA 0x1000 /* Supports Send DMA */
1247 #define QIB_HAS_VLSUPP 0x2000 /* Supports multiple VLs; PBC different */
1248 #define QIB_HAS_HDRSUPP 0x4000 /* Supports header suppression */
1249 #define QIB_BADINTR 0x8000 /* severe interrupt problems */
1250 #define QIB_DCA_ENABLED 0x10000 /* Direct Cache Access enabled */
1251 #define QIB_HAS_QSFP 0x20000 /* device (card instance) has QSFP */
1254 * values for ppd->lflags (_ib_port_ related flags)
1256 #define QIBL_LINKV 0x1 /* IB link state valid */
1257 #define QIBL_LINKDOWN 0x8 /* IB link is down */
1258 #define QIBL_LINKINIT 0x10 /* IB link level is up */
1259 #define QIBL_LINKARMED 0x20 /* IB link is ARMED */
1260 #define QIBL_LINKACTIVE 0x40 /* IB link is ACTIVE */
1261 /* leave a gap for more IB-link state */
1262 #define QIBL_IB_AUTONEG_INPROG 0x1000 /* non-IBTA DDR/QDR neg active */
1263 #define QIBL_IB_AUTONEG_FAILED 0x2000 /* non-IBTA DDR/QDR neg failed */
1264 #define QIBL_IB_LINK_DISABLED 0x4000 /* Linkdown-disable forced,
1265 * Do not try to bring up */
1266 #define QIBL_IB_FORCE_NOTIFY 0x8000 /* force notify on next ib change */
1268 /* IB dword length mask in PBC (lower 11 bits); same for all chips */
1269 #define QIB_PBC_LENGTH_MASK ((1 << 11) - 1)
1272 /* ctxt_flag bit offsets */
1273 /* waiting for a packet to arrive */
1274 #define QIB_CTXT_WAITING_RCV 2
1275 /* master has not finished initializing */
1276 #define QIB_CTXT_MASTER_UNINIT 4
1277 /* waiting for an urgent packet to arrive */
1278 #define QIB_CTXT_WAITING_URG 5
1280 /* free up any allocated data at closes */
1281 void qib_free_data(struct qib_ctxtdata *dd);
1282 void qib_chg_pioavailkernel(struct qib_devdata *, unsigned, unsigned,
1283 u32, struct qib_ctxtdata *);
1284 struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *,
1285 const struct pci_device_id *);
1286 struct qib_devdata *qib_init_iba7220_funcs(struct pci_dev *,
1287 const struct pci_device_id *);
1288 struct qib_devdata *qib_init_iba6120_funcs(struct pci_dev *,
1289 const struct pci_device_id *);
1290 void qib_free_devdata(struct qib_devdata *);
1291 struct qib_devdata *qib_alloc_devdata(struct pci_dev *pdev, size_t extra);
1293 #define QIB_TWSI_NO_DEV 0xFF
1294 /* Below qib_twsi_ functions must be called with eep_lock held */
1295 int qib_twsi_reset(struct qib_devdata *dd);
1296 int qib_twsi_blk_rd(struct qib_devdata *dd, int dev, int addr, void *buffer,
1298 int qib_twsi_blk_wr(struct qib_devdata *dd, int dev, int addr,
1299 const void *buffer, int len);
1300 void qib_get_eeprom_info(struct qib_devdata *);
1301 int qib_update_eeprom_log(struct qib_devdata *dd);
1302 void qib_inc_eeprom_err(struct qib_devdata *dd, u32 eidx, u32 incr);
1303 void qib_dump_lookup_output_queue(struct qib_devdata *);
1304 void qib_force_pio_avail_update(struct qib_devdata *);
1305 void qib_clear_symerror_on_linkup(unsigned long opaque);
1308 * Set LED override, only the two LSBs have "public" meaning, but
1309 * any non-zero value substitutes them for the Link and LinkTrain
1312 #define QIB_LED_PHYS 1 /* Physical (linktraining) GREEN LED */
1313 #define QIB_LED_LOG 2 /* Logical (link) YELLOW LED */
1314 void qib_set_led_override(struct qib_pportdata *ppd, unsigned int val);
1316 /* send dma routines */
1317 int qib_setup_sdma(struct qib_pportdata *);
1318 void qib_teardown_sdma(struct qib_pportdata *);
1319 void __qib_sdma_intr(struct qib_pportdata *);
1320 void qib_sdma_intr(struct qib_pportdata *);
1321 int qib_sdma_verbs_send(struct qib_pportdata *, struct qib_sge_state *,
1322 u32, struct qib_verbs_txreq *);
1323 /* ppd->sdma_lock should be locked before calling this. */
1324 int qib_sdma_make_progress(struct qib_pportdata *dd);
1326 static inline int qib_sdma_empty(const struct qib_pportdata *ppd)
1328 return ppd->sdma_descq_added == ppd->sdma_descq_removed;
1331 /* must be called under qib_sdma_lock */
1332 static inline u16 qib_sdma_descq_freecnt(const struct qib_pportdata *ppd)
1334 return ppd->sdma_descq_cnt -
1335 (ppd->sdma_descq_added - ppd->sdma_descq_removed) - 1;
1338 static inline int __qib_sdma_running(struct qib_pportdata *ppd)
1340 return ppd->sdma_state.current_state == qib_sdma_state_s99_running;
1342 int qib_sdma_running(struct qib_pportdata *);
1344 void __qib_sdma_process_event(struct qib_pportdata *, enum qib_sdma_events);
1345 void qib_sdma_process_event(struct qib_pportdata *, enum qib_sdma_events);
1348 * number of words used for protocol header if not set by qib_userinit();
1350 #define QIB_DFLT_RCVHDRSIZE 9
1353 * We need to be able to handle an IB header of at least 24 dwords.
1354 * We need the rcvhdrq large enough to handle largest IB header, but
1355 * still have room for a 2KB MTU standard IB packet.
1356 * Additionally, some processor/memory controller combinations
1357 * benefit quite strongly from having the DMA'ed data be cacheline
1358 * aligned and a cacheline multiple, so we set the size to 32 dwords
1359 * (2 64-byte primary cachelines for pretty much all processors of
1360 * interest). The alignment hurts nothing, other than using somewhat
1363 #define QIB_RCVHDR_ENTSIZE 32
1365 int qib_get_user_pages(unsigned long, size_t, struct page **);
1366 void qib_release_user_pages(struct page **, size_t);
1367 int qib_eeprom_read(struct qib_devdata *, u8, void *, int);
1368 int qib_eeprom_write(struct qib_devdata *, u8, const void *, int);
1369 u32 __iomem *qib_getsendbuf_range(struct qib_devdata *, u32 *, u32, u32);
1370 void qib_sendbuf_done(struct qib_devdata *, unsigned);
1372 static inline void qib_clear_rcvhdrtail(const struct qib_ctxtdata *rcd)
1374 *((u64 *) rcd->rcvhdrtail_kvaddr) = 0ULL;
1377 static inline u32 qib_get_rcvhdrtail(const struct qib_ctxtdata *rcd)
1380 * volatile because it's a DMA target from the chip, routine is
1381 * inlined, and don't want register caching or reordering.
1383 return (u32) le64_to_cpu(
1384 *((volatile __le64 *)rcd->rcvhdrtail_kvaddr)); /* DMA'ed */
1387 static inline u32 qib_get_hdrqtail(const struct qib_ctxtdata *rcd)
1389 const struct qib_devdata *dd = rcd->dd;
1392 if (dd->flags & QIB_NODMA_RTAIL) {
1396 rhf_addr = (__le32 *) rcd->rcvhdrq +
1397 rcd->head + dd->rhf_offset;
1398 seq = qib_hdrget_seq(rhf_addr);
1399 hdrqtail = rcd->head;
1400 if (seq == rcd->seq_cnt)
1403 hdrqtail = qib_get_rcvhdrtail(rcd);
1412 extern const char ib_qib_version[];
1414 int qib_device_create(struct qib_devdata *);
1415 void qib_device_remove(struct qib_devdata *);
1417 int qib_create_port_files(struct ib_device *ibdev, u8 port_num,
1418 struct kobject *kobj);
1419 int qib_verbs_register_sysfs(struct qib_devdata *);
1420 void qib_verbs_unregister_sysfs(struct qib_devdata *);
1421 /* Hook for sysfs read of QSFP */
1422 extern int qib_qsfp_dump(struct qib_pportdata *ppd, char *buf, int len);
1424 int __init qib_init_qibfs(void);
1425 int __exit qib_exit_qibfs(void);
1427 int qibfs_add(struct qib_devdata *);
1428 int qibfs_remove(struct qib_devdata *);
1430 int qib_pcie_init(struct pci_dev *, const struct pci_device_id *);
1431 int qib_pcie_ddinit(struct qib_devdata *, struct pci_dev *,
1432 const struct pci_device_id *);
1433 void qib_pcie_ddcleanup(struct qib_devdata *);
1434 int qib_pcie_params(struct qib_devdata *, u32, u32 *, struct qib_msix_entry *);
1435 int qib_reinit_intr(struct qib_devdata *);
1436 void qib_enable_intx(struct pci_dev *);
1437 void qib_nomsi(struct qib_devdata *);
1438 void qib_nomsix(struct qib_devdata *);
1439 void qib_pcie_getcmd(struct qib_devdata *, u16 *, u8 *, u8 *);
1440 void qib_pcie_reenable(struct qib_devdata *, u16, u8, u8);
1443 * dma_addr wrappers - all 0's invalid for hw
1445 dma_addr_t qib_map_page(struct pci_dev *, struct page *, unsigned long,
1447 const char *qib_get_unit_name(int unit);
1450 * Flush write combining store buffers (if present) and perform a write
1453 #if defined(CONFIG_X86_64)
1454 #define qib_flush_wc() asm volatile("sfence" : : : "memory")
1456 #define qib_flush_wc() wmb() /* no reorder around wc flush */
1459 /* global module parameter variables */
1460 extern unsigned qib_ibmtu;
1461 extern ushort qib_cfgctxts;
1462 extern ushort qib_num_cfg_vls;
1463 extern ushort qib_mini_init; /* If set, do few (ideally 0) writes to chip */
1464 extern unsigned qib_n_krcv_queues;
1465 extern unsigned qib_sdma_fetch_arb;
1466 extern unsigned qib_compat_ddr_negotiate;
1467 extern int qib_special_trigger;
1468 extern unsigned qib_numa_aware;
1470 extern struct mutex qib_mutex;
1472 /* Number of seconds before our card status check... */
1473 #define STATUS_TIMEOUT 60
1475 #define QIB_DRV_NAME "ib_qib"
1476 #define QIB_USER_MINOR_BASE 0
1477 #define QIB_TRACE_MINOR 127
1478 #define QIB_DIAGPKT_MINOR 128
1479 #define QIB_DIAG_MINOR_BASE 129
1480 #define QIB_NMINORS 255
1482 #define PCI_VENDOR_ID_PATHSCALE 0x1fc1
1483 #define PCI_VENDOR_ID_QLOGIC 0x1077
1484 #define PCI_DEVICE_ID_QLOGIC_IB_6120 0x10
1485 #define PCI_DEVICE_ID_QLOGIC_IB_7220 0x7220
1486 #define PCI_DEVICE_ID_QLOGIC_IB_7322 0x7322
1489 * qib_early_err is used (only!) to print early errors before devdata is
1490 * allocated, or when dd->pcidev may not be valid, and at the tail end of
1491 * cleanup when devdata may have been freed, etc. qib_dev_porterr is
1492 * the same as qib_dev_err, but is used when the message really needs
1493 * the IB port# to be definitive as to what's happening..
1494 * All of these go to the trace log, and the trace log entry is done
1495 * first to avoid possible serial port delays from printk.
1497 #define qib_early_err(dev, fmt, ...) \
1499 dev_err(dev, fmt, ##__VA_ARGS__); \
1502 #define qib_dev_err(dd, fmt, ...) \
1504 dev_err(&(dd)->pcidev->dev, "%s: " fmt, \
1505 qib_get_unit_name((dd)->unit), ##__VA_ARGS__); \
1508 #define qib_dev_porterr(dd, port, fmt, ...) \
1510 dev_err(&(dd)->pcidev->dev, "%s: IB%u:%u " fmt, \
1511 qib_get_unit_name((dd)->unit), (dd)->unit, (port), \
1515 #define qib_devinfo(pcidev, fmt, ...) \
1517 dev_info(&(pcidev)->dev, fmt, ##__VA_ARGS__); \
1521 * this is used for formatting hw error messages...
1523 struct qib_hwerror_msgs {
1529 #define QLOGIC_IB_HWE_MSG(a, b) { .mask = a, .msg = b }
1531 /* in qib_intr.c... */
1532 void qib_format_hwerrors(u64 hwerrs,
1533 const struct qib_hwerror_msgs *hwerrmsgs,
1534 size_t nhwerrmsgs, char *msg, size_t lmsg);
1535 #endif /* _QIB_KERNEL_H */