1 /* This file is part of the Emulex RoCE Device Driver for
2 * RoCE (RDMA over Converged Ethernet) adapters.
3 * Copyright (C) 2012-2015 Emulex. All rights reserved.
4 * EMULEX and SLI are trademarks of Emulex.
7 * This software is available to you under a choice of one of two licenses.
8 * You may choose to be licensed under the terms of the GNU General Public
9 * License (GPL) Version 2, available from the file COPYING in the main
10 * directory of this source tree, or the BSD license below:
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
16 * - Redistributions of source code must retain the above copyright notice,
17 * this list of conditions and the following disclaimer.
19 * - Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the distribution.
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 * Contact Information:
36 * linux-drivers@emulex.com
40 * Costa Mesa, CA 92626
43 #ifndef __OCRDMA_SLI_H__
44 #define __OCRDMA_SLI_H__
47 OCRDMA_ASIC_GEN_SKH_R = 0x04,
48 OCRDMA_ASIC_GEN_LANCER = 0x0B
52 OCRDMA_ASIC_REV_A0 = 0x00,
53 OCRDMA_ASIC_REV_B0 = 0x10,
54 OCRDMA_ASIC_REV_C0 = 0x20
57 #define OCRDMA_SUBSYS_ROCE 10
59 OCRDMA_CMD_QUERY_CONFIG = 1,
60 OCRDMA_CMD_ALLOC_PD = 2,
61 OCRDMA_CMD_DEALLOC_PD = 3,
63 OCRDMA_CMD_CREATE_AH_TBL = 4,
64 OCRDMA_CMD_DELETE_AH_TBL = 5,
66 OCRDMA_CMD_CREATE_QP = 6,
67 OCRDMA_CMD_QUERY_QP = 7,
68 OCRDMA_CMD_MODIFY_QP = 8 ,
69 OCRDMA_CMD_DELETE_QP = 9,
71 OCRDMA_CMD_RSVD1 = 10,
72 OCRDMA_CMD_ALLOC_LKEY = 11,
73 OCRDMA_CMD_DEALLOC_LKEY = 12,
74 OCRDMA_CMD_REGISTER_NSMR = 13,
75 OCRDMA_CMD_REREGISTER_NSMR = 14,
76 OCRDMA_CMD_REGISTER_NSMR_CONT = 15,
77 OCRDMA_CMD_QUERY_NSMR = 16,
78 OCRDMA_CMD_ALLOC_MW = 17,
79 OCRDMA_CMD_QUERY_MW = 18,
81 OCRDMA_CMD_CREATE_SRQ = 19,
82 OCRDMA_CMD_QUERY_SRQ = 20,
83 OCRDMA_CMD_MODIFY_SRQ = 21,
84 OCRDMA_CMD_DELETE_SRQ = 22,
86 OCRDMA_CMD_ATTACH_MCAST = 23,
87 OCRDMA_CMD_DETACH_MCAST = 24,
89 OCRDMA_CMD_CREATE_RBQ = 25,
90 OCRDMA_CMD_DESTROY_RBQ = 26,
92 OCRDMA_CMD_GET_RDMA_STATS = 27,
93 OCRDMA_CMD_ALLOC_PD_RANGE = 28,
94 OCRDMA_CMD_DEALLOC_PD_RANGE = 29,
99 #define OCRDMA_SUBSYS_COMMON 1
101 OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1 = 5,
102 OCRDMA_CMD_CREATE_CQ = 12,
103 OCRDMA_CMD_CREATE_EQ = 13,
104 OCRDMA_CMD_CREATE_MQ = 21,
105 OCRDMA_CMD_GET_CTRL_ATTRIBUTES = 32,
106 OCRDMA_CMD_GET_FW_VER = 35,
107 OCRDMA_CMD_MODIFY_EQ_DELAY = 41,
108 OCRDMA_CMD_DELETE_MQ = 53,
109 OCRDMA_CMD_DELETE_CQ = 54,
110 OCRDMA_CMD_DELETE_EQ = 55,
111 OCRDMA_CMD_GET_FW_CONFIG = 58,
112 OCRDMA_CMD_CREATE_MQ_EXT = 90,
113 OCRDMA_CMD_PHY_DETAILS = 102
122 #define OCRDMA_MAX_SGID 16
124 #define OCRDMA_MAX_QP 2048
125 #define OCRDMA_MAX_CQ 2048
126 #define OCRDMA_MAX_STAG 16384
129 OCRDMA_DB_RQ_OFFSET = 0xE0,
130 OCRDMA_DB_GEN2_RQ_OFFSET = 0x100,
131 OCRDMA_DB_SQ_OFFSET = 0x60,
132 OCRDMA_DB_GEN2_SQ_OFFSET = 0x1C0,
133 OCRDMA_DB_SRQ_OFFSET = OCRDMA_DB_RQ_OFFSET,
134 OCRDMA_DB_GEN2_SRQ_OFFSET = OCRDMA_DB_GEN2_RQ_OFFSET,
135 OCRDMA_DB_CQ_OFFSET = 0x120,
136 OCRDMA_DB_EQ_OFFSET = OCRDMA_DB_CQ_OFFSET,
137 OCRDMA_DB_MQ_OFFSET = 0x140,
139 OCRDMA_DB_SQ_SHIFT = 16,
140 OCRDMA_DB_RQ_SHIFT = 24
143 #define OCRDMA_ROUDP_FLAGS_SHIFT 0x03
145 #define OCRDMA_DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
146 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK 0x0C00 /* bits 10-11 of qid at 12-11 */
147 /* qid #2 msbits at 12-11 */
148 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT 0x1
149 #define OCRDMA_DB_CQ_NUM_POPPED_SHIFT 16 /* bits 16 - 28 */
151 #define OCRDMA_DB_CQ_REARM_SHIFT 29 /* bit 29 */
153 #define OCRDMA_DB_CQ_SOLICIT_SHIFT 31 /* bit 31 */
155 #define OCRDMA_EQ_ID_MASK 0x1FF /* bits 0 - 8 */
156 #define OCRDMA_EQ_ID_EXT_MASK 0x3e00 /* bits 9-13 */
157 #define OCRDMA_EQ_ID_EXT_MASK_SHIFT 2 /* qid bits 9-13 at 11-15 */
159 /* Clear the interrupt for this eq */
160 #define OCRDMA_EQ_CLR_SHIFT 9 /* bit 9 */
162 #define OCRDMA_EQ_TYPE_SHIFT 10 /* bit 10 */
163 /* Number of event entries processed */
164 #define OCRDMA_NUM_EQE_SHIFT 16 /* bits 16 - 28 */
166 #define OCRDMA_REARM_SHIFT 29 /* bit 29 */
168 #define OCRDMA_MQ_ID_MASK 0x7FF /* bits 0 - 10 */
169 /* Number of entries posted */
170 #define OCRDMA_MQ_NUM_MQE_SHIFT 16 /* bits 16 - 29 */
172 #define OCRDMA_MIN_HPAGE_SIZE 4096
174 #define OCRDMA_MIN_Q_PAGE_SIZE 4096
175 #define OCRDMA_MAX_Q_PAGES 8
177 #define OCRDMA_SLI_ASIC_ID_OFFSET 0x9C
178 #define OCRDMA_SLI_ASIC_REV_MASK 0x000000FF
179 #define OCRDMA_SLI_ASIC_GEN_NUM_MASK 0x0000FF00
180 #define OCRDMA_SLI_ASIC_GEN_NUM_SHIFT 0x08
191 #define OCRDMA_MAX_Q_PAGE_SIZE_CNT 8
192 #define OCRDMA_Q_PAGE_BASE_SIZE (OCRDMA_MIN_Q_PAGE_SIZE * OCRDMA_MAX_Q_PAGES)
194 #define MAX_OCRDMA_QP_PAGES 8
195 #define OCRDMA_MAX_WQE_MEM_SIZE (MAX_OCRDMA_QP_PAGES * OCRDMA_MIN_HQ_PAGE_SIZE)
197 #define OCRDMA_CREATE_CQ_MAX_PAGES 4
198 #define OCRDMA_DPP_CQE_SIZE 4
200 #define OCRDMA_GEN2_MAX_CQE 1024
201 #define OCRDMA_GEN2_CQ_PAGE_SIZE 4096
202 #define OCRDMA_GEN2_WQE_SIZE 256
203 #define OCRDMA_MAX_CQE 4095
204 #define OCRDMA_CQ_PAGE_SIZE 16384
205 #define OCRDMA_WQE_SIZE 128
206 #define OCRDMA_WQE_STRIDE 8
207 #define OCRDMA_WQE_ALIGN_BYTES 16
209 #define MAX_OCRDMA_SRQ_PAGES MAX_OCRDMA_QP_PAGES
212 OCRDMA_MCH_OPCODE_SHIFT = 0,
213 OCRDMA_MCH_OPCODE_MASK = 0xFF,
214 OCRDMA_MCH_SUBSYS_SHIFT = 8,
215 OCRDMA_MCH_SUBSYS_MASK = 0xFF00
218 /* mailbox cmd header */
219 struct ocrdma_mbx_hdr {
221 u32 timeout; /* in seconds */
227 OCRDMA_MBX_RSP_OPCODE_SHIFT = 0,
228 OCRDMA_MBX_RSP_OPCODE_MASK = 0xFF,
229 OCRDMA_MBX_RSP_SUBSYS_SHIFT = 8,
230 OCRDMA_MBX_RSP_SUBSYS_MASK = 0xFF << OCRDMA_MBX_RSP_SUBSYS_SHIFT,
232 OCRDMA_MBX_RSP_STATUS_SHIFT = 0,
233 OCRDMA_MBX_RSP_STATUS_MASK = 0xFF,
234 OCRDMA_MBX_RSP_ASTATUS_SHIFT = 8,
235 OCRDMA_MBX_RSP_ASTATUS_MASK = 0xFF << OCRDMA_MBX_RSP_ASTATUS_SHIFT
238 /* mailbox cmd response */
239 struct ocrdma_mbx_rsp {
247 OCRDMA_MQE_EMBEDDED = 1,
248 OCRDMA_MQE_NONEMBEDDED = 0
251 struct ocrdma_mqe_sge {
258 OCRDMA_MQE_HDR_EMB_SHIFT = 0,
259 OCRDMA_MQE_HDR_EMB_MASK = BIT(0),
260 OCRDMA_MQE_HDR_SGE_CNT_SHIFT = 3,
261 OCRDMA_MQE_HDR_SGE_CNT_MASK = 0x1F << OCRDMA_MQE_HDR_SGE_CNT_SHIFT,
262 OCRDMA_MQE_HDR_SPECIAL_SHIFT = 24,
263 OCRDMA_MQE_HDR_SPECIAL_MASK = 0xFF << OCRDMA_MQE_HDR_SPECIAL_SHIFT
266 struct ocrdma_mqe_hdr {
267 u32 spcl_sge_cnt_emb;
274 struct ocrdma_mqe_emb_cmd {
275 struct ocrdma_mbx_hdr mch;
280 struct ocrdma_mqe_hdr hdr;
282 struct ocrdma_mqe_emb_cmd emb_req;
284 struct ocrdma_mqe_sge sge[19];
287 struct ocrdma_mbx_rsp rsp;
291 #define OCRDMA_EQ_LEN 4096
292 #define OCRDMA_MQ_CQ_LEN 256
293 #define OCRDMA_MQ_LEN 128
295 #define PAGE_SHIFT_4K 12
296 #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
298 /* Returns number of pages spanned by the data starting at the given addr */
299 #define PAGES_4K_SPANNED(_address, size) \
300 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
301 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
303 struct ocrdma_delete_q_req {
304 struct ocrdma_mbx_hdr req;
313 #define MAX_OCRDMA_EQ_PAGES 8
314 struct ocrdma_create_eq_req {
315 struct ocrdma_mbx_hdr req;
321 struct ocrdma_pa pa[MAX_OCRDMA_EQ_PAGES];
325 OCRDMA_CREATE_EQ_VALID = BIT(29),
326 OCRDMA_CREATE_EQ_CNT_SHIFT = 26,
327 OCRDMA_CREATE_CQ_DELAY_SHIFT = 13,
330 struct ocrdma_create_eq_rsp {
331 struct ocrdma_mbx_rsp rsp;
335 #define OCRDMA_EQ_MINOR_OTHER 0x1
337 struct ocrmda_set_eqd {
340 u32 delay_multiplier;
343 struct ocrdma_modify_eqd_cmd {
344 struct ocrdma_mbx_hdr req;
346 struct ocrmda_set_eqd set_eqd[8];
349 struct ocrdma_modify_eqd_req {
350 struct ocrdma_mqe_hdr hdr;
351 struct ocrdma_modify_eqd_cmd cmd;
355 struct ocrdma_modify_eq_delay_rsp {
356 struct ocrdma_mbx_rsp hdr;
361 OCRDMA_MCQE_STATUS_SHIFT = 0,
362 OCRDMA_MCQE_STATUS_MASK = 0xFFFF,
363 OCRDMA_MCQE_ESTATUS_SHIFT = 16,
364 OCRDMA_MCQE_ESTATUS_MASK = 0xFFFF << OCRDMA_MCQE_ESTATUS_SHIFT,
365 OCRDMA_MCQE_CONS_SHIFT = 27,
366 OCRDMA_MCQE_CONS_MASK = BIT(27),
367 OCRDMA_MCQE_CMPL_SHIFT = 28,
368 OCRDMA_MCQE_CMPL_MASK = BIT(28),
369 OCRDMA_MCQE_AE_SHIFT = 30,
370 OCRDMA_MCQE_AE_MASK = BIT(30),
371 OCRDMA_MCQE_VALID_SHIFT = 31,
372 OCRDMA_MCQE_VALID_MASK = BIT(31)
379 u32 valid_ae_cmpl_cons;
383 OCRDMA_AE_MCQE_QPVALID = BIT(31),
384 OCRDMA_AE_MCQE_QPID_MASK = 0xFFFF,
386 OCRDMA_AE_MCQE_CQVALID = BIT(31),
387 OCRDMA_AE_MCQE_CQID_MASK = 0xFFFF,
388 OCRDMA_AE_MCQE_VALID = BIT(31),
389 OCRDMA_AE_MCQE_AE = BIT(30),
390 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT = 16,
391 OCRDMA_AE_MCQE_EVENT_TYPE_MASK =
392 0xFF << OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT,
393 OCRDMA_AE_MCQE_EVENT_CODE_SHIFT = 8,
394 OCRDMA_AE_MCQE_EVENT_CODE_MASK =
395 0xFF << OCRDMA_AE_MCQE_EVENT_CODE_SHIFT
397 struct ocrdma_ae_mcqe {
405 OCRDMA_AE_PVID_MCQE_ENABLED_SHIFT = 0,
406 OCRDMA_AE_PVID_MCQE_ENABLED_MASK = 0xFF,
407 OCRDMA_AE_PVID_MCQE_TAG_SHIFT = 16,
408 OCRDMA_AE_PVID_MCQE_TAG_MASK = 0xFFFF << OCRDMA_AE_PVID_MCQE_TAG_SHIFT
411 struct ocrdma_ae_pvid_mcqe {
419 OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT = 16,
420 OCRDMA_AE_MPA_MCQE_REQ_ID_MASK = 0xFFFF <<
421 OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT,
423 OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT = 8,
424 OCRDMA_AE_MPA_MCQE_EVENT_CODE_MASK = 0xFF <<
425 OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT,
426 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT = 16,
427 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_MASK = 0xFF <<
428 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT,
429 OCRDMA_AE_MPA_MCQE_EVENT_AE_SHIFT = 30,
430 OCRDMA_AE_MPA_MCQE_EVENT_AE_MASK = BIT(30),
431 OCRDMA_AE_MPA_MCQE_EVENT_VALID_SHIFT = 31,
432 OCRDMA_AE_MPA_MCQE_EVENT_VALID_MASK = BIT(31)
435 struct ocrdma_ae_mpa_mcqe {
443 OCRDMA_AE_QP_MCQE_NEW_QP_STATE_SHIFT = 0,
444 OCRDMA_AE_QP_MCQE_NEW_QP_STATE_MASK = 0xFFFF,
445 OCRDMA_AE_QP_MCQE_QP_ID_SHIFT = 16,
446 OCRDMA_AE_QP_MCQE_QP_ID_MASK = 0xFFFF <<
447 OCRDMA_AE_QP_MCQE_QP_ID_SHIFT,
449 OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT = 8,
450 OCRDMA_AE_QP_MCQE_EVENT_CODE_MASK = 0xFF <<
451 OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT,
452 OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT = 16,
453 OCRDMA_AE_QP_MCQE_EVENT_TYPE_MASK = 0xFF <<
454 OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT,
455 OCRDMA_AE_QP_MCQE_EVENT_AE_SHIFT = 30,
456 OCRDMA_AE_QP_MCQE_EVENT_AE_MASK = BIT(30),
457 OCRDMA_AE_QP_MCQE_EVENT_VALID_SHIFT = 31,
458 OCRDMA_AE_QP_MCQE_EVENT_VALID_MASK = BIT(31)
461 struct ocrdma_ae_qp_mcqe {
468 #define OCRDMA_ASYNC_RDMA_EVE_CODE 0x14
469 #define OCRDMA_ASYNC_GRP5_EVE_CODE 0x5
471 enum ocrdma_async_grp5_events {
472 OCRDMA_ASYNC_EVENT_QOS_VALUE = 0x01,
473 OCRDMA_ASYNC_EVENT_COS_VALUE = 0x02,
474 OCRDMA_ASYNC_EVENT_PVID_STATE = 0x03
477 enum OCRDMA_ASYNC_EVENT_TYPE {
478 OCRDMA_CQ_ERROR = 0x00,
479 OCRDMA_CQ_OVERRUN_ERROR = 0x01,
480 OCRDMA_CQ_QPCAT_ERROR = 0x02,
481 OCRDMA_QP_ACCESS_ERROR = 0x03,
482 OCRDMA_QP_COMM_EST_EVENT = 0x04,
483 OCRDMA_SQ_DRAINED_EVENT = 0x05,
484 OCRDMA_DEVICE_FATAL_EVENT = 0x08,
485 OCRDMA_SRQCAT_ERROR = 0x0E,
486 OCRDMA_SRQ_LIMIT_EVENT = 0x0F,
487 OCRDMA_QP_LAST_WQE_EVENT = 0x10,
489 OCRDMA_MAX_ASYNC_ERRORS
492 /* mailbox command request and responses */
494 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT = 2,
495 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK = BIT(2),
496 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT = 3,
497 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK = BIT(3),
498 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT = 8,
499 OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK = 0xFFFFFF <<
500 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT,
502 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT = 16,
503 OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK = 0xFFFF <<
504 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT,
505 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT = 8,
506 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK = 0xFF <<
507 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT,
509 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT = 0,
510 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK = 0xFFFF,
511 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT = 16,
512 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK = 0xFFFF <<
513 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT,
515 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT = 0,
516 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK = 0xFFFF,
517 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT = 16,
518 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK = 0xFFFF <<
519 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT,
521 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET = 24,
522 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK = 0xFF <<
523 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET,
524 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET = 16,
525 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK = 0xFF <<
526 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET,
527 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET = 0,
528 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_MASK = 0xFFFF <<
529 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET,
531 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET = 16,
532 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK = 0xFFFF <<
533 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET,
534 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET = 0,
535 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_MASK = 0xFFFF <<
536 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET,
538 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET = 16,
539 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_MASK = 0xFFFF <<
540 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET,
541 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET = 0,
542 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_MASK = 0xFFFF <<
543 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET,
545 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET = 0,
546 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_MASK = 0xFFFF <<
547 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET,
549 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET = 16,
550 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_MASK = 0xFFFF <<
551 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET,
552 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET = 0,
553 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK = 0xFFFF <<
554 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET,
556 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET = 16,
557 OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK = 0xFFFF <<
558 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET,
559 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET = 0,
560 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK = 0xFFFF <<
561 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET,
563 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET = 16,
564 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_MASK = 0xFFFF <<
565 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET,
566 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET = 0,
567 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK = 0xFFFF <<
568 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET,
571 struct ocrdma_mbx_query_config {
572 struct ocrdma_mqe_hdr hdr;
573 struct ocrdma_mbx_rsp rsp;
574 u32 qp_srq_cq_ird_ord;
575 u32 max_pd_ca_ack_delay;
576 u32 max_write_send_sge;
577 u32 max_ird_ord_per_qp;
578 u32 max_shared_ird_ord;
585 u32 max_pages_per_frmr;
587 u32 max_mcast_qp_attach;
588 u32 max_total_mcast_qp_attach;
589 u32 wqe_rqe_stride_max_dpp_cqs;
590 u32 max_srq_rpir_qps;
591 u32 max_dpp_pds_credits;
592 u32 max_dpp_credits_pds_per_pd;
593 u32 max_wqes_rqes_per_q;
594 u32 max_cq_cqes_per_cq;
598 struct ocrdma_fw_ver_rsp {
599 struct ocrdma_mqe_hdr hdr;
600 struct ocrdma_mbx_rsp rsp;
605 struct ocrdma_fw_conf_rsp {
606 struct ocrdma_mqe_hdr hdr;
607 struct ocrdma_mbx_rsp rsp;
632 OCRDMA_FN_MODE_RDMA = 0x4
636 OCRDMA_IF_TYPE_MASK = 0xFFFF0000,
637 OCRDMA_IF_TYPE_SHIFT = 0x10,
638 OCRDMA_PHY_TYPE_MASK = 0x0000FFFF,
639 OCRDMA_FUTURE_DETAILS_MASK = 0xFFFF0000,
640 OCRDMA_FUTURE_DETAILS_SHIFT = 0x10,
641 OCRDMA_EX_PHY_DETAILS_MASK = 0x0000FFFF,
642 OCRDMA_FSPEED_SUPP_MASK = 0xFFFF0000,
643 OCRDMA_FSPEED_SUPP_SHIFT = 0x10,
644 OCRDMA_ASPEED_SUPP_MASK = 0x0000FFFF
647 struct ocrdma_get_phy_info_rsp {
648 struct ocrdma_mqe_hdr hdr;
649 struct ocrdma_mbx_rsp rsp;
659 OCRDMA_PHY_SPEED_ZERO = 0x0,
660 OCRDMA_PHY_SPEED_10MBPS = 0x1,
661 OCRDMA_PHY_SPEED_100MBPS = 0x2,
662 OCRDMA_PHY_SPEED_1GBPS = 0x4,
663 OCRDMA_PHY_SPEED_10GBPS = 0x8,
664 OCRDMA_PHY_SPEED_40GBPS = 0x20
668 OCRDMA_PORT_NUM_MASK = 0x3F,
669 OCRDMA_PT_MASK = 0xC0,
670 OCRDMA_PT_SHIFT = 0x6,
671 OCRDMA_LINK_DUP_MASK = 0x0000FF00,
672 OCRDMA_LINK_DUP_SHIFT = 0x8,
673 OCRDMA_PHY_PS_MASK = 0x00FF0000,
674 OCRDMA_PHY_PS_SHIFT = 0x10,
675 OCRDMA_PHY_PFLT_MASK = 0xFF000000,
676 OCRDMA_PHY_PFLT_SHIFT = 0x18,
677 OCRDMA_QOS_LNKSP_MASK = 0xFFFF0000,
678 OCRDMA_QOS_LNKSP_SHIFT = 0x10,
679 OCRDMA_LLST_MASK = 0xFF,
680 OCRDMA_PLFC_MASK = 0x00000400,
681 OCRDMA_PLFC_SHIFT = 0x8,
682 OCRDMA_PLRFC_MASK = 0x00000200,
683 OCRDMA_PLRFC_SHIFT = 0x8,
684 OCRDMA_PLTFC_MASK = 0x00000100,
685 OCRDMA_PLTFC_SHIFT = 0x8
688 struct ocrdma_get_link_speed_rsp {
689 struct ocrdma_mqe_hdr hdr;
690 struct ocrdma_mbx_rsp rsp;
692 u32 pflt_pps_ld_pnum;
698 OCRDMA_PHYS_LINK_SPEED_ZERO = 0x0,
699 OCRDMA_PHYS_LINK_SPEED_10MBPS = 0x1,
700 OCRDMA_PHYS_LINK_SPEED_100MBPS = 0x2,
701 OCRDMA_PHYS_LINK_SPEED_1GBPS = 0x3,
702 OCRDMA_PHYS_LINK_SPEED_10GBPS = 0x4,
703 OCRDMA_PHYS_LINK_SPEED_20GBPS = 0x5,
704 OCRDMA_PHYS_LINK_SPEED_25GBPS = 0x6,
705 OCRDMA_PHYS_LINK_SPEED_40GBPS = 0x7,
706 OCRDMA_PHYS_LINK_SPEED_100GBPS = 0x8
710 OCRDMA_CREATE_CQ_VER2 = 2,
711 OCRDMA_CREATE_CQ_VER3 = 3,
713 OCRDMA_CREATE_CQ_PAGE_CNT_MASK = 0xFFFF,
714 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT = 16,
715 OCRDMA_CREATE_CQ_PAGE_SIZE_MASK = 0xFF,
717 OCRDMA_CREATE_CQ_COALESCWM_SHIFT = 12,
718 OCRDMA_CREATE_CQ_COALESCWM_MASK = BIT(13) | BIT(12),
719 OCRDMA_CREATE_CQ_FLAGS_NODELAY = BIT(14),
720 OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID = BIT(15),
722 OCRDMA_CREATE_CQ_EQ_ID_MASK = 0xFFFF,
723 OCRDMA_CREATE_CQ_CQE_COUNT_MASK = 0xFFFF
727 OCRDMA_CREATE_CQ_VER0 = 0,
728 OCRDMA_CREATE_CQ_DPP = 1,
729 OCRDMA_CREATE_CQ_TYPE_SHIFT = 24,
730 OCRDMA_CREATE_CQ_EQID_SHIFT = 22,
732 OCRDMA_CREATE_CQ_CNT_SHIFT = 27,
733 OCRDMA_CREATE_CQ_FLAGS_VALID = BIT(29),
734 OCRDMA_CREATE_CQ_FLAGS_EVENTABLE = BIT(31),
735 OCRDMA_CREATE_CQ_DEF_FLAGS = OCRDMA_CREATE_CQ_FLAGS_VALID |
736 OCRDMA_CREATE_CQ_FLAGS_EVENTABLE |
737 OCRDMA_CREATE_CQ_FLAGS_NODELAY
740 struct ocrdma_create_cq_cmd {
741 struct ocrdma_mbx_hdr req;
747 struct ocrdma_pa pa[OCRDMA_CREATE_CQ_MAX_PAGES];
750 struct ocrdma_create_cq {
751 struct ocrdma_mqe_hdr hdr;
752 struct ocrdma_create_cq_cmd cmd;
756 OCRDMA_CREATE_CQ_CMD_PDID_SHIFT = 0x10
760 OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK = 0xFFFF
763 struct ocrdma_create_cq_cmd_rsp {
764 struct ocrdma_mbx_rsp rsp;
768 struct ocrdma_create_cq_rsp {
769 struct ocrdma_mqe_hdr hdr;
770 struct ocrdma_create_cq_cmd_rsp rsp;
774 OCRDMA_CREATE_MQ_V0_CQ_ID_SHIFT = 22,
775 OCRDMA_CREATE_MQ_CQ_ID_SHIFT = 16,
776 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT = 16,
777 OCRDMA_CREATE_MQ_VALID = BIT(31),
778 OCRDMA_CREATE_MQ_ASYNC_CQ_VALID = BIT(0)
781 struct ocrdma_create_mq_req {
782 struct ocrdma_mbx_hdr req;
784 u32 async_event_bitmap;
785 u32 async_cqid_ringsize;
787 u32 async_cqid_valid;
789 struct ocrdma_pa pa[8];
792 struct ocrdma_create_mq_rsp {
793 struct ocrdma_mbx_rsp rsp;
798 OCRDMA_DESTROY_CQ_QID_SHIFT = 0,
799 OCRDMA_DESTROY_CQ_QID_MASK = 0xFFFF,
800 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT = 16,
801 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_MASK = 0xFFFF <<
802 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT
805 struct ocrdma_destroy_cq {
806 struct ocrdma_mqe_hdr hdr;
807 struct ocrdma_mbx_hdr req;
809 u32 bypass_flush_qid;
812 struct ocrdma_destroy_cq_rsp {
813 struct ocrdma_mqe_hdr hdr;
814 struct ocrdma_mbx_rsp rsp;
824 OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT = 0,
825 OCRDMA_CREATE_QP_REQ_PD_ID_MASK = 0xFFFF,
826 OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT = 16,
827 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT = 19,
828 OCRDMA_CREATE_QP_REQ_QPT_SHIFT = 29,
829 OCRDMA_CREATE_QP_REQ_QPT_MASK = BIT(31) | BIT(30) | BIT(29),
831 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT = 0,
832 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK = 0xFFFF,
833 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT = 16,
834 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK = 0xFFFF <<
835 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT,
837 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT = 0,
838 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK = 0xFFFF,
839 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT = 16,
840 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK = 0xFFFF <<
841 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT,
843 OCRDMA_CREATE_QP_REQ_FMR_EN_SHIFT = 0,
844 OCRDMA_CREATE_QP_REQ_FMR_EN_MASK = BIT(0),
845 OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_SHIFT = 1,
846 OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK = BIT(1),
847 OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_SHIFT = 2,
848 OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK = BIT(2),
849 OCRDMA_CREATE_QP_REQ_INB_WREN_SHIFT = 3,
850 OCRDMA_CREATE_QP_REQ_INB_WREN_MASK = BIT(3),
851 OCRDMA_CREATE_QP_REQ_INB_RDEN_SHIFT = 4,
852 OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK = BIT(4),
853 OCRDMA_CREATE_QP_REQ_USE_SRQ_SHIFT = 5,
854 OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK = BIT(5),
855 OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_SHIFT = 6,
856 OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_MASK = BIT(6),
857 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_SHIFT = 7,
858 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK = BIT(7),
859 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_SHIFT = 8,
860 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_MASK = BIT(8),
861 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT = 16,
862 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK = 0xFFFF <<
863 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT,
865 OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT = 0,
866 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK = 0xFFFF,
867 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT = 16,
868 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK = 0xFFFF <<
869 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT,
871 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT = 0,
872 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK = 0xFFFF,
873 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT = 16,
874 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK = 0xFFFF <<
875 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT,
877 OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT = 0,
878 OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK = 0xFFFF,
879 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT = 16,
880 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK = 0xFFFF <<
881 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT,
883 OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT = 0,
884 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK = 0xFFFF,
885 OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT = 16,
886 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK = 0xFFFF <<
887 OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT,
889 OCRDMA_CREATE_QP_REQ_DPP_CQPID_SHIFT = 0,
890 OCRDMA_CREATE_QP_REQ_DPP_CQPID_MASK = 0xFFFF,
891 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT = 16,
892 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_MASK = 0xFFFF <<
893 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT
897 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT = 16,
898 OCRDMA_CREATE_QP_RSP_DPP_PAGE_SHIFT = 1
901 #define MAX_OCRDMA_IRD_PAGES 4
903 enum ocrdma_qp_flags {
904 OCRDMA_QP_MW_BIND = 1,
905 OCRDMA_QP_LKEY0 = (1 << 1),
906 OCRDMA_QP_FAST_REG = (1 << 2),
907 OCRDMA_QP_INB_RD = (1 << 6),
908 OCRDMA_QP_INB_WR = (1 << 7),
911 enum ocrdma_qp_state {
917 OCRDMA_QPS_SQ_DRAINING = 5,
922 struct ocrdma_create_qp_req {
923 struct ocrdma_mqe_hdr hdr;
924 struct ocrdma_mbx_hdr req;
928 u32 max_sge_send_write;
929 u32 max_sge_recv_flags;
934 struct ocrdma_pa wq_addr[MAX_OCRDMA_QP_PAGES];
935 struct ocrdma_pa rq_addr[MAX_OCRDMA_QP_PAGES];
936 u32 dpp_credits_cqid;
938 struct ocrdma_pa ird_addr[MAX_OCRDMA_IRD_PAGES];
942 OCRDMA_CREATE_QP_RSP_QP_ID_SHIFT = 0,
943 OCRDMA_CREATE_QP_RSP_QP_ID_MASK = 0xFFFF,
945 OCRDMA_CREATE_QP_RSP_MAX_RQE_SHIFT = 0,
946 OCRDMA_CREATE_QP_RSP_MAX_RQE_MASK = 0xFFFF,
947 OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT = 16,
948 OCRDMA_CREATE_QP_RSP_MAX_WQE_MASK = 0xFFFF <<
949 OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT,
951 OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_SHIFT = 0,
952 OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_MASK = 0xFFFF,
953 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT = 16,
954 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_MASK = 0xFFFF <<
955 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT,
957 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT = 16,
958 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_MASK = 0xFFFF <<
959 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT,
961 OCRDMA_CREATE_QP_RSP_MAX_IRD_SHIFT = 0,
962 OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK = 0xFFFF,
963 OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT = 16,
964 OCRDMA_CREATE_QP_RSP_MAX_ORD_MASK = 0xFFFF <<
965 OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT,
967 OCRDMA_CREATE_QP_RSP_RQ_ID_SHIFT = 0,
968 OCRDMA_CREATE_QP_RSP_RQ_ID_MASK = 0xFFFF,
969 OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT = 16,
970 OCRDMA_CREATE_QP_RSP_SQ_ID_MASK = 0xFFFF <<
971 OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT,
973 OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK = BIT(0),
974 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT = 1,
975 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK = 0x7FFF <<
976 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT,
977 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT = 16,
978 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK = 0xFFFF <<
979 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT,
982 struct ocrdma_create_qp_rsp {
983 struct ocrdma_mqe_hdr hdr;
984 struct ocrdma_mbx_rsp rsp;
988 u32 max_sge_send_write;
995 struct ocrdma_destroy_qp {
996 struct ocrdma_mqe_hdr hdr;
997 struct ocrdma_mbx_hdr req;
1001 struct ocrdma_destroy_qp_rsp {
1002 struct ocrdma_mqe_hdr hdr;
1003 struct ocrdma_mbx_rsp rsp;
1007 OCRDMA_MODIFY_QP_ID_SHIFT = 0,
1008 OCRDMA_MODIFY_QP_ID_MASK = 0xFFFF,
1010 OCRDMA_QP_PARA_QPS_VALID = BIT(0),
1011 OCRDMA_QP_PARA_SQD_ASYNC_VALID = BIT(1),
1012 OCRDMA_QP_PARA_PKEY_VALID = BIT(2),
1013 OCRDMA_QP_PARA_QKEY_VALID = BIT(3),
1014 OCRDMA_QP_PARA_PMTU_VALID = BIT(4),
1015 OCRDMA_QP_PARA_ACK_TO_VALID = BIT(5),
1016 OCRDMA_QP_PARA_RETRY_CNT_VALID = BIT(6),
1017 OCRDMA_QP_PARA_RRC_VALID = BIT(7),
1018 OCRDMA_QP_PARA_RQPSN_VALID = BIT(8),
1019 OCRDMA_QP_PARA_MAX_IRD_VALID = BIT(9),
1020 OCRDMA_QP_PARA_MAX_ORD_VALID = BIT(10),
1021 OCRDMA_QP_PARA_RNT_VALID = BIT(11),
1022 OCRDMA_QP_PARA_SQPSN_VALID = BIT(12),
1023 OCRDMA_QP_PARA_DST_QPN_VALID = BIT(13),
1024 OCRDMA_QP_PARA_MAX_WQE_VALID = BIT(14),
1025 OCRDMA_QP_PARA_MAX_RQE_VALID = BIT(15),
1026 OCRDMA_QP_PARA_SGE_SEND_VALID = BIT(16),
1027 OCRDMA_QP_PARA_SGE_RECV_VALID = BIT(17),
1028 OCRDMA_QP_PARA_SGE_WR_VALID = BIT(18),
1029 OCRDMA_QP_PARA_INB_RDEN_VALID = BIT(19),
1030 OCRDMA_QP_PARA_INB_WREN_VALID = BIT(20),
1031 OCRDMA_QP_PARA_FLOW_LBL_VALID = BIT(21),
1032 OCRDMA_QP_PARA_BIND_EN_VALID = BIT(22),
1033 OCRDMA_QP_PARA_ZLKEY_EN_VALID = BIT(23),
1034 OCRDMA_QP_PARA_FMR_EN_VALID = BIT(24),
1035 OCRDMA_QP_PARA_INBAT_EN_VALID = BIT(25),
1036 OCRDMA_QP_PARA_VLAN_EN_VALID = BIT(26),
1038 OCRDMA_MODIFY_QP_FLAGS_RD = BIT(0),
1039 OCRDMA_MODIFY_QP_FLAGS_WR = BIT(1),
1040 OCRDMA_MODIFY_QP_FLAGS_SEND = BIT(2),
1041 OCRDMA_MODIFY_QP_FLAGS_ATOMIC = BIT(3)
1045 OCRDMA_QP_PARAMS_SRQ_ID_SHIFT = 0,
1046 OCRDMA_QP_PARAMS_SRQ_ID_MASK = 0xFFFF,
1048 OCRDMA_QP_PARAMS_MAX_RQE_SHIFT = 0,
1049 OCRDMA_QP_PARAMS_MAX_RQE_MASK = 0xFFFF,
1050 OCRDMA_QP_PARAMS_MAX_WQE_SHIFT = 16,
1051 OCRDMA_QP_PARAMS_MAX_WQE_MASK = 0xFFFF <<
1052 OCRDMA_QP_PARAMS_MAX_WQE_SHIFT,
1054 OCRDMA_QP_PARAMS_MAX_SGE_WRITE_SHIFT = 0,
1055 OCRDMA_QP_PARAMS_MAX_SGE_WRITE_MASK = 0xFFFF,
1056 OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT = 16,
1057 OCRDMA_QP_PARAMS_MAX_SGE_SEND_MASK = 0xFFFF <<
1058 OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT,
1060 OCRDMA_QP_PARAMS_FLAGS_FMR_EN = BIT(0),
1061 OCRDMA_QP_PARAMS_FLAGS_LKEY_0_EN = BIT(1),
1062 OCRDMA_QP_PARAMS_FLAGS_BIND_MW_EN = BIT(2),
1063 OCRDMA_QP_PARAMS_FLAGS_INBWR_EN = BIT(3),
1064 OCRDMA_QP_PARAMS_FLAGS_INBRD_EN = BIT(4),
1065 OCRDMA_QP_PARAMS_STATE_SHIFT = 5,
1066 OCRDMA_QP_PARAMS_STATE_MASK = BIT(5) | BIT(6) | BIT(7),
1067 OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC = BIT(8),
1068 OCRDMA_QP_PARAMS_FLAGS_INB_ATEN = BIT(9),
1069 OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT = 16,
1070 OCRDMA_QP_PARAMS_MAX_SGE_RECV_MASK = 0xFFFF <<
1071 OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT,
1073 OCRDMA_QP_PARAMS_MAX_IRD_SHIFT = 0,
1074 OCRDMA_QP_PARAMS_MAX_IRD_MASK = 0xFFFF,
1075 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT = 16,
1076 OCRDMA_QP_PARAMS_MAX_ORD_MASK = 0xFFFF <<
1077 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT,
1079 OCRDMA_QP_PARAMS_RQ_CQID_SHIFT = 0,
1080 OCRDMA_QP_PARAMS_RQ_CQID_MASK = 0xFFFF,
1081 OCRDMA_QP_PARAMS_WQ_CQID_SHIFT = 16,
1082 OCRDMA_QP_PARAMS_WQ_CQID_MASK = 0xFFFF <<
1083 OCRDMA_QP_PARAMS_WQ_CQID_SHIFT,
1085 OCRDMA_QP_PARAMS_RQ_PSN_SHIFT = 0,
1086 OCRDMA_QP_PARAMS_RQ_PSN_MASK = 0xFFFFFF,
1087 OCRDMA_QP_PARAMS_HOP_LMT_SHIFT = 24,
1088 OCRDMA_QP_PARAMS_HOP_LMT_MASK = 0xFF <<
1089 OCRDMA_QP_PARAMS_HOP_LMT_SHIFT,
1091 OCRDMA_QP_PARAMS_SQ_PSN_SHIFT = 0,
1092 OCRDMA_QP_PARAMS_SQ_PSN_MASK = 0xFFFFFF,
1093 OCRDMA_QP_PARAMS_TCLASS_SHIFT = 24,
1094 OCRDMA_QP_PARAMS_TCLASS_MASK = 0xFF <<
1095 OCRDMA_QP_PARAMS_TCLASS_SHIFT,
1097 OCRDMA_QP_PARAMS_DEST_QPN_SHIFT = 0,
1098 OCRDMA_QP_PARAMS_DEST_QPN_MASK = 0xFFFFFF,
1099 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT = 24,
1100 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK = 0x7 <<
1101 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT,
1102 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT = 27,
1103 OCRDMA_QP_PARAMS_ACK_TIMEOUT_MASK = 0x1F <<
1104 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT,
1106 OCRDMA_QP_PARAMS_PKEY_IDNEX_SHIFT = 0,
1107 OCRDMA_QP_PARAMS_PKEY_INDEX_MASK = 0xFFFF,
1108 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT = 18,
1109 OCRDMA_QP_PARAMS_PATH_MTU_MASK = 0x3FFF <<
1110 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT,
1112 OCRDMA_QP_PARAMS_FLOW_LABEL_SHIFT = 0,
1113 OCRDMA_QP_PARAMS_FLOW_LABEL_MASK = 0xFFFFF,
1114 OCRDMA_QP_PARAMS_SL_SHIFT = 20,
1115 OCRDMA_QP_PARAMS_SL_MASK = 0xF <<
1116 OCRDMA_QP_PARAMS_SL_SHIFT,
1117 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT = 24,
1118 OCRDMA_QP_PARAMS_RETRY_CNT_MASK = 0x7 <<
1119 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT,
1120 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT = 27,
1121 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK = 0x1F <<
1122 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT,
1124 OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_SHIFT = 0,
1125 OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_MASK = 0xFFFF,
1126 OCRDMA_QP_PARAMS_VLAN_SHIFT = 16,
1127 OCRDMA_QP_PARAMS_VLAN_MASK = 0xFFFF <<
1128 OCRDMA_QP_PARAMS_VLAN_SHIFT
1131 struct ocrdma_qp_params {
1134 u32 max_sge_send_write;
1135 u32 max_sge_recv_flags;
1140 u32 ack_to_rnr_rtc_dest_qpn;
1141 u32 path_mtu_pkey_indx;
1146 u32 vlan_dmac_b4_to_b5;
1151 struct ocrdma_modify_qp {
1152 struct ocrdma_mqe_hdr hdr;
1153 struct ocrdma_mbx_hdr req;
1155 struct ocrdma_qp_params params;
1158 u32 num_outstanding_atomic_rd;
1162 OCRDMA_MODIFY_QP_RSP_MAX_RQE_SHIFT = 0,
1163 OCRDMA_MODIFY_QP_RSP_MAX_RQE_MASK = 0xFFFF,
1164 OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT = 16,
1165 OCRDMA_MODIFY_QP_RSP_MAX_WQE_MASK = 0xFFFF <<
1166 OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT,
1168 OCRDMA_MODIFY_QP_RSP_MAX_IRD_SHIFT = 0,
1169 OCRDMA_MODIFY_QP_RSP_MAX_IRD_MASK = 0xFFFF,
1170 OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT = 16,
1171 OCRDMA_MODIFY_QP_RSP_MAX_ORD_MASK = 0xFFFF <<
1172 OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT
1175 struct ocrdma_modify_qp_rsp {
1176 struct ocrdma_mqe_hdr hdr;
1177 struct ocrdma_mbx_rsp rsp;
1183 struct ocrdma_query_qp {
1184 struct ocrdma_mqe_hdr hdr;
1185 struct ocrdma_mbx_hdr req;
1187 #define OCRDMA_QUERY_UP_QP_ID_SHIFT 0
1188 #define OCRDMA_QUERY_UP_QP_ID_MASK 0xFFFFFF
1192 struct ocrdma_query_qp_rsp {
1193 struct ocrdma_mqe_hdr hdr;
1194 struct ocrdma_mbx_rsp rsp;
1195 struct ocrdma_qp_params params;
1196 u32 dpp_credits_cqid;
1201 OCRDMA_CREATE_SRQ_PD_ID_SHIFT = 0,
1202 OCRDMA_CREATE_SRQ_PD_ID_MASK = 0xFFFF,
1203 OCRDMA_CREATE_SRQ_PG_SZ_SHIFT = 16,
1204 OCRDMA_CREATE_SRQ_PG_SZ_MASK = 0x3 <<
1205 OCRDMA_CREATE_SRQ_PG_SZ_SHIFT,
1207 OCRDMA_CREATE_SRQ_MAX_RQE_SHIFT = 0,
1208 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT = 16,
1209 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_MASK = 0xFFFF <<
1210 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT,
1212 OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT = 0,
1213 OCRDMA_CREATE_SRQ_RQE_SIZE_MASK = 0xFFFF,
1214 OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT = 16,
1215 OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_MASK = 0xFFFF <<
1216 OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT
1219 struct ocrdma_create_srq {
1220 struct ocrdma_mqe_hdr hdr;
1221 struct ocrdma_mbx_hdr req;
1226 struct ocrdma_pa rq_addr[MAX_OCRDMA_SRQ_PAGES];
1230 OCRDMA_CREATE_SRQ_RSP_SRQ_ID_SHIFT = 0,
1231 OCRDMA_CREATE_SRQ_RSP_SRQ_ID_MASK = 0xFFFFFF,
1233 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT = 0,
1234 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK = 0xFFFF,
1235 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT = 16,
1236 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK = 0xFFFF <<
1237 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT
1240 struct ocrdma_create_srq_rsp {
1241 struct ocrdma_mqe_hdr hdr;
1242 struct ocrdma_mbx_rsp rsp;
1245 u32 max_sge_rqe_allocated;
1249 OCRDMA_MODIFY_SRQ_ID_SHIFT = 0,
1250 OCRDMA_MODIFY_SRQ_ID_MASK = 0xFFFFFF,
1252 OCRDMA_MODIFY_SRQ_MAX_RQE_SHIFT = 0,
1253 OCRDMA_MODIFY_SRQ_MAX_RQE_MASK = 0xFFFF,
1254 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT = 16,
1255 OCRDMA_MODIFY_SRQ__LIMIT_MASK = 0xFFFF <<
1256 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT
1259 struct ocrdma_modify_srq {
1260 struct ocrdma_mqe_hdr hdr;
1261 struct ocrdma_mbx_rsp rep;
1268 OCRDMA_QUERY_SRQ_ID_SHIFT = 0,
1269 OCRDMA_QUERY_SRQ_ID_MASK = 0xFFFFFF
1272 struct ocrdma_query_srq {
1273 struct ocrdma_mqe_hdr hdr;
1274 struct ocrdma_mbx_rsp req;
1280 OCRDMA_QUERY_SRQ_RSP_PD_ID_SHIFT = 0,
1281 OCRDMA_QUERY_SRQ_RSP_PD_ID_MASK = 0xFFFF,
1282 OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT = 16,
1283 OCRDMA_QUERY_SRQ_RSP_MAX_RQE_MASK = 0xFFFF <<
1284 OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT,
1286 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_SHIFT = 0,
1287 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK = 0xFFFF,
1288 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT = 16,
1289 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_MASK = 0xFFFF <<
1290 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT
1293 struct ocrdma_query_srq_rsp {
1294 struct ocrdma_mqe_hdr hdr;
1295 struct ocrdma_mbx_rsp req;
1298 u32 srq_lmt_max_sge;
1302 OCRDMA_DESTROY_SRQ_ID_SHIFT = 0,
1303 OCRDMA_DESTROY_SRQ_ID_MASK = 0xFFFFFF
1306 struct ocrdma_destroy_srq {
1307 struct ocrdma_mqe_hdr hdr;
1308 struct ocrdma_mbx_rsp req;
1314 OCRDMA_ALLOC_PD_ENABLE_DPP = BIT(16),
1315 OCRDMA_DPP_PAGE_SIZE = 4096
1318 struct ocrdma_alloc_pd {
1319 struct ocrdma_mqe_hdr hdr;
1320 struct ocrdma_mbx_hdr req;
1321 u32 enable_dpp_rsvd;
1325 OCRDMA_ALLOC_PD_RSP_DPP = BIT(16),
1326 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT = 20,
1327 OCRDMA_ALLOC_PD_RSP_PDID_MASK = 0xFFFF,
1330 struct ocrdma_alloc_pd_rsp {
1331 struct ocrdma_mqe_hdr hdr;
1332 struct ocrdma_mbx_rsp rsp;
1336 struct ocrdma_dealloc_pd {
1337 struct ocrdma_mqe_hdr hdr;
1338 struct ocrdma_mbx_hdr req;
1342 struct ocrdma_dealloc_pd_rsp {
1343 struct ocrdma_mqe_hdr hdr;
1344 struct ocrdma_mbx_rsp rsp;
1347 struct ocrdma_alloc_pd_range {
1348 struct ocrdma_mqe_hdr hdr;
1349 struct ocrdma_mbx_hdr req;
1350 u32 enable_dpp_rsvd;
1354 struct ocrdma_alloc_pd_range_rsp {
1355 struct ocrdma_mqe_hdr hdr;
1356 struct ocrdma_mbx_rsp rsp;
1362 OCRDMA_ALLOC_PD_RNG_RSP_START_PDID_MASK = 0xFFFF,
1365 struct ocrdma_dealloc_pd_range {
1366 struct ocrdma_mqe_hdr hdr;
1367 struct ocrdma_mbx_hdr req;
1372 struct ocrdma_dealloc_pd_range_rsp {
1373 struct ocrdma_mqe_hdr hdr;
1374 struct ocrdma_mbx_hdr req;
1379 OCRDMA_ADDR_CHECK_ENABLE = 1,
1380 OCRDMA_ADDR_CHECK_DISABLE = 0
1384 OCRDMA_ALLOC_LKEY_PD_ID_SHIFT = 0,
1385 OCRDMA_ALLOC_LKEY_PD_ID_MASK = 0xFFFF,
1387 OCRDMA_ALLOC_LKEY_ADDR_CHECK_SHIFT = 0,
1388 OCRDMA_ALLOC_LKEY_ADDR_CHECK_MASK = BIT(0),
1389 OCRDMA_ALLOC_LKEY_FMR_SHIFT = 1,
1390 OCRDMA_ALLOC_LKEY_FMR_MASK = BIT(1),
1391 OCRDMA_ALLOC_LKEY_REMOTE_INV_SHIFT = 2,
1392 OCRDMA_ALLOC_LKEY_REMOTE_INV_MASK = BIT(2),
1393 OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT = 3,
1394 OCRDMA_ALLOC_LKEY_REMOTE_WR_MASK = BIT(3),
1395 OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT = 4,
1396 OCRDMA_ALLOC_LKEY_REMOTE_RD_MASK = BIT(4),
1397 OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT = 5,
1398 OCRDMA_ALLOC_LKEY_LOCAL_WR_MASK = BIT(5),
1399 OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_MASK = BIT(6),
1400 OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT = 6,
1401 OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT = 16,
1402 OCRDMA_ALLOC_LKEY_PBL_SIZE_MASK = 0xFFFF <<
1403 OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT
1406 struct ocrdma_alloc_lkey {
1407 struct ocrdma_mqe_hdr hdr;
1408 struct ocrdma_mbx_hdr req;
1414 struct ocrdma_alloc_lkey_rsp {
1415 struct ocrdma_mqe_hdr hdr;
1416 struct ocrdma_mbx_rsp rsp;
1422 struct ocrdma_dealloc_lkey {
1423 struct ocrdma_mqe_hdr hdr;
1424 struct ocrdma_mbx_hdr req;
1430 struct ocrdma_dealloc_lkey_rsp {
1431 struct ocrdma_mqe_hdr hdr;
1432 struct ocrdma_mbx_rsp rsp;
1435 #define MAX_OCRDMA_NSMR_PBL (u32)22
1436 #define MAX_OCRDMA_PBL_SIZE 65536
1437 #define MAX_OCRDMA_PBL_PER_LKEY 32767
1440 OCRDMA_REG_NSMR_LRKEY_INDEX_SHIFT = 0,
1441 OCRDMA_REG_NSMR_LRKEY_INDEX_MASK = 0xFFFFFF,
1442 OCRDMA_REG_NSMR_LRKEY_SHIFT = 24,
1443 OCRDMA_REG_NSMR_LRKEY_MASK = 0xFF <<
1444 OCRDMA_REG_NSMR_LRKEY_SHIFT,
1446 OCRDMA_REG_NSMR_PD_ID_SHIFT = 0,
1447 OCRDMA_REG_NSMR_PD_ID_MASK = 0xFFFF,
1448 OCRDMA_REG_NSMR_NUM_PBL_SHIFT = 16,
1449 OCRDMA_REG_NSMR_NUM_PBL_MASK = 0xFFFF <<
1450 OCRDMA_REG_NSMR_NUM_PBL_SHIFT,
1452 OCRDMA_REG_NSMR_PBE_SIZE_SHIFT = 0,
1453 OCRDMA_REG_NSMR_PBE_SIZE_MASK = 0xFFFF,
1454 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT = 16,
1455 OCRDMA_REG_NSMR_HPAGE_SIZE_MASK = 0xFF <<
1456 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT,
1457 OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT = 24,
1458 OCRDMA_REG_NSMR_BIND_MEMWIN_MASK = BIT(24),
1459 OCRDMA_REG_NSMR_ZB_SHIFT = 25,
1460 OCRDMA_REG_NSMR_ZB_SHIFT_MASK = BIT(25),
1461 OCRDMA_REG_NSMR_REMOTE_INV_SHIFT = 26,
1462 OCRDMA_REG_NSMR_REMOTE_INV_MASK = BIT(26),
1463 OCRDMA_REG_NSMR_REMOTE_WR_SHIFT = 27,
1464 OCRDMA_REG_NSMR_REMOTE_WR_MASK = BIT(27),
1465 OCRDMA_REG_NSMR_REMOTE_RD_SHIFT = 28,
1466 OCRDMA_REG_NSMR_REMOTE_RD_MASK = BIT(28),
1467 OCRDMA_REG_NSMR_LOCAL_WR_SHIFT = 29,
1468 OCRDMA_REG_NSMR_LOCAL_WR_MASK = BIT(29),
1469 OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT = 30,
1470 OCRDMA_REG_NSMR_REMOTE_ATOMIC_MASK = BIT(30),
1471 OCRDMA_REG_NSMR_LAST_SHIFT = 31,
1472 OCRDMA_REG_NSMR_LAST_MASK = BIT(31)
1475 struct ocrdma_reg_nsmr {
1476 struct ocrdma_mqe_hdr hdr;
1477 struct ocrdma_mbx_hdr cmd;
1481 u32 flags_hpage_pbe_sz;
1488 struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL];
1492 OCRDMA_REG_NSMR_CONT_PBL_SHIFT = 0,
1493 OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK = 0xFFFF,
1494 OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT = 16,
1495 OCRDMA_REG_NSMR_CONT_NUM_PBL_MASK = 0xFFFF <<
1496 OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT,
1498 OCRDMA_REG_NSMR_CONT_LAST_SHIFT = 31,
1499 OCRDMA_REG_NSMR_CONT_LAST_MASK = BIT(31)
1502 struct ocrdma_reg_nsmr_cont {
1503 struct ocrdma_mqe_hdr hdr;
1504 struct ocrdma_mbx_hdr cmd;
1510 struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL];
1519 OCRDMA_REG_NSMR_RSP_NUM_PBL_SHIFT = 16,
1520 OCRDMA_REG_NSMR_RSP_NUM_PBL_MASK = 0xFFFF0000
1522 struct ocrdma_reg_nsmr_rsp {
1523 struct ocrdma_mqe_hdr hdr;
1524 struct ocrdma_mbx_rsp rsp;
1531 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_SHIFT = 0,
1532 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_MASK = 0xFFFFFF,
1533 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT = 24,
1534 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_MASK = 0xFF <<
1535 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT,
1537 OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT = 16,
1538 OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_MASK = 0xFFFF <<
1539 OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT
1542 struct ocrdma_reg_nsmr_cont_rsp {
1543 struct ocrdma_mqe_hdr hdr;
1544 struct ocrdma_mbx_rsp rsp;
1546 u32 lrkey_key_index;
1551 OCRDMA_ALLOC_MW_PD_ID_SHIFT = 0,
1552 OCRDMA_ALLOC_MW_PD_ID_MASK = 0xFFFF
1555 struct ocrdma_alloc_mw {
1556 struct ocrdma_mqe_hdr hdr;
1557 struct ocrdma_mbx_hdr req;
1563 OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_SHIFT = 0,
1564 OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_MASK = 0xFFFFFF
1567 struct ocrdma_alloc_mw_rsp {
1568 struct ocrdma_mqe_hdr hdr;
1569 struct ocrdma_mbx_rsp rsp;
1574 struct ocrdma_attach_mcast {
1575 struct ocrdma_mqe_hdr hdr;
1576 struct ocrdma_mbx_hdr req;
1580 u32 vlan_mac_b4_to_b5;
1583 struct ocrdma_attach_mcast_rsp {
1584 struct ocrdma_mqe_hdr hdr;
1585 struct ocrdma_mbx_rsp rsp;
1588 struct ocrdma_detach_mcast {
1589 struct ocrdma_mqe_hdr hdr;
1590 struct ocrdma_mbx_hdr req;
1594 u32 vlan_mac_b4_to_b5;
1597 struct ocrdma_detach_mcast_rsp {
1598 struct ocrdma_mqe_hdr hdr;
1599 struct ocrdma_mbx_rsp rsp;
1603 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT = 19,
1604 OCRDMA_CREATE_AH_NUM_PAGES_MASK = 0xF <<
1605 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT,
1607 OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT = 16,
1608 OCRDMA_CREATE_AH_PAGE_SIZE_MASK = 0x7 <<
1609 OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT,
1611 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT = 23,
1612 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK = 0x1FF <<
1613 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT,
1616 #define OCRDMA_AH_TBL_PAGES 8
1618 struct ocrdma_create_ah_tbl {
1619 struct ocrdma_mqe_hdr hdr;
1620 struct ocrdma_mbx_hdr req;
1623 struct ocrdma_pa tbl_addr[8];
1626 struct ocrdma_create_ah_tbl_rsp {
1627 struct ocrdma_mqe_hdr hdr;
1628 struct ocrdma_mbx_rsp rsp;
1632 struct ocrdma_delete_ah_tbl {
1633 struct ocrdma_mqe_hdr hdr;
1634 struct ocrdma_mbx_hdr req;
1638 struct ocrdma_delete_ah_tbl_rsp {
1639 struct ocrdma_mqe_hdr hdr;
1640 struct ocrdma_mbx_rsp rsp;
1644 OCRDMA_EQE_VALID_SHIFT = 0,
1645 OCRDMA_EQE_VALID_MASK = BIT(0),
1646 OCRDMA_EQE_MAJOR_CODE_MASK = 0x0E,
1647 OCRDMA_EQE_MAJOR_CODE_SHIFT = 0x01,
1648 OCRDMA_EQE_FOR_CQE_MASK = 0xFFFE,
1649 OCRDMA_EQE_RESOURCE_ID_SHIFT = 16,
1650 OCRDMA_EQE_RESOURCE_ID_MASK = 0xFFFF <<
1651 OCRDMA_EQE_RESOURCE_ID_SHIFT,
1655 OCRDMA_MAJOR_CODE_COMPLETION = 0x00,
1656 OCRDMA_MAJOR_CODE_SENTINAL = 0x01
1663 enum OCRDMA_CQE_STATUS {
1664 OCRDMA_CQE_SUCCESS = 0,
1665 OCRDMA_CQE_LOC_LEN_ERR,
1666 OCRDMA_CQE_LOC_QP_OP_ERR,
1667 OCRDMA_CQE_LOC_EEC_OP_ERR,
1668 OCRDMA_CQE_LOC_PROT_ERR,
1669 OCRDMA_CQE_WR_FLUSH_ERR,
1670 OCRDMA_CQE_MW_BIND_ERR,
1671 OCRDMA_CQE_BAD_RESP_ERR,
1672 OCRDMA_CQE_LOC_ACCESS_ERR,
1673 OCRDMA_CQE_REM_INV_REQ_ERR,
1674 OCRDMA_CQE_REM_ACCESS_ERR,
1675 OCRDMA_CQE_REM_OP_ERR,
1676 OCRDMA_CQE_RETRY_EXC_ERR,
1677 OCRDMA_CQE_RNR_RETRY_EXC_ERR,
1678 OCRDMA_CQE_LOC_RDD_VIOL_ERR,
1679 OCRDMA_CQE_REM_INV_RD_REQ_ERR,
1680 OCRDMA_CQE_REM_ABORT_ERR,
1681 OCRDMA_CQE_INV_EECN_ERR,
1682 OCRDMA_CQE_INV_EEC_STATE_ERR,
1683 OCRDMA_CQE_FATAL_ERR,
1684 OCRDMA_CQE_RESP_TIMEOUT_ERR,
1685 OCRDMA_CQE_GENERAL_ERR,
1692 OCRDMA_CQE_WQEIDX_SHIFT = 0,
1693 OCRDMA_CQE_WQEIDX_MASK = 0xFFFF,
1696 OCRDMA_CQE_UD_XFER_LEN_SHIFT = 16,
1697 OCRDMA_CQE_PKEY_SHIFT = 0,
1698 OCRDMA_CQE_PKEY_MASK = 0xFFFF,
1701 OCRDMA_CQE_QPN_SHIFT = 0,
1702 OCRDMA_CQE_QPN_MASK = 0x0000FFFF,
1704 OCRDMA_CQE_BUFTAG_SHIFT = 16,
1705 OCRDMA_CQE_BUFTAG_MASK = 0xFFFF << OCRDMA_CQE_BUFTAG_SHIFT,
1708 OCRDMA_CQE_UD_STATUS_SHIFT = 24,
1709 OCRDMA_CQE_UD_STATUS_MASK = 0x7 << OCRDMA_CQE_UD_STATUS_SHIFT,
1710 OCRDMA_CQE_STATUS_SHIFT = 16,
1711 OCRDMA_CQE_STATUS_MASK = 0xFF << OCRDMA_CQE_STATUS_SHIFT,
1712 OCRDMA_CQE_VALID = BIT(31),
1713 OCRDMA_CQE_INVALIDATE = BIT(30),
1714 OCRDMA_CQE_QTYPE = BIT(29),
1715 OCRDMA_CQE_IMM = BIT(28),
1716 OCRDMA_CQE_WRITE_IMM = BIT(27),
1717 OCRDMA_CQE_QTYPE_SQ = 0,
1718 OCRDMA_CQE_QTYPE_RQ = 1,
1719 OCRDMA_CQE_SRCQP_MASK = 0xFFFFFF
1746 u32 flags_status_srcqpn; /* w3 */
1757 OCRDMA_FLAG_SIG = 0x1,
1758 OCRDMA_FLAG_INV = 0x2,
1759 OCRDMA_FLAG_FENCE_L = 0x4,
1760 OCRDMA_FLAG_FENCE_R = 0x8,
1761 OCRDMA_FLAG_SOLICIT = 0x10,
1762 OCRDMA_FLAG_IMM = 0x20,
1763 OCRDMA_FLAG_AH_VLAN_PR = 0x40,
1766 OCRDMA_LKEY_FLAG_LOCAL_WR = 0x1,
1767 OCRDMA_LKEY_FLAG_REMOTE_RD = 0x2,
1768 OCRDMA_LKEY_FLAG_REMOTE_WR = 0x4,
1769 OCRDMA_LKEY_FLAG_VATO = 0x8,
1772 enum OCRDMA_WQE_OPCODE {
1773 OCRDMA_WRITE = 0x06,
1775 OCRDMA_RESV0 = 0x02,
1777 OCRDMA_CMP_SWP = 0x14,
1778 OCRDMA_BIND_MW = 0x10,
1779 OCRDMA_FR_MR = 0x11,
1780 OCRDMA_RESV1 = 0x0A,
1781 OCRDMA_LKEY_INV = 0x15,
1782 OCRDMA_FETCH_ADD = 0x13,
1783 OCRDMA_POST_RQ = 0x12
1787 OCRDMA_TYPE_INLINE = 0x0,
1788 OCRDMA_TYPE_LKEY = 0x1,
1792 OCRDMA_WQE_OPCODE_SHIFT = 0,
1793 OCRDMA_WQE_OPCODE_MASK = 0x0000001F,
1794 OCRDMA_WQE_FLAGS_SHIFT = 5,
1795 OCRDMA_WQE_TYPE_SHIFT = 16,
1796 OCRDMA_WQE_TYPE_MASK = 0x00030000,
1797 OCRDMA_WQE_SIZE_SHIFT = 18,
1798 OCRDMA_WQE_SIZE_MASK = 0xFF,
1799 OCRDMA_WQE_NXT_WQE_SIZE_SHIFT = 25,
1801 OCRDMA_WQE_LKEY_FLAGS_SHIFT = 0,
1802 OCRDMA_WQE_LKEY_FLAGS_MASK = 0xF
1805 /* header WQE for all the SQ and RQ operations */
1806 struct ocrdma_hdr_wqe {
1810 u32 rsvd_lkey_flags;
1819 struct ocrdma_ewqe_ud_hdr {
1826 /* extended wqe followed by hdr_wqe for Fast Memory register */
1827 struct ocrdma_ewqe_fr {
1838 struct ocrdma_eth_basic {
1844 struct ocrdma_eth_vlan {
1849 #define OCRDMA_ROCE_ETH_TYPE 0x8915
1850 __be16 roce_eth_type;
1855 __be32 pdid_hoplimit;
1861 #define OCRDMA_AV_VALID BIT(7)
1862 #define OCRDMA_AV_VLAN_VALID BIT(1)
1865 struct ocrdma_eth_vlan eth_hdr;
1866 struct ocrdma_grh grh;
1870 struct ocrdma_rsrc_stats {
1884 u32 r64K_to_2M_nsmr;
1885 u32 r2M_to_44M_nsmr;
1886 u32 r44M_to_1G_nsmr;
1888 u32 nsmr_count_4G_to_32G;
1889 u32 r32G_to_64G_nsmr;
1890 u32 r64G_to_128G_nsmr;
1891 u32 r128G_to_higher_nsmr;
1901 struct ocrdma_db_err_stats {
1902 u32 sq_doorbell_errors;
1903 u32 cq_doorbell_errors;
1904 u32 rq_srq_doorbell_errors;
1905 u32 cq_overflow_errors;
1909 struct ocrdma_wqe_stats {
1910 u32 large_send_rc_wqes_lo;
1911 u32 large_send_rc_wqes_hi;
1912 u32 large_write_rc_wqes_lo;
1913 u32 large_write_rc_wqes_hi;
1919 u32 mw_bind_wqes_lo;
1920 u32 mw_bind_wqes_hi;
1921 u32 invalidate_wqes_lo;
1922 u32 invalidate_wqes_hi;
1928 struct ocrdma_tx_stats {
1935 u32 read_rsp_pkts_lo;
1936 u32 read_rsp_pkts_hi;
1943 u32 read_req_bytes_lo;
1944 u32 read_req_bytes_hi;
1945 u32 read_rsp_bytes_lo;
1946 u32 read_rsp_bytes_hi;
1952 struct ocrdma_tx_qp_err_stats {
1953 u32 local_length_errors;
1954 u32 local_protection_errors;
1955 u32 local_qp_operation_errors;
1956 u32 retry_count_exceeded_errors;
1957 u32 rnr_retry_count_exceeded_errors;
1961 struct ocrdma_rx_stats {
1962 u32 roce_frame_bytes_lo;
1963 u32 roce_frame_bytes_hi;
1964 u32 roce_frame_icrc_drops;
1965 u32 roce_frame_payload_len_drops;
1968 u32 psn_error_request_packets;
1969 u32 psn_error_resp_packets;
1970 u32 rnr_nak_timeouts;
1971 u32 rnr_nak_receives;
1972 u32 roce_frame_rxmt_drops;
1973 u32 nak_count_psn_sequence_errors;
1974 u32 rc_drop_count_lookup_errors;
1982 struct ocrdma_rx_qp_err_stats {
1983 u32 nak_invalid_requst_errors;
1984 u32 nak_remote_operation_errors;
1985 u32 nak_count_remote_access_errors;
1986 u32 local_length_errors;
1987 u32 local_protection_errors;
1988 u32 local_qp_operation_errors;
1992 struct ocrdma_tx_dbg_stats {
1996 struct ocrdma_rx_dbg_stats {
2000 struct ocrdma_rdma_stats_req {
2001 struct ocrdma_mbx_hdr hdr;
2006 struct ocrdma_rdma_stats_resp {
2007 struct ocrdma_mbx_hdr hdr;
2008 struct ocrdma_rsrc_stats act_rsrc_stats;
2009 struct ocrdma_rsrc_stats th_rsrc_stats;
2010 struct ocrdma_db_err_stats db_err_stats;
2011 struct ocrdma_wqe_stats wqe_stats;
2012 struct ocrdma_tx_stats tx_stats;
2013 struct ocrdma_tx_qp_err_stats tx_qp_err_stats;
2014 struct ocrdma_rx_stats rx_stats;
2015 struct ocrdma_rx_qp_err_stats rx_qp_err_stats;
2016 struct ocrdma_tx_dbg_stats tx_dbg_stats;
2017 struct ocrdma_rx_dbg_stats rx_dbg_stats;
2021 OCRDMA_HBA_ATTRB_EPROM_VER_LO_MASK = 0xFF,
2022 OCRDMA_HBA_ATTRB_EPROM_VER_HI_MASK = 0xFF00,
2023 OCRDMA_HBA_ATTRB_EPROM_VER_HI_SHIFT = 0x08,
2024 OCRDMA_HBA_ATTRB_CDBLEN_MASK = 0xFFFF,
2025 OCRDMA_HBA_ATTRB_ASIC_REV_MASK = 0xFF0000,
2026 OCRDMA_HBA_ATTRB_ASIC_REV_SHIFT = 0x10,
2027 OCRDMA_HBA_ATTRB_GUID0_MASK = 0xFF000000,
2028 OCRDMA_HBA_ATTRB_GUID0_SHIFT = 0x18,
2029 OCRDMA_HBA_ATTRB_GUID13_MASK = 0xFF,
2030 OCRDMA_HBA_ATTRB_GUID14_MASK = 0xFF00,
2031 OCRDMA_HBA_ATTRB_GUID14_SHIFT = 0x08,
2032 OCRDMA_HBA_ATTRB_GUID15_MASK = 0xFF0000,
2033 OCRDMA_HBA_ATTRB_GUID15_SHIFT = 0x10,
2034 OCRDMA_HBA_ATTRB_PCNT_MASK = 0xFF000000,
2035 OCRDMA_HBA_ATTRB_PCNT_SHIFT = 0x18,
2036 OCRDMA_HBA_ATTRB_LDTOUT_MASK = 0xFFFF,
2037 OCRDMA_HBA_ATTRB_ISCSI_VER_MASK = 0xFF0000,
2038 OCRDMA_HBA_ATTRB_ISCSI_VER_SHIFT = 0x10,
2039 OCRDMA_HBA_ATTRB_MFUNC_DEV_MASK = 0xFF000000,
2040 OCRDMA_HBA_ATTRB_MFUNC_DEV_SHIFT = 0x18,
2041 OCRDMA_HBA_ATTRB_CV_MASK = 0xFF,
2042 OCRDMA_HBA_ATTRB_HBA_ST_MASK = 0xFF00,
2043 OCRDMA_HBA_ATTRB_HBA_ST_SHIFT = 0x08,
2044 OCRDMA_HBA_ATTRB_MAX_DOMS_MASK = 0xFF0000,
2045 OCRDMA_HBA_ATTRB_MAX_DOMS_SHIFT = 0x10,
2046 OCRDMA_HBA_ATTRB_PTNUM_MASK = 0x3F000000,
2047 OCRDMA_HBA_ATTRB_PTNUM_SHIFT = 0x18,
2048 OCRDMA_HBA_ATTRB_PT_MASK = 0xC0000000,
2049 OCRDMA_HBA_ATTRB_PT_SHIFT = 0x1E,
2050 OCRDMA_HBA_ATTRB_ISCSI_FET_MASK = 0xFF,
2051 OCRDMA_HBA_ATTRB_ASIC_GEN_MASK = 0xFF00,
2052 OCRDMA_HBA_ATTRB_ASIC_GEN_SHIFT = 0x08,
2053 OCRDMA_HBA_ATTRB_PCI_VID_MASK = 0xFFFF,
2054 OCRDMA_HBA_ATTRB_PCI_DID_MASK = 0xFFFF0000,
2055 OCRDMA_HBA_ATTRB_PCI_DID_SHIFT = 0x10,
2056 OCRDMA_HBA_ATTRB_PCI_SVID_MASK = 0xFFFF,
2057 OCRDMA_HBA_ATTRB_PCI_SSID_MASK = 0xFFFF0000,
2058 OCRDMA_HBA_ATTRB_PCI_SSID_SHIFT = 0x10,
2059 OCRDMA_HBA_ATTRB_PCI_BUSNUM_MASK = 0xFF,
2060 OCRDMA_HBA_ATTRB_PCI_DEVNUM_MASK = 0xFF00,
2061 OCRDMA_HBA_ATTRB_PCI_DEVNUM_SHIFT = 0x08,
2062 OCRDMA_HBA_ATTRB_PCI_FUNCNUM_MASK = 0xFF0000,
2063 OCRDMA_HBA_ATTRB_PCI_FUNCNUM_SHIFT = 0x10,
2064 OCRDMA_HBA_ATTRB_IF_TYPE_MASK = 0xFF000000,
2065 OCRDMA_HBA_ATTRB_IF_TYPE_SHIFT = 0x18,
2066 OCRDMA_HBA_ATTRB_NETFIL_MASK =0xFF
2069 struct mgmt_hba_attribs {
2070 u8 flashrom_version_string[32];
2071 u8 manufacturer_name[32];
2072 u32 supported_modes;
2073 u32 rsvd_eprom_verhi_verlo;
2076 u8 ncsi_ver_string[12];
2077 u32 default_extended_timeout;
2078 u8 controller_model_number[32];
2079 u8 controller_description[64];
2080 u8 controller_serial_number[32];
2081 u8 ip_version_string[32];
2082 u8 firmware_version_string[32];
2083 u8 bios_version_string[32];
2084 u8 redboot_version_string[32];
2085 u8 driver_version_string[32];
2086 u8 fw_on_flash_version_string[32];
2087 u32 functionalities_supported;
2088 u32 guid0_asicrev_cdblen;
2089 u8 generational_guid[12];
2091 u32 mfuncdev_iscsi_ldtout;
2092 u32 ptpnum_maxdoms_hbast_cv;
2093 u32 firmware_post_status;
2095 u32 res_asicgen_iscsi_feaures;
2099 struct mgmt_controller_attrib {
2100 struct mgmt_hba_attribs hba_attribs;
2103 u32 ityp_fnum_devnum_bnum;
2110 struct ocrdma_get_ctrl_attribs_rsp {
2111 struct ocrdma_mbx_hdr hdr;
2112 struct mgmt_controller_attrib ctrl_attribs;
2115 #define OCRDMA_SUBSYS_DCBX 0x10
2117 enum OCRDMA_DCBX_OPCODE {
2118 OCRDMA_CMD_GET_DCBX_CONFIG = 0x01
2121 enum OCRDMA_DCBX_PARAM_TYPE {
2122 OCRDMA_PARAMETER_TYPE_ADMIN = 0x00,
2123 OCRDMA_PARAMETER_TYPE_OPER = 0x01,
2124 OCRDMA_PARAMETER_TYPE_PEER = 0x02
2127 enum OCRDMA_DCBX_APP_PROTO {
2128 OCRDMA_APP_PROTO_ROCE = 0x8915
2131 enum OCRDMA_DCBX_PROTO {
2132 OCRDMA_PROTO_SELECT_L2 = 0x00,
2133 OCRDMA_PROTO_SELECT_L4 = 0x01
2136 enum OCRDMA_DCBX_APP_PARAM {
2137 OCRDMA_APP_PARAM_APP_PROTO_MASK = 0xFFFF,
2138 OCRDMA_APP_PARAM_PROTO_SEL_MASK = 0xFF,
2139 OCRDMA_APP_PARAM_PROTO_SEL_SHIFT = 0x10,
2140 OCRDMA_APP_PARAM_VALID_MASK = 0xFF,
2141 OCRDMA_APP_PARAM_VALID_SHIFT = 0x18
2144 enum OCRDMA_DCBX_STATE_FLAGS {
2145 OCRDMA_STATE_FLAG_ENABLED = 0x01,
2146 OCRDMA_STATE_FLAG_ADDVERTISED = 0x02,
2147 OCRDMA_STATE_FLAG_WILLING = 0x04,
2148 OCRDMA_STATE_FLAG_SYNC = 0x08,
2149 OCRDMA_STATE_FLAG_UNSUPPORTED = 0x40000000,
2150 OCRDMA_STATE_FLAG_NEG_FAILD = 0x80000000
2153 enum OCRDMA_TCV_AEV_OPV_ST {
2154 OCRDMA_DCBX_TC_SUPPORT_MASK = 0xFF,
2155 OCRDMA_DCBX_TC_SUPPORT_SHIFT = 0x18,
2156 OCRDMA_DCBX_APP_ENTRY_SHIFT = 0x10,
2157 OCRDMA_DCBX_OP_PARAM_SHIFT = 0x08,
2158 OCRDMA_DCBX_STATE_MASK = 0xFF
2161 struct ocrdma_app_parameter {
2162 u32 valid_proto_app;
2167 struct ocrdma_dcbx_cfg {
2177 struct ocrdma_app_parameter app_param[15];
2180 struct ocrdma_get_dcbx_cfg_req {
2181 struct ocrdma_mbx_hdr hdr;
2185 struct ocrdma_get_dcbx_cfg_rsp {
2186 struct ocrdma_mbx_rsp hdr;
2187 struct ocrdma_dcbx_cfg cfg;
2190 #endif /* __OCRDMA_SLI_H__ */