2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006 Cisco Systems, Inc. All rights reserved.
5 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 * $Id: mthca_cq.c 1369 2004-12-20 16:17:07Z roland $
39 #include <linux/init.h>
40 #include <linux/hardirq.h>
44 #include <rdma/ib_pack.h>
46 #include "mthca_dev.h"
47 #include "mthca_cmd.h"
48 #include "mthca_memfree.h"
51 MTHCA_MAX_DIRECT_CQ_SIZE = 4 * PAGE_SIZE
55 MTHCA_CQ_ENTRY_SIZE = 0x20
59 * Must be packed because start is 64 bits but only aligned to 32 bits.
61 struct mthca_cq_context {
64 __be32 logsize_usrpage;
65 __be32 error_eqn; /* Tavor only */
69 __be32 last_notified_index;
70 __be32 solicit_producer_index;
71 __be32 consumer_index;
72 __be32 producer_index;
74 __be32 ci_db; /* Arbel only */
75 __be32 state_db; /* Arbel only */
77 } __attribute__((packed));
79 #define MTHCA_CQ_STATUS_OK ( 0 << 28)
80 #define MTHCA_CQ_STATUS_OVERFLOW ( 9 << 28)
81 #define MTHCA_CQ_STATUS_WRITE_FAIL (10 << 28)
82 #define MTHCA_CQ_FLAG_TR ( 1 << 18)
83 #define MTHCA_CQ_FLAG_OI ( 1 << 17)
84 #define MTHCA_CQ_STATE_DISARMED ( 0 << 8)
85 #define MTHCA_CQ_STATE_ARMED ( 1 << 8)
86 #define MTHCA_CQ_STATE_ARMED_SOL ( 4 << 8)
87 #define MTHCA_EQ_STATE_FIRED (10 << 8)
90 MTHCA_ERROR_CQE_OPCODE_MASK = 0xfe
94 SYNDROME_LOCAL_LENGTH_ERR = 0x01,
95 SYNDROME_LOCAL_QP_OP_ERR = 0x02,
96 SYNDROME_LOCAL_EEC_OP_ERR = 0x03,
97 SYNDROME_LOCAL_PROT_ERR = 0x04,
98 SYNDROME_WR_FLUSH_ERR = 0x05,
99 SYNDROME_MW_BIND_ERR = 0x06,
100 SYNDROME_BAD_RESP_ERR = 0x10,
101 SYNDROME_LOCAL_ACCESS_ERR = 0x11,
102 SYNDROME_REMOTE_INVAL_REQ_ERR = 0x12,
103 SYNDROME_REMOTE_ACCESS_ERR = 0x13,
104 SYNDROME_REMOTE_OP_ERR = 0x14,
105 SYNDROME_RETRY_EXC_ERR = 0x15,
106 SYNDROME_RNR_RETRY_EXC_ERR = 0x16,
107 SYNDROME_LOCAL_RDD_VIOL_ERR = 0x20,
108 SYNDROME_REMOTE_INVAL_RD_REQ_ERR = 0x21,
109 SYNDROME_REMOTE_ABORTED_ERR = 0x22,
110 SYNDROME_INVAL_EECN_ERR = 0x23,
111 SYNDROME_INVAL_EEC_STATE_ERR = 0x24
120 __be32 imm_etype_pkey_eec;
129 struct mthca_err_cqe {
142 #define MTHCA_CQ_ENTRY_OWNER_SW (0 << 7)
143 #define MTHCA_CQ_ENTRY_OWNER_HW (1 << 7)
145 #define MTHCA_TAVOR_CQ_DB_INC_CI (1 << 24)
146 #define MTHCA_TAVOR_CQ_DB_REQ_NOT (2 << 24)
147 #define MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL (3 << 24)
148 #define MTHCA_TAVOR_CQ_DB_SET_CI (4 << 24)
149 #define MTHCA_TAVOR_CQ_DB_REQ_NOT_MULT (5 << 24)
151 #define MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL (1 << 24)
152 #define MTHCA_ARBEL_CQ_DB_REQ_NOT (2 << 24)
153 #define MTHCA_ARBEL_CQ_DB_REQ_NOT_MULT (3 << 24)
155 static inline struct mthca_cqe *get_cqe_from_buf(struct mthca_cq_buf *buf,
159 return buf->queue.direct.buf + (entry * MTHCA_CQ_ENTRY_SIZE);
161 return buf->queue.page_list[entry * MTHCA_CQ_ENTRY_SIZE / PAGE_SIZE].buf
162 + (entry * MTHCA_CQ_ENTRY_SIZE) % PAGE_SIZE;
165 static inline struct mthca_cqe *get_cqe(struct mthca_cq *cq, int entry)
167 return get_cqe_from_buf(&cq->buf, entry);
170 static inline struct mthca_cqe *cqe_sw(struct mthca_cqe *cqe)
172 return MTHCA_CQ_ENTRY_OWNER_HW & cqe->owner ? NULL : cqe;
175 static inline struct mthca_cqe *next_cqe_sw(struct mthca_cq *cq)
177 return cqe_sw(get_cqe(cq, cq->cons_index & cq->ibcq.cqe));
180 static inline void set_cqe_hw(struct mthca_cqe *cqe)
182 cqe->owner = MTHCA_CQ_ENTRY_OWNER_HW;
185 static void dump_cqe(struct mthca_dev *dev, void *cqe_ptr)
187 __be32 *cqe = cqe_ptr;
189 (void) cqe; /* avoid warning if mthca_dbg compiled away... */
190 mthca_dbg(dev, "CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n",
191 be32_to_cpu(cqe[0]), be32_to_cpu(cqe[1]), be32_to_cpu(cqe[2]),
192 be32_to_cpu(cqe[3]), be32_to_cpu(cqe[4]), be32_to_cpu(cqe[5]),
193 be32_to_cpu(cqe[6]), be32_to_cpu(cqe[7]));
197 * incr is ignored in native Arbel (mem-free) mode, so cq->cons_index
198 * should be correct before calling update_cons_index().
200 static inline void update_cons_index(struct mthca_dev *dev, struct mthca_cq *cq,
205 if (mthca_is_memfree(dev)) {
206 *cq->set_ci_db = cpu_to_be32(cq->cons_index);
209 doorbell[0] = cpu_to_be32(MTHCA_TAVOR_CQ_DB_INC_CI | cq->cqn);
210 doorbell[1] = cpu_to_be32(incr - 1);
212 mthca_write64(doorbell,
213 dev->kar + MTHCA_CQ_DOORBELL,
214 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
216 * Make sure doorbells don't leak out of CQ spinlock
217 * and reach the HCA out of order:
223 void mthca_cq_completion(struct mthca_dev *dev, u32 cqn)
227 cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
230 mthca_warn(dev, "Completion event for bogus CQ %08x\n", cqn);
236 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
239 void mthca_cq_event(struct mthca_dev *dev, u32 cqn,
240 enum ib_event_type event_type)
243 struct ib_event event;
245 spin_lock(&dev->cq_table.lock);
247 cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
251 spin_unlock(&dev->cq_table.lock);
254 mthca_warn(dev, "Async event for bogus CQ %08x\n", cqn);
258 event.device = &dev->ib_dev;
259 event.event = event_type;
260 event.element.cq = &cq->ibcq;
261 if (cq->ibcq.event_handler)
262 cq->ibcq.event_handler(&event, cq->ibcq.cq_context);
264 spin_lock(&dev->cq_table.lock);
267 spin_unlock(&dev->cq_table.lock);
270 static inline int is_recv_cqe(struct mthca_cqe *cqe)
272 if ((cqe->opcode & MTHCA_ERROR_CQE_OPCODE_MASK) ==
273 MTHCA_ERROR_CQE_OPCODE_MASK)
274 return !(cqe->opcode & 0x01);
276 return !(cqe->is_send & 0x80);
279 void mthca_cq_clean(struct mthca_dev *dev, struct mthca_cq *cq, u32 qpn,
280 struct mthca_srq *srq)
282 struct mthca_cqe *cqe;
286 spin_lock_irq(&cq->lock);
289 * First we need to find the current producer index, so we
290 * know where to start cleaning from. It doesn't matter if HW
291 * adds new entries after this loop -- the QP we're worried
292 * about is already in RESET, so the new entries won't come
293 * from our QP and therefore don't need to be checked.
295 for (prod_index = cq->cons_index;
296 cqe_sw(get_cqe(cq, prod_index & cq->ibcq.cqe));
298 if (prod_index == cq->cons_index + cq->ibcq.cqe)
302 mthca_dbg(dev, "Cleaning QPN %06x from CQN %06x; ci %d, pi %d\n",
303 qpn, cq->cqn, cq->cons_index, prod_index);
306 * Now sweep backwards through the CQ, removing CQ entries
307 * that match our QP by copying older entries on top of them.
309 while ((int) --prod_index - (int) cq->cons_index >= 0) {
310 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
311 if (cqe->my_qpn == cpu_to_be32(qpn)) {
312 if (srq && is_recv_cqe(cqe))
313 mthca_free_srq_wqe(srq, be32_to_cpu(cqe->wqe));
316 memcpy(get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe),
317 cqe, MTHCA_CQ_ENTRY_SIZE);
322 cq->cons_index += nfreed;
323 update_cons_index(dev, cq, nfreed);
326 spin_unlock_irq(&cq->lock);
329 void mthca_cq_resize_copy_cqes(struct mthca_cq *cq)
334 * In Tavor mode, the hardware keeps the consumer and producer
335 * indices mod the CQ size. Since we might be making the CQ
336 * bigger, we need to deal with the case where the producer
337 * index wrapped around before the CQ was resized.
339 if (!mthca_is_memfree(to_mdev(cq->ibcq.device)) &&
340 cq->ibcq.cqe < cq->resize_buf->cqe) {
341 cq->cons_index &= cq->ibcq.cqe;
342 if (cqe_sw(get_cqe(cq, cq->ibcq.cqe)))
343 cq->cons_index -= cq->ibcq.cqe + 1;
346 for (i = cq->cons_index; cqe_sw(get_cqe(cq, i & cq->ibcq.cqe)); ++i)
347 memcpy(get_cqe_from_buf(&cq->resize_buf->buf,
348 i & cq->resize_buf->cqe),
349 get_cqe(cq, i & cq->ibcq.cqe), MTHCA_CQ_ENTRY_SIZE);
352 int mthca_alloc_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int nent)
357 ret = mthca_buf_alloc(dev, nent * MTHCA_CQ_ENTRY_SIZE,
358 MTHCA_MAX_DIRECT_CQ_SIZE,
359 &buf->queue, &buf->is_direct,
360 &dev->driver_pd, 1, &buf->mr);
364 for (i = 0; i < nent; ++i)
365 set_cqe_hw(get_cqe_from_buf(buf, i));
370 void mthca_free_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int cqe)
372 mthca_buf_free(dev, (cqe + 1) * MTHCA_CQ_ENTRY_SIZE, &buf->queue,
373 buf->is_direct, &buf->mr);
376 static void handle_error_cqe(struct mthca_dev *dev, struct mthca_cq *cq,
377 struct mthca_qp *qp, int wqe_index, int is_send,
378 struct mthca_err_cqe *cqe,
379 struct ib_wc *entry, int *free_cqe)
384 if (cqe->syndrome == SYNDROME_LOCAL_QP_OP_ERR) {
385 mthca_dbg(dev, "local QP operation err "
386 "(QPN %06x, WQE @ %08x, CQN %06x, index %d)\n",
387 be32_to_cpu(cqe->my_qpn), be32_to_cpu(cqe->wqe),
388 cq->cqn, cq->cons_index);
393 * For completions in error, only work request ID, status, vendor error
394 * (and freed resource count for RD) have to be set.
396 switch (cqe->syndrome) {
397 case SYNDROME_LOCAL_LENGTH_ERR:
398 entry->status = IB_WC_LOC_LEN_ERR;
400 case SYNDROME_LOCAL_QP_OP_ERR:
401 entry->status = IB_WC_LOC_QP_OP_ERR;
403 case SYNDROME_LOCAL_EEC_OP_ERR:
404 entry->status = IB_WC_LOC_EEC_OP_ERR;
406 case SYNDROME_LOCAL_PROT_ERR:
407 entry->status = IB_WC_LOC_PROT_ERR;
409 case SYNDROME_WR_FLUSH_ERR:
410 entry->status = IB_WC_WR_FLUSH_ERR;
412 case SYNDROME_MW_BIND_ERR:
413 entry->status = IB_WC_MW_BIND_ERR;
415 case SYNDROME_BAD_RESP_ERR:
416 entry->status = IB_WC_BAD_RESP_ERR;
418 case SYNDROME_LOCAL_ACCESS_ERR:
419 entry->status = IB_WC_LOC_ACCESS_ERR;
421 case SYNDROME_REMOTE_INVAL_REQ_ERR:
422 entry->status = IB_WC_REM_INV_REQ_ERR;
424 case SYNDROME_REMOTE_ACCESS_ERR:
425 entry->status = IB_WC_REM_ACCESS_ERR;
427 case SYNDROME_REMOTE_OP_ERR:
428 entry->status = IB_WC_REM_OP_ERR;
430 case SYNDROME_RETRY_EXC_ERR:
431 entry->status = IB_WC_RETRY_EXC_ERR;
433 case SYNDROME_RNR_RETRY_EXC_ERR:
434 entry->status = IB_WC_RNR_RETRY_EXC_ERR;
436 case SYNDROME_LOCAL_RDD_VIOL_ERR:
437 entry->status = IB_WC_LOC_RDD_VIOL_ERR;
439 case SYNDROME_REMOTE_INVAL_RD_REQ_ERR:
440 entry->status = IB_WC_REM_INV_RD_REQ_ERR;
442 case SYNDROME_REMOTE_ABORTED_ERR:
443 entry->status = IB_WC_REM_ABORT_ERR;
445 case SYNDROME_INVAL_EECN_ERR:
446 entry->status = IB_WC_INV_EECN_ERR;
448 case SYNDROME_INVAL_EEC_STATE_ERR:
449 entry->status = IB_WC_INV_EEC_STATE_ERR;
452 entry->status = IB_WC_GENERAL_ERR;
456 entry->vendor_err = cqe->vendor_err;
459 * Mem-free HCAs always generate one CQE per WQE, even in the
460 * error case, so we don't have to check the doorbell count, etc.
462 if (mthca_is_memfree(dev))
465 mthca_free_err_wqe(dev, qp, is_send, wqe_index, &dbd, &new_wqe);
468 * If we're at the end of the WQE chain, or we've used up our
469 * doorbell count, free the CQE. Otherwise just update it for
470 * the next poll operation.
472 if (!(new_wqe & cpu_to_be32(0x3f)) || (!cqe->db_cnt && dbd))
475 cqe->db_cnt = cpu_to_be16(be16_to_cpu(cqe->db_cnt) - dbd);
477 cqe->syndrome = SYNDROME_WR_FLUSH_ERR;
482 static inline int mthca_poll_one(struct mthca_dev *dev,
484 struct mthca_qp **cur_qp,
489 struct mthca_cqe *cqe;
496 cqe = next_cqe_sw(cq);
501 * Make sure we read CQ entry contents after we've checked the
507 mthca_dbg(dev, "%x/%d: CQE -> QPN %06x, WQE @ %08x\n",
508 cq->cqn, cq->cons_index, be32_to_cpu(cqe->my_qpn),
509 be32_to_cpu(cqe->wqe));
513 is_error = (cqe->opcode & MTHCA_ERROR_CQE_OPCODE_MASK) ==
514 MTHCA_ERROR_CQE_OPCODE_MASK;
515 is_send = is_error ? cqe->opcode & 0x01 : cqe->is_send & 0x80;
517 if (!*cur_qp || be32_to_cpu(cqe->my_qpn) != (*cur_qp)->qpn) {
519 * We do not have to take the QP table lock here,
520 * because CQs will be locked while QPs are removed
523 *cur_qp = mthca_array_get(&dev->qp_table.qp,
524 be32_to_cpu(cqe->my_qpn) &
525 (dev->limits.num_qps - 1));
527 mthca_warn(dev, "CQ entry for unknown QP %06x\n",
528 be32_to_cpu(cqe->my_qpn) & 0xffffff);
534 entry->qp_num = (*cur_qp)->qpn;
538 wqe_index = ((be32_to_cpu(cqe->wqe) - (*cur_qp)->send_wqe_offset)
540 entry->wr_id = (*cur_qp)->wrid[wqe_index +
542 } else if ((*cur_qp)->ibqp.srq) {
543 struct mthca_srq *srq = to_msrq((*cur_qp)->ibqp.srq);
544 u32 wqe = be32_to_cpu(cqe->wqe);
546 wqe_index = wqe >> srq->wqe_shift;
547 entry->wr_id = srq->wrid[wqe_index];
548 mthca_free_srq_wqe(srq, wqe);
552 wqe = be32_to_cpu(cqe->wqe);
553 wqe_index = wqe >> wq->wqe_shift;
555 * WQE addr == base - 1 might be reported in receive completion
556 * with error instead of (rq size - 1) by Sinai FW 1.0.800 and
557 * Arbel FW 5.1.400. This bug should be fixed in later FW revs.
559 if (unlikely(wqe_index < 0))
560 wqe_index = wq->max - 1;
561 entry->wr_id = (*cur_qp)->wrid[wqe_index];
565 if (wq->last_comp < wqe_index)
566 wq->tail += wqe_index - wq->last_comp;
568 wq->tail += wqe_index + wq->max - wq->last_comp;
570 wq->last_comp = wqe_index;
574 handle_error_cqe(dev, cq, *cur_qp, wqe_index, is_send,
575 (struct mthca_err_cqe *) cqe,
582 switch (cqe->opcode) {
583 case MTHCA_OPCODE_RDMA_WRITE:
584 entry->opcode = IB_WC_RDMA_WRITE;
586 case MTHCA_OPCODE_RDMA_WRITE_IMM:
587 entry->opcode = IB_WC_RDMA_WRITE;
588 entry->wc_flags |= IB_WC_WITH_IMM;
590 case MTHCA_OPCODE_SEND:
591 entry->opcode = IB_WC_SEND;
593 case MTHCA_OPCODE_SEND_IMM:
594 entry->opcode = IB_WC_SEND;
595 entry->wc_flags |= IB_WC_WITH_IMM;
597 case MTHCA_OPCODE_RDMA_READ:
598 entry->opcode = IB_WC_RDMA_READ;
599 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
601 case MTHCA_OPCODE_ATOMIC_CS:
602 entry->opcode = IB_WC_COMP_SWAP;
603 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
605 case MTHCA_OPCODE_ATOMIC_FA:
606 entry->opcode = IB_WC_FETCH_ADD;
607 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
609 case MTHCA_OPCODE_BIND_MW:
610 entry->opcode = IB_WC_BIND_MW;
613 entry->opcode = MTHCA_OPCODE_INVALID;
617 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
618 switch (cqe->opcode & 0x1f) {
619 case IB_OPCODE_SEND_LAST_WITH_IMMEDIATE:
620 case IB_OPCODE_SEND_ONLY_WITH_IMMEDIATE:
621 entry->wc_flags = IB_WC_WITH_IMM;
622 entry->imm_data = cqe->imm_etype_pkey_eec;
623 entry->opcode = IB_WC_RECV;
625 case IB_OPCODE_RDMA_WRITE_LAST_WITH_IMMEDIATE:
626 case IB_OPCODE_RDMA_WRITE_ONLY_WITH_IMMEDIATE:
627 entry->wc_flags = IB_WC_WITH_IMM;
628 entry->imm_data = cqe->imm_etype_pkey_eec;
629 entry->opcode = IB_WC_RECV_RDMA_WITH_IMM;
633 entry->opcode = IB_WC_RECV;
636 entry->slid = be16_to_cpu(cqe->rlid);
637 entry->sl = be16_to_cpu(cqe->sl_g_mlpath) >> 12;
638 entry->src_qp = be32_to_cpu(cqe->rqpn) & 0xffffff;
639 entry->dlid_path_bits = be16_to_cpu(cqe->sl_g_mlpath) & 0x7f;
640 entry->pkey_index = be32_to_cpu(cqe->imm_etype_pkey_eec) >> 16;
641 entry->wc_flags |= be16_to_cpu(cqe->sl_g_mlpath) & 0x80 ?
645 entry->status = IB_WC_SUCCESS;
648 if (likely(free_cqe)) {
657 int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
660 struct mthca_dev *dev = to_mdev(ibcq->device);
661 struct mthca_cq *cq = to_mcq(ibcq);
662 struct mthca_qp *qp = NULL;
668 spin_lock_irqsave(&cq->lock, flags);
672 while (npolled < num_entries) {
673 err = mthca_poll_one(dev, cq, &qp,
674 &freed, entry + npolled);
682 update_cons_index(dev, cq, freed);
686 * If a CQ resize is in progress and we discovered that the
687 * old buffer is empty, then peek in the new buffer, and if
688 * it's not empty, switch to the new buffer and continue
691 if (unlikely(err == -EAGAIN && cq->resize_buf &&
692 cq->resize_buf->state == CQ_RESIZE_READY)) {
694 * In Tavor mode, the hardware keeps the producer
695 * index modulo the CQ size. Since we might be making
696 * the CQ bigger, we need to mask our consumer index
697 * using the size of the old CQ buffer before looking
698 * in the new CQ buffer.
700 if (!mthca_is_memfree(dev))
701 cq->cons_index &= cq->ibcq.cqe;
703 if (cqe_sw(get_cqe_from_buf(&cq->resize_buf->buf,
704 cq->cons_index & cq->resize_buf->cqe))) {
705 struct mthca_cq_buf tbuf;
710 cq->buf = cq->resize_buf->buf;
711 cq->ibcq.cqe = cq->resize_buf->cqe;
713 cq->resize_buf->buf = tbuf;
714 cq->resize_buf->cqe = tcqe;
715 cq->resize_buf->state = CQ_RESIZE_SWAPPED;
721 spin_unlock_irqrestore(&cq->lock, flags);
723 return err == 0 || err == -EAGAIN ? npolled : err;
726 int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify)
730 doorbell[0] = cpu_to_be32((notify == IB_CQ_SOLICITED ?
731 MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL :
732 MTHCA_TAVOR_CQ_DB_REQ_NOT) |
734 doorbell[1] = (__force __be32) 0xffffffff;
736 mthca_write64(doorbell,
737 to_mdev(cq->device)->kar + MTHCA_CQ_DOORBELL,
738 MTHCA_GET_DOORBELL_LOCK(&to_mdev(cq->device)->doorbell_lock));
743 int mthca_arbel_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify notify)
745 struct mthca_cq *cq = to_mcq(ibcq);
751 ci = cpu_to_be32(cq->cons_index);
754 doorbell[1] = cpu_to_be32((cq->cqn << 8) | (2 << 5) | (sn << 3) |
755 (notify == IB_CQ_SOLICITED ? 1 : 2));
757 mthca_write_db_rec(doorbell, cq->arm_db);
760 * Make sure that the doorbell record in host memory is
761 * written before ringing the doorbell via PCI MMIO.
765 doorbell[0] = cpu_to_be32((sn << 28) |
766 (notify == IB_CQ_SOLICITED ?
767 MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL :
768 MTHCA_ARBEL_CQ_DB_REQ_NOT) |
772 mthca_write64(doorbell,
773 to_mdev(ibcq->device)->kar + MTHCA_CQ_DOORBELL,
774 MTHCA_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->doorbell_lock));
779 int mthca_init_cq(struct mthca_dev *dev, int nent,
780 struct mthca_ucontext *ctx, u32 pdn,
783 struct mthca_mailbox *mailbox;
784 struct mthca_cq_context *cq_context;
788 cq->ibcq.cqe = nent - 1;
789 cq->is_kernel = !ctx;
791 cq->cqn = mthca_alloc(&dev->cq_table.alloc);
795 if (mthca_is_memfree(dev)) {
796 err = mthca_table_get(dev, dev->cq_table.table, cq->cqn);
805 cq->set_ci_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_SET_CI,
806 cq->cqn, &cq->set_ci_db);
807 if (cq->set_ci_db_index < 0)
810 cq->arm_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_ARM,
811 cq->cqn, &cq->arm_db);
812 if (cq->arm_db_index < 0)
817 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
821 cq_context = mailbox->buf;
824 err = mthca_alloc_cq_buf(dev, &cq->buf, nent);
826 goto err_out_mailbox;
829 spin_lock_init(&cq->lock);
831 init_waitqueue_head(&cq->wait);
832 mutex_init(&cq->mutex);
834 memset(cq_context, 0, sizeof *cq_context);
835 cq_context->flags = cpu_to_be32(MTHCA_CQ_STATUS_OK |
836 MTHCA_CQ_STATE_DISARMED |
838 cq_context->logsize_usrpage = cpu_to_be32((ffs(nent) - 1) << 24);
840 cq_context->logsize_usrpage |= cpu_to_be32(ctx->uar.index);
842 cq_context->logsize_usrpage |= cpu_to_be32(dev->driver_uar.index);
843 cq_context->error_eqn = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn);
844 cq_context->comp_eqn = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_COMP].eqn);
845 cq_context->pd = cpu_to_be32(pdn);
846 cq_context->lkey = cpu_to_be32(cq->buf.mr.ibmr.lkey);
847 cq_context->cqn = cpu_to_be32(cq->cqn);
849 if (mthca_is_memfree(dev)) {
850 cq_context->ci_db = cpu_to_be32(cq->set_ci_db_index);
851 cq_context->state_db = cpu_to_be32(cq->arm_db_index);
854 err = mthca_SW2HW_CQ(dev, mailbox, cq->cqn, &status);
856 mthca_warn(dev, "SW2HW_CQ failed (%d)\n", err);
857 goto err_out_free_mr;
861 mthca_warn(dev, "SW2HW_CQ returned status 0x%02x\n",
864 goto err_out_free_mr;
867 spin_lock_irq(&dev->cq_table.lock);
868 if (mthca_array_set(&dev->cq_table.cq,
869 cq->cqn & (dev->limits.num_cqs - 1),
871 spin_unlock_irq(&dev->cq_table.lock);
872 goto err_out_free_mr;
874 spin_unlock_irq(&dev->cq_table.lock);
878 mthca_free_mailbox(dev, mailbox);
884 mthca_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
887 mthca_free_mailbox(dev, mailbox);
890 if (cq->is_kernel && mthca_is_memfree(dev))
891 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index);
894 if (cq->is_kernel && mthca_is_memfree(dev))
895 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index);
898 mthca_table_put(dev, dev->cq_table.table, cq->cqn);
901 mthca_free(&dev->cq_table.alloc, cq->cqn);
906 static inline int get_cq_refcount(struct mthca_dev *dev, struct mthca_cq *cq)
910 spin_lock_irq(&dev->cq_table.lock);
912 spin_unlock_irq(&dev->cq_table.lock);
917 void mthca_free_cq(struct mthca_dev *dev,
920 struct mthca_mailbox *mailbox;
924 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
925 if (IS_ERR(mailbox)) {
926 mthca_warn(dev, "No memory for mailbox to free CQ.\n");
930 err = mthca_HW2SW_CQ(dev, mailbox, cq->cqn, &status);
932 mthca_warn(dev, "HW2SW_CQ failed (%d)\n", err);
934 mthca_warn(dev, "HW2SW_CQ returned status 0x%02x\n", status);
937 __be32 *ctx = mailbox->buf;
940 printk(KERN_ERR "context for CQN %x (cons index %x, next sw %d)\n",
941 cq->cqn, cq->cons_index,
942 cq->is_kernel ? !!next_cqe_sw(cq) : 0);
943 for (j = 0; j < 16; ++j)
944 printk(KERN_ERR "[%2x] %08x\n", j * 4, be32_to_cpu(ctx[j]));
947 spin_lock_irq(&dev->cq_table.lock);
948 mthca_array_clear(&dev->cq_table.cq,
949 cq->cqn & (dev->limits.num_cqs - 1));
951 spin_unlock_irq(&dev->cq_table.lock);
953 if (dev->mthca_flags & MTHCA_FLAG_MSI_X)
954 synchronize_irq(dev->eq_table.eq[MTHCA_EQ_COMP].msi_x_vector);
956 synchronize_irq(dev->pdev->irq);
958 wait_event(cq->wait, !get_cq_refcount(dev, cq));
961 mthca_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
962 if (mthca_is_memfree(dev)) {
963 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index);
964 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index);
968 mthca_table_put(dev, dev->cq_table.table, cq->cqn);
969 mthca_free(&dev->cq_table.alloc, cq->cqn);
970 mthca_free_mailbox(dev, mailbox);
973 int __devinit mthca_init_cq_table(struct mthca_dev *dev)
977 spin_lock_init(&dev->cq_table.lock);
979 err = mthca_alloc_init(&dev->cq_table.alloc,
982 dev->limits.reserved_cqs);
986 err = mthca_array_init(&dev->cq_table.cq,
987 dev->limits.num_cqs);
989 mthca_alloc_cleanup(&dev->cq_table.alloc);
994 void mthca_cleanup_cq_table(struct mthca_dev *dev)
996 mthca_array_cleanup(&dev->cq_table.cq, dev->limits.num_cqs);
997 mthca_alloc_cleanup(&dev->cq_table.alloc);