drivers/infiniband/hw/mlx5/cq.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/kref.h>
  34 #include <rdma/ib_umem.h>
  35 #include <rdma/ib_user_verbs.h>
  36 #include <rdma/ib_cache.h>
  37 #include "mlx5_ib.h"
  38 #include "user.h"
  39
  40 static void mlx5_ib_cq_comp(struct mlx5_core_cq *cq)
  41 {
  42         struct ib_cq *ibcq = &to_mibcq(cq)->ibcq;
  43
  44         ibcq->comp_handler(ibcq, ibcq->cq_context);
  45 }
  46
  47 static void mlx5_ib_cq_event(struct mlx5_core_cq *mcq, enum mlx5_event type)
  48 {
  49         struct mlx5_ib_cq *cq = container_of(mcq, struct mlx5_ib_cq, mcq);
  50         struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
  51         struct ib_cq *ibcq = &cq->ibcq;
  52         struct ib_event event;
  53
  54         if (type != MLX5_EVENT_TYPE_CQ_ERROR) {
  55                 mlx5_ib_warn(dev, "Unexpected event type %d on CQ %06x\n",
  56                              type, mcq->cqn);
  57                 return;
  58         }
  59
  60         if (ibcq->event_handler) {
  61                 event.device     = &dev->ib_dev;
  62                 event.event      = IB_EVENT_CQ_ERR;
  63                 event.element.cq = ibcq;
  64                 ibcq->event_handler(&event, ibcq->cq_context);
  65         }
  66 }
  67
  68 static void *get_cqe_from_buf(struct mlx5_ib_cq_buf *buf, int n, int size)
  69 {
  70         return mlx5_buf_offset(&buf->buf, n * size);
  71 }
  72
  73 static void *get_cqe(struct mlx5_ib_cq *cq, int n)
  74 {
  75         return get_cqe_from_buf(&cq->buf, n, cq->mcq.cqe_sz);
  76 }
  77
  78 static u8 sw_ownership_bit(int n, int nent)
  79 {
  80         return (n & nent) ? 1 : 0;
  81 }
  82
  83 static void *get_sw_cqe(struct mlx5_ib_cq *cq, int n)
  84 {
  85         void *cqe = get_cqe(cq, n & cq->ibcq.cqe);
  86         struct mlx5_cqe64 *cqe64;
  87
  88         cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
  89
  90         if (likely((cqe64->op_own) >> 4 != MLX5_CQE_INVALID) &&
  91             !((cqe64->op_own & MLX5_CQE_OWNER_MASK) ^ !!(n & (cq->ibcq.cqe + 1)))) {
  92                 return cqe;
  93         } else {
  94                 return NULL;
  95         }
  96 }
  97
  98 static void *next_cqe_sw(struct mlx5_ib_cq *cq)
  99 {
 100         return get_sw_cqe(cq, cq->mcq.cons_index);
 101 }
 102
 103 static enum ib_wc_opcode get_umr_comp(struct mlx5_ib_wq *wq, int idx)
 104 {
 105         switch (wq->wr_data[idx]) {
 106         case MLX5_IB_WR_UMR:
 107                 return 0;
 108
 109         case IB_WR_LOCAL_INV:
 110                 return IB_WC_LOCAL_INV;
 111
 112         case IB_WR_REG_MR:
 113                 return IB_WC_REG_MR;
 114
 115         default:
 116                 pr_warn("unknown completion status\n");
 117                 return 0;
 118         }
 119 }
 120
 121 static void handle_good_req(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
 122                             struct mlx5_ib_wq *wq, int idx)
 123 {
 124         wc->wc_flags = 0;
 125         switch (be32_to_cpu(cqe->sop_drop_qpn) >> 24) {
 126         case MLX5_OPCODE_RDMA_WRITE_IMM:
 127                 wc->wc_flags |= IB_WC_WITH_IMM;
 128         case MLX5_OPCODE_RDMA_WRITE:
 129                 wc->opcode    = IB_WC_RDMA_WRITE;
 130                 break;
 131         case MLX5_OPCODE_SEND_IMM:
 132                 wc->wc_flags |= IB_WC_WITH_IMM;
 133         case MLX5_OPCODE_SEND:
 134         case MLX5_OPCODE_SEND_INVAL:
 135                 wc->opcode    = IB_WC_SEND;
 136                 break;
 137         case MLX5_OPCODE_RDMA_READ:
 138                 wc->opcode    = IB_WC_RDMA_READ;
 139                 wc->byte_len  = be32_to_cpu(cqe->byte_cnt);
 140                 break;
 141         case MLX5_OPCODE_ATOMIC_CS:
 142                 wc->opcode    = IB_WC_COMP_SWAP;
 143                 wc->byte_len  = 8;
 144                 break;
 145         case MLX5_OPCODE_ATOMIC_FA:
 146                 wc->opcode    = IB_WC_FETCH_ADD;
 147                 wc->byte_len  = 8;
 148                 break;
 149         case MLX5_OPCODE_ATOMIC_MASKED_CS:
 150                 wc->opcode    = IB_WC_MASKED_COMP_SWAP;
 151                 wc->byte_len  = 8;
 152                 break;
 153         case MLX5_OPCODE_ATOMIC_MASKED_FA:
 154                 wc->opcode    = IB_WC_MASKED_FETCH_ADD;
 155                 wc->byte_len  = 8;
 156                 break;
 157         case MLX5_OPCODE_BIND_MW:
 158                 wc->opcode    = IB_WC_BIND_MW;
 159                 break;
 160         case MLX5_OPCODE_UMR:
 161                 wc->opcode = get_umr_comp(wq, idx);
 162                 break;
 163         }
 164 }
 165
 166 enum {
 167         MLX5_GRH_IN_BUFFER = 1,
 168         MLX5_GRH_IN_CQE    = 2,
 169 };
 170
 171 static void handle_responder(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
 172                              struct mlx5_ib_qp *qp)
 173 {
 174         struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
 175         struct mlx5_ib_srq *srq;
 176         struct mlx5_ib_wq *wq;
 177         u16 wqe_ctr;
 178         u8 g;
 179
 180         if (qp->ibqp.srq || qp->ibqp.xrcd) {
 181                 struct mlx5_core_srq *msrq = NULL;
 182
 183                 if (qp->ibqp.xrcd) {
 184                         msrq = mlx5_core_get_srq(dev->mdev,
 185                                                  be32_to_cpu(cqe->srqn));
 186                         srq = to_mibsrq(msrq);
 187                 } else {
 188                         srq = to_msrq(qp->ibqp.srq);
 189                 }
 190                 if (srq) {
 191                         wqe_ctr = be16_to_cpu(cqe->wqe_counter);
 192                         wc->wr_id = srq->wrid[wqe_ctr];
 193                         mlx5_ib_free_srq_wqe(srq, wqe_ctr);
 194                         if (msrq && atomic_dec_and_test(&msrq->refcount))
 195                                 complete(&msrq->free);
 196                 }
 197         } else {
 198                 wq        = &qp->rq;
 199                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
 200                 ++wq->tail;
 201         }
 202         wc->byte_len = be32_to_cpu(cqe->byte_cnt);
 203
 204         switch (cqe->op_own >> 4) {
 205         case MLX5_CQE_RESP_WR_IMM:
 206                 wc->opcode      = IB_WC_RECV_RDMA_WITH_IMM;
 207                 wc->wc_flags    = IB_WC_WITH_IMM;
 208                 wc->ex.imm_data = cqe->imm_inval_pkey;
 209                 break;
 210         case MLX5_CQE_RESP_SEND:
 211                 wc->opcode   = IB_WC_RECV;
 212                 wc->wc_flags = 0;
 213                 break;
 214         case MLX5_CQE_RESP_SEND_IMM:
 215                 wc->opcode      = IB_WC_RECV;
 216                 wc->wc_flags    = IB_WC_WITH_IMM;
 217                 wc->ex.imm_data = cqe->imm_inval_pkey;
 218                 break;
 219         case MLX5_CQE_RESP_SEND_INV:
 220                 wc->opcode      = IB_WC_RECV;
 221                 wc->wc_flags    = IB_WC_WITH_INVALIDATE;
 222                 wc->ex.invalidate_rkey = be32_to_cpu(cqe->imm_inval_pkey);
 223                 break;
 224         }
 225         wc->slid           = be16_to_cpu(cqe->slid);
 226         wc->sl             = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0xf;
 227         wc->src_qp         = be32_to_cpu(cqe->flags_rqpn) & 0xffffff;
 228         wc->dlid_path_bits = cqe->ml_path;
 229         g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
 230         wc->wc_flags |= g ? IB_WC_GRH : 0;
 231         if (unlikely(is_qp1(qp->ibqp.qp_type))) {
 232                 u16 pkey = be32_to_cpu(cqe->imm_inval_pkey) & 0xffff;
 233
 234                 ib_find_cached_pkey(&dev->ib_dev, qp->port, pkey,
 235                                     &wc->pkey_index);
 236         } else {
 237                 wc->pkey_index = 0;
 238         }
 239 }
 240
 241 static void dump_cqe(struct mlx5_ib_dev *dev, struct mlx5_err_cqe *cqe)
 242 {
 243         __be32 *p = (__be32 *)cqe;
 244         int i;
 245
 246         mlx5_ib_warn(dev, "dump error cqe\n");
 247         for (i = 0; i < sizeof(*cqe) / 16; i++, p += 4)
 248                 pr_info("%08x %08x %08x %08x\n", be32_to_cpu(p[0]),
 249                         be32_to_cpu(p[1]), be32_to_cpu(p[2]),
 250                         be32_to_cpu(p[3]));
 251 }
 252
 253 static void mlx5_handle_error_cqe(struct mlx5_ib_dev *dev,
 254                                   struct mlx5_err_cqe *cqe,
 255                                   struct ib_wc *wc)
 256 {
 257         int dump = 1;
 258
 259         switch (cqe->syndrome) {
 260         case MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR:
 261                 wc->status = IB_WC_LOC_LEN_ERR;
 262                 break;
 263         case MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR:
 264                 wc->status = IB_WC_LOC_QP_OP_ERR;
 265                 break;
 266         case MLX5_CQE_SYNDROME_LOCAL_PROT_ERR:
 267                 wc->status = IB_WC_LOC_PROT_ERR;
 268                 break;
 269         case MLX5_CQE_SYNDROME_WR_FLUSH_ERR:
 270                 dump = 0;
 271                 wc->status = IB_WC_WR_FLUSH_ERR;
 272                 break;
 273         case MLX5_CQE_SYNDROME_MW_BIND_ERR:
 274                 wc->status = IB_WC_MW_BIND_ERR;
 275                 break;
 276         case MLX5_CQE_SYNDROME_BAD_RESP_ERR:
 277                 wc->status = IB_WC_BAD_RESP_ERR;
 278                 break;
 279         case MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR:
 280                 wc->status = IB_WC_LOC_ACCESS_ERR;
 281                 break;
 282         case MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
 283                 wc->status = IB_WC_REM_INV_REQ_ERR;
 284                 break;
 285         case MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR:
 286                 wc->status = IB_WC_REM_ACCESS_ERR;
 287                 break;
 288         case MLX5_CQE_SYNDROME_REMOTE_OP_ERR:
 289                 wc->status = IB_WC_REM_OP_ERR;
 290                 break;
 291         case MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
 292                 wc->status = IB_WC_RETRY_EXC_ERR;
 293                 dump = 0;
 294                 break;
 295         case MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
 296                 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
 297                 dump = 0;
 298                 break;
 299         case MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR:
 300                 wc->status = IB_WC_REM_ABORT_ERR;
 301                 break;
 302         default:
 303                 wc->status = IB_WC_GENERAL_ERR;
 304                 break;
 305         }
 306
 307         wc->vendor_err = cqe->vendor_err_synd;
 308         if (dump)
 309                 dump_cqe(dev, cqe);
 310 }
 311
 312 static int is_atomic_response(struct mlx5_ib_qp *qp, uint16_t idx)
 313 {
 314         /* TBD: waiting decision
 315         */
 316         return 0;
 317 }
 318
 319 static void *mlx5_get_atomic_laddr(struct mlx5_ib_qp *qp, uint16_t idx)
 320 {
 321         struct mlx5_wqe_data_seg *dpseg;
 322         void *addr;
 323
 324         dpseg = mlx5_get_send_wqe(qp, idx) + sizeof(struct mlx5_wqe_ctrl_seg) +
 325                 sizeof(struct mlx5_wqe_raddr_seg) +
 326                 sizeof(struct mlx5_wqe_atomic_seg);
 327         addr = (void *)(unsigned long)be64_to_cpu(dpseg->addr);
 328         return addr;
 329 }
 330
 331 static void handle_atomic(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64,
 332                           uint16_t idx)
 333 {
 334         void *addr;
 335         int byte_count;
 336         int i;
 337
 338         if (!is_atomic_response(qp, idx))
 339                 return;
 340
 341         byte_count = be32_to_cpu(cqe64->byte_cnt);
 342         addr = mlx5_get_atomic_laddr(qp, idx);
 343
 344         if (byte_count == 4) {
 345                 *(uint32_t *)addr = be32_to_cpu(*((__be32 *)addr));
 346         } else {
 347                 for (i = 0; i < byte_count; i += 8) {
 348                         *(uint64_t *)addr = be64_to_cpu(*((__be64 *)addr));
 349                         addr += 8;
 350                 }
 351         }
 352
 353         return;
 354 }
 355
 356 static void handle_atomics(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64,
 357                            u16 tail, u16 head)
 358 {
 359         u16 idx;
 360
 361         do {
 362                 idx = tail & (qp->sq.wqe_cnt - 1);
 363                 handle_atomic(qp, cqe64, idx);
 364                 if (idx == head)
 365                         break;
 366
 367                 tail = qp->sq.w_list[idx].next;
 368         } while (1);
 369         tail = qp->sq.w_list[idx].next;
 370         qp->sq.last_poll = tail;
 371 }
 372
 373 static void free_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf)
 374 {
 375         mlx5_buf_free(dev->mdev, &buf->buf);
 376 }
 377
 378 static void get_sig_err_item(struct mlx5_sig_err_cqe *cqe,
 379                              struct ib_sig_err *item)
 380 {
 381         u16 syndrome = be16_to_cpu(cqe->syndrome);
 382
 383 #define GUARD_ERR   (1 << 13)
 384 #define APPTAG_ERR  (1 << 12)
 385 #define REFTAG_ERR  (1 << 11)
 386
 387         if (syndrome & GUARD_ERR) {
 388                 item->err_type = IB_SIG_BAD_GUARD;
 389                 item->expected = be32_to_cpu(cqe->expected_trans_sig) >> 16;
 390                 item->actual = be32_to_cpu(cqe->actual_trans_sig) >> 16;
 391         } else
 392         if (syndrome & REFTAG_ERR) {
 393                 item->err_type = IB_SIG_BAD_REFTAG;
 394                 item->expected = be32_to_cpu(cqe->expected_reftag);
 395                 item->actual = be32_to_cpu(cqe->actual_reftag);
 396         } else
 397         if (syndrome & APPTAG_ERR) {
 398                 item->err_type = IB_SIG_BAD_APPTAG;
 399                 item->expected = be32_to_cpu(cqe->expected_trans_sig) & 0xffff;
 400                 item->actual = be32_to_cpu(cqe->actual_trans_sig) & 0xffff;
 401         } else {
 402                 pr_err("Got signature completion error with bad syndrome %04x\n",
 403                        syndrome);
 404         }
 405
 406         item->sig_err_offset = be64_to_cpu(cqe->err_offset);
 407         item->key = be32_to_cpu(cqe->mkey);
 408 }
 409
 410 static int mlx5_poll_one(struct mlx5_ib_cq *cq,
 411                          struct mlx5_ib_qp **cur_qp,
 412                          struct ib_wc *wc)
 413 {
 414         struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
 415         struct mlx5_err_cqe *err_cqe;
 416         struct mlx5_cqe64 *cqe64;
 417         struct mlx5_core_qp *mqp;
 418         struct mlx5_ib_wq *wq;
 419         struct mlx5_sig_err_cqe *sig_err_cqe;
 420         struct mlx5_core_mr *mmr;
 421         struct mlx5_ib_mr *mr;
 422         uint8_t opcode;
 423         uint32_t qpn;
 424         u16 wqe_ctr;
 425         void *cqe;
 426         int idx;
 427
 428 repoll:
 429         cqe = next_cqe_sw(cq);
 430         if (!cqe)
 431                 return -EAGAIN;
 432
 433         cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
 434
 435         ++cq->mcq.cons_index;
 436
 437         /* Make sure we read CQ entry contents after we've checked the
 438          * ownership bit.
 439          */
 440         rmb();
 441
 442         opcode = cqe64->op_own >> 4;
 443         if (unlikely(opcode == MLX5_CQE_RESIZE_CQ)) {
 444                 if (likely(cq->resize_buf)) {
 445                         free_cq_buf(dev, &cq->buf);
 446                         cq->buf = *cq->resize_buf;
 447                         kfree(cq->resize_buf);
 448                         cq->resize_buf = NULL;
 449                         goto repoll;
 450                 } else {
 451                         mlx5_ib_warn(dev, "unexpected resize cqe\n");
 452                 }
 453         }
 454
 455         qpn = ntohl(cqe64->sop_drop_qpn) & 0xffffff;
 456         if (!*cur_qp || (qpn != (*cur_qp)->ibqp.qp_num)) {
 457                 /* We do not have to take the QP table lock here,
 458                  * because CQs will be locked while QPs are removed
 459                  * from the table.
 460                  */
 461                 mqp = __mlx5_qp_lookup(dev->mdev, qpn);
 462                 if (unlikely(!mqp)) {
 463                         mlx5_ib_warn(dev, "CQE@CQ %06x for unknown QPN %6x\n",
 464                                      cq->mcq.cqn, qpn);
 465                         return -EINVAL;
 466                 }
 467
 468                 *cur_qp = to_mibqp(mqp);
 469         }
 470
 471         wc->qp  = &(*cur_qp)->ibqp;
 472         switch (opcode) {
 473         case MLX5_CQE_REQ:
 474                 wq = &(*cur_qp)->sq;
 475                 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
 476                 idx = wqe_ctr & (wq->wqe_cnt - 1);
 477                 handle_good_req(wc, cqe64, wq, idx);
 478                 handle_atomics(*cur_qp, cqe64, wq->last_poll, idx);
 479                 wc->wr_id = wq->wrid[idx];
 480                 wq->tail = wq->wqe_head[idx] + 1;
 481                 wc->status = IB_WC_SUCCESS;
 482                 break;
 483         case MLX5_CQE_RESP_WR_IMM:
 484         case MLX5_CQE_RESP_SEND:
 485         case MLX5_CQE_RESP_SEND_IMM:
 486         case MLX5_CQE_RESP_SEND_INV:
 487                 handle_responder(wc, cqe64, *cur_qp);
 488                 wc->status = IB_WC_SUCCESS;
 489                 break;
 490         case MLX5_CQE_RESIZE_CQ:
 491                 break;
 492         case MLX5_CQE_REQ_ERR:
 493         case MLX5_CQE_RESP_ERR:
 494                 err_cqe = (struct mlx5_err_cqe *)cqe64;
 495                 mlx5_handle_error_cqe(dev, err_cqe, wc);
 496                 mlx5_ib_dbg(dev, "%s error cqe on cqn 0x%x:\n",
 497                             opcode == MLX5_CQE_REQ_ERR ?
 498                             "Requestor" : "Responder", cq->mcq.cqn);
 499                 mlx5_ib_dbg(dev, "syndrome 0x%x, vendor syndrome 0x%x\n",
 500                             err_cqe->syndrome, err_cqe->vendor_err_synd);
 501                 if (opcode == MLX5_CQE_REQ_ERR) {
 502                         wq = &(*cur_qp)->sq;
 503                         wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
 504                         idx = wqe_ctr & (wq->wqe_cnt - 1);
 505                         wc->wr_id = wq->wrid[idx];
 506                         wq->tail = wq->wqe_head[idx] + 1;
 507                 } else {
 508                         struct mlx5_ib_srq *srq;
 509
 510                         if ((*cur_qp)->ibqp.srq) {
 511                                 srq = to_msrq((*cur_qp)->ibqp.srq);
 512                                 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
 513                                 wc->wr_id = srq->wrid[wqe_ctr];
 514                                 mlx5_ib_free_srq_wqe(srq, wqe_ctr);
 515                         } else {
 516                                 wq = &(*cur_qp)->rq;
 517                                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
 518                                 ++wq->tail;
 519                         }
 520                 }
 521                 break;
 522         case MLX5_CQE_SIG_ERR:
 523                 sig_err_cqe = (struct mlx5_sig_err_cqe *)cqe64;
 524
 525                 read_lock(&dev->mdev->priv.mr_table.lock);
 526                 mmr = __mlx5_mr_lookup(dev->mdev,
 527                                        mlx5_base_mkey(be32_to_cpu(sig_err_cqe->mkey)));
 528                 if (unlikely(!mmr)) {
 529                         read_unlock(&dev->mdev->priv.mr_table.lock);
 530                         mlx5_ib_warn(dev, "CQE@CQ %06x for unknown MR %6x\n",
 531                                      cq->mcq.cqn, be32_to_cpu(sig_err_cqe->mkey));
 532                         return -EINVAL;
 533                 }
 534
 535                 mr = to_mibmr(mmr);
 536                 get_sig_err_item(sig_err_cqe, &mr->sig->err_item);
 537                 mr->sig->sig_err_exists = true;
 538                 mr->sig->sigerr_count++;
 539
 540                 mlx5_ib_warn(dev, "CQN: 0x%x Got SIGERR on key: 0x%x err_type %x err_offset %llx expected %x actual %x\n",
 541                              cq->mcq.cqn, mr->sig->err_item.key,
 542                              mr->sig->err_item.err_type,
 543                              mr->sig->err_item.sig_err_offset,
 544                              mr->sig->err_item.expected,
 545                              mr->sig->err_item.actual);
 546
 547                 read_unlock(&dev->mdev->priv.mr_table.lock);
 548                 goto repoll;
 549         }
 550
 551         return 0;
 552 }
 553
 554 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
 555 {
 556         struct mlx5_ib_cq *cq = to_mcq(ibcq);
 557         struct mlx5_ib_qp *cur_qp = NULL;
 558         unsigned long flags;
 559         int npolled;
 560         int err = 0;
 561
 562         spin_lock_irqsave(&cq->lock, flags);
 563
 564         for (npolled = 0; npolled < num_entries; npolled++) {
 565                 err = mlx5_poll_one(cq, &cur_qp, wc + npolled);
 566                 if (err)
 567                         break;
 568         }
 569
 570         if (npolled)
 571                 mlx5_cq_set_ci(&cq->mcq);
 572
 573         spin_unlock_irqrestore(&cq->lock, flags);
 574
 575         if (err == 0 || err == -EAGAIN)
 576                 return npolled;
 577         else
 578                 return err;
 579 }
 580
 581 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
 582 {
 583         struct mlx5_core_dev *mdev = to_mdev(ibcq->device)->mdev;
 584         void __iomem *uar_page = mdev->priv.uuari.uars[0].map;
 585
 586         mlx5_cq_arm(&to_mcq(ibcq)->mcq,
 587                     (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
 588                     MLX5_CQ_DB_REQ_NOT_SOL : MLX5_CQ_DB_REQ_NOT,
 589                     uar_page,
 590                     MLX5_GET_DOORBELL_LOCK(&mdev->priv.cq_uar_lock),
 591                     to_mcq(ibcq)->mcq.cons_index);
 592
 593         return 0;
 594 }
 595
 596 static int alloc_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf,
 597                         int nent, int cqe_size)
 598 {
 599         int err;
 600
 601         err = mlx5_buf_alloc(dev->mdev, nent * cqe_size, &buf->buf);
 602         if (err)
 603                 return err;
 604
 605         buf->cqe_size = cqe_size;
 606         buf->nent = nent;
 607
 608         return 0;
 609 }
 610
 611 static int create_cq_user(struct mlx5_ib_dev *dev, struct ib_udata *udata,
 612                           struct ib_ucontext *context, struct mlx5_ib_cq *cq,
 613                           int entries, struct mlx5_create_cq_mbox_in **cqb,
 614                           int *cqe_size, int *index, int *inlen)
 615 {
 616         struct mlx5_ib_create_cq ucmd;
 617         size_t ucmdlen;
 618         int page_shift;
 619         int npages;
 620         int ncont;
 621         int err;
 622
 623         ucmdlen =
 624                 (udata->inlen - sizeof(struct ib_uverbs_cmd_hdr) <
 625                  sizeof(ucmd)) ? (sizeof(ucmd) -
 626                                   sizeof(ucmd.reserved)) : sizeof(ucmd);
 627
 628         if (ib_copy_from_udata(&ucmd, udata, ucmdlen))
 629                 return -EFAULT;
 630
 631         if (ucmdlen == sizeof(ucmd) &&
 632             ucmd.reserved != 0)
 633                 return -EINVAL;
 634
 635         if (ucmd.cqe_size != 64 && ucmd.cqe_size != 128)
 636                 return -EINVAL;
 637
 638         *cqe_size = ucmd.cqe_size;
 639
 640         cq->buf.umem = ib_umem_get(context, ucmd.buf_addr,
 641                                    entries * ucmd.cqe_size,
 642                                    IB_ACCESS_LOCAL_WRITE, 1);
 643         if (IS_ERR(cq->buf.umem)) {
 644                 err = PTR_ERR(cq->buf.umem);
 645                 return err;
 646         }
 647
 648         err = mlx5_ib_db_map_user(to_mucontext(context), ucmd.db_addr,
 649                                   &cq->db);
 650         if (err)
 651                 goto err_umem;
 652
 653         mlx5_ib_cont_pages(cq->buf.umem, ucmd.buf_addr, &npages, &page_shift,
 654                            &ncont, NULL);
 655         mlx5_ib_dbg(dev, "addr 0x%llx, size %u, npages %d, page_shift %d, ncont %d\n",
 656                     ucmd.buf_addr, entries * ucmd.cqe_size, npages, page_shift, ncont);
 657
 658         *inlen = sizeof(**cqb) + sizeof(*(*cqb)->pas) * ncont;
 659         *cqb = mlx5_vzalloc(*inlen);
 660         if (!*cqb) {
 661                 err = -ENOMEM;
 662                 goto err_db;
 663         }
 664         mlx5_ib_populate_pas(dev, cq->buf.umem, page_shift, (*cqb)->pas, 0);
 665         (*cqb)->ctx.log_pg_sz = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
 666
 667         *index = to_mucontext(context)->uuari.uars[0].index;
 668
 669         return 0;
 670
 671 err_db:
 672         mlx5_ib_db_unmap_user(to_mucontext(context), &cq->db);
 673
 674 err_umem:
 675         ib_umem_release(cq->buf.umem);
 676         return err;
 677 }
 678
 679 static void destroy_cq_user(struct mlx5_ib_cq *cq, struct ib_ucontext *context)
 680 {
 681         mlx5_ib_db_unmap_user(to_mucontext(context), &cq->db);
 682         ib_umem_release(cq->buf.umem);
 683 }
 684
 685 static void init_cq_buf(struct mlx5_ib_cq *cq, struct mlx5_ib_cq_buf *buf)
 686 {
 687         int i;
 688         void *cqe;
 689         struct mlx5_cqe64 *cqe64;
 690
 691         for (i = 0; i < buf->nent; i++) {
 692                 cqe = get_cqe_from_buf(buf, i, buf->cqe_size);
 693                 cqe64 = buf->cqe_size == 64 ? cqe : cqe + 64;
 694                 cqe64->op_own = MLX5_CQE_INVALID << 4;
 695         }
 696 }
 697
 698 static int create_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
 699                             int entries, int cqe_size,
 700                             struct mlx5_create_cq_mbox_in **cqb,
 701                             int *index, int *inlen)
 702 {
 703         int err;
 704
 705         err = mlx5_db_alloc(dev->mdev, &cq->db);
 706         if (err)
 707                 return err;
 708
 709         cq->mcq.set_ci_db  = cq->db.db;
 710         cq->mcq.arm_db     = cq->db.db + 1;
 711         cq->mcq.cqe_sz = cqe_size;
 712
 713         err = alloc_cq_buf(dev, &cq->buf, entries, cqe_size);
 714         if (err)
 715                 goto err_db;
 716
 717         init_cq_buf(cq, &cq->buf);
 718
 719         *inlen = sizeof(**cqb) + sizeof(*(*cqb)->pas) * cq->buf.buf.npages;
 720         *cqb = mlx5_vzalloc(*inlen);
 721         if (!*cqb) {
 722                 err = -ENOMEM;
 723                 goto err_buf;
 724         }
 725         mlx5_fill_page_array(&cq->buf.buf, (*cqb)->pas);
 726
 727         (*cqb)->ctx.log_pg_sz = cq->buf.buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT;
 728         *index = dev->mdev->priv.uuari.uars[0].index;
 729
 730         return 0;
 731
 732 err_buf:
 733         free_cq_buf(dev, &cq->buf);
 734
 735 err_db:
 736         mlx5_db_free(dev->mdev, &cq->db);
 737         return err;
 738 }
 739
 740 static void destroy_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq)
 741 {
 742         free_cq_buf(dev, &cq->buf);
 743         mlx5_db_free(dev->mdev, &cq->db);
 744 }
 745
 746 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev,
 747                                 const struct ib_cq_init_attr *attr,
 748                                 struct ib_ucontext *context,
 749                                 struct ib_udata *udata)
 750 {
 751         int entries = attr->cqe;
 752         int vector = attr->comp_vector;
 753         struct mlx5_create_cq_mbox_in *cqb = NULL;
 754         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 755         struct mlx5_ib_cq *cq;
 756         int uninitialized_var(index);
 757         int uninitialized_var(inlen);
 758         int cqe_size;
 759         unsigned int irqn;
 760         int eqn;
 761         int err;
 762
 763         if (attr->flags)
 764                 return ERR_PTR(-EINVAL);
 765
 766         if (entries < 0 ||
 767             (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))))
 768                 return ERR_PTR(-EINVAL);
 769
 770         entries = roundup_pow_of_two(entries + 1);
 771         if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)))
 772                 return ERR_PTR(-EINVAL);
 773
 774         cq = kzalloc(sizeof(*cq), GFP_KERNEL);
 775         if (!cq)
 776                 return ERR_PTR(-ENOMEM);
 777
 778         cq->ibcq.cqe = entries - 1;
 779         mutex_init(&cq->resize_mutex);
 780         spin_lock_init(&cq->lock);
 781         cq->resize_buf = NULL;
 782         cq->resize_umem = NULL;
 783
 784         if (context) {
 785                 err = create_cq_user(dev, udata, context, cq, entries,
 786                                      &cqb, &cqe_size, &index, &inlen);
 787                 if (err)
 788                         goto err_create;
 789         } else {
 790                 /* for now choose 64 bytes till we have a proper interface */
 791                 cqe_size = 64;
 792                 err = create_cq_kernel(dev, cq, entries, cqe_size, &cqb,
 793                                        &index, &inlen);
 794                 if (err)
 795                         goto err_create;
 796         }
 797
 798         cq->cqe_size = cqe_size;
 799         cqb->ctx.cqe_sz_flags = cqe_sz_to_mlx_sz(cqe_size) << 5;
 800         cqb->ctx.log_sz_usr_page = cpu_to_be32((ilog2(entries) << 24) | index);
 801         err = mlx5_vector2eqn(dev->mdev, vector, &eqn, &irqn);
 802         if (err)
 803                 goto err_cqb;
 804
 805         cqb->ctx.c_eqn = cpu_to_be16(eqn);
 806         cqb->ctx.db_record_addr = cpu_to_be64(cq->db.dma);
 807
 808         err = mlx5_core_create_cq(dev->mdev, &cq->mcq, cqb, inlen);
 809         if (err)
 810                 goto err_cqb;
 811
 812         mlx5_ib_dbg(dev, "cqn 0x%x\n", cq->mcq.cqn);
 813         cq->mcq.irqn = irqn;
 814         cq->mcq.comp  = mlx5_ib_cq_comp;
 815         cq->mcq.event = mlx5_ib_cq_event;
 816
 817         if (context)
 818                 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof(__u32))) {
 819                         err = -EFAULT;
 820                         goto err_cmd;
 821                 }
 822
 823
 824         kvfree(cqb);
 825         return &cq->ibcq;
 826
 827 err_cmd:
 828         mlx5_core_destroy_cq(dev->mdev, &cq->mcq);
 829
 830 err_cqb:
 831         kvfree(cqb);
 832         if (context)
 833                 destroy_cq_user(cq, context);
 834         else
 835                 destroy_cq_kernel(dev, cq);
 836
 837 err_create:
 838         kfree(cq);
 839
 840         return ERR_PTR(err);
 841 }
 842
 843
 844 int mlx5_ib_destroy_cq(struct ib_cq *cq)
 845 {
 846         struct mlx5_ib_dev *dev = to_mdev(cq->device);
 847         struct mlx5_ib_cq *mcq = to_mcq(cq);
 848         struct ib_ucontext *context = NULL;
 849
 850         if (cq->uobject)
 851                 context = cq->uobject->context;
 852
 853         mlx5_core_destroy_cq(dev->mdev, &mcq->mcq);
 854         if (context)
 855                 destroy_cq_user(mcq, context);
 856         else
 857                 destroy_cq_kernel(dev, mcq);
 858
 859         kfree(mcq);
 860
 861         return 0;
 862 }
 863
 864 static int is_equal_rsn(struct mlx5_cqe64 *cqe64, u32 rsn)
 865 {
 866         return rsn == (ntohl(cqe64->sop_drop_qpn) & 0xffffff);
 867 }
 868
 869 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 rsn, struct mlx5_ib_srq *srq)
 870 {
 871         struct mlx5_cqe64 *cqe64, *dest64;
 872         void *cqe, *dest;
 873         u32 prod_index;
 874         int nfreed = 0;
 875         u8 owner_bit;
 876
 877         if (!cq)
 878                 return;
 879
 880         /* First we need to find the current producer index, so we
 881          * know where to start cleaning from.  It doesn't matter if HW
 882          * adds new entries after this loop -- the QP we're worried
 883          * about is already in RESET, so the new entries won't come
 884          * from our QP and therefore don't need to be checked.
 885          */
 886         for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); prod_index++)
 887                 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe)
 888                         break;
 889
 890         /* Now sweep backwards through the CQ, removing CQ entries
 891          * that match our QP by copying older entries on top of them.
 892          */
 893         while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
 894                 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
 895                 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
 896                 if (is_equal_rsn(cqe64, rsn)) {
 897                         if (srq && (ntohl(cqe64->srqn) & 0xffffff))
 898                                 mlx5_ib_free_srq_wqe(srq, be16_to_cpu(cqe64->wqe_counter));
 899                         ++nfreed;
 900                 } else if (nfreed) {
 901                         dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe);
 902                         dest64 = (cq->mcq.cqe_sz == 64) ? dest : dest + 64;
 903                         owner_bit = dest64->op_own & MLX5_CQE_OWNER_MASK;
 904                         memcpy(dest, cqe, cq->mcq.cqe_sz);
 905                         dest64->op_own = owner_bit |
 906                                 (dest64->op_own & ~MLX5_CQE_OWNER_MASK);
 907                 }
 908         }
 909
 910         if (nfreed) {
 911                 cq->mcq.cons_index += nfreed;
 912                 /* Make sure update of buffer contents is done before
 913                  * updating consumer index.
 914                  */
 915                 wmb();
 916                 mlx5_cq_set_ci(&cq->mcq);
 917         }
 918 }
 919
 920 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq)
 921 {
 922         if (!cq)
 923                 return;
 924
 925         spin_lock_irq(&cq->lock);
 926         __mlx5_ib_cq_clean(cq, qpn, srq);
 927         spin_unlock_irq(&cq->lock);
 928 }
 929
 930 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
 931 {
 932         struct mlx5_modify_cq_mbox_in *in;
 933         struct mlx5_ib_dev *dev = to_mdev(cq->device);
 934         struct mlx5_ib_cq *mcq = to_mcq(cq);
 935         int err;
 936         u32 fsel;
 937
 938         if (!MLX5_CAP_GEN(dev->mdev, cq_moderation))
 939                 return -ENOSYS;
 940
 941         in = kzalloc(sizeof(*in), GFP_KERNEL);
 942         if (!in)
 943                 return -ENOMEM;
 944
 945         in->cqn = cpu_to_be32(mcq->mcq.cqn);
 946         fsel = (MLX5_CQ_MODIFY_PERIOD | MLX5_CQ_MODIFY_COUNT);
 947         in->ctx.cq_period = cpu_to_be16(cq_period);
 948         in->ctx.cq_max_count = cpu_to_be16(cq_count);
 949         in->field_select = cpu_to_be32(fsel);
 950         err = mlx5_core_modify_cq(dev->mdev, &mcq->mcq, in, sizeof(*in));
 951         kfree(in);
 952
 953         if (err)
 954                 mlx5_ib_warn(dev, "modify cq 0x%x failed\n", mcq->mcq.cqn);
 955
 956         return err;
 957 }
 958
 959 static int resize_user(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
 960                        int entries, struct ib_udata *udata, int *npas,
 961                        int *page_shift, int *cqe_size)
 962 {
 963         struct mlx5_ib_resize_cq ucmd;
 964         struct ib_umem *umem;
 965         int err;
 966         int npages;
 967         struct ib_ucontext *context = cq->buf.umem->context;
 968
 969         err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
 970         if (err)
 971                 return err;
 972
 973         if (ucmd.reserved0 || ucmd.reserved1)
 974                 return -EINVAL;
 975
 976         umem = ib_umem_get(context, ucmd.buf_addr, entries * ucmd.cqe_size,
 977                            IB_ACCESS_LOCAL_WRITE, 1);
 978         if (IS_ERR(umem)) {
 979                 err = PTR_ERR(umem);
 980                 return err;
 981         }
 982
 983         mlx5_ib_cont_pages(umem, ucmd.buf_addr, &npages, page_shift,
 984                            npas, NULL);
 985
 986         cq->resize_umem = umem;
 987         *cqe_size = ucmd.cqe_size;
 988
 989         return 0;
 990 }
 991
 992 static void un_resize_user(struct mlx5_ib_cq *cq)
 993 {
 994         ib_umem_release(cq->resize_umem);
 995 }
 996
 997 static int resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
 998                          int entries, int cqe_size)
 999 {
1000         int err;
1001
1002         cq->resize_buf = kzalloc(sizeof(*cq->resize_buf), GFP_KERNEL);
1003         if (!cq->resize_buf)
1004                 return -ENOMEM;
1005
1006         err = alloc_cq_buf(dev, cq->resize_buf, entries, cqe_size);
1007         if (err)
1008                 goto ex;
1009
1010         init_cq_buf(cq, cq->resize_buf);
1011
1012         return 0;
1013
1014 ex:
1015         kfree(cq->resize_buf);
1016         return err;
1017 }
1018
1019 static void un_resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq)
1020 {
1021         free_cq_buf(dev, cq->resize_buf);
1022         cq->resize_buf = NULL;
1023 }
1024
1025 static int copy_resize_cqes(struct mlx5_ib_cq *cq)
1026 {
1027         struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
1028         struct mlx5_cqe64 *scqe64;
1029         struct mlx5_cqe64 *dcqe64;
1030         void *start_cqe;
1031         void *scqe;
1032         void *dcqe;
1033         int ssize;
1034         int dsize;
1035         int i;
1036         u8 sw_own;
1037
1038         ssize = cq->buf.cqe_size;
1039         dsize = cq->resize_buf->cqe_size;
1040         if (ssize != dsize) {
1041                 mlx5_ib_warn(dev, "resize from different cqe size is not supported\n");
1042                 return -EINVAL;
1043         }
1044
1045         i = cq->mcq.cons_index;
1046         scqe = get_sw_cqe(cq, i);
1047         scqe64 = ssize == 64 ? scqe : scqe + 64;
1048         start_cqe = scqe;
1049         if (!scqe) {
1050                 mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1051                 return -EINVAL;
1052         }
1053
1054         while ((scqe64->op_own >> 4) != MLX5_CQE_RESIZE_CQ) {
1055                 dcqe = get_cqe_from_buf(cq->resize_buf,
1056                                         (i + 1) & (cq->resize_buf->nent),
1057                                         dsize);
1058                 dcqe64 = dsize == 64 ? dcqe : dcqe + 64;
1059                 sw_own = sw_ownership_bit(i + 1, cq->resize_buf->nent);
1060                 memcpy(dcqe, scqe, dsize);
1061                 dcqe64->op_own = (dcqe64->op_own & ~MLX5_CQE_OWNER_MASK) | sw_own;
1062
1063                 ++i;
1064                 scqe = get_sw_cqe(cq, i);
1065                 scqe64 = ssize == 64 ? scqe : scqe + 64;
1066                 if (!scqe) {
1067                         mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1068                         return -EINVAL;
1069                 }
1070
1071                 if (scqe == start_cqe) {
1072                         pr_warn("resize CQ failed to get resize CQE, CQN 0x%x\n",
1073                                 cq->mcq.cqn);
1074                         return -ENOMEM;
1075                 }
1076         }
1077         ++cq->mcq.cons_index;
1078         return 0;
1079 }
1080
1081 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
1082 {
1083         struct mlx5_ib_dev *dev = to_mdev(ibcq->device);
1084         struct mlx5_ib_cq *cq = to_mcq(ibcq);
1085         struct mlx5_modify_cq_mbox_in *in;
1086         int err;
1087         int npas;
1088         int page_shift;
1089         int inlen;
1090         int uninitialized_var(cqe_size);
1091         unsigned long flags;
1092
1093         if (!MLX5_CAP_GEN(dev->mdev, cq_resize)) {
1094                 pr_info("Firmware does not support resize CQ\n");
1095                 return -ENOSYS;
1096         }
1097
1098         if (entries < 1)
1099                 return -EINVAL;
1100
1101         entries = roundup_pow_of_two(entries + 1);
1102         if (entries >  (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)) + 1)
1103                 return -EINVAL;
1104
1105         if (entries == ibcq->cqe + 1)
1106                 return 0;
1107
1108         mutex_lock(&cq->resize_mutex);
1109         if (udata) {
1110                 err = resize_user(dev, cq, entries, udata, &npas, &page_shift,
1111                                   &cqe_size);
1112         } else {
1113                 cqe_size = 64;
1114                 err = resize_kernel(dev, cq, entries, cqe_size);
1115                 if (!err) {
1116                         npas = cq->resize_buf->buf.npages;
1117                         page_shift = cq->resize_buf->buf.page_shift;
1118                 }
1119         }
1120
1121         if (err)
1122                 goto ex;
1123
1124         inlen = sizeof(*in) + npas * sizeof(in->pas[0]);
1125         in = mlx5_vzalloc(inlen);
1126         if (!in) {
1127                 err = -ENOMEM;
1128                 goto ex_resize;
1129         }
1130
1131         if (udata)
1132                 mlx5_ib_populate_pas(dev, cq->resize_umem, page_shift,
1133                                      in->pas, 0);
1134         else
1135                 mlx5_fill_page_array(&cq->resize_buf->buf, in->pas);
1136
1137         in->field_select = cpu_to_be32(MLX5_MODIFY_CQ_MASK_LOG_SIZE  |
1138                                        MLX5_MODIFY_CQ_MASK_PG_OFFSET |
1139                                        MLX5_MODIFY_CQ_MASK_PG_SIZE);
1140         in->ctx.log_pg_sz = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
1141         in->ctx.cqe_sz_flags = cqe_sz_to_mlx_sz(cqe_size) << 5;
1142         in->ctx.page_offset = 0;
1143         in->ctx.log_sz_usr_page = cpu_to_be32(ilog2(entries) << 24);
1144         in->hdr.opmod = cpu_to_be16(MLX5_CQ_OPMOD_RESIZE);
1145         in->cqn = cpu_to_be32(cq->mcq.cqn);
1146
1147         err = mlx5_core_modify_cq(dev->mdev, &cq->mcq, in, inlen);
1148         if (err)
1149                 goto ex_alloc;
1150
1151         if (udata) {
1152                 cq->ibcq.cqe = entries - 1;
1153                 ib_umem_release(cq->buf.umem);
1154                 cq->buf.umem = cq->resize_umem;
1155                 cq->resize_umem = NULL;
1156         } else {
1157                 struct mlx5_ib_cq_buf tbuf;
1158                 int resized = 0;
1159
1160                 spin_lock_irqsave(&cq->lock, flags);
1161                 if (cq->resize_buf) {
1162                         err = copy_resize_cqes(cq);
1163                         if (!err) {
1164                                 tbuf = cq->buf;
1165                                 cq->buf = *cq->resize_buf;
1166                                 kfree(cq->resize_buf);
1167                                 cq->resize_buf = NULL;
1168                                 resized = 1;
1169                         }
1170                 }
1171                 cq->ibcq.cqe = entries - 1;
1172                 spin_unlock_irqrestore(&cq->lock, flags);
1173                 if (resized)
1174                         free_cq_buf(dev, &tbuf);
1175         }
1176         mutex_unlock(&cq->resize_mutex);
1177
1178         kvfree(in);
1179         return 0;
1180
1181 ex_alloc:
1182         kvfree(in);
1183
1184 ex_resize:
1185         if (udata)
1186                 un_resize_user(cq);
1187         else
1188                 un_resize_kernel(dev, cq);
1189 ex:
1190         mutex_unlock(&cq->resize_mutex);
1191         return err;
1192 }
1193
1194 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq)
1195 {
1196         struct mlx5_ib_cq *cq;
1197
1198         if (!ibcq)
1199                 return 128;
1200
1201         cq = to_mcq(ibcq);
1202         return cq->cqe_size;
1203 }