drivers/infiniband/hw/mlx4/qp.c

   1 /*
   2  * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
   3  * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/log2.h>
  35 #include <linux/slab.h>
  36 #include <linux/netdevice.h>
  37
  38 #include <rdma/ib_cache.h>
  39 #include <rdma/ib_pack.h>
  40 #include <rdma/ib_addr.h>
  41 #include <rdma/ib_mad.h>
  42
  43 #include <linux/mlx4/driver.h>
  44 #include <linux/mlx4/qp.h>
  45
  46 #include "mlx4_ib.h"
  47 #include "user.h"
  48
  49 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
  50                              struct mlx4_ib_cq *recv_cq);
  51 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
  52                                struct mlx4_ib_cq *recv_cq);
  53
  54 enum {
  55         MLX4_IB_ACK_REQ_FREQ    = 8,
  56 };
  57
  58 enum {
  59         MLX4_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  60         MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  61         MLX4_IB_LINK_TYPE_IB            = 0,
  62         MLX4_IB_LINK_TYPE_ETH           = 1
  63 };
  64
  65 enum {
  66         /*
  67          * Largest possible UD header: send with GRH and immediate
  68          * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
  69          * tag.  (LRH would only use 8 bytes, so Ethernet is the
  70          * biggest case)
  71          */
  72         MLX4_IB_UD_HEADER_SIZE          = 82,
  73         MLX4_IB_LSO_HEADER_SPARE        = 128,
  74 };
  75
  76 enum {
  77         MLX4_IB_IBOE_ETHERTYPE          = 0x8915
  78 };
  79
  80 struct mlx4_ib_sqp {
  81         struct mlx4_ib_qp       qp;
  82         int                     pkey_index;
  83         u32                     qkey;
  84         u32                     send_psn;
  85         struct ib_ud_header     ud_header;
  86         u8                      header_buf[MLX4_IB_UD_HEADER_SIZE];
  87 };
  88
  89 enum {
  90         MLX4_IB_MIN_SQ_STRIDE   = 6,
  91         MLX4_IB_CACHE_LINE_SIZE = 64,
  92 };
  93
  94 enum {
  95         MLX4_RAW_QP_MTU         = 7,
  96         MLX4_RAW_QP_MSGMAX      = 31,
  97 };
  98
  99 #ifndef ETH_ALEN
 100 #define ETH_ALEN        6
 101 #endif
 102
 103 static const __be32 mlx4_ib_opcode[] = {
 104         [IB_WR_SEND]                            = cpu_to_be32(MLX4_OPCODE_SEND),
 105         [IB_WR_LSO]                             = cpu_to_be32(MLX4_OPCODE_LSO),
 106         [IB_WR_SEND_WITH_IMM]                   = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
 107         [IB_WR_RDMA_WRITE]                      = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
 108         [IB_WR_RDMA_WRITE_WITH_IMM]             = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
 109         [IB_WR_RDMA_READ]                       = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
 110         [IB_WR_ATOMIC_CMP_AND_SWP]              = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
 111         [IB_WR_ATOMIC_FETCH_AND_ADD]            = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
 112         [IB_WR_SEND_WITH_INV]                   = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
 113         [IB_WR_LOCAL_INV]                       = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
 114         [IB_WR_FAST_REG_MR]                     = cpu_to_be32(MLX4_OPCODE_FMR),
 115         [IB_WR_REG_MR]                          = cpu_to_be32(MLX4_OPCODE_FMR),
 116         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
 117         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
 118         [IB_WR_BIND_MW]                         = cpu_to_be32(MLX4_OPCODE_BIND_MW),
 119 };
 120
 121 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
 122 {
 123         return container_of(mqp, struct mlx4_ib_sqp, qp);
 124 }
 125
 126 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 127 {
 128         if (!mlx4_is_master(dev->dev))
 129                 return 0;
 130
 131         return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
 132                qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
 133                 8 * MLX4_MFUNC_MAX;
 134 }
 135
 136 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 137 {
 138         int proxy_sqp = 0;
 139         int real_sqp = 0;
 140         int i;
 141         /* PPF or Native -- real SQP */
 142         real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
 143                     qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
 144                     qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
 145         if (real_sqp)
 146                 return 1;
 147         /* VF or PF -- proxy SQP */
 148         if (mlx4_is_mfunc(dev->dev)) {
 149                 for (i = 0; i < dev->dev->caps.num_ports; i++) {
 150                         if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] ||
 151                             qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) {
 152                                 proxy_sqp = 1;
 153                                 break;
 154                         }
 155                 }
 156         }
 157         return proxy_sqp;
 158 }
 159
 160 /* used for INIT/CLOSE port logic */
 161 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 162 {
 163         int proxy_qp0 = 0;
 164         int real_qp0 = 0;
 165         int i;
 166         /* PPF or Native -- real QP0 */
 167         real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
 168                     qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
 169                     qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
 170         if (real_qp0)
 171                 return 1;
 172         /* VF or PF -- proxy QP0 */
 173         if (mlx4_is_mfunc(dev->dev)) {
 174                 for (i = 0; i < dev->dev->caps.num_ports; i++) {
 175                         if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) {
 176                                 proxy_qp0 = 1;
 177                                 break;
 178                         }
 179                 }
 180         }
 181         return proxy_qp0;
 182 }
 183
 184 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
 185 {
 186         return mlx4_buf_offset(&qp->buf, offset);
 187 }
 188
 189 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
 190 {
 191         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 192 }
 193
 194 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
 195 {
 196         return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
 197 }
 198
 199 /*
 200  * Stamp a SQ WQE so that it is invalid if prefetched by marking the
 201  * first four bytes of every 64 byte chunk with
 202  *     0x7FFFFFF | (invalid_ownership_value << 31).
 203  *
 204  * When the max work request size is less than or equal to the WQE
 205  * basic block size, as an optimization, we can stamp all WQEs with
 206  * 0xffffffff, and skip the very first chunk of each WQE.
 207  */
 208 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
 209 {
 210         __be32 *wqe;
 211         int i;
 212         int s;
 213         int ind;
 214         void *buf;
 215         __be32 stamp;
 216         struct mlx4_wqe_ctrl_seg *ctrl;
 217
 218         if (qp->sq_max_wqes_per_wr > 1) {
 219                 s = roundup(size, 1U << qp->sq.wqe_shift);
 220                 for (i = 0; i < s; i += 64) {
 221                         ind = (i >> qp->sq.wqe_shift) + n;
 222                         stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
 223                                                        cpu_to_be32(0xffffffff);
 224                         buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
 225                         wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
 226                         *wqe = stamp;
 227                 }
 228         } else {
 229                 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 230                 s = (ctrl->fence_size & 0x3f) << 4;
 231                 for (i = 64; i < s; i += 64) {
 232                         wqe = buf + i;
 233                         *wqe = cpu_to_be32(0xffffffff);
 234                 }
 235         }
 236 }
 237
 238 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
 239 {
 240         struct mlx4_wqe_ctrl_seg *ctrl;
 241         struct mlx4_wqe_inline_seg *inl;
 242         void *wqe;
 243         int s;
 244
 245         ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 246         s = sizeof(struct mlx4_wqe_ctrl_seg);
 247
 248         if (qp->ibqp.qp_type == IB_QPT_UD) {
 249                 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
 250                 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
 251                 memset(dgram, 0, sizeof *dgram);
 252                 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
 253                 s += sizeof(struct mlx4_wqe_datagram_seg);
 254         }
 255
 256         /* Pad the remainder of the WQE with an inline data segment. */
 257         if (size > s) {
 258                 inl = wqe + s;
 259                 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
 260         }
 261         ctrl->srcrb_flags = 0;
 262         ctrl->fence_size = size / 16;
 263         /*
 264          * Make sure descriptor is fully written before setting ownership bit
 265          * (because HW can start executing as soon as we do).
 266          */
 267         wmb();
 268
 269         ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
 270                 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
 271
 272         stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
 273 }
 274
 275 /* Post NOP WQE to prevent wrap-around in the middle of WR */
 276 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
 277 {
 278         unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
 279         if (unlikely(s < qp->sq_max_wqes_per_wr)) {
 280                 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
 281                 ind += s;
 282         }
 283         return ind;
 284 }
 285
 286 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
 287 {
 288         struct ib_event event;
 289         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 290
 291         if (type == MLX4_EVENT_TYPE_PATH_MIG)
 292                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
 293
 294         if (ibqp->event_handler) {
 295                 event.device     = ibqp->device;
 296                 event.element.qp = ibqp;
 297                 switch (type) {
 298                 case MLX4_EVENT_TYPE_PATH_MIG:
 299                         event.event = IB_EVENT_PATH_MIG;
 300                         break;
 301                 case MLX4_EVENT_TYPE_COMM_EST:
 302                         event.event = IB_EVENT_COMM_EST;
 303                         break;
 304                 case MLX4_EVENT_TYPE_SQ_DRAINED:
 305                         event.event = IB_EVENT_SQ_DRAINED;
 306                         break;
 307                 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
 308                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 309                         break;
 310                 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
 311                         event.event = IB_EVENT_QP_FATAL;
 312                         break;
 313                 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
 314                         event.event = IB_EVENT_PATH_MIG_ERR;
 315                         break;
 316                 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 317                         event.event = IB_EVENT_QP_REQ_ERR;
 318                         break;
 319                 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
 320                         event.event = IB_EVENT_QP_ACCESS_ERR;
 321                         break;
 322                 default:
 323                         pr_warn("Unexpected event type %d "
 324                                "on QP %06x\n", type, qp->qpn);
 325                         return;
 326                 }
 327
 328                 ibqp->event_handler(&event, ibqp->qp_context);
 329         }
 330 }
 331
 332 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
 333 {
 334         /*
 335          * UD WQEs must have a datagram segment.
 336          * RC and UC WQEs might have a remote address segment.
 337          * MLX WQEs need two extra inline data segments (for the UD
 338          * header and space for the ICRC).
 339          */
 340         switch (type) {
 341         case MLX4_IB_QPT_UD:
 342                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 343                         sizeof (struct mlx4_wqe_datagram_seg) +
 344                         ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
 345         case MLX4_IB_QPT_PROXY_SMI_OWNER:
 346         case MLX4_IB_QPT_PROXY_SMI:
 347         case MLX4_IB_QPT_PROXY_GSI:
 348                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 349                         sizeof (struct mlx4_wqe_datagram_seg) + 64;
 350         case MLX4_IB_QPT_TUN_SMI_OWNER:
 351         case MLX4_IB_QPT_TUN_GSI:
 352                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 353                         sizeof (struct mlx4_wqe_datagram_seg);
 354
 355         case MLX4_IB_QPT_UC:
 356                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 357                         sizeof (struct mlx4_wqe_raddr_seg);
 358         case MLX4_IB_QPT_RC:
 359                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 360                         sizeof (struct mlx4_wqe_atomic_seg) +
 361                         sizeof (struct mlx4_wqe_raddr_seg);
 362         case MLX4_IB_QPT_SMI:
 363         case MLX4_IB_QPT_GSI:
 364                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 365                         ALIGN(MLX4_IB_UD_HEADER_SIZE +
 366                               DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
 367                                            MLX4_INLINE_ALIGN) *
 368                               sizeof (struct mlx4_wqe_inline_seg),
 369                               sizeof (struct mlx4_wqe_data_seg)) +
 370                         ALIGN(4 +
 371                               sizeof (struct mlx4_wqe_inline_seg),
 372                               sizeof (struct mlx4_wqe_data_seg));
 373         default:
 374                 return sizeof (struct mlx4_wqe_ctrl_seg);
 375         }
 376 }
 377
 378 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 379                        int is_user, int has_rq, struct mlx4_ib_qp *qp)
 380 {
 381         /* Sanity check RQ size before proceeding */
 382         if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
 383             cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
 384                 return -EINVAL;
 385
 386         if (!has_rq) {
 387                 if (cap->max_recv_wr)
 388                         return -EINVAL;
 389
 390                 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
 391         } else {
 392                 /* HW requires >= 1 RQ entry with >= 1 gather entry */
 393                 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
 394                         return -EINVAL;
 395
 396                 qp->rq.wqe_cnt   = roundup_pow_of_two(max(1U, cap->max_recv_wr));
 397                 qp->rq.max_gs    = roundup_pow_of_two(max(1U, cap->max_recv_sge));
 398                 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
 399         }
 400
 401         /* leave userspace return values as they were, so as not to break ABI */
 402         if (is_user) {
 403                 cap->max_recv_wr  = qp->rq.max_post = qp->rq.wqe_cnt;
 404                 cap->max_recv_sge = qp->rq.max_gs;
 405         } else {
 406                 cap->max_recv_wr  = qp->rq.max_post =
 407                         min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
 408                 cap->max_recv_sge = min(qp->rq.max_gs,
 409                                         min(dev->dev->caps.max_sq_sg,
 410                                             dev->dev->caps.max_rq_sg));
 411         }
 412
 413         return 0;
 414 }
 415
 416 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 417                               enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
 418 {
 419         int s;
 420
 421         /* Sanity check SQ size before proceeding */
 422         if (cap->max_send_wr  > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
 423             cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
 424             cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
 425             sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
 426                 return -EINVAL;
 427
 428         /*
 429          * For MLX transport we need 2 extra S/G entries:
 430          * one for the header and one for the checksum at the end
 431          */
 432         if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
 433              type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
 434             cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
 435                 return -EINVAL;
 436
 437         s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
 438                 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
 439                 send_wqe_overhead(type, qp->flags);
 440
 441         if (s > dev->dev->caps.max_sq_desc_sz)
 442                 return -EINVAL;
 443
 444         /*
 445          * Hermon supports shrinking WQEs, such that a single work
 446          * request can include multiple units of 1 << wqe_shift.  This
 447          * way, work requests can differ in size, and do not have to
 448          * be a power of 2 in size, saving memory and speeding up send
 449          * WR posting.  Unfortunately, if we do this then the
 450          * wqe_index field in CQEs can't be used to look up the WR ID
 451          * anymore, so we do this only if selective signaling is off.
 452          *
 453          * Further, on 32-bit platforms, we can't use vmap() to make
 454          * the QP buffer virtually contiguous.  Thus we have to use
 455          * constant-sized WRs to make sure a WR is always fully within
 456          * a single page-sized chunk.
 457          *
 458          * Finally, we use NOP work requests to pad the end of the
 459          * work queue, to avoid wrap-around in the middle of WR.  We
 460          * set NEC bit to avoid getting completions with error for
 461          * these NOP WRs, but since NEC is only supported starting
 462          * with firmware 2.2.232, we use constant-sized WRs for older
 463          * firmware.
 464          *
 465          * And, since MLX QPs only support SEND, we use constant-sized
 466          * WRs in this case.
 467          *
 468          * We look for the smallest value of wqe_shift such that the
 469          * resulting number of wqes does not exceed device
 470          * capabilities.
 471          *
 472          * We set WQE size to at least 64 bytes, this way stamping
 473          * invalidates each WQE.
 474          */
 475         if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
 476             qp->sq_signal_bits && BITS_PER_LONG == 64 &&
 477             type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
 478             !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
 479                       MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
 480                 qp->sq.wqe_shift = ilog2(64);
 481         else
 482                 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
 483
 484         for (;;) {
 485                 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
 486
 487                 /*
 488                  * We need to leave 2 KB + 1 WR of headroom in the SQ to
 489                  * allow HW to prefetch.
 490                  */
 491                 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
 492                 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
 493                                                     qp->sq_max_wqes_per_wr +
 494                                                     qp->sq_spare_wqes);
 495
 496                 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
 497                         break;
 498
 499                 if (qp->sq_max_wqes_per_wr <= 1)
 500                         return -EINVAL;
 501
 502                 ++qp->sq.wqe_shift;
 503         }
 504
 505         qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
 506                              (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
 507                          send_wqe_overhead(type, qp->flags)) /
 508                 sizeof (struct mlx4_wqe_data_seg);
 509
 510         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 511                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 512         if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
 513                 qp->rq.offset = 0;
 514                 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 515         } else {
 516                 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
 517                 qp->sq.offset = 0;
 518         }
 519
 520         cap->max_send_wr  = qp->sq.max_post =
 521                 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
 522         cap->max_send_sge = min(qp->sq.max_gs,
 523                                 min(dev->dev->caps.max_sq_sg,
 524                                     dev->dev->caps.max_rq_sg));
 525         /* We don't support inline sends for kernel QPs (yet) */
 526         cap->max_inline_data = 0;
 527
 528         return 0;
 529 }
 530
 531 static int set_user_sq_size(struct mlx4_ib_dev *dev,
 532                             struct mlx4_ib_qp *qp,
 533                             struct mlx4_ib_create_qp *ucmd)
 534 {
 535         /* Sanity check SQ size before proceeding */
 536         if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes       ||
 537             ucmd->log_sq_stride >
 538                 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
 539             ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
 540                 return -EINVAL;
 541
 542         qp->sq.wqe_cnt   = 1 << ucmd->log_sq_bb_count;
 543         qp->sq.wqe_shift = ucmd->log_sq_stride;
 544
 545         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 546                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 547
 548         return 0;
 549 }
 550
 551 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 552 {
 553         int i;
 554
 555         qp->sqp_proxy_rcv =
 556                 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
 557                         GFP_KERNEL);
 558         if (!qp->sqp_proxy_rcv)
 559                 return -ENOMEM;
 560         for (i = 0; i < qp->rq.wqe_cnt; i++) {
 561                 qp->sqp_proxy_rcv[i].addr =
 562                         kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
 563                                 GFP_KERNEL);
 564                 if (!qp->sqp_proxy_rcv[i].addr)
 565                         goto err;
 566                 qp->sqp_proxy_rcv[i].map =
 567                         ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
 568                                           sizeof (struct mlx4_ib_proxy_sqp_hdr),
 569                                           DMA_FROM_DEVICE);
 570                 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
 571                         kfree(qp->sqp_proxy_rcv[i].addr);
 572                         goto err;
 573                 }
 574         }
 575         return 0;
 576
 577 err:
 578         while (i > 0) {
 579                 --i;
 580                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 581                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
 582                                     DMA_FROM_DEVICE);
 583                 kfree(qp->sqp_proxy_rcv[i].addr);
 584         }
 585         kfree(qp->sqp_proxy_rcv);
 586         qp->sqp_proxy_rcv = NULL;
 587         return -ENOMEM;
 588 }
 589
 590 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 591 {
 592         int i;
 593
 594         for (i = 0; i < qp->rq.wqe_cnt; i++) {
 595                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 596                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
 597                                     DMA_FROM_DEVICE);
 598                 kfree(qp->sqp_proxy_rcv[i].addr);
 599         }
 600         kfree(qp->sqp_proxy_rcv);
 601 }
 602
 603 static int qp_has_rq(struct ib_qp_init_attr *attr)
 604 {
 605         if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
 606                 return 0;
 607
 608         return !attr->srq;
 609 }
 610
 611 static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
 612 {
 613         int i;
 614         for (i = 0; i < dev->caps.num_ports; i++) {
 615                 if (qpn == dev->caps.qp0_proxy[i])
 616                         return !!dev->caps.qp0_qkey[i];
 617         }
 618         return 0;
 619 }
 620
 621 static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
 622                                     struct mlx4_ib_qp *qp)
 623 {
 624         mutex_lock(&dev->counters_table[qp->port - 1].mutex);
 625         mlx4_counter_free(dev->dev, qp->counter_index->index);
 626         list_del(&qp->counter_index->list);
 627         mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
 628
 629         kfree(qp->counter_index);
 630         qp->counter_index = NULL;
 631 }
 632
 633 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
 634                             struct ib_qp_init_attr *init_attr,
 635                             struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp,
 636                             gfp_t gfp)
 637 {
 638         int qpn;
 639         int err;
 640         struct mlx4_ib_sqp *sqp;
 641         struct mlx4_ib_qp *qp;
 642         enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
 643         struct mlx4_ib_cq *mcq;
 644         unsigned long flags;
 645
 646         /* When tunneling special qps, we use a plain UD qp */
 647         if (sqpn) {
 648                 if (mlx4_is_mfunc(dev->dev) &&
 649                     (!mlx4_is_master(dev->dev) ||
 650                      !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
 651                         if (init_attr->qp_type == IB_QPT_GSI)
 652                                 qp_type = MLX4_IB_QPT_PROXY_GSI;
 653                         else {
 654                                 if (mlx4_is_master(dev->dev) ||
 655                                     qp0_enabled_vf(dev->dev, sqpn))
 656                                         qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
 657                                 else
 658                                         qp_type = MLX4_IB_QPT_PROXY_SMI;
 659                         }
 660                 }
 661                 qpn = sqpn;
 662                 /* add extra sg entry for tunneling */
 663                 init_attr->cap.max_recv_sge++;
 664         } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
 665                 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
 666                         container_of(init_attr,
 667                                      struct mlx4_ib_qp_tunnel_init_attr, init_attr);
 668                 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
 669                      tnl_init->proxy_qp_type != IB_QPT_GSI)   ||
 670                     !mlx4_is_master(dev->dev))
 671                         return -EINVAL;
 672                 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
 673                         qp_type = MLX4_IB_QPT_TUN_GSI;
 674                 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
 675                          mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
 676                                              tnl_init->port))
 677                         qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
 678                 else
 679                         qp_type = MLX4_IB_QPT_TUN_SMI;
 680                 /* we are definitely in the PPF here, since we are creating
 681                  * tunnel QPs. base_tunnel_sqpn is therefore valid. */
 682                 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
 683                         + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
 684                 sqpn = qpn;
 685         }
 686
 687         if (!*caller_qp) {
 688                 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
 689                     (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
 690                                 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
 691                         sqp = kzalloc(sizeof (struct mlx4_ib_sqp), gfp);
 692                         if (!sqp)
 693                                 return -ENOMEM;
 694                         qp = &sqp->qp;
 695                         qp->pri.vid = 0xFFFF;
 696                         qp->alt.vid = 0xFFFF;
 697                 } else {
 698                         qp = kzalloc(sizeof (struct mlx4_ib_qp), gfp);
 699                         if (!qp)
 700                                 return -ENOMEM;
 701                         qp->pri.vid = 0xFFFF;
 702                         qp->alt.vid = 0xFFFF;
 703                 }
 704         } else
 705                 qp = *caller_qp;
 706
 707         qp->mlx4_ib_qp_type = qp_type;
 708
 709         mutex_init(&qp->mutex);
 710         spin_lock_init(&qp->sq.lock);
 711         spin_lock_init(&qp->rq.lock);
 712         INIT_LIST_HEAD(&qp->gid_list);
 713         INIT_LIST_HEAD(&qp->steering_rules);
 714
 715         qp->state        = IB_QPS_RESET;
 716         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
 717                 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
 718
 719         err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp);
 720         if (err)
 721                 goto err;
 722
 723         if (pd->uobject) {
 724                 struct mlx4_ib_create_qp ucmd;
 725
 726                 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
 727                         err = -EFAULT;
 728                         goto err;
 729                 }
 730
 731                 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
 732
 733                 err = set_user_sq_size(dev, qp, &ucmd);
 734                 if (err)
 735                         goto err;
 736
 737                 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
 738                                        qp->buf_size, 0, 0);
 739                 if (IS_ERR(qp->umem)) {
 740                         err = PTR_ERR(qp->umem);
 741                         goto err;
 742                 }
 743
 744                 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
 745                                     ilog2(qp->umem->page_size), &qp->mtt);
 746                 if (err)
 747                         goto err_buf;
 748
 749                 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
 750                 if (err)
 751                         goto err_mtt;
 752
 753                 if (qp_has_rq(init_attr)) {
 754                         err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
 755                                                   ucmd.db_addr, &qp->db);
 756                         if (err)
 757                                 goto err_mtt;
 758                 }
 759         } else {
 760                 qp->sq_no_prefetch = 0;
 761
 762                 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 763                         qp->flags |= MLX4_IB_QP_LSO;
 764
 765                 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
 766                         if (dev->steering_support ==
 767                             MLX4_STEERING_MODE_DEVICE_MANAGED)
 768                                 qp->flags |= MLX4_IB_QP_NETIF;
 769                         else
 770                                 goto err;
 771                 }
 772
 773                 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
 774                 if (err)
 775                         goto err;
 776
 777                 if (qp_has_rq(init_attr)) {
 778                         err = mlx4_db_alloc(dev->dev, &qp->db, 0, gfp);
 779                         if (err)
 780                                 goto err;
 781
 782                         *qp->db.db = 0;
 783                 }
 784
 785                 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf, gfp)) {
 786                         err = -ENOMEM;
 787                         goto err_db;
 788                 }
 789
 790                 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
 791                                     &qp->mtt);
 792                 if (err)
 793                         goto err_buf;
 794
 795                 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf, gfp);
 796                 if (err)
 797                         goto err_mtt;
 798
 799                 qp->sq.wrid  = kmalloc(qp->sq.wqe_cnt * sizeof (u64), gfp);
 800                 qp->rq.wrid  = kmalloc(qp->rq.wqe_cnt * sizeof (u64), gfp);
 801                 if (!qp->sq.wrid || !qp->rq.wrid) {
 802                         err = -ENOMEM;
 803                         goto err_wrid;
 804                 }
 805         }
 806
 807         if (sqpn) {
 808                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
 809                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
 810                         if (alloc_proxy_bufs(pd->device, qp)) {
 811                                 err = -ENOMEM;
 812                                 goto err_wrid;
 813                         }
 814                 }
 815         } else {
 816                 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
 817                  * otherwise, the WQE BlueFlame setup flow wrongly causes
 818                  * VLAN insertion. */
 819                 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
 820                         err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
 821                                                     (init_attr->cap.max_send_wr ?
 822                                                      MLX4_RESERVE_ETH_BF_QP : 0) |
 823                                                     (init_attr->cap.max_recv_wr ?
 824                                                      MLX4_RESERVE_A0_QP : 0));
 825                 else
 826                         if (qp->flags & MLX4_IB_QP_NETIF)
 827                                 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
 828                         else
 829                                 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
 830                                                             &qpn, 0);
 831                 if (err)
 832                         goto err_proxy;
 833         }
 834
 835         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
 836                 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
 837
 838         err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp, gfp);
 839         if (err)
 840                 goto err_qpn;
 841
 842         if (init_attr->qp_type == IB_QPT_XRC_TGT)
 843                 qp->mqp.qpn |= (1 << 23);
 844
 845         /*
 846          * Hardware wants QPN written in big-endian order (after
 847          * shifting) for send doorbell.  Precompute this value to save
 848          * a little bit when posting sends.
 849          */
 850         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
 851
 852         qp->mqp.event = mlx4_ib_qp_event;
 853         if (!*caller_qp)
 854                 *caller_qp = qp;
 855
 856         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
 857         mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
 858                          to_mcq(init_attr->recv_cq));
 859         /* Maintain device to QPs access, needed for further handling
 860          * via reset flow
 861          */
 862         list_add_tail(&qp->qps_list, &dev->qp_list);
 863         /* Maintain CQ to QPs access, needed for further handling
 864          * via reset flow
 865          */
 866         mcq = to_mcq(init_attr->send_cq);
 867         list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
 868         mcq = to_mcq(init_attr->recv_cq);
 869         list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
 870         mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
 871                            to_mcq(init_attr->recv_cq));
 872         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
 873         return 0;
 874
 875 err_qpn:
 876         if (!sqpn) {
 877                 if (qp->flags & MLX4_IB_QP_NETIF)
 878                         mlx4_ib_steer_qp_free(dev, qpn, 1);
 879                 else
 880                         mlx4_qp_release_range(dev->dev, qpn, 1);
 881         }
 882 err_proxy:
 883         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
 884                 free_proxy_bufs(pd->device, qp);
 885 err_wrid:
 886         if (pd->uobject) {
 887                 if (qp_has_rq(init_attr))
 888                         mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
 889         } else {
 890                 kfree(qp->sq.wrid);
 891                 kfree(qp->rq.wrid);
 892         }
 893
 894 err_mtt:
 895         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 896
 897 err_buf:
 898         if (pd->uobject)
 899                 ib_umem_release(qp->umem);
 900         else
 901                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 902
 903 err_db:
 904         if (!pd->uobject && qp_has_rq(init_attr))
 905                 mlx4_db_free(dev->dev, &qp->db);
 906
 907 err:
 908         if (!*caller_qp)
 909                 kfree(qp);
 910         return err;
 911 }
 912
 913 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
 914 {
 915         switch (state) {
 916         case IB_QPS_RESET:      return MLX4_QP_STATE_RST;
 917         case IB_QPS_INIT:       return MLX4_QP_STATE_INIT;
 918         case IB_QPS_RTR:        return MLX4_QP_STATE_RTR;
 919         case IB_QPS_RTS:        return MLX4_QP_STATE_RTS;
 920         case IB_QPS_SQD:        return MLX4_QP_STATE_SQD;
 921         case IB_QPS_SQE:        return MLX4_QP_STATE_SQER;
 922         case IB_QPS_ERR:        return MLX4_QP_STATE_ERR;
 923         default:                return -1;
 924         }
 925 }
 926
 927 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 928         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
 929 {
 930         if (send_cq == recv_cq) {
 931                 spin_lock(&send_cq->lock);
 932                 __acquire(&recv_cq->lock);
 933         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 934                 spin_lock(&send_cq->lock);
 935                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
 936         } else {
 937                 spin_lock(&recv_cq->lock);
 938                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
 939         }
 940 }
 941
 942 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 943         __releases(&send_cq->lock) __releases(&recv_cq->lock)
 944 {
 945         if (send_cq == recv_cq) {
 946                 __release(&recv_cq->lock);
 947                 spin_unlock(&send_cq->lock);
 948         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 949                 spin_unlock(&recv_cq->lock);
 950                 spin_unlock(&send_cq->lock);
 951         } else {
 952                 spin_unlock(&send_cq->lock);
 953                 spin_unlock(&recv_cq->lock);
 954         }
 955 }
 956
 957 static void del_gid_entries(struct mlx4_ib_qp *qp)
 958 {
 959         struct mlx4_ib_gid_entry *ge, *tmp;
 960
 961         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
 962                 list_del(&ge->list);
 963                 kfree(ge);
 964         }
 965 }
 966
 967 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
 968 {
 969         if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
 970                 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
 971         else
 972                 return to_mpd(qp->ibqp.pd);
 973 }
 974
 975 static void get_cqs(struct mlx4_ib_qp *qp,
 976                     struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
 977 {
 978         switch (qp->ibqp.qp_type) {
 979         case IB_QPT_XRC_TGT:
 980                 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
 981                 *recv_cq = *send_cq;
 982                 break;
 983         case IB_QPT_XRC_INI:
 984                 *send_cq = to_mcq(qp->ibqp.send_cq);
 985                 *recv_cq = *send_cq;
 986                 break;
 987         default:
 988                 *send_cq = to_mcq(qp->ibqp.send_cq);
 989                 *recv_cq = to_mcq(qp->ibqp.recv_cq);
 990                 break;
 991         }
 992 }
 993
 994 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
 995                               int is_user)
 996 {
 997         struct mlx4_ib_cq *send_cq, *recv_cq;
 998         unsigned long flags;
 999
1000         if (qp->state != IB_QPS_RESET) {
1001                 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1002                                    MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1003                         pr_warn("modify QP %06x to RESET failed.\n",
1004                                qp->mqp.qpn);
1005                 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
1006                         mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1007                         qp->pri.smac = 0;
1008                         qp->pri.smac_port = 0;
1009                 }
1010                 if (qp->alt.smac) {
1011                         mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1012                         qp->alt.smac = 0;
1013                 }
1014                 if (qp->pri.vid < 0x1000) {
1015                         mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1016                         qp->pri.vid = 0xFFFF;
1017                         qp->pri.candidate_vid = 0xFFFF;
1018                         qp->pri.update_vid = 0;
1019                 }
1020                 if (qp->alt.vid < 0x1000) {
1021                         mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1022                         qp->alt.vid = 0xFFFF;
1023                         qp->alt.candidate_vid = 0xFFFF;
1024                         qp->alt.update_vid = 0;
1025                 }
1026         }
1027
1028         get_cqs(qp, &send_cq, &recv_cq);
1029
1030         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1031         mlx4_ib_lock_cqs(send_cq, recv_cq);
1032
1033         /* del from lists under both locks above to protect reset flow paths */
1034         list_del(&qp->qps_list);
1035         list_del(&qp->cq_send_list);
1036         list_del(&qp->cq_recv_list);
1037         if (!is_user) {
1038                 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1039                                  qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1040                 if (send_cq != recv_cq)
1041                         __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1042         }
1043
1044         mlx4_qp_remove(dev->dev, &qp->mqp);
1045
1046         mlx4_ib_unlock_cqs(send_cq, recv_cq);
1047         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1048
1049         mlx4_qp_free(dev->dev, &qp->mqp);
1050
1051         if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1052                 if (qp->flags & MLX4_IB_QP_NETIF)
1053                         mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
1054                 else
1055                         mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1056         }
1057
1058         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1059
1060         if (is_user) {
1061                 if (qp->rq.wqe_cnt)
1062                         mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
1063                                               &qp->db);
1064                 ib_umem_release(qp->umem);
1065         } else {
1066                 kfree(qp->sq.wrid);
1067                 kfree(qp->rq.wrid);
1068                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1069                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1070                         free_proxy_bufs(&dev->ib_dev, qp);
1071                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1072                 if (qp->rq.wqe_cnt)
1073                         mlx4_db_free(dev->dev, &qp->db);
1074         }
1075
1076         del_gid_entries(qp);
1077 }
1078
1079 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1080 {
1081         /* Native or PPF */
1082         if (!mlx4_is_mfunc(dev->dev) ||
1083             (mlx4_is_master(dev->dev) &&
1084              attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1085                 return  dev->dev->phys_caps.base_sqpn +
1086                         (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1087                         attr->port_num - 1;
1088         }
1089         /* PF or VF -- creating proxies */
1090         if (attr->qp_type == IB_QPT_SMI)
1091                 return dev->dev->caps.qp0_proxy[attr->port_num - 1];
1092         else
1093                 return dev->dev->caps.qp1_proxy[attr->port_num - 1];
1094 }
1095
1096 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1097                                 struct ib_qp_init_attr *init_attr,
1098                                 struct ib_udata *udata)
1099 {
1100         struct mlx4_ib_qp *qp = NULL;
1101         int err;
1102         int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1103         u16 xrcdn = 0;
1104         gfp_t gfp;
1105
1106         gfp = (init_attr->create_flags & MLX4_IB_QP_CREATE_USE_GFP_NOIO) ?
1107                 GFP_NOIO : GFP_KERNEL;
1108         /*
1109          * We only support LSO, vendor flag1, and multicast loopback blocking,
1110          * and only for kernel UD QPs.
1111          */
1112         if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1113                                         MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
1114                                         MLX4_IB_SRIOV_TUNNEL_QP |
1115                                         MLX4_IB_SRIOV_SQP |
1116                                         MLX4_IB_QP_NETIF |
1117                                         MLX4_IB_QP_CREATE_USE_GFP_NOIO))
1118                 return ERR_PTR(-EINVAL);
1119
1120         if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1121                 if (init_attr->qp_type != IB_QPT_UD)
1122                         return ERR_PTR(-EINVAL);
1123         }
1124
1125         if (init_attr->create_flags &&
1126             ((udata && init_attr->create_flags & ~(sup_u_create_flags)) ||
1127              ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
1128                                            MLX4_IB_QP_CREATE_USE_GFP_NOIO |
1129                                            MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)) &&
1130               init_attr->qp_type != IB_QPT_UD) ||
1131              ((init_attr->create_flags & MLX4_IB_SRIOV_SQP) &&
1132               init_attr->qp_type > IB_QPT_GSI)))
1133                 return ERR_PTR(-EINVAL);
1134
1135         switch (init_attr->qp_type) {
1136         case IB_QPT_XRC_TGT:
1137                 pd = to_mxrcd(init_attr->xrcd)->pd;
1138                 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1139                 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1140                 /* fall through */
1141         case IB_QPT_XRC_INI:
1142                 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1143                         return ERR_PTR(-ENOSYS);
1144                 init_attr->recv_cq = init_attr->send_cq;
1145                 /* fall through */
1146         case IB_QPT_RC:
1147         case IB_QPT_UC:
1148         case IB_QPT_RAW_PACKET:
1149                 qp = kzalloc(sizeof *qp, gfp);
1150                 if (!qp)
1151                         return ERR_PTR(-ENOMEM);
1152                 qp->pri.vid = 0xFFFF;
1153                 qp->alt.vid = 0xFFFF;
1154                 /* fall through */
1155         case IB_QPT_UD:
1156         {
1157                 err = create_qp_common(to_mdev(pd->device), pd, init_attr,
1158                                        udata, 0, &qp, gfp);
1159                 if (err)
1160                         return ERR_PTR(err);
1161
1162                 qp->ibqp.qp_num = qp->mqp.qpn;
1163                 qp->xrcdn = xrcdn;
1164
1165                 break;
1166         }
1167         case IB_QPT_SMI:
1168         case IB_QPT_GSI:
1169         {
1170                 /* Userspace is not allowed to create special QPs: */
1171                 if (udata)
1172                         return ERR_PTR(-EINVAL);
1173
1174                 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
1175                                        get_sqp_num(to_mdev(pd->device), init_attr),
1176                                        &qp, gfp);
1177                 if (err)
1178                         return ERR_PTR(err);
1179
1180                 qp->port        = init_attr->port_num;
1181                 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
1182
1183                 break;
1184         }
1185         default:
1186                 /* Don't support raw QPs */
1187                 return ERR_PTR(-EINVAL);
1188         }
1189
1190         return &qp->ibqp;
1191 }
1192
1193 int mlx4_ib_destroy_qp(struct ib_qp *qp)
1194 {
1195         struct mlx4_ib_dev *dev = to_mdev(qp->device);
1196         struct mlx4_ib_qp *mqp = to_mqp(qp);
1197         struct mlx4_ib_pd *pd;
1198
1199         if (is_qp0(dev, mqp))
1200                 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1201
1202         if (dev->qp1_proxy[mqp->port - 1] == mqp) {
1203                 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1204                 dev->qp1_proxy[mqp->port - 1] = NULL;
1205                 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1206         }
1207
1208         if (mqp->counter_index)
1209                 mlx4_ib_free_qp_counter(dev, mqp);
1210
1211         pd = get_pd(mqp);
1212         destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
1213
1214         if (is_sqp(dev, mqp))
1215                 kfree(to_msqp(mqp));
1216         else
1217                 kfree(mqp);
1218
1219         return 0;
1220 }
1221
1222 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
1223 {
1224         switch (type) {
1225         case MLX4_IB_QPT_RC:            return MLX4_QP_ST_RC;
1226         case MLX4_IB_QPT_UC:            return MLX4_QP_ST_UC;
1227         case MLX4_IB_QPT_UD:            return MLX4_QP_ST_UD;
1228         case MLX4_IB_QPT_XRC_INI:
1229         case MLX4_IB_QPT_XRC_TGT:       return MLX4_QP_ST_XRC;
1230         case MLX4_IB_QPT_SMI:
1231         case MLX4_IB_QPT_GSI:
1232         case MLX4_IB_QPT_RAW_PACKET:    return MLX4_QP_ST_MLX;
1233
1234         case MLX4_IB_QPT_PROXY_SMI_OWNER:
1235         case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1236                                                 MLX4_QP_ST_MLX : -1);
1237         case MLX4_IB_QPT_PROXY_SMI:
1238         case MLX4_IB_QPT_TUN_SMI:
1239         case MLX4_IB_QPT_PROXY_GSI:
1240         case MLX4_IB_QPT_TUN_GSI:       return (mlx4_is_mfunc(dev->dev) ?
1241                                                 MLX4_QP_ST_UD : -1);
1242         default:                        return -1;
1243         }
1244 }
1245
1246 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
1247                                    int attr_mask)
1248 {
1249         u8 dest_rd_atomic;
1250         u32 access_flags;
1251         u32 hw_access_flags = 0;
1252
1253         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1254                 dest_rd_atomic = attr->max_dest_rd_atomic;
1255         else
1256                 dest_rd_atomic = qp->resp_depth;
1257
1258         if (attr_mask & IB_QP_ACCESS_FLAGS)
1259                 access_flags = attr->qp_access_flags;
1260         else
1261                 access_flags = qp->atomic_rd_en;
1262
1263         if (!dest_rd_atomic)
1264                 access_flags &= IB_ACCESS_REMOTE_WRITE;
1265
1266         if (access_flags & IB_ACCESS_REMOTE_READ)
1267                 hw_access_flags |= MLX4_QP_BIT_RRE;
1268         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1269                 hw_access_flags |= MLX4_QP_BIT_RAE;
1270         if (access_flags & IB_ACCESS_REMOTE_WRITE)
1271                 hw_access_flags |= MLX4_QP_BIT_RWE;
1272
1273         return cpu_to_be32(hw_access_flags);
1274 }
1275
1276 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
1277                             int attr_mask)
1278 {
1279         if (attr_mask & IB_QP_PKEY_INDEX)
1280                 sqp->pkey_index = attr->pkey_index;
1281         if (attr_mask & IB_QP_QKEY)
1282                 sqp->qkey = attr->qkey;
1283         if (attr_mask & IB_QP_SQ_PSN)
1284                 sqp->send_psn = attr->sq_psn;
1285 }
1286
1287 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1288 {
1289         path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1290 }
1291
1292 static int _mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
1293                           u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
1294                           struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
1295 {
1296         int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
1297                 IB_LINK_LAYER_ETHERNET;
1298         int vidx;
1299         int smac_index;
1300         int err;
1301
1302
1303         path->grh_mylmc     = ah->src_path_bits & 0x7f;
1304         path->rlid          = cpu_to_be16(ah->dlid);
1305         if (ah->static_rate) {
1306                 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
1307                 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1308                        !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1309                         --path->static_rate;
1310         } else
1311                 path->static_rate = 0;
1312
1313         if (ah->ah_flags & IB_AH_GRH) {
1314                 int real_sgid_index = mlx4_ib_gid_index_to_real_index(dev,
1315                                                                       port,
1316                                                                       ah->grh.sgid_index);
1317
1318                 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
1319                         pr_err("sgid_index (%u) too large. max is %d\n",
1320                                real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
1321                         return -1;
1322                 }
1323
1324                 path->grh_mylmc |= 1 << 7;
1325                 path->mgid_index = real_sgid_index;
1326                 path->hop_limit  = ah->grh.hop_limit;
1327                 path->tclass_flowlabel =
1328                         cpu_to_be32((ah->grh.traffic_class << 20) |
1329                                     (ah->grh.flow_label));
1330                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1331         }
1332
1333         if (is_eth) {
1334                 if (!(ah->ah_flags & IB_AH_GRH))
1335                         return -1;
1336
1337                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1338                         ((port - 1) << 6) | ((ah->sl & 7) << 3);
1339
1340                 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
1341                 if (vlan_tag < 0x1000) {
1342                         if (smac_info->vid < 0x1000) {
1343                                 /* both valid vlan ids */
1344                                 if (smac_info->vid != vlan_tag) {
1345                                         /* different VIDs.  unreg old and reg new */
1346                                         err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1347                                         if (err)
1348                                                 return err;
1349                                         smac_info->candidate_vid = vlan_tag;
1350                                         smac_info->candidate_vlan_index = vidx;
1351                                         smac_info->candidate_vlan_port = port;
1352                                         smac_info->update_vid = 1;
1353                                         path->vlan_index = vidx;
1354                                 } else {
1355                                         path->vlan_index = smac_info->vlan_index;
1356                                 }
1357                         } else {
1358                                 /* no current vlan tag in qp */
1359                                 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1360                                 if (err)
1361                                         return err;
1362                                 smac_info->candidate_vid = vlan_tag;
1363                                 smac_info->candidate_vlan_index = vidx;
1364                                 smac_info->candidate_vlan_port = port;
1365                                 smac_info->update_vid = 1;
1366                                 path->vlan_index = vidx;
1367                         }
1368                         path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
1369                         path->fl = 1 << 6;
1370                 } else {
1371                         /* have current vlan tag. unregister it at modify-qp success */
1372                         if (smac_info->vid < 0x1000) {
1373                                 smac_info->candidate_vid = 0xFFFF;
1374                                 smac_info->update_vid = 1;
1375                         }
1376                 }
1377
1378                 /* get smac_index for RoCE use.
1379                  * If no smac was yet assigned, register one.
1380                  * If one was already assigned, but the new mac differs,
1381                  * unregister the old one and register the new one.
1382                 */
1383                 if ((!smac_info->smac && !smac_info->smac_port) ||
1384                     smac_info->smac != smac) {
1385                         /* register candidate now, unreg if needed, after success */
1386                         smac_index = mlx4_register_mac(dev->dev, port, smac);
1387                         if (smac_index >= 0) {
1388                                 smac_info->candidate_smac_index = smac_index;
1389                                 smac_info->candidate_smac = smac;
1390                                 smac_info->candidate_smac_port = port;
1391                         } else {
1392                                 return -EINVAL;
1393                         }
1394                 } else {
1395                         smac_index = smac_info->smac_index;
1396                 }
1397
1398                 memcpy(path->dmac, ah->dmac, 6);
1399                 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1400                 /* put MAC table smac index for IBoE */
1401                 path->grh_mylmc = (u8) (smac_index) | 0x80;
1402         } else {
1403                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1404                         ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
1405         }
1406
1407         return 0;
1408 }
1409
1410 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1411                          enum ib_qp_attr_mask qp_attr_mask,
1412                          struct mlx4_ib_qp *mqp,
1413                          struct mlx4_qp_path *path, u8 port,
1414                          u16 vlan_id, u8 *smac)
1415 {
1416         return _mlx4_set_path(dev, &qp->ah_attr,
1417                               mlx4_mac_to_u64(smac),
1418                               vlan_id,
1419                               path, &mqp->pri, port);
1420 }
1421
1422 static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1423                              const struct ib_qp_attr *qp,
1424                              enum ib_qp_attr_mask qp_attr_mask,
1425                              struct mlx4_ib_qp *mqp,
1426                              struct mlx4_qp_path *path, u8 port)
1427 {
1428         return _mlx4_set_path(dev, &qp->alt_ah_attr,
1429                               0,
1430                               0xffff,
1431                               path, &mqp->alt, port);
1432 }
1433
1434 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1435 {
1436         struct mlx4_ib_gid_entry *ge, *tmp;
1437
1438         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1439                 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1440                         ge->added = 1;
1441                         ge->port = qp->port;
1442                 }
1443         }
1444 }
1445
1446 static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev,
1447                                     struct mlx4_ib_qp *qp,
1448                                     struct mlx4_qp_context *context)
1449 {
1450         u64 u64_mac;
1451         int smac_index;
1452
1453         u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
1454
1455         context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
1456         if (!qp->pri.smac && !qp->pri.smac_port) {
1457                 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1458                 if (smac_index >= 0) {
1459                         qp->pri.candidate_smac_index = smac_index;
1460                         qp->pri.candidate_smac = u64_mac;
1461                         qp->pri.candidate_smac_port = qp->port;
1462                         context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1463                 } else {
1464                         return -ENOENT;
1465                 }
1466         }
1467         return 0;
1468 }
1469
1470 static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1471 {
1472         struct counter_index *new_counter_index;
1473         int err;
1474         u32 tmp_idx;
1475
1476         if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
1477             IB_LINK_LAYER_ETHERNET ||
1478             !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
1479             !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
1480                 return 0;
1481
1482         err = mlx4_counter_alloc(dev->dev, &tmp_idx);
1483         if (err)
1484                 return err;
1485
1486         new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
1487         if (!new_counter_index) {
1488                 mlx4_counter_free(dev->dev, tmp_idx);
1489                 return -ENOMEM;
1490         }
1491
1492         new_counter_index->index = tmp_idx;
1493         new_counter_index->allocated = 1;
1494         qp->counter_index = new_counter_index;
1495
1496         mutex_lock(&dev->counters_table[qp->port - 1].mutex);
1497         list_add_tail(&new_counter_index->list,
1498                       &dev->counters_table[qp->port - 1].counters_list);
1499         mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
1500
1501         return 0;
1502 }
1503
1504 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1505                                const struct ib_qp_attr *attr, int attr_mask,
1506                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
1507 {
1508         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1509         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1510         struct mlx4_ib_pd *pd;
1511         struct mlx4_ib_cq *send_cq, *recv_cq;
1512         struct mlx4_qp_context *context;
1513         enum mlx4_qp_optpar optpar = 0;
1514         int sqd_event;
1515         int steer_qp = 0;
1516         int err = -EINVAL;
1517         int counter_index;
1518
1519         /* APM is not supported under RoCE */
1520         if (attr_mask & IB_QP_ALT_PATH &&
1521             rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1522             IB_LINK_LAYER_ETHERNET)
1523                 return -ENOTSUPP;
1524
1525         context = kzalloc(sizeof *context, GFP_KERNEL);
1526         if (!context)
1527                 return -ENOMEM;
1528
1529         context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1530                                      (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
1531
1532         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
1533                 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1534         else {
1535                 optpar |= MLX4_QP_OPTPAR_PM_STATE;
1536                 switch (attr->path_mig_state) {
1537                 case IB_MIG_MIGRATED:
1538                         context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1539                         break;
1540                 case IB_MIG_REARM:
1541                         context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
1542                         break;
1543                 case IB_MIG_ARMED:
1544                         context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
1545                         break;
1546                 }
1547         }
1548
1549         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
1550                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
1551         else if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1552                 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
1553         else if (ibqp->qp_type == IB_QPT_UD) {
1554                 if (qp->flags & MLX4_IB_QP_LSO)
1555                         context->mtu_msgmax = (IB_MTU_4096 << 5) |
1556                                               ilog2(dev->dev->caps.max_gso_sz);
1557                 else
1558                         context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
1559         } else if (attr_mask & IB_QP_PATH_MTU) {
1560                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
1561                         pr_err("path MTU (%u) is invalid\n",
1562                                attr->path_mtu);
1563                         goto out;
1564                 }
1565                 context->mtu_msgmax = (attr->path_mtu << 5) |
1566                         ilog2(dev->dev->caps.max_msg_sz);
1567         }
1568
1569         if (qp->rq.wqe_cnt)
1570                 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
1571         context->rq_size_stride |= qp->rq.wqe_shift - 4;
1572
1573         if (qp->sq.wqe_cnt)
1574                 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
1575         context->sq_size_stride |= qp->sq.wqe_shift - 4;
1576
1577         if (new_state == IB_QPS_RESET && qp->counter_index)
1578                 mlx4_ib_free_qp_counter(dev, qp);
1579
1580         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1581                 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
1582                 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
1583                 if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1584                         context->param3 |= cpu_to_be32(1 << 30);
1585         }
1586
1587         if (qp->ibqp.uobject)
1588                 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
1589         else
1590                 context->usr_page = cpu_to_be32(dev->priv_uar.index);
1591
1592         if (attr_mask & IB_QP_DEST_QPN)
1593                 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1594
1595         if (attr_mask & IB_QP_PORT) {
1596                 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1597                     !(attr_mask & IB_QP_AV)) {
1598                         mlx4_set_sched(&context->pri_path, attr->port_num);
1599                         optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1600                 }
1601         }
1602
1603         if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
1604                 err = create_qp_lb_counter(dev, qp);
1605                 if (err)
1606                         goto out;
1607
1608                 counter_index =
1609                         dev->counters_table[qp->port - 1].default_counter;
1610                 if (qp->counter_index)
1611                         counter_index = qp->counter_index->index;
1612
1613                 if (counter_index != -1) {
1614                         context->pri_path.counter_index = counter_index;
1615                         optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
1616                         if (qp->counter_index) {
1617                                 context->pri_path.fl |=
1618                                         MLX4_FL_ETH_SRC_CHECK_MC_LB;
1619                                 context->pri_path.vlan_control |=
1620                                         MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
1621                         }
1622                 } else
1623                         context->pri_path.counter_index =
1624                                 MLX4_SINK_COUNTER_INDEX(dev->dev);
1625
1626                 if (qp->flags & MLX4_IB_QP_NETIF) {
1627                         mlx4_ib_steer_qp_reg(dev, qp, 1);
1628                         steer_qp = 1;
1629                 }
1630         }
1631
1632         if (attr_mask & IB_QP_PKEY_INDEX) {
1633                 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1634                         context->pri_path.disable_pkey_check = 0x40;
1635                 context->pri_path.pkey_index = attr->pkey_index;
1636                 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1637         }
1638
1639         if (attr_mask & IB_QP_AV) {
1640                 u8 port_num = mlx4_is_bonded(to_mdev(ibqp->device)->dev) ? 1 :
1641                         attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1642                 union ib_gid gid;
1643                 struct ib_gid_attr gid_attr;
1644                 u16 vlan = 0xffff;
1645                 u8 smac[ETH_ALEN];
1646                 int status = 0;
1647
1648                 if (rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
1649                     attr->ah_attr.ah_flags & IB_AH_GRH) {
1650                         int index = attr->ah_attr.grh.sgid_index;
1651
1652                         status = ib_get_cached_gid(ibqp->device, port_num,
1653                                                    index, &gid, &gid_attr);
1654                         if (!status && !memcmp(&gid, &zgid, sizeof(gid)))
1655                                 status = -ENOENT;
1656                         if (!status && gid_attr.ndev) {
1657                                 vlan = rdma_vlan_dev_vlan_id(gid_attr.ndev);
1658                                 memcpy(smac, gid_attr.ndev->dev_addr, ETH_ALEN);
1659                                 dev_put(gid_attr.ndev);
1660                         }
1661                 }
1662                 if (status)
1663                         goto out;
1664
1665                 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
1666                                   port_num, vlan, smac))
1667                         goto out;
1668
1669                 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1670                            MLX4_QP_OPTPAR_SCHED_QUEUE);
1671         }
1672
1673         if (attr_mask & IB_QP_TIMEOUT) {
1674                 context->pri_path.ackto |= attr->timeout << 3;
1675                 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1676         }
1677
1678         if (attr_mask & IB_QP_ALT_PATH) {
1679                 if (attr->alt_port_num == 0 ||
1680                     attr->alt_port_num > dev->dev->caps.num_ports)
1681                         goto out;
1682
1683                 if (attr->alt_pkey_index >=
1684                     dev->dev->caps.pkey_table_len[attr->alt_port_num])
1685                         goto out;
1686
1687                 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
1688                                       &context->alt_path,
1689                                       attr->alt_port_num))
1690                         goto out;
1691
1692                 context->alt_path.pkey_index = attr->alt_pkey_index;
1693                 context->alt_path.ackto = attr->alt_timeout << 3;
1694                 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1695         }
1696
1697         pd = get_pd(qp);
1698         get_cqs(qp, &send_cq, &recv_cq);
1699         context->pd       = cpu_to_be32(pd->pdn);
1700         context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
1701         context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
1702         context->params1  = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
1703
1704         /* Set "fast registration enabled" for all kernel QPs */
1705         if (!qp->ibqp.uobject)
1706                 context->params1 |= cpu_to_be32(1 << 11);
1707
1708         if (attr_mask & IB_QP_RNR_RETRY) {
1709                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1710                 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1711         }
1712
1713         if (attr_mask & IB_QP_RETRY_CNT) {
1714                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1715                 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1716         }
1717
1718         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1719                 if (attr->max_rd_atomic)
1720                         context->params1 |=
1721                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1722                 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1723         }
1724
1725         if (attr_mask & IB_QP_SQ_PSN)
1726                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1727
1728         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1729                 if (attr->max_dest_rd_atomic)
1730                         context->params2 |=
1731                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1732                 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1733         }
1734
1735         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1736                 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1737                 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1738         }
1739
1740         if (ibqp->srq)
1741                 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1742
1743         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1744                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1745                 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1746         }
1747         if (attr_mask & IB_QP_RQ_PSN)
1748                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1749
1750         /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
1751         if (attr_mask & IB_QP_QKEY) {
1752                 if (qp->mlx4_ib_qp_type &
1753                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
1754                         context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1755                 else {
1756                         if (mlx4_is_mfunc(dev->dev) &&
1757                             !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
1758                             (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
1759                             MLX4_RESERVED_QKEY_BASE) {
1760                                 pr_err("Cannot use reserved QKEY"
1761                                        " 0x%x (range 0xffff0000..0xffffffff"
1762                                        " is reserved)\n", attr->qkey);
1763                                 err = -EINVAL;
1764                                 goto out;
1765                         }
1766                         context->qkey = cpu_to_be32(attr->qkey);
1767                 }
1768                 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1769         }
1770
1771         if (ibqp->srq)
1772                 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1773
1774         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1775                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1776
1777         if (cur_state == IB_QPS_INIT &&
1778             new_state == IB_QPS_RTR  &&
1779             (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
1780              ibqp->qp_type == IB_QPT_UD ||
1781              ibqp->qp_type == IB_QPT_RAW_PACKET)) {
1782                 context->pri_path.sched_queue = (qp->port - 1) << 6;
1783                 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
1784                     qp->mlx4_ib_qp_type &
1785                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
1786                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1787                         if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
1788                                 context->pri_path.fl = 0x80;
1789                 } else {
1790                         if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1791                                 context->pri_path.fl = 0x80;
1792                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1793                 }
1794                 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1795                     IB_LINK_LAYER_ETHERNET) {
1796                         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
1797                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
1798                                 context->pri_path.feup = 1 << 7; /* don't fsm */
1799                         /* handle smac_index */
1800                         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
1801                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
1802                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
1803                                 err = handle_eth_ud_smac_index(dev, qp, context);
1804                                 if (err) {
1805                                         err = -EINVAL;
1806                                         goto out;
1807                                 }
1808                                 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1809                                         dev->qp1_proxy[qp->port - 1] = qp;
1810                         }
1811                 }
1812         }
1813
1814         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1815                 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
1816                                         MLX4_IB_LINK_TYPE_ETH;
1817                 if (dev->dev->caps.tunnel_offload_mode ==  MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1818                         /* set QP to receive both tunneled & non-tunneled packets */
1819                         if (!(context->flags & cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET)))
1820                                 context->srqn = cpu_to_be32(7 << 28);
1821                 }
1822         }
1823
1824         if (ibqp->qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
1825                 int is_eth = rdma_port_get_link_layer(
1826                                 &dev->ib_dev, qp->port) ==
1827                                 IB_LINK_LAYER_ETHERNET;
1828                 if (is_eth) {
1829                         context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
1830                         optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
1831                 }
1832         }
1833
1834
1835         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
1836             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1837                 sqd_event = 1;
1838         else
1839                 sqd_event = 0;
1840
1841         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1842                 context->rlkey |= (1 << 4);
1843
1844         /*
1845          * Before passing a kernel QP to the HW, make sure that the
1846          * ownership bits of the send queue are set and the SQ
1847          * headroom is stamped so that the hardware doesn't start
1848          * processing stale work requests.
1849          */
1850         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1851                 struct mlx4_wqe_ctrl_seg *ctrl;
1852                 int i;
1853
1854                 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
1855                         ctrl = get_send_wqe(qp, i);
1856                         ctrl->owner_opcode = cpu_to_be32(1 << 31);
1857                         if (qp->sq_max_wqes_per_wr == 1)
1858                                 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
1859
1860                         stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
1861                 }
1862         }
1863
1864         err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1865                              to_mlx4_state(new_state), context, optpar,
1866                              sqd_event, &qp->mqp);
1867         if (err)
1868                 goto out;
1869
1870         qp->state = new_state;
1871
1872         if (attr_mask & IB_QP_ACCESS_FLAGS)
1873                 qp->atomic_rd_en = attr->qp_access_flags;
1874         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1875                 qp->resp_depth = attr->max_dest_rd_atomic;
1876         if (attr_mask & IB_QP_PORT) {
1877                 qp->port = attr->port_num;
1878                 update_mcg_macs(dev, qp);
1879         }
1880         if (attr_mask & IB_QP_ALT_PATH)
1881                 qp->alt_port = attr->alt_port_num;
1882
1883         if (is_sqp(dev, qp))
1884                 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1885
1886         /*
1887          * If we moved QP0 to RTR, bring the IB link up; if we moved
1888          * QP0 to RESET or ERROR, bring the link back down.
1889          */
1890         if (is_qp0(dev, qp)) {
1891                 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
1892                         if (mlx4_INIT_PORT(dev->dev, qp->port))
1893                                 pr_warn("INIT_PORT failed for port %d\n",
1894                                        qp->port);
1895
1896                 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1897                     (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1898                         mlx4_CLOSE_PORT(dev->dev, qp->port);
1899         }
1900
1901         /*
1902          * If we moved a kernel QP to RESET, clean up all old CQ
1903          * entries and reinitialize the QP.
1904          */
1905         if (new_state == IB_QPS_RESET) {
1906                 if (!ibqp->uobject) {
1907                         mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1908                                          ibqp->srq ? to_msrq(ibqp->srq) : NULL);
1909                         if (send_cq != recv_cq)
1910                                 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1911
1912                         qp->rq.head = 0;
1913                         qp->rq.tail = 0;
1914                         qp->sq.head = 0;
1915                         qp->sq.tail = 0;
1916                         qp->sq_next_wqe = 0;
1917                         if (qp->rq.wqe_cnt)
1918                                 *qp->db.db  = 0;
1919
1920                         if (qp->flags & MLX4_IB_QP_NETIF)
1921                                 mlx4_ib_steer_qp_reg(dev, qp, 0);
1922                 }
1923                 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
1924                         mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1925                         qp->pri.smac = 0;
1926                         qp->pri.smac_port = 0;
1927                 }
1928                 if (qp->alt.smac) {
1929                         mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1930                         qp->alt.smac = 0;
1931                 }
1932                 if (qp->pri.vid < 0x1000) {
1933                         mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1934                         qp->pri.vid = 0xFFFF;
1935                         qp->pri.candidate_vid = 0xFFFF;
1936                         qp->pri.update_vid = 0;
1937                 }
1938
1939                 if (qp->alt.vid < 0x1000) {
1940                         mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1941                         qp->alt.vid = 0xFFFF;
1942                         qp->alt.candidate_vid = 0xFFFF;
1943                         qp->alt.update_vid = 0;
1944                 }
1945         }
1946 out:
1947         if (err && qp->counter_index)
1948                 mlx4_ib_free_qp_counter(dev, qp);
1949         if (err && steer_qp)
1950                 mlx4_ib_steer_qp_reg(dev, qp, 0);
1951         kfree(context);
1952         if (qp->pri.candidate_smac ||
1953             (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
1954                 if (err) {
1955                         mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
1956                 } else {
1957                         if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
1958                                 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1959                         qp->pri.smac = qp->pri.candidate_smac;
1960                         qp->pri.smac_index = qp->pri.candidate_smac_index;
1961                         qp->pri.smac_port = qp->pri.candidate_smac_port;
1962                 }
1963                 qp->pri.candidate_smac = 0;
1964                 qp->pri.candidate_smac_index = 0;
1965                 qp->pri.candidate_smac_port = 0;
1966         }
1967         if (qp->alt.candidate_smac) {
1968                 if (err) {
1969                         mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
1970                 } else {
1971                         if (qp->alt.smac)
1972                                 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1973                         qp->alt.smac = qp->alt.candidate_smac;
1974                         qp->alt.smac_index = qp->alt.candidate_smac_index;
1975                         qp->alt.smac_port = qp->alt.candidate_smac_port;
1976                 }
1977                 qp->alt.candidate_smac = 0;
1978                 qp->alt.candidate_smac_index = 0;
1979                 qp->alt.candidate_smac_port = 0;
1980         }
1981
1982         if (qp->pri.update_vid) {
1983                 if (err) {
1984                         if (qp->pri.candidate_vid < 0x1000)
1985                                 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
1986                                                      qp->pri.candidate_vid);
1987                 } else {
1988                         if (qp->pri.vid < 0x1000)
1989                                 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
1990                                                      qp->pri.vid);
1991                         qp->pri.vid = qp->pri.candidate_vid;
1992                         qp->pri.vlan_port = qp->pri.candidate_vlan_port;
1993                         qp->pri.vlan_index =  qp->pri.candidate_vlan_index;
1994                 }
1995                 qp->pri.candidate_vid = 0xFFFF;
1996                 qp->pri.update_vid = 0;
1997         }
1998
1999         if (qp->alt.update_vid) {
2000                 if (err) {
2001                         if (qp->alt.candidate_vid < 0x1000)
2002                                 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
2003                                                      qp->alt.candidate_vid);
2004                 } else {
2005                         if (qp->alt.vid < 0x1000)
2006                                 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
2007                                                      qp->alt.vid);
2008                         qp->alt.vid = qp->alt.candidate_vid;
2009                         qp->alt.vlan_port = qp->alt.candidate_vlan_port;
2010                         qp->alt.vlan_index =  qp->alt.candidate_vlan_index;
2011                 }
2012                 qp->alt.candidate_vid = 0xFFFF;
2013                 qp->alt.update_vid = 0;
2014         }
2015
2016         return err;
2017 }
2018
2019 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2020                       int attr_mask, struct ib_udata *udata)
2021 {
2022         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2023         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2024         enum ib_qp_state cur_state, new_state;
2025         int err = -EINVAL;
2026         int ll;
2027         mutex_lock(&qp->mutex);
2028
2029         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2030         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2031
2032         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2033                 ll = IB_LINK_LAYER_UNSPECIFIED;
2034         } else {
2035                 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2036                 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2037         }
2038
2039         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
2040                                 attr_mask, ll)) {
2041                 pr_debug("qpn 0x%x: invalid attribute mask specified "
2042                          "for transition %d to %d. qp_type %d,"
2043                          " attr_mask 0x%x\n",
2044                          ibqp->qp_num, cur_state, new_state,
2045                          ibqp->qp_type, attr_mask);
2046                 goto out;
2047         }
2048
2049         if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2050                 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2051                         if ((ibqp->qp_type == IB_QPT_RC) ||
2052                             (ibqp->qp_type == IB_QPT_UD) ||
2053                             (ibqp->qp_type == IB_QPT_UC) ||
2054                             (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2055                             (ibqp->qp_type == IB_QPT_XRC_INI)) {
2056                                 attr->port_num = mlx4_ib_bond_next_port(dev);
2057                         }
2058                 } else {
2059                         /* no sense in changing port_num
2060                          * when ports are bonded */
2061                         attr_mask &= ~IB_QP_PORT;
2062                 }
2063         }
2064
2065         if ((attr_mask & IB_QP_PORT) &&
2066             (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
2067                 pr_debug("qpn 0x%x: invalid port number (%d) specified "
2068                          "for transition %d to %d. qp_type %d\n",
2069                          ibqp->qp_num, attr->port_num, cur_state,
2070                          new_state, ibqp->qp_type);
2071                 goto out;
2072         }
2073
2074         if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2075             (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2076              IB_LINK_LAYER_ETHERNET))
2077                 goto out;
2078
2079         if (attr_mask & IB_QP_PKEY_INDEX) {
2080                 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2081                 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2082                         pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2083                                  "for transition %d to %d. qp_type %d\n",
2084                                  ibqp->qp_num, attr->pkey_index, cur_state,
2085                                  new_state, ibqp->qp_type);
2086                         goto out;
2087                 }
2088         }
2089
2090         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2091             attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
2092                 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2093                          "Transition %d to %d. qp_type %d\n",
2094                          ibqp->qp_num, attr->max_rd_atomic, cur_state,
2095                          new_state, ibqp->qp_type);
2096                 goto out;
2097         }
2098
2099         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2100             attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
2101                 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2102                          "Transition %d to %d. qp_type %d\n",
2103                          ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2104                          new_state, ibqp->qp_type);
2105                 goto out;
2106         }
2107
2108         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2109                 err = 0;
2110                 goto out;
2111         }
2112
2113         err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2114
2115         if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2116                 attr->port_num = 1;
2117
2118 out:
2119         mutex_unlock(&qp->mutex);
2120         return err;
2121 }
2122
2123 static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2124 {
2125         int i;
2126         for (i = 0; i < dev->caps.num_ports; i++) {
2127                 if (qpn == dev->caps.qp0_proxy[i] ||
2128                     qpn == dev->caps.qp0_tunnel[i]) {
2129                         *qkey = dev->caps.qp0_qkey[i];
2130                         return 0;
2131                 }
2132         }
2133         return -EINVAL;
2134 }
2135
2136 static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
2137                                   struct ib_ud_wr *wr,
2138                                   void *wqe, unsigned *mlx_seg_len)
2139 {
2140         struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2141         struct ib_device *ib_dev = &mdev->ib_dev;
2142         struct mlx4_wqe_mlx_seg *mlx = wqe;
2143         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2144         struct mlx4_ib_ah *ah = to_mah(wr->ah);
2145         u16 pkey;
2146         u32 qkey;
2147         int send_size;
2148         int header_size;
2149         int spc;
2150         int i;
2151
2152         if (wr->wr.opcode != IB_WR_SEND)
2153                 return -EINVAL;
2154
2155         send_size = 0;
2156
2157         for (i = 0; i < wr->wr.num_sge; ++i)
2158                 send_size += wr->wr.sg_list[i].length;
2159
2160         /* for proxy-qp0 sends, need to add in size of tunnel header */
2161         /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2162         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2163                 send_size += sizeof (struct mlx4_ib_tunnel_header);
2164
2165         ib_ud_header_init(send_size, 1, 0, 0, 0, 0, &sqp->ud_header);
2166
2167         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2168                 sqp->ud_header.lrh.service_level =
2169                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2170                 sqp->ud_header.lrh.destination_lid =
2171                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2172                 sqp->ud_header.lrh.source_lid =
2173                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2174         }
2175
2176         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2177
2178         /* force loopback */
2179         mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2180         mlx->rlid = sqp->ud_header.lrh.destination_lid;
2181
2182         sqp->ud_header.lrh.virtual_lane    = 0;
2183         sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
2184         ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2185         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2186         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
2187                 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
2188         else
2189                 sqp->ud_header.bth.destination_qpn =
2190                         cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]);
2191
2192         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2193         if (mlx4_is_master(mdev->dev)) {
2194                 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2195                         return -EINVAL;
2196         } else {
2197                 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2198                         return -EINVAL;
2199         }
2200         sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2201         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2202
2203         sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
2204         sqp->ud_header.immediate_present = 0;
2205
2206         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2207
2208         /*
2209          * Inline data segments may not cross a 64 byte boundary.  If
2210          * our UD header is bigger than the space available up to the
2211          * next 64 byte boundary in the WQE, use two inline data
2212          * segments to hold the UD header.
2213          */
2214         spc = MLX4_INLINE_ALIGN -
2215               ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2216         if (header_size <= spc) {
2217                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2218                 memcpy(inl + 1, sqp->header_buf, header_size);
2219                 i = 1;
2220         } else {
2221                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2222                 memcpy(inl + 1, sqp->header_buf, spc);
2223
2224                 inl = (void *) (inl + 1) + spc;
2225                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2226                 /*
2227                  * Need a barrier here to make sure all the data is
2228                  * visible before the byte_count field is set.
2229                  * Otherwise the HCA prefetcher could grab the 64-byte
2230                  * chunk with this inline segment and get a valid (!=
2231                  * 0xffffffff) byte count but stale data, and end up
2232                  * generating a packet with bad headers.
2233                  *
2234                  * The first inline segment's byte_count field doesn't
2235                  * need a barrier, because it comes after a
2236                  * control/MLX segment and therefore is at an offset
2237                  * of 16 mod 64.
2238                  */
2239                 wmb();
2240                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2241                 i = 2;
2242         }
2243
2244         *mlx_seg_len =
2245         ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2246         return 0;
2247 }
2248
2249 static void mlx4_u64_to_smac(u8 *dst_mac, u64 src_mac)
2250 {
2251         int i;
2252
2253         for (i = ETH_ALEN; i; i--) {
2254                 dst_mac[i - 1] = src_mac & 0xff;
2255                 src_mac >>= 8;
2256         }
2257 }
2258
2259 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_ud_wr *wr,
2260                             void *wqe, unsigned *mlx_seg_len)
2261 {
2262         struct ib_device *ib_dev = sqp->qp.ibqp.device;
2263         struct mlx4_wqe_mlx_seg *mlx = wqe;
2264         struct mlx4_wqe_ctrl_seg *ctrl = wqe;
2265         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2266         struct mlx4_ib_ah *ah = to_mah(wr->ah);
2267         union ib_gid sgid;
2268         u16 pkey;
2269         int send_size;
2270         int header_size;
2271         int spc;
2272         int i;
2273         int err = 0;
2274         u16 vlan = 0xffff;
2275         bool is_eth;
2276         bool is_vlan = false;
2277         bool is_grh;
2278
2279         send_size = 0;
2280         for (i = 0; i < wr->wr.num_sge; ++i)
2281                 send_size += wr->wr.sg_list[i].length;
2282
2283         is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
2284         is_grh = mlx4_ib_ah_grh_present(ah);
2285         if (is_eth) {
2286                 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2287                         /* When multi-function is enabled, the ib_core gid
2288                          * indexes don't necessarily match the hw ones, so
2289                          * we must use our own cache */
2290                         err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
2291                                                            be32_to_cpu(ah->av.ib.port_pd) >> 24,
2292                                                            ah->av.ib.gid_index, &sgid.raw[0]);
2293                         if (err)
2294                                 return err;
2295                 } else  {
2296                         err = ib_get_cached_gid(ib_dev,
2297                                                 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2298                                                 ah->av.ib.gid_index, &sgid,
2299                                                 NULL);
2300                         if (!err && !memcmp(&sgid, &zgid, sizeof(sgid)))
2301                                 err = -ENOENT;
2302                         if (err)
2303                                 return err;
2304                 }
2305
2306                 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
2307                         vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
2308                         is_vlan = 1;
2309                 }
2310         }
2311         ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 0, &sqp->ud_header);
2312
2313         if (!is_eth) {
2314                 sqp->ud_header.lrh.service_level =
2315                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2316                 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
2317                 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2318         }
2319
2320         if (is_grh) {
2321                 sqp->ud_header.grh.traffic_class =
2322                         (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
2323                 sqp->ud_header.grh.flow_label    =
2324                         ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
2325                 sqp->ud_header.grh.hop_limit     = ah->av.ib.hop_limit;
2326                 if (is_eth)
2327                         memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
2328                 else {
2329                 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2330                         /* When multi-function is enabled, the ib_core gid
2331                          * indexes don't necessarily match the hw ones, so
2332                          * we must use our own cache */
2333                         sqp->ud_header.grh.source_gid.global.subnet_prefix =
2334                                 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2335                                                        subnet_prefix;
2336                         sqp->ud_header.grh.source_gid.global.interface_id =
2337                                 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2338                                                guid_cache[ah->av.ib.gid_index];
2339                 } else
2340                         ib_get_cached_gid(ib_dev,
2341                                           be32_to_cpu(ah->av.ib.port_pd) >> 24,
2342                                           ah->av.ib.gid_index,
2343                                           &sqp->ud_header.grh.source_gid, NULL);
2344                 }
2345                 memcpy(sqp->ud_header.grh.destination_gid.raw,
2346                        ah->av.ib.dgid, 16);
2347         }
2348
2349         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2350
2351         if (!is_eth) {
2352                 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
2353                                           (sqp->ud_header.lrh.destination_lid ==
2354                                            IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
2355                                           (sqp->ud_header.lrh.service_level << 8));
2356                 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
2357                         mlx->flags |= cpu_to_be32(0x1); /* force loopback */
2358                 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2359         }
2360
2361         switch (wr->wr.opcode) {
2362         case IB_WR_SEND:
2363                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
2364                 sqp->ud_header.immediate_present = 0;
2365                 break;
2366         case IB_WR_SEND_WITH_IMM:
2367                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2368                 sqp->ud_header.immediate_present = 1;
2369                 sqp->ud_header.immediate_data    = wr->wr.ex.imm_data;
2370                 break;
2371         default:
2372                 return -EINVAL;
2373         }
2374
2375         if (is_eth) {
2376                 struct in6_addr in6;
2377
2378                 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
2379
2380                 mlx->sched_prio = cpu_to_be16(pcp);
2381
2382                 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
2383                 /* FIXME: cache smac value? */
2384                 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
2385                 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
2386                 memcpy(&in6, sgid.raw, sizeof(in6));
2387
2388                 if (!mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2389                         u64 mac = atomic64_read(&to_mdev(ib_dev)->iboe.mac[sqp->qp.port - 1]);
2390                         u8 smac[ETH_ALEN];
2391
2392                         mlx4_u64_to_smac(smac, mac);
2393                         memcpy(sqp->ud_header.eth.smac_h, smac, ETH_ALEN);
2394                 } else {
2395                         /* use the src mac of the tunnel */
2396                         memcpy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac, ETH_ALEN);
2397                 }
2398
2399                 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
2400                         mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
2401                 if (!is_vlan) {
2402                         sqp->ud_header.eth.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
2403                 } else {
2404                         sqp->ud_header.vlan.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
2405                         sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
2406                 }
2407         } else {
2408                 sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
2409                 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
2410                         sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
2411         }
2412         sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
2413         if (!sqp->qp.ibqp.qp_num)
2414                 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
2415         else
2416                 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index, &pkey);
2417         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2418         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
2419         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2420         sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
2421                                                sqp->qkey : wr->remote_qkey);
2422         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
2423
2424         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2425
2426         if (0) {
2427                 pr_err("built UD header of size %d:\n", header_size);
2428                 for (i = 0; i < header_size / 4; ++i) {
2429                         if (i % 8 == 0)
2430                                 pr_err("  [%02x] ", i * 4);
2431                         pr_cont(" %08x",
2432                                 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
2433                         if ((i + 1) % 8 == 0)
2434                                 pr_cont("\n");
2435                 }
2436                 pr_err("\n");
2437         }
2438
2439         /*
2440          * Inline data segments may not cross a 64 byte boundary.  If
2441          * our UD header is bigger than the space available up to the
2442          * next 64 byte boundary in the WQE, use two inline data
2443          * segments to hold the UD header.
2444          */
2445         spc = MLX4_INLINE_ALIGN -
2446                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2447         if (header_size <= spc) {
2448                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2449                 memcpy(inl + 1, sqp->header_buf, header_size);
2450                 i = 1;
2451         } else {
2452                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2453                 memcpy(inl + 1, sqp->header_buf, spc);
2454
2455                 inl = (void *) (inl + 1) + spc;
2456                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2457                 /*
2458                  * Need a barrier here to make sure all the data is
2459                  * visible before the byte_count field is set.
2460                  * Otherwise the HCA prefetcher could grab the 64-byte
2461                  * chunk with this inline segment and get a valid (!=
2462                  * 0xffffffff) byte count but stale data, and end up
2463                  * generating a packet with bad headers.
2464                  *
2465                  * The first inline segment's byte_count field doesn't
2466                  * need a barrier, because it comes after a
2467                  * control/MLX segment and therefore is at an offset
2468                  * of 16 mod 64.
2469                  */
2470                 wmb();
2471                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2472                 i = 2;
2473         }
2474
2475         *mlx_seg_len =
2476                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2477         return 0;
2478 }
2479
2480 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2481 {
2482         unsigned cur;
2483         struct mlx4_ib_cq *cq;
2484
2485         cur = wq->head - wq->tail;
2486         if (likely(cur + nreq < wq->max_post))
2487                 return 0;
2488
2489         cq = to_mcq(ib_cq);
2490         spin_lock(&cq->lock);
2491         cur = wq->head - wq->tail;
2492         spin_unlock(&cq->lock);
2493
2494         return cur + nreq >= wq->max_post;
2495 }
2496
2497 static __be32 convert_access(int acc)
2498 {
2499         return (acc & IB_ACCESS_REMOTE_ATOMIC ?
2500                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC)       : 0) |
2501                (acc & IB_ACCESS_REMOTE_WRITE  ?
2502                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
2503                (acc & IB_ACCESS_REMOTE_READ   ?
2504                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ)  : 0) |
2505                (acc & IB_ACCESS_LOCAL_WRITE   ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE)  : 0) |
2506                 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
2507 }
2508
2509 static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg,
2510                         struct ib_reg_wr *wr)
2511 {
2512         struct mlx4_ib_mr *mr = to_mmr(wr->mr);
2513
2514         fseg->flags             = convert_access(wr->access);
2515         fseg->mem_key           = cpu_to_be32(wr->key);
2516         fseg->buf_list          = cpu_to_be64(mr->page_map);
2517         fseg->start_addr        = cpu_to_be64(mr->ibmr.iova);
2518         fseg->reg_len           = cpu_to_be64(mr->ibmr.length);
2519         fseg->offset            = 0; /* XXX -- is this just for ZBVA? */
2520         fseg->page_size         = cpu_to_be32(ilog2(mr->ibmr.page_size));
2521         fseg->reserved[0]       = 0;
2522         fseg->reserved[1]       = 0;
2523 }
2524
2525 static void set_fmr_seg(struct mlx4_wqe_fmr_seg *fseg,
2526                 struct ib_fast_reg_wr *wr)
2527 {
2528         struct mlx4_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->page_list);
2529         int i;
2530
2531         for (i = 0; i < wr->page_list_len; ++i)
2532                 mfrpl->mapped_page_list[i] =
2533                         cpu_to_be64(wr->page_list->page_list[i] |
2534                                     MLX4_MTT_FLAG_PRESENT);
2535
2536         fseg->flags             = convert_access(wr->access_flags);
2537         fseg->mem_key           = cpu_to_be32(wr->rkey);
2538         fseg->buf_list          = cpu_to_be64(mfrpl->map);
2539         fseg->start_addr        = cpu_to_be64(wr->iova_start);
2540         fseg->reg_len           = cpu_to_be64(wr->length);
2541         fseg->offset            = 0; /* XXX -- is this just for ZBVA? */
2542         fseg->page_size         = cpu_to_be32(wr->page_shift);
2543         fseg->reserved[0]       = 0;
2544         fseg->reserved[1]       = 0;
2545 }
2546
2547 static void set_bind_seg(struct mlx4_wqe_bind_seg *bseg,
2548                 struct ib_bind_mw_wr *wr)
2549 {
2550         bseg->flags1 =
2551                 convert_access(wr->bind_info.mw_access_flags) &
2552                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ  |
2553                             MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE |
2554                             MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC);
2555         bseg->flags2 = 0;
2556         if (wr->mw->type == IB_MW_TYPE_2)
2557                 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_TYPE_2);
2558         if (wr->bind_info.mw_access_flags & IB_ZERO_BASED)
2559                 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_ZERO_BASED);
2560         bseg->new_rkey = cpu_to_be32(wr->rkey);
2561         bseg->lkey = cpu_to_be32(wr->bind_info.mr->lkey);
2562         bseg->addr = cpu_to_be64(wr->bind_info.addr);
2563         bseg->length = cpu_to_be64(wr->bind_info.length);
2564 }
2565
2566 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
2567 {
2568         memset(iseg, 0, sizeof(*iseg));
2569         iseg->mem_key = cpu_to_be32(rkey);
2570 }
2571
2572 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
2573                                           u64 remote_addr, u32 rkey)
2574 {
2575         rseg->raddr    = cpu_to_be64(remote_addr);
2576         rseg->rkey     = cpu_to_be32(rkey);
2577         rseg->reserved = 0;
2578 }
2579
2580 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg,
2581                 struct ib_atomic_wr *wr)
2582 {
2583         if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
2584                 aseg->swap_add = cpu_to_be64(wr->swap);
2585                 aseg->compare  = cpu_to_be64(wr->compare_add);
2586         } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
2587                 aseg->swap_add = cpu_to_be64(wr->compare_add);
2588                 aseg->compare  = cpu_to_be64(wr->compare_add_mask);
2589         } else {
2590                 aseg->swap_add = cpu_to_be64(wr->compare_add);
2591                 aseg->compare  = 0;
2592         }
2593
2594 }
2595
2596 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
2597                                   struct ib_atomic_wr *wr)
2598 {
2599         aseg->swap_add          = cpu_to_be64(wr->swap);
2600         aseg->swap_add_mask     = cpu_to_be64(wr->swap_mask);
2601         aseg->compare           = cpu_to_be64(wr->compare_add);
2602         aseg->compare_mask      = cpu_to_be64(wr->compare_add_mask);
2603 }
2604
2605 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
2606                              struct ib_ud_wr *wr)
2607 {
2608         memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));
2609         dseg->dqpn = cpu_to_be32(wr->remote_qpn);
2610         dseg->qkey = cpu_to_be32(wr->remote_qkey);
2611         dseg->vlan = to_mah(wr->ah)->av.eth.vlan;
2612         memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);
2613 }
2614
2615 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
2616                                     struct mlx4_wqe_datagram_seg *dseg,
2617                                     struct ib_ud_wr *wr,
2618                                     enum mlx4_ib_qp_type qpt)
2619 {
2620         union mlx4_ext_av *av = &to_mah(wr->ah)->av;
2621         struct mlx4_av sqp_av = {0};
2622         int port = *((u8 *) &av->ib.port_pd) & 0x3;
2623
2624         /* force loopback */
2625         sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
2626         sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
2627         sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
2628                         cpu_to_be32(0xf0000000);
2629
2630         memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
2631         if (qpt == MLX4_IB_QPT_PROXY_GSI)
2632                 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]);
2633         else
2634                 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp0_tunnel[port - 1]);
2635         /* Use QKEY from the QP context, which is set by master */
2636         dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2637 }
2638
2639 static void build_tunnel_header(struct ib_ud_wr *wr, void *wqe, unsigned *mlx_seg_len)
2640 {
2641         struct mlx4_wqe_inline_seg *inl = wqe;
2642         struct mlx4_ib_tunnel_header hdr;
2643         struct mlx4_ib_ah *ah = to_mah(wr->ah);
2644         int spc;
2645         int i;
2646
2647         memcpy(&hdr.av, &ah->av, sizeof hdr.av);
2648         hdr.remote_qpn = cpu_to_be32(wr->remote_qpn);
2649         hdr.pkey_index = cpu_to_be16(wr->pkey_index);
2650         hdr.qkey = cpu_to_be32(wr->remote_qkey);
2651         memcpy(hdr.mac, ah->av.eth.mac, 6);
2652         hdr.vlan = ah->av.eth.vlan;
2653
2654         spc = MLX4_INLINE_ALIGN -
2655                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2656         if (sizeof (hdr) <= spc) {
2657                 memcpy(inl + 1, &hdr, sizeof (hdr));
2658                 wmb();
2659                 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
2660                 i = 1;
2661         } else {
2662                 memcpy(inl + 1, &hdr, spc);
2663                 wmb();
2664                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2665
2666                 inl = (void *) (inl + 1) + spc;
2667                 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
2668                 wmb();
2669                 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
2670                 i = 2;
2671         }
2672
2673         *mlx_seg_len =
2674                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
2675 }
2676
2677 static void set_mlx_icrc_seg(void *dseg)
2678 {
2679         u32 *t = dseg;
2680         struct mlx4_wqe_inline_seg *iseg = dseg;
2681
2682         t[1] = 0;
2683
2684         /*
2685          * Need a barrier here before writing the byte_count field to
2686          * make sure that all the data is visible before the
2687          * byte_count field is set.  Otherwise, if the segment begins
2688          * a new cacheline, the HCA prefetcher could grab the 64-byte
2689          * chunk and get a valid (!= * 0xffffffff) byte count but
2690          * stale data, and end up sending the wrong data.
2691          */
2692         wmb();
2693
2694         iseg->byte_count = cpu_to_be32((1 << 31) | 4);
2695 }
2696
2697 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2698 {
2699         dseg->lkey       = cpu_to_be32(sg->lkey);
2700         dseg->addr       = cpu_to_be64(sg->addr);
2701
2702         /*
2703          * Need a barrier here before writing the byte_count field to
2704          * make sure that all the data is visible before the
2705          * byte_count field is set.  Otherwise, if the segment begins
2706          * a new cacheline, the HCA prefetcher could grab the 64-byte
2707          * chunk and get a valid (!= * 0xffffffff) byte count but
2708          * stale data, and end up sending the wrong data.
2709          */
2710         wmb();
2711
2712         dseg->byte_count = cpu_to_be32(sg->length);
2713 }
2714
2715 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2716 {
2717         dseg->byte_count = cpu_to_be32(sg->length);
2718         dseg->lkey       = cpu_to_be32(sg->lkey);
2719         dseg->addr       = cpu_to_be64(sg->addr);
2720 }
2721
2722 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_ud_wr *wr,
2723                          struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
2724                          __be32 *lso_hdr_sz, __be32 *blh)
2725 {
2726         unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16);
2727
2728         if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
2729                 *blh = cpu_to_be32(1 << 6);
2730
2731         if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
2732                      wr->wr.num_sge > qp->sq.max_gs - (halign >> 4)))
2733                 return -EINVAL;
2734
2735         memcpy(wqe->header, wr->header, wr->hlen);
2736
2737         *lso_hdr_sz  = cpu_to_be32(wr->mss << 16 | wr->hlen);
2738         *lso_seg_len = halign;
2739         return 0;
2740 }
2741
2742 static __be32 send_ieth(struct ib_send_wr *wr)
2743 {
2744         switch (wr->opcode) {
2745         case IB_WR_SEND_WITH_IMM:
2746         case IB_WR_RDMA_WRITE_WITH_IMM:
2747                 return wr->ex.imm_data;
2748
2749         case IB_WR_SEND_WITH_INV:
2750                 return cpu_to_be32(wr->ex.invalidate_rkey);
2751
2752         default:
2753                 return 0;
2754         }
2755 }
2756
2757 static void add_zero_len_inline(void *wqe)
2758 {
2759         struct mlx4_wqe_inline_seg *inl = wqe;
2760         memset(wqe, 0, 16);
2761         inl->byte_count = cpu_to_be32(1 << 31);
2762 }
2763
2764 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2765                       struct ib_send_wr **bad_wr)
2766 {
2767         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2768         void *wqe;
2769         struct mlx4_wqe_ctrl_seg *ctrl;
2770         struct mlx4_wqe_data_seg *dseg;
2771         unsigned long flags;
2772         int nreq;
2773         int err = 0;
2774         unsigned ind;
2775         int uninitialized_var(stamp);
2776         int uninitialized_var(size);
2777         unsigned uninitialized_var(seglen);
2778         __be32 dummy;
2779         __be32 *lso_wqe;
2780         __be32 uninitialized_var(lso_hdr_sz);
2781         __be32 blh;
2782         int i;
2783         struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
2784
2785         spin_lock_irqsave(&qp->sq.lock, flags);
2786         if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
2787                 err = -EIO;
2788                 *bad_wr = wr;
2789                 nreq = 0;
2790                 goto out;
2791         }
2792
2793         ind = qp->sq_next_wqe;
2794
2795         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2796                 lso_wqe = &dummy;
2797                 blh = 0;
2798
2799                 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
2800                         err = -ENOMEM;
2801                         *bad_wr = wr;
2802                         goto out;
2803                 }
2804
2805                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
2806                         err = -EINVAL;
2807                         *bad_wr = wr;
2808                         goto out;
2809                 }
2810
2811                 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
2812                 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
2813
2814                 ctrl->srcrb_flags =
2815                         (wr->send_flags & IB_SEND_SIGNALED ?
2816                          cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
2817                         (wr->send_flags & IB_SEND_SOLICITED ?
2818                          cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
2819                         ((wr->send_flags & IB_SEND_IP_CSUM) ?
2820                          cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
2821                                      MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
2822                         qp->sq_signal_bits;
2823
2824                 ctrl->imm = send_ieth(wr);
2825
2826                 wqe += sizeof *ctrl;
2827                 size = sizeof *ctrl / 16;
2828
2829                 switch (qp->mlx4_ib_qp_type) {
2830                 case MLX4_IB_QPT_RC:
2831                 case MLX4_IB_QPT_UC:
2832                         switch (wr->opcode) {
2833                         case IB_WR_ATOMIC_CMP_AND_SWP:
2834                         case IB_WR_ATOMIC_FETCH_AND_ADD:
2835                         case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
2836                                 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
2837                                               atomic_wr(wr)->rkey);
2838                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2839
2840                                 set_atomic_seg(wqe, atomic_wr(wr));
2841                                 wqe  += sizeof (struct mlx4_wqe_atomic_seg);
2842
2843                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2844                                          sizeof (struct mlx4_wqe_atomic_seg)) / 16;
2845
2846                                 break;
2847
2848                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
2849                                 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
2850                                               atomic_wr(wr)->rkey);
2851                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2852
2853                                 set_masked_atomic_seg(wqe, atomic_wr(wr));
2854                                 wqe  += sizeof (struct mlx4_wqe_masked_atomic_seg);
2855
2856                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2857                                          sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
2858
2859                                 break;
2860
2861                         case IB_WR_RDMA_READ:
2862                         case IB_WR_RDMA_WRITE:
2863                         case IB_WR_RDMA_WRITE_WITH_IMM:
2864                                 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
2865                                               rdma_wr(wr)->rkey);
2866                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2867                                 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
2868                                 break;
2869
2870                         case IB_WR_LOCAL_INV:
2871                                 ctrl->srcrb_flags |=
2872                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2873                                 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
2874                                 wqe  += sizeof (struct mlx4_wqe_local_inval_seg);
2875                                 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
2876                                 break;
2877
2878                         case IB_WR_FAST_REG_MR:
2879                                 ctrl->srcrb_flags |=
2880                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2881                                 set_fmr_seg(wqe, fast_reg_wr(wr));
2882                                 wqe  += sizeof (struct mlx4_wqe_fmr_seg);
2883                                 size += sizeof (struct mlx4_wqe_fmr_seg) / 16;
2884                                 break;
2885
2886                         case IB_WR_REG_MR:
2887                                 ctrl->srcrb_flags |=
2888                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2889                                 set_reg_seg(wqe, reg_wr(wr));
2890                                 wqe  += sizeof(struct mlx4_wqe_fmr_seg);
2891                                 size += sizeof(struct mlx4_wqe_fmr_seg) / 16;
2892                                 break;
2893
2894                         case IB_WR_BIND_MW:
2895                                 ctrl->srcrb_flags |=
2896                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2897                                 set_bind_seg(wqe, bind_mw_wr(wr));
2898                                 wqe  += sizeof(struct mlx4_wqe_bind_seg);
2899                                 size += sizeof(struct mlx4_wqe_bind_seg) / 16;
2900                                 break;
2901                         default:
2902                                 /* No extra segments required for sends */
2903                                 break;
2904                         }
2905                         break;
2906
2907                 case MLX4_IB_QPT_TUN_SMI_OWNER:
2908                         err =  build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
2909                                         ctrl, &seglen);
2910                         if (unlikely(err)) {
2911                                 *bad_wr = wr;
2912                                 goto out;
2913                         }
2914                         wqe  += seglen;
2915                         size += seglen / 16;
2916                         break;
2917                 case MLX4_IB_QPT_TUN_SMI:
2918                 case MLX4_IB_QPT_TUN_GSI:
2919                         /* this is a UD qp used in MAD responses to slaves. */
2920                         set_datagram_seg(wqe, ud_wr(wr));
2921                         /* set the forced-loopback bit in the data seg av */
2922                         *(__be32 *) wqe |= cpu_to_be32(0x80000000);
2923                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2924                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2925                         break;
2926                 case MLX4_IB_QPT_UD:
2927                         set_datagram_seg(wqe, ud_wr(wr));
2928                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2929                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2930
2931                         if (wr->opcode == IB_WR_LSO) {
2932                                 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen,
2933                                                 &lso_hdr_sz, &blh);
2934                                 if (unlikely(err)) {
2935                                         *bad_wr = wr;
2936                                         goto out;
2937                                 }
2938                                 lso_wqe = (__be32 *) wqe;
2939                                 wqe  += seglen;
2940                                 size += seglen / 16;
2941                         }
2942                         break;
2943
2944                 case MLX4_IB_QPT_PROXY_SMI_OWNER:
2945                         err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
2946                                         ctrl, &seglen);
2947                         if (unlikely(err)) {
2948                                 *bad_wr = wr;
2949                                 goto out;
2950                         }
2951                         wqe  += seglen;
2952                         size += seglen / 16;
2953                         /* to start tunnel header on a cache-line boundary */
2954                         add_zero_len_inline(wqe);
2955                         wqe += 16;
2956                         size++;
2957                         build_tunnel_header(ud_wr(wr), wqe, &seglen);
2958                         wqe  += seglen;
2959                         size += seglen / 16;
2960                         break;
2961                 case MLX4_IB_QPT_PROXY_SMI:
2962                 case MLX4_IB_QPT_PROXY_GSI:
2963                         /* If we are tunneling special qps, this is a UD qp.
2964                          * In this case we first add a UD segment targeting
2965                          * the tunnel qp, and then add a header with address
2966                          * information */
2967                         set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe,
2968                                                 ud_wr(wr),
2969                                                 qp->mlx4_ib_qp_type);
2970                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2971                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2972                         build_tunnel_header(ud_wr(wr), wqe, &seglen);
2973                         wqe  += seglen;
2974                         size += seglen / 16;
2975                         break;
2976
2977                 case MLX4_IB_QPT_SMI:
2978                 case MLX4_IB_QPT_GSI:
2979                         err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl,
2980                                         &seglen);
2981                         if (unlikely(err)) {
2982                                 *bad_wr = wr;
2983                                 goto out;
2984                         }
2985                         wqe  += seglen;
2986                         size += seglen / 16;
2987                         break;
2988
2989                 default:
2990                         break;
2991                 }
2992
2993                 /*
2994                  * Write data segments in reverse order, so as to
2995                  * overwrite cacheline stamp last within each
2996                  * cacheline.  This avoids issues with WQE
2997                  * prefetching.
2998                  */
2999
3000                 dseg = wqe;
3001                 dseg += wr->num_sge - 1;
3002                 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
3003
3004                 /* Add one more inline data segment for ICRC for MLX sends */
3005                 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
3006                              qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
3007                              qp->mlx4_ib_qp_type &
3008                              (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
3009                         set_mlx_icrc_seg(dseg + 1);
3010                         size += sizeof (struct mlx4_wqe_data_seg) / 16;
3011                 }
3012
3013                 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
3014                         set_data_seg(dseg, wr->sg_list + i);
3015
3016                 /*
3017                  * Possibly overwrite stamping in cacheline with LSO
3018                  * segment only after making sure all data segments
3019                  * are written.
3020                  */
3021                 wmb();
3022                 *lso_wqe = lso_hdr_sz;
3023
3024                 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
3025                                     MLX4_WQE_CTRL_FENCE : 0) | size;
3026
3027                 /*
3028                  * Make sure descriptor is fully written before
3029                  * setting ownership bit (because HW can start
3030                  * executing as soon as we do).
3031                  */
3032                 wmb();
3033
3034                 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
3035                         *bad_wr = wr;
3036                         err = -EINVAL;
3037                         goto out;
3038                 }
3039
3040                 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
3041                         (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
3042
3043                 stamp = ind + qp->sq_spare_wqes;
3044                 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
3045
3046                 /*
3047                  * We can improve latency by not stamping the last
3048                  * send queue WQE until after ringing the doorbell, so
3049                  * only stamp here if there are still more WQEs to post.
3050                  *
3051                  * Same optimization applies to padding with NOP wqe
3052                  * in case of WQE shrinking (used to prevent wrap-around
3053                  * in the middle of WR).
3054                  */
3055                 if (wr->next) {
3056                         stamp_send_wqe(qp, stamp, size * 16);
3057                         ind = pad_wraparound(qp, ind);
3058                 }
3059         }
3060
3061 out:
3062         if (likely(nreq)) {
3063                 qp->sq.head += nreq;
3064
3065                 /*
3066                  * Make sure that descriptors are written before
3067                  * doorbell record.
3068                  */
3069                 wmb();
3070
3071                 writel(qp->doorbell_qpn,
3072                        to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
3073
3074                 /*
3075                  * Make sure doorbells don't leak out of SQ spinlock
3076                  * and reach the HCA out of order.
3077                  */
3078                 mmiowb();
3079
3080                 stamp_send_wqe(qp, stamp, size * 16);
3081
3082                 ind = pad_wraparound(qp, ind);
3083                 qp->sq_next_wqe = ind;
3084         }
3085
3086         spin_unlock_irqrestore(&qp->sq.lock, flags);
3087
3088         return err;
3089 }
3090
3091 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
3092                       struct ib_recv_wr **bad_wr)
3093 {
3094         struct mlx4_ib_qp *qp = to_mqp(ibqp);
3095         struct mlx4_wqe_data_seg *scat;
3096         unsigned long flags;
3097         int err = 0;
3098         int nreq;
3099         int ind;
3100         int max_gs;
3101         int i;
3102         struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
3103
3104         max_gs = qp->rq.max_gs;
3105         spin_lock_irqsave(&qp->rq.lock, flags);
3106
3107         if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
3108                 err = -EIO;
3109                 *bad_wr = wr;
3110                 nreq = 0;
3111                 goto out;
3112         }
3113
3114         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
3115
3116         for (nreq = 0; wr; ++nreq, wr = wr->next) {
3117                 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
3118                         err = -ENOMEM;
3119                         *bad_wr = wr;
3120                         goto out;
3121                 }
3122
3123                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3124                         err = -EINVAL;
3125                         *bad_wr = wr;
3126                         goto out;
3127                 }
3128
3129                 scat = get_recv_wqe(qp, ind);
3130
3131                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3132                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3133                         ib_dma_sync_single_for_device(ibqp->device,
3134                                                       qp->sqp_proxy_rcv[ind].map,
3135                                                       sizeof (struct mlx4_ib_proxy_sqp_hdr),
3136                                                       DMA_FROM_DEVICE);
3137                         scat->byte_count =
3138                                 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3139                         /* use dma lkey from upper layer entry */
3140                         scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3141                         scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3142                         scat++;
3143                         max_gs--;
3144                 }
3145
3146                 for (i = 0; i < wr->num_sge; ++i)
3147                         __set_data_seg(scat + i, wr->sg_list + i);
3148
3149                 if (i < max_gs) {
3150                         scat[i].byte_count = 0;
3151                         scat[i].lkey       = cpu_to_be32(MLX4_INVALID_LKEY);
3152                         scat[i].addr       = 0;
3153                 }
3154
3155                 qp->rq.wrid[ind] = wr->wr_id;
3156
3157                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
3158         }
3159
3160 out:
3161         if (likely(nreq)) {
3162                 qp->rq.head += nreq;
3163
3164                 /*
3165                  * Make sure that descriptors are written before
3166                  * doorbell record.
3167                  */
3168                 wmb();
3169
3170                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3171         }
3172
3173         spin_unlock_irqrestore(&qp->rq.lock, flags);
3174
3175         return err;
3176 }
3177
3178 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3179 {
3180         switch (mlx4_state) {
3181         case MLX4_QP_STATE_RST:      return IB_QPS_RESET;
3182         case MLX4_QP_STATE_INIT:     return IB_QPS_INIT;
3183         case MLX4_QP_STATE_RTR:      return IB_QPS_RTR;
3184         case MLX4_QP_STATE_RTS:      return IB_QPS_RTS;
3185         case MLX4_QP_STATE_SQ_DRAINING:
3186         case MLX4_QP_STATE_SQD:      return IB_QPS_SQD;
3187         case MLX4_QP_STATE_SQER:     return IB_QPS_SQE;
3188         case MLX4_QP_STATE_ERR:      return IB_QPS_ERR;
3189         default:                     return -1;
3190         }
3191 }
3192
3193 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3194 {
3195         switch (mlx4_mig_state) {
3196         case MLX4_QP_PM_ARMED:          return IB_MIG_ARMED;
3197         case MLX4_QP_PM_REARM:          return IB_MIG_REARM;
3198         case MLX4_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
3199         default: return -1;
3200         }
3201 }
3202
3203 static int to_ib_qp_access_flags(int mlx4_flags)
3204 {
3205         int ib_flags = 0;
3206
3207         if (mlx4_flags & MLX4_QP_BIT_RRE)
3208                 ib_flags |= IB_ACCESS_REMOTE_READ;
3209         if (mlx4_flags & MLX4_QP_BIT_RWE)
3210                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3211         if (mlx4_flags & MLX4_QP_BIT_RAE)
3212                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3213
3214         return ib_flags;
3215 }
3216
3217 static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
3218                                 struct mlx4_qp_path *path)
3219 {
3220         struct mlx4_dev *dev = ibdev->dev;
3221         int is_eth;
3222
3223         memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
3224         ib_ah_attr->port_num      = path->sched_queue & 0x40 ? 2 : 1;
3225
3226         if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
3227                 return;
3228
3229         is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) ==
3230                 IB_LINK_LAYER_ETHERNET;
3231         if (is_eth)
3232                 ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) |
3233                 ((path->sched_queue & 4) << 1);
3234         else
3235                 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
3236
3237         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
3238         ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
3239         ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
3240         ib_ah_attr->ah_flags      = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
3241         if (ib_ah_attr->ah_flags) {
3242                 ib_ah_attr->grh.sgid_index = path->mgid_index;
3243                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
3244                 ib_ah_attr->grh.traffic_class =
3245                         (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
3246                 ib_ah_attr->grh.flow_label =
3247                         be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
3248                 memcpy(ib_ah_attr->grh.dgid.raw,
3249                         path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
3250         }
3251 }
3252
3253 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3254                      struct ib_qp_init_attr *qp_init_attr)
3255 {
3256         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
3257         struct mlx4_ib_qp *qp = to_mqp(ibqp);
3258         struct mlx4_qp_context context;
3259         int mlx4_state;
3260         int err = 0;
3261
3262         mutex_lock(&qp->mutex);
3263
3264         if (qp->state == IB_QPS_RESET) {
3265                 qp_attr->qp_state = IB_QPS_RESET;
3266                 goto done;
3267         }
3268
3269         err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
3270         if (err) {
3271                 err = -EINVAL;
3272                 goto out;
3273         }
3274
3275         mlx4_state = be32_to_cpu(context.flags) >> 28;
3276
3277         qp->state                    = to_ib_qp_state(mlx4_state);
3278         qp_attr->qp_state            = qp->state;
3279         qp_attr->path_mtu            = context.mtu_msgmax >> 5;
3280         qp_attr->path_mig_state      =
3281                 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
3282         qp_attr->qkey                = be32_to_cpu(context.qkey);
3283         qp_attr->rq_psn              = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
3284         qp_attr->sq_psn              = be32_to_cpu(context.next_send_psn) & 0xffffff;
3285         qp_attr->dest_qp_num         = be32_to_cpu(context.remote_qpn) & 0xffffff;
3286         qp_attr->qp_access_flags     =
3287                 to_ib_qp_access_flags(be32_to_cpu(context.params2));
3288
3289         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
3290                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
3291                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
3292                 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
3293                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
3294         }
3295
3296         qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
3297         if (qp_attr->qp_state == IB_QPS_INIT)
3298                 qp_attr->port_num = qp->port;
3299         else
3300                 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
3301
3302         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3303         qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
3304
3305         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
3306
3307         qp_attr->max_dest_rd_atomic =
3308                 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
3309         qp_attr->min_rnr_timer      =
3310                 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
3311         qp_attr->timeout            = context.pri_path.ackto >> 3;
3312         qp_attr->retry_cnt          = (be32_to_cpu(context.params1) >> 16) & 0x7;
3313         qp_attr->rnr_retry          = (be32_to_cpu(context.params1) >> 13) & 0x7;
3314         qp_attr->alt_timeout        = context.alt_path.ackto >> 3;
3315
3316 done:
3317         qp_attr->cur_qp_state        = qp_attr->qp_state;
3318         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
3319         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
3320
3321         if (!ibqp->uobject) {
3322                 qp_attr->cap.max_send_wr  = qp->sq.wqe_cnt;
3323                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
3324         } else {
3325                 qp_attr->cap.max_send_wr  = 0;
3326                 qp_attr->cap.max_send_sge = 0;
3327         }
3328
3329         /*
3330          * We don't support inline sends for kernel QPs (yet), and we
3331          * don't know what userspace's value should be.
3332          */
3333         qp_attr->cap.max_inline_data = 0;
3334
3335         qp_init_attr->cap            = qp_attr->cap;
3336
3337         qp_init_attr->create_flags = 0;
3338         if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
3339                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
3340
3341         if (qp->flags & MLX4_IB_QP_LSO)
3342                 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
3343
3344         if (qp->flags & MLX4_IB_QP_NETIF)
3345                 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
3346
3347         qp_init_attr->sq_sig_type =
3348                 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
3349                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
3350
3351 out:
3352         mutex_unlock(&qp->mutex);
3353         return err;
3354 }
3355