1 #ifndef _IPATH_KERNEL_H
2 #define _IPATH_KERNEL_H
4 * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
5 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 * This header file is the base header file for infinipath kernel code
38 * ipath_user.h serves a similar purpose for user code.
41 #include <linux/interrupt.h>
42 #include <linux/pci.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/mutex.h>
46 #include <rdma/ib_verbs.h>
48 #include "ipath_common.h"
49 #include "ipath_debug.h"
50 #include "ipath_registers.h"
52 /* only s/w major version of InfiniPath we can handle */
53 #define IPATH_CHIP_VERS_MAJ 2U
55 /* don't care about this except printing */
56 #define IPATH_CHIP_VERS_MIN 0U
58 /* temporary, maybe always */
59 extern struct infinipath_stats ipath_stats;
61 #define IPATH_CHIP_SWVERSION IPATH_CHIP_VERS_MAJ
63 * First-cut critierion for "device is active" is
64 * two thousand dwords combined Tx, Rx traffic per
65 * 5-second interval. SMA packets are 64 dwords,
66 * and occur "a few per second", presumably each way.
68 #define IPATH_TRAFFIC_ACTIVE_THRESHOLD (2000)
70 * Struct used to indicate which errors are logged in each of the
71 * error-counters that are logged to EEPROM. A counter is incremented
72 * _once_ (saturating at 255) for each event with any bits set in
73 * the error or hwerror register masks below.
75 #define IPATH_EEP_LOG_CNT (4)
76 struct ipath_eep_log_mask {
81 struct ipath_portdata {
82 void **port_rcvegrbuf;
83 dma_addr_t *port_rcvegrbuf_phys;
84 /* rcvhdrq base, needs mmap before useful */
86 /* kernel virtual address where hdrqtail is updated */
87 void *port_rcvhdrtail_kvaddr;
89 * temp buffer for expected send setup, allocated at open, instead
92 void *port_tid_pg_list;
93 /* when waiting for rcv or pioavail */
94 wait_queue_head_t port_wait;
96 * rcvegr bufs base, physical, must fit
97 * in 44 bits so 32 bit programs mmap64 44 bit works)
99 dma_addr_t port_rcvegr_phys;
100 /* mmap of hdrq, must fit in 44 bits */
101 dma_addr_t port_rcvhdrq_phys;
102 dma_addr_t port_rcvhdrqtailaddr_phys;
104 * number of opens (including slave subports) on this instance
105 * (ignoring forks, dup, etc. for now)
109 * how much space to leave at start of eager TID entries for
110 * protocol use, on each TID
112 /* instead of calculating it */
114 /* non-zero if port is being shared. */
115 u16 port_subport_cnt;
116 /* non-zero if port is being shared. */
118 /* chip offset of PIO buffers for this port */
120 /* how many alloc_pages() chunks in port_rcvegrbuf_pages */
121 u32 port_rcvegrbuf_chunks;
122 /* how many egrbufs per chunk */
123 u32 port_rcvegrbufs_perchunk;
124 /* order for port_rcvegrbuf_pages */
125 size_t port_rcvegrbuf_size;
126 /* rcvhdrq size (for freeing) */
127 size_t port_rcvhdrq_size;
128 /* next expected TID to check when looking for free */
130 /* next expected TID to check */
131 unsigned long port_flag;
133 unsigned long int_flag;
134 /* WAIT_RCV that timed out, no interrupt */
136 /* WAIT_PIO that timed out, no interrupt */
138 /* WAIT_RCV already happened, no wait */
140 /* WAIT_PIO already happened, no wait */
142 /* total number of rcvhdrqfull errors */
145 * Used to suppress multiple instances of same
146 * port staying stuck at same point.
148 u32 port_lastrcvhdrqtail;
149 /* saved total number of rcvhdrqfull errors for poll edge trigger */
150 u32 port_hdrqfull_poll;
151 /* total number of polled urgent packets */
153 /* saved total number of polled urgent packets for poll edge trigger */
154 u32 port_urgent_poll;
155 /* pid of process using this port */
157 pid_t port_subpid[INFINIPATH_MAX_SUBPORT];
158 /* same size as task_struct .comm[] */
160 /* pkeys set by this use of this port */
162 /* so file ops can get at unit */
163 struct ipath_devdata *port_dd;
164 /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */
165 void *subport_uregbase;
166 /* An array of pages for the eager receive buffers * N */
167 void *subport_rcvegrbuf;
168 /* An array of pages for the eager header queue entries * N */
169 void *subport_rcvhdr_base;
170 /* The version of the library which opened this port */
172 /* Bitmask of active slaves */
174 /* Type of packets or conditions we want to poll for */
176 /* port rcvhdrq head offset */
183 * control information for layered drivers
185 struct _ipath_layer {
189 struct ipath_skbinfo {
195 * Possible IB config parameters for ipath_f_get/set_ib_cfg()
197 #define IPATH_IB_CFG_LIDLMC 0 /* Get/set LID (LS16b) and Mask (MS16b) */
198 #define IPATH_IB_CFG_HRTBT 1 /* Get/set Heartbeat off/enable/auto */
199 #define IPATH_IB_HRTBT_ON 3 /* Heartbeat enabled, sent every 100msec */
200 #define IPATH_IB_HRTBT_OFF 0 /* Heartbeat off */
201 #define IPATH_IB_CFG_LWID_ENB 2 /* Get/set allowed Link-width */
202 #define IPATH_IB_CFG_LWID 3 /* Get currently active Link-width */
203 #define IPATH_IB_CFG_SPD_ENB 4 /* Get/set allowed Link speeds */
204 #define IPATH_IB_CFG_SPD 5 /* Get current Link spd */
205 #define IPATH_IB_CFG_RXPOL_ENB 6 /* Get/set Auto-RX-polarity enable */
206 #define IPATH_IB_CFG_LREV_ENB 7 /* Get/set Auto-Lane-reversal enable */
207 #define IPATH_IB_CFG_LINKLATENCY 8 /* Get Auto-Lane-reversal enable */
210 struct ipath_devdata {
211 struct list_head ipath_list;
213 struct ipath_kregs const *ipath_kregs;
214 struct ipath_cregs const *ipath_cregs;
216 /* mem-mapped pointer to base of chip regs */
217 u64 __iomem *ipath_kregbase;
218 /* end of mem-mapped chip space; range checking */
219 u64 __iomem *ipath_kregend;
220 /* physical address of chip for io_remap, etc. */
221 unsigned long ipath_physaddr;
222 /* base of memory alloced for ipath_kregbase, for free */
223 u64 *ipath_kregalloc;
225 * virtual address where port0 rcvhdrqtail updated for this unit.
226 * only written to by the chip, not the driver.
228 volatile __le64 *ipath_hdrqtailptr;
229 /* ipath_cfgports pointers */
230 struct ipath_portdata **ipath_pd;
231 /* sk_buffs used by port 0 eager receive queue */
232 struct ipath_skbinfo *ipath_port0_skbinfo;
233 /* kvirt address of 1st 2k pio buffer */
234 void __iomem *ipath_pio2kbase;
235 /* kvirt address of 1st 4k pio buffer */
236 void __iomem *ipath_pio4kbase;
238 * points to area where PIOavail registers will be DMA'ed.
239 * Has to be on a page of it's own, because the page will be
240 * mapped into user program space. This copy is *ONLY* ever
241 * written by DMA, not by the driver! Need a copy per device
242 * when we get to multiple devices
244 volatile __le64 *ipath_pioavailregs_dma;
245 /* physical address where updates occur */
246 dma_addr_t ipath_pioavailregs_phys;
247 struct _ipath_layer ipath_layer;
249 int (*ipath_f_intrsetup)(struct ipath_devdata *);
250 /* fallback to alternate interrupt type if possible */
251 int (*ipath_f_intr_fallback)(struct ipath_devdata *);
252 /* setup on-chip bus config */
253 int (*ipath_f_bus)(struct ipath_devdata *, struct pci_dev *);
254 /* hard reset chip */
255 int (*ipath_f_reset)(struct ipath_devdata *);
256 int (*ipath_f_get_boardname)(struct ipath_devdata *, char *,
258 void (*ipath_f_init_hwerrors)(struct ipath_devdata *);
259 void (*ipath_f_handle_hwerrors)(struct ipath_devdata *, char *,
261 void (*ipath_f_quiet_serdes)(struct ipath_devdata *);
262 int (*ipath_f_bringup_serdes)(struct ipath_devdata *);
263 int (*ipath_f_early_init)(struct ipath_devdata *);
264 void (*ipath_f_clear_tids)(struct ipath_devdata *, unsigned);
265 void (*ipath_f_put_tid)(struct ipath_devdata *, u64 __iomem*,
267 void (*ipath_f_tidtemplate)(struct ipath_devdata *);
268 void (*ipath_f_cleanup)(struct ipath_devdata *);
269 void (*ipath_f_setextled)(struct ipath_devdata *, u64, u64);
270 /* fill out chip-specific fields */
271 int (*ipath_f_get_base_info)(struct ipath_portdata *, void *);
273 void (*ipath_f_free_irq)(struct ipath_devdata *);
274 struct ipath_message_header *(*ipath_f_get_msgheader)
275 (struct ipath_devdata *, __le32 *);
276 void (*ipath_f_config_ports)(struct ipath_devdata *, ushort);
277 int (*ipath_f_get_ib_cfg)(struct ipath_devdata *, int);
278 int (*ipath_f_set_ib_cfg)(struct ipath_devdata *, int, u32);
279 void (*ipath_f_config_jint)(struct ipath_devdata *, u16 , u16);
280 void (*ipath_f_read_counters)(struct ipath_devdata *,
281 struct infinipath_counters *);
282 void (*ipath_f_xgxs_reset)(struct ipath_devdata *);
283 /* per chip actions needed for IB Link up/down changes */
284 int (*ipath_f_ib_updown)(struct ipath_devdata *, int, u64);
286 struct ipath_ibdev *verbs_dev;
287 struct timer_list verbs_timer;
288 /* total dwords sent (summed from counter) */
290 /* total dwords rcvd (summed from counter) */
292 /* total packets sent (summed from counter) */
294 /* total packets rcvd (summed from counter) */
296 /* ipath_statusp initially points to this. */
298 /* GUID for this interface, in network order */
301 * aggregrate of error bits reported since last cleared, for
302 * limiting of error reporting
304 ipath_err_t ipath_lasterror;
306 * aggregrate of error bits reported since last cleared, for
307 * limiting of hwerror reporting
309 ipath_err_t ipath_lasthwerror;
310 /* errors masked because they occur too fast */
311 ipath_err_t ipath_maskederrs;
312 /* time in jiffies at which to re-enable maskederrs */
313 unsigned long ipath_unmasktime;
314 /* count of egrfull errors, combined for all ports */
315 u64 ipath_last_tidfull;
316 /* for ipath_qcheck() */
317 u64 ipath_lastport0rcv_cnt;
318 /* template for writing TIDs */
319 u64 ipath_tidtemplate;
320 /* value to write to free TIDs */
321 u64 ipath_tidinvalid;
322 /* IBA6120 rcv interrupt setup */
323 u64 ipath_rhdrhead_intr_off;
325 /* size of memory at ipath_kregbase */
327 /* number of registers used for pioavail */
329 /* IPATH_POLL, etc. */
331 /* ipath_flags driver is waiting for */
332 u32 ipath_state_wanted;
333 /* last buffer for user use, first buf for kernel use is this
335 u32 ipath_lastport_piobuf;
336 /* is a stats timer active */
337 u32 ipath_stats_timer_active;
338 /* number of interrupts for this device -- saturates... */
339 u32 ipath_int_counter;
340 /* dwords sent read from counter */
342 /* dwords received read from counter */
344 /* sent packets read from counter */
346 /* received packets read from counter */
348 /* pio bufs allocated per port */
351 * number of ports configured as max; zero is set to number chip
352 * supports, less gives more pio bufs/port, etc.
355 /* count of port 0 hdrqfull errors */
356 u32 ipath_p0_hdrqfull;
357 /* port 0 number of receive eager buffers */
358 u32 ipath_p0_rcvegrcnt;
361 * index of last piobuffer we used. Speeds up searching, by
362 * starting at this point. Doesn't matter if multiple cpu's use and
363 * update, last updater is only write that matters. Whenever it
364 * wraps, we update shadow copies. Need a copy per device when we
365 * get to multiple devices
367 u32 ipath_lastpioindex;
368 /* max length of freezemsg */
371 * consecutive times we wanted a PIO buffer but were unable to
374 u32 ipath_consec_nopiobuf;
376 * hint that we should update ipath_pioavailshadow before
377 * looking for a PIO buffer
379 u32 ipath_upd_pio_shadow;
380 /* so we can rewrite it after a chip reset */
382 /* so we can rewrite it after a chip reset */
385 /* interrupt number */
387 /* HT/PCI Vendor ID (here for NodeInfo) */
389 /* HT/PCI Device ID (here for NodeInfo) */
391 /* offset in HT config space of slave/primary interface block */
392 u8 ipath_ht_slave_off;
393 /* for write combining settings */
394 unsigned long ipath_wc_cookie;
395 unsigned long ipath_wc_base;
396 unsigned long ipath_wc_len;
397 /* ref count for each pkey */
398 atomic_t ipath_pkeyrefs[4];
399 /* shadow copy of all exptids physaddr; used only by funcsim */
400 u64 *ipath_tidsimshadow;
401 /* shadow copy of struct page *'s for exp tid pages */
402 struct page **ipath_pageshadow;
403 /* shadow copy of dma handles for exp tid pages */
404 dma_addr_t *ipath_physshadow;
405 u64 __iomem *ipath_egrtidbase;
406 /* lock to workaround chip bug 9437 */
407 spinlock_t ipath_tid_lock;
408 spinlock_t ipath_sendctrl_lock;
412 * this address is mapped readonly into user processes so they can
413 * get status cheaply, whenever they want.
416 /* freeze msg if hw error put chip in freeze */
417 char *ipath_freezemsg;
418 /* pci access data structure */
419 struct pci_dev *pcidev;
420 struct cdev *user_cdev;
421 struct cdev *diag_cdev;
422 struct class_device *user_class_dev;
423 struct class_device *diag_class_dev;
424 /* timer used to prevent stats overflow, error throttling, etc. */
425 struct timer_list ipath_stats_timer;
426 void *ipath_dummy_hdrq; /* used after port close */
427 dma_addr_t ipath_dummy_hdrq_phys;
429 unsigned long ipath_ureg_align; /* user register alignment */
432 * Shadow copies of registers; size indicates read access size.
433 * Most of them are readonly, but some are write-only register,
434 * where we manipulate the bits in the shadow copy, and then write
435 * the shadow copy to infinipath.
437 * We deliberately make most of these 32 bits, since they have
438 * restricted range. For any that we read, we won't to generate 32
439 * bit accesses, since Opteron will generate 2 separate 32 bit HT
440 * transactions for a 64 bit read, and we want to avoid unnecessary
444 /* This is the 64 bit group */
447 * shadow of pioavail, check to be sure it's large enough at
450 unsigned long ipath_pioavailshadow[8];
451 /* shadow of kr_gpio_out, for rmw ops */
453 /* shadow the gpio mask register */
455 /* shadow the gpio output enable, etc... */
457 /* kr_revision shadow */
460 * shadow of ibcctrl, for interrupt handling of link changes,
465 * last ibcstatus, to suppress "duplicate" status change messages,
468 u64 ipath_lastibcstat;
469 /* hwerrmask shadow */
470 ipath_err_t ipath_hwerrmask;
471 ipath_err_t ipath_errormask; /* errormask shadow */
472 /* interrupt config reg shadow */
474 /* kr_sendpiobufbase value */
475 u64 ipath_piobufbase;
477 /* these are the "32 bit" regs */
480 * number of GUIDs in the flash for this interface; may need some
481 * rethinking for setting on other ifaces
485 * the following two are 32-bit bitmasks, but {test,clear,set}_bit
486 * all expect bit fields to be "unsigned long"
488 /* shadow kr_rcvctrl */
489 unsigned long ipath_rcvctrl;
490 /* shadow kr_sendctrl */
491 unsigned long ipath_sendctrl;
492 unsigned long ipath_lastcancel; /* to not count armlaunch after cancel */
494 /* value we put in kr_rcvhdrcnt */
496 /* value we put in kr_rcvhdrsize */
497 u32 ipath_rcvhdrsize;
498 /* value we put in kr_rcvhdrentsize */
499 u32 ipath_rcvhdrentsize;
500 /* offset of last entry in rcvhdrq */
502 /* kr_portcnt value */
504 /* kr_pagealign value */
506 /* number of "2KB" PIO buffers */
508 /* size in bytes of "2KB" PIO buffers */
510 /* number of "4KB" PIO buffers */
512 /* size in bytes of "4KB" PIO buffers */
514 /* kr_rcvegrbase value */
515 u32 ipath_rcvegrbase;
516 /* kr_rcvegrcnt value */
518 /* kr_rcvtidbase value */
519 u32 ipath_rcvtidbase;
520 /* kr_rcvtidcnt value */
526 /* kr_counterregbase */
528 /* shadow the control register contents */
530 /* PCI revision register (HTC rev on FPGA) */
533 /* chip address space used by 4k pio buffers */
535 /* The MTU programmed for this unit */
538 * The max size IB packet, included IB headers that we can send.
539 * Starts same as ipath_piosize, but is affected when ibmtu is
540 * changed, or by size of eager buffers
544 * ibmaxlen at init time, limited by chip and by receive buffer
545 * size. Not changed after init.
547 u32 ipath_init_ibmaxlen;
548 /* size of each rcvegrbuffer */
549 u32 ipath_rcvegrbufsize;
550 /* width (2,4,8,16,32) from HT config reg */
552 /* HT speed (200,400,800,1000) from HT config */
555 * number of sequential ibcstatus change for polling active/quiet
556 * (i.e., link not coming up).
559 /* low and high portions of MSI capability/vector */
561 /* saved after PCIe init for restore after reset */
563 /* MSI data (vector) saved for restore */
565 /* MLID programmed for this instance */
567 /* LID programmed for this instance */
569 /* list of pkeys programmed; 0 if not set */
572 * ASCII serial number, from flash, large enough for original
573 * all digit strings, and longer QLogic serial number format
576 /* human readable board version */
577 u8 ipath_boardversion[80];
578 /* chip major rev, from ipath_revision */
580 /* chip minor rev, from ipath_revision */
582 /* board rev, from ipath_revision */
585 u8 ipath_r_portenable_shift;
586 u8 ipath_r_intravail_shift;
587 u8 ipath_r_tailupd_shift;
588 u8 ipath_r_portcfg_shift;
590 /* unit # of this chip, if present */
592 /* saved for restore after reset */
593 u8 ipath_pci_cacheline;
594 /* LID mask control */
596 /* link width supported */
597 u8 ipath_link_width_supported;
598 /* link speed supported */
599 u8 ipath_link_speed_supported;
600 u8 ipath_link_width_enabled;
601 u8 ipath_link_speed_enabled;
602 u8 ipath_link_width_active;
603 u8 ipath_link_speed_active;
604 /* Rx Polarity inversion (compensate for ~tx on partner) */
607 /* local link integrity counter */
608 u32 ipath_lli_counter;
609 /* local link integrity errors */
610 u32 ipath_lli_errors;
612 * Above counts only cases where _successive_ LocalLinkIntegrity
613 * errors were seen in the receive headers of kern-packets.
614 * Below are the three (monotonically increasing) counters
615 * maintained via GPIO interrupts on iba6120-rev2.
617 u32 ipath_rxfc_unsupvl_errs;
618 u32 ipath_overrun_thresh_errs;
621 /* status check work */
622 struct delayed_work status_work;
625 * Not all devices managed by a driver instance are the same
626 * type, so these fields must be per-device.
628 u64 ipath_i_bitsextant;
629 ipath_err_t ipath_e_bitsextant;
630 ipath_err_t ipath_hwe_bitsextant;
633 * Below should be computable from number of ports,
634 * since they are never modified.
636 u32 ipath_i_rcvavail_mask;
637 u32 ipath_i_rcvurg_mask;
638 u16 ipath_i_rcvurg_shift;
639 u16 ipath_i_rcvavail_shift;
642 * Register bits for selecting i2c direction and values, used for
645 u16 ipath_gpio_sda_num;
646 u16 ipath_gpio_scl_num;
650 /* lock for doing RMW of shadows/regs for ExtCtrl and GPIO */
651 spinlock_t ipath_gpio_lock;
654 * IB link and linktraining states and masks that vary per chip in
655 * some way. Set at init, to avoid each IB status change interrupt
664 u16 ipath_rhf_offset; /* offset of RHF within receive header entry */
667 * shift/mask for linkcmd, linkinitcmd, maxpktlen in ibccontol
668 * reg. Changes for IBA7220
670 u8 ibcc_lic_mask; /* LinkInitCmd */
671 u8 ibcc_lc_shift; /* LinkCmd */
672 u8 ibcc_mpl_shift; /* Maxpktlen */
676 /* used to override LED behavior */
677 u8 ipath_led_override; /* Substituted for normal value, if non-zero */
678 u16 ipath_led_override_timeoff; /* delta to next timer event */
679 u8 ipath_led_override_vals[2]; /* Alternates per blink-frame */
680 u8 ipath_led_override_phase; /* Just counts, LSB picks from vals[] */
681 atomic_t ipath_led_override_timer_active;
682 /* Used to flash LEDs in override mode */
683 struct timer_list ipath_led_override_timer;
685 /* Support (including locks) for EEPROM logging of errors and time */
686 /* control access to actual counters, timer */
687 spinlock_t ipath_eep_st_lock;
688 /* control high-level access to EEPROM */
689 struct mutex ipath_eep_lock;
690 /* Below inc'd by ipath_snap_cntrs(), locked by ipath_eep_st_lock */
691 uint64_t ipath_traffic_wds;
692 /* active time is kept in seconds, but logged in hours */
693 atomic_t ipath_active_time;
694 /* Below are nominal shadow of EEPROM, new since last EEPROM update */
695 uint8_t ipath_eep_st_errs[IPATH_EEP_LOG_CNT];
696 uint8_t ipath_eep_st_new_errs[IPATH_EEP_LOG_CNT];
697 uint16_t ipath_eep_hrs;
699 * masks for which bits of errs, hwerrs that cause
700 * each of the counters to increment.
702 struct ipath_eep_log_mask ipath_eep_st_masks[IPATH_EEP_LOG_CNT];
704 /* interrupt mitigation reload register info */
705 u16 ipath_jint_idle_ticks; /* idle clock ticks */
706 u16 ipath_jint_max_packets; /* max packets across all ports */
709 /* Private data for file operations */
710 struct ipath_filedata {
711 struct ipath_portdata *pd;
715 extern struct list_head ipath_dev_list;
716 extern spinlock_t ipath_devs_lock;
717 extern struct ipath_devdata *ipath_lookup(int unit);
719 int ipath_init_chip(struct ipath_devdata *, int);
720 int ipath_enable_wc(struct ipath_devdata *dd);
721 void ipath_disable_wc(struct ipath_devdata *dd);
722 int ipath_count_units(int *npresentp, int *nupp, u32 *maxportsp);
723 void ipath_shutdown_device(struct ipath_devdata *);
724 void ipath_clear_freeze(struct ipath_devdata *);
726 struct file_operations;
727 int ipath_cdev_init(int minor, char *name, const struct file_operations *fops,
728 struct cdev **cdevp, struct class_device **class_devp);
729 void ipath_cdev_cleanup(struct cdev **cdevp,
730 struct class_device **class_devp);
732 int ipath_diag_add(struct ipath_devdata *);
733 void ipath_diag_remove(struct ipath_devdata *);
735 extern wait_queue_head_t ipath_state_wait;
737 int ipath_user_add(struct ipath_devdata *dd);
738 void ipath_user_remove(struct ipath_devdata *dd);
740 struct sk_buff *ipath_alloc_skb(struct ipath_devdata *dd, gfp_t);
742 extern int ipath_diag_inuse;
744 irqreturn_t ipath_intr(int irq, void *devid);
745 int ipath_decode_err(char *buf, size_t blen, ipath_err_t err);
746 #if __IPATH_INFO || __IPATH_DBG
747 extern const char *ipath_ibcstatus_str[];
750 /* clean up any per-chip chip-specific stuff */
751 void ipath_chip_cleanup(struct ipath_devdata *);
752 /* clean up any chip type-specific stuff */
753 void ipath_chip_done(void);
755 /* check to see if we have to force ordering for write combining */
756 int ipath_unordered_wc(void);
758 void ipath_disarm_piobufs(struct ipath_devdata *, unsigned first,
760 void ipath_cancel_sends(struct ipath_devdata *, int);
762 int ipath_create_rcvhdrq(struct ipath_devdata *, struct ipath_portdata *);
763 void ipath_free_pddata(struct ipath_devdata *, struct ipath_portdata *);
765 int ipath_parse_ushort(const char *str, unsigned short *valp);
767 void ipath_kreceive(struct ipath_portdata *);
768 int ipath_setrcvhdrsize(struct ipath_devdata *, unsigned);
769 int ipath_reset_device(int);
770 void ipath_get_faststats(unsigned long);
771 int ipath_set_linkstate(struct ipath_devdata *, u8);
772 int ipath_set_mtu(struct ipath_devdata *, u16);
773 int ipath_set_lid(struct ipath_devdata *, u32, u8);
774 int ipath_set_rx_pol_inv(struct ipath_devdata *dd, u8 new_pol_inv);
776 /* for use in system calls, where we want to know device type, etc. */
777 #define port_fp(fp) ((struct ipath_filedata *)(fp)->private_data)->pd
778 #define subport_fp(fp) \
779 ((struct ipath_filedata *)(fp)->private_data)->subport
780 #define tidcursor_fp(fp) \
781 ((struct ipath_filedata *)(fp)->private_data)->tidcursor
784 * values for ipath_flags
786 /* The chip is up and initted */
787 #define IPATH_INITTED 0x2
788 /* set if any user code has set kr_rcvhdrsize */
789 #define IPATH_RCVHDRSZ_SET 0x4
790 /* The chip is present and valid for accesses */
791 #define IPATH_PRESENT 0x8
792 /* HT link0 is only 8 bits wide, ignore upper byte crc
794 #define IPATH_8BIT_IN_HT0 0x10
795 /* HT link1 is only 8 bits wide, ignore upper byte crc
797 #define IPATH_8BIT_IN_HT1 0x20
798 /* The link is down */
799 #define IPATH_LINKDOWN 0x40
800 /* The link level is up (0x11) */
801 #define IPATH_LINKINIT 0x80
802 /* The link is in the armed (0x21) state */
803 #define IPATH_LINKARMED 0x100
804 /* The link is in the active (0x31) state */
805 #define IPATH_LINKACTIVE 0x200
806 /* link current state is unknown */
807 #define IPATH_LINKUNK 0x400
808 /* Write combining flush needed for PIO */
809 #define IPATH_PIO_FLUSH_WC 0x1000
810 /* no IB cable, or no device on IB cable */
811 #define IPATH_NOCABLE 0x4000
812 /* Supports port zero per packet receive interrupts via
814 #define IPATH_GPIO_INTR 0x8000
815 /* uses the coded 4byte TID, not 8 byte */
816 #define IPATH_4BYTE_TID 0x10000
817 /* packet/word counters are 32 bit, else those 4 counters
819 #define IPATH_32BITCOUNTERS 0x20000
820 /* can miss port0 rx interrupts */
821 /* Interrupt register is 64 bits */
822 #define IPATH_INTREG_64 0x40000
823 #define IPATH_DISABLED 0x80000 /* administratively disabled */
824 /* Use GPIO interrupts for new counters */
825 #define IPATH_GPIO_ERRINTRS 0x100000
826 #define IPATH_SWAP_PIOBUFS 0x200000
828 /* Bits in GPIO for the added interrupts */
829 #define IPATH_GPIO_PORT0_BIT 2
830 #define IPATH_GPIO_RXUVL_BIT 3
831 #define IPATH_GPIO_OVRUN_BIT 4
832 #define IPATH_GPIO_LLI_BIT 5
833 #define IPATH_GPIO_ERRINTR_MASK 0x38
835 /* portdata flag bit offsets */
836 /* waiting for a packet to arrive */
837 #define IPATH_PORT_WAITING_RCV 2
838 /* master has not finished initializing */
839 #define IPATH_PORT_MASTER_UNINIT 4
840 /* waiting for an urgent packet to arrive */
841 #define IPATH_PORT_WAITING_URG 5
843 /* free up any allocated data at closes */
844 void ipath_free_data(struct ipath_portdata *dd);
845 u32 __iomem *ipath_getpiobuf(struct ipath_devdata *, u32 *);
846 void ipath_init_iba6120_funcs(struct ipath_devdata *);
847 void ipath_init_iba6110_funcs(struct ipath_devdata *);
848 void ipath_get_eeprom_info(struct ipath_devdata *);
849 int ipath_update_eeprom_log(struct ipath_devdata *dd);
850 void ipath_inc_eeprom_err(struct ipath_devdata *dd, u32 eidx, u32 incr);
851 u64 ipath_snap_cntr(struct ipath_devdata *, ipath_creg);
852 void signal_ib_event(struct ipath_devdata *dd, enum ib_event_type ev);
855 * Set LED override, only the two LSBs have "public" meaning, but
856 * any non-zero value substitutes them for the Link and LinkTrain
859 #define IPATH_LED_PHYS 1 /* Physical (linktraining) GREEN LED */
860 #define IPATH_LED_LOG 2 /* Logical (link) YELLOW LED */
861 void ipath_set_led_override(struct ipath_devdata *dd, unsigned int val);
864 * number of words used for protocol header if not set by ipath_userinit();
866 #define IPATH_DFLT_RCVHDRSIZE 9
868 int ipath_get_user_pages(unsigned long, size_t, struct page **);
869 void ipath_release_user_pages(struct page **, size_t);
870 void ipath_release_user_pages_on_close(struct page **, size_t);
871 int ipath_eeprom_read(struct ipath_devdata *, u8, void *, int);
872 int ipath_eeprom_write(struct ipath_devdata *, u8, const void *, int);
874 /* these are used for the registers that vary with port */
875 void ipath_write_kreg_port(const struct ipath_devdata *, ipath_kreg,
879 * We could have a single register get/put routine, that takes a group type,
880 * but this is somewhat clearer and cleaner. It also gives us some error
881 * checking. 64 bit register reads should always work, but are inefficient
882 * on opteron (the northbridge always generates 2 separate HT 32 bit reads),
883 * so we use kreg32 wherever possible. User register and counter register
884 * reads are always 32 bit reads, so only one form of those routines.
888 * At the moment, none of the s-registers are writable, so no
889 * ipath_write_sreg(), and none of the c-registers are writable, so no
890 * ipath_write_creg().
894 * ipath_read_ureg32 - read 32-bit virtualized per-port register
896 * @regno: register number
899 * Return the contents of a register that is virtualized to be per port.
900 * Returns -1 on errors (not distinguishable from valid contents at
901 * runtime; we may add a separate error variable at some point).
903 static inline u32 ipath_read_ureg32(const struct ipath_devdata *dd,
904 ipath_ureg regno, int port)
906 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
909 return readl(regno + (u64 __iomem *)
910 (dd->ipath_uregbase +
911 (char __iomem *)dd->ipath_kregbase +
912 dd->ipath_ureg_align * port));
916 * ipath_write_ureg - write 32-bit virtualized per-port register
918 * @regno: register number
922 * Write the contents of a register that is virtualized to be per port.
924 static inline void ipath_write_ureg(const struct ipath_devdata *dd,
925 ipath_ureg regno, u64 value, int port)
927 u64 __iomem *ubase = (u64 __iomem *)
928 (dd->ipath_uregbase + (char __iomem *) dd->ipath_kregbase +
929 dd->ipath_ureg_align * port);
930 if (dd->ipath_kregbase)
931 writeq(value, &ubase[regno]);
934 static inline u32 ipath_read_kreg32(const struct ipath_devdata *dd,
937 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
939 return readl((u32 __iomem *) & dd->ipath_kregbase[regno]);
942 static inline u64 ipath_read_kreg64(const struct ipath_devdata *dd,
945 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
948 return readq(&dd->ipath_kregbase[regno]);
951 static inline void ipath_write_kreg(const struct ipath_devdata *dd,
952 ipath_kreg regno, u64 value)
954 if (dd->ipath_kregbase)
955 writeq(value, &dd->ipath_kregbase[regno]);
958 static inline u64 ipath_read_creg(const struct ipath_devdata *dd,
961 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
964 return readq(regno + (u64 __iomem *)
965 (dd->ipath_cregbase +
966 (char __iomem *)dd->ipath_kregbase));
969 static inline u32 ipath_read_creg32(const struct ipath_devdata *dd,
972 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
974 return readl(regno + (u64 __iomem *)
975 (dd->ipath_cregbase +
976 (char __iomem *)dd->ipath_kregbase));
979 static inline void ipath_write_creg(const struct ipath_devdata *dd,
980 ipath_creg regno, u64 value)
982 if (dd->ipath_kregbase)
983 writeq(value, regno + (u64 __iomem *)
984 (dd->ipath_cregbase +
985 (char __iomem *)dd->ipath_kregbase));
988 static inline void ipath_clear_rcvhdrtail(const struct ipath_portdata *pd)
990 *((u64 *) pd->port_rcvhdrtail_kvaddr) = 0ULL;
993 static inline u32 ipath_get_rcvhdrtail(const struct ipath_portdata *pd)
995 return (u32) le64_to_cpu(*((volatile __le64 *)
996 pd->port_rcvhdrtail_kvaddr));
999 static inline u64 ipath_read_ireg(const struct ipath_devdata *dd, ipath_kreg r)
1001 return (dd->ipath_flags & IPATH_INTREG_64) ?
1002 ipath_read_kreg64(dd, r) : ipath_read_kreg32(dd, r);
1006 * from contents of IBCStatus (or a saved copy), return linkstate
1007 * Report ACTIVE_DEFER as ACTIVE, because we treat them the same
1008 * everywhere, anyway (and should be, for almost all purposes).
1010 static inline u32 ipath_ib_linkstate(struct ipath_devdata *dd, u64 ibcs)
1012 u32 state = (u32)(ibcs >> dd->ibcs_ls_shift) &
1013 INFINIPATH_IBCS_LINKSTATE_MASK;
1014 if (state == INFINIPATH_IBCS_L_STATE_ACT_DEFER)
1015 state = INFINIPATH_IBCS_L_STATE_ACTIVE;
1019 /* from contents of IBCStatus (or a saved copy), return linktrainingstate */
1020 static inline u32 ipath_ib_linktrstate(struct ipath_devdata *dd, u64 ibcs)
1022 return (u32)(ibcs >> INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) &
1030 struct device_driver;
1032 extern const char ib_ipath_version[];
1034 extern struct attribute_group *ipath_driver_attr_groups[];
1036 int ipath_device_create_group(struct device *, struct ipath_devdata *);
1037 void ipath_device_remove_group(struct device *, struct ipath_devdata *);
1038 int ipath_expose_reset(struct device *);
1040 int ipath_init_ipathfs(void);
1041 void ipath_exit_ipathfs(void);
1042 int ipathfs_add_device(struct ipath_devdata *);
1043 int ipathfs_remove_device(struct ipath_devdata *);
1046 * dma_addr wrappers - all 0's invalid for hw
1048 dma_addr_t ipath_map_page(struct pci_dev *, struct page *, unsigned long,
1050 dma_addr_t ipath_map_single(struct pci_dev *, void *, size_t, int);
1053 * Flush write combining store buffers (if present) and perform a write
1056 #if defined(CONFIG_X86_64)
1057 #define ipath_flush_wc() asm volatile("sfence" ::: "memory")
1059 #define ipath_flush_wc() wmb()
1062 extern unsigned ipath_debug; /* debugging bit mask */
1064 #define IPATH_MAX_PARITY_ATTEMPTS 10000 /* max times to try recovery */
1066 const char *ipath_get_unit_name(int unit);
1068 extern struct mutex ipath_mutex;
1070 #define IPATH_DRV_NAME "ib_ipath"
1071 #define IPATH_MAJOR 233
1072 #define IPATH_USER_MINOR_BASE 0
1073 #define IPATH_DIAGPKT_MINOR 127
1074 #define IPATH_DIAG_MINOR_BASE 129
1075 #define IPATH_NMINORS 255
1077 #define ipath_dev_err(dd,fmt,...) \
1079 const struct ipath_devdata *__dd = (dd); \
1081 dev_err(&__dd->pcidev->dev, "%s: " fmt, \
1082 ipath_get_unit_name(__dd->ipath_unit), \
1085 printk(KERN_ERR IPATH_DRV_NAME ": %s: " fmt, \
1086 ipath_get_unit_name(__dd->ipath_unit), \
1090 #if _IPATH_DEBUGGING
1092 # define __IPATH_DBG_WHICH(which,fmt,...) \
1094 if(unlikely(ipath_debug&(which))) \
1095 printk(KERN_DEBUG IPATH_DRV_NAME ": %s: " fmt, \
1096 __func__,##__VA_ARGS__); \
1099 # define ipath_dbg(fmt,...) \
1100 __IPATH_DBG_WHICH(__IPATH_DBG,fmt,##__VA_ARGS__)
1101 # define ipath_cdbg(which,fmt,...) \
1102 __IPATH_DBG_WHICH(__IPATH_##which##DBG,fmt,##__VA_ARGS__)
1104 #else /* ! _IPATH_DEBUGGING */
1106 # define ipath_dbg(fmt,...)
1107 # define ipath_cdbg(which,fmt,...)
1109 #endif /* _IPATH_DEBUGGING */
1112 * this is used for formatting hw error messages...
1114 struct ipath_hwerror_msgs {
1119 #define INFINIPATH_HWE_MSG(a, b) { .mask = INFINIPATH_HWE_##a, .msg = b }
1121 /* in ipath_intr.c... */
1122 void ipath_format_hwerrors(u64 hwerrs,
1123 const struct ipath_hwerror_msgs *hwerrmsgs,
1125 char *msg, size_t lmsg);
1127 #endif /* _IPATH_KERNEL_H */