2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/module.h>
37 static int ocqp_support = 1;
38 module_param(ocqp_support, int, 0644);
39 MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)");
41 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
44 spin_lock_irqsave(&qhp->lock, flag);
45 qhp->attr.state = state;
46 spin_unlock_irqrestore(&qhp->lock, flag);
49 static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
51 c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
54 static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
56 dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
57 pci_unmap_addr(sq, mapping));
60 static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
63 dealloc_oc_sq(rdev, sq);
65 dealloc_host_sq(rdev, sq);
68 static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
70 if (!ocqp_support || !t4_ocqp_supported())
72 sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
75 sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
76 rdev->lldi.vr->ocq.start;
77 sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
78 rdev->lldi.vr->ocq.start);
79 sq->flags |= T4_SQ_ONCHIP;
83 static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
85 sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
86 &(sq->dma_addr), GFP_KERNEL);
89 sq->phys_addr = virt_to_phys(sq->queue);
90 pci_unmap_addr_set(sq, mapping, sq->dma_addr);
94 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
95 struct c4iw_dev_ucontext *uctx)
98 * uP clears EQ contexts when the connection exits rdma mode,
99 * so no need to post a RESET WR for these EQs.
101 dma_free_coherent(&(rdev->lldi.pdev->dev),
102 wq->rq.memsize, wq->rq.queue,
103 dma_unmap_addr(&wq->rq, mapping));
104 dealloc_sq(rdev, &wq->sq);
105 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
108 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
109 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
113 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
114 struct t4_cq *rcq, struct t4_cq *scq,
115 struct c4iw_dev_ucontext *uctx)
117 int user = (uctx != &rdev->uctx);
118 struct fw_ri_res_wr *res_wr;
119 struct fw_ri_res *res;
121 struct c4iw_wr_wait wr_wait;
126 wq->sq.qid = c4iw_get_qpid(rdev, uctx);
130 wq->rq.qid = c4iw_get_qpid(rdev, uctx);
135 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
140 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
147 * RQT must be a power of 2.
149 wq->rq.rqt_size = roundup_pow_of_two(wq->rq.size);
150 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
151 if (!wq->rq.rqt_hwaddr)
155 if (alloc_oc_sq(rdev, &wq->sq) && alloc_host_sq(rdev, &wq->sq))
158 if (alloc_host_sq(rdev, &wq->sq))
160 memset(wq->sq.queue, 0, wq->sq.memsize);
161 dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
163 wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev),
164 wq->rq.memsize, &(wq->rq.dma_addr),
168 PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
169 __func__, wq->sq.queue,
170 (unsigned long long)virt_to_phys(wq->sq.queue),
172 (unsigned long long)virt_to_phys(wq->rq.queue));
173 memset(wq->rq.queue, 0, wq->rq.memsize);
174 dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
176 wq->db = rdev->lldi.db_reg;
177 wq->gts = rdev->lldi.gts_reg;
179 wq->sq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
180 (wq->sq.qid << rdev->qpshift);
181 wq->sq.udb &= PAGE_MASK;
182 wq->rq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
183 (wq->rq.qid << rdev->qpshift);
184 wq->rq.udb &= PAGE_MASK;
189 /* build fw_ri_res_wr */
190 wr_len = sizeof *res_wr + 2 * sizeof *res;
192 skb = alloc_skb(wr_len, GFP_KERNEL);
197 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
199 res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
200 memset(res_wr, 0, wr_len);
201 res_wr->op_nres = cpu_to_be32(
202 FW_WR_OP(FW_RI_RES_WR) |
203 V_FW_RI_RES_WR_NRES(2) |
205 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
206 res_wr->cookie = (unsigned long) &wr_wait;
208 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
209 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
212 * eqsize is the number of 64B entries plus the status page size.
214 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
216 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
217 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
218 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
219 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
220 (t4_sq_onchip(&wq->sq) ? F_FW_RI_RES_WR_ONCHIP : 0) |
221 V_FW_RI_RES_WR_IQID(scq->cqid));
222 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
223 V_FW_RI_RES_WR_DCAEN(0) |
224 V_FW_RI_RES_WR_DCACPU(0) |
225 V_FW_RI_RES_WR_FBMIN(2) |
226 V_FW_RI_RES_WR_FBMAX(2) |
227 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
228 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
229 V_FW_RI_RES_WR_EQSIZE(eqsize));
230 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
231 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
233 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
234 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
237 * eqsize is the number of 64B entries plus the status page size.
239 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
240 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
241 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
242 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
243 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
244 V_FW_RI_RES_WR_IQID(rcq->cqid));
245 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
246 V_FW_RI_RES_WR_DCAEN(0) |
247 V_FW_RI_RES_WR_DCACPU(0) |
248 V_FW_RI_RES_WR_FBMIN(2) |
249 V_FW_RI_RES_WR_FBMAX(2) |
250 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
251 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
252 V_FW_RI_RES_WR_EQSIZE(eqsize));
253 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
254 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
256 c4iw_init_wr_wait(&wr_wait);
258 ret = c4iw_ofld_send(rdev, skb);
261 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__);
265 PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%llx rqudb 0x%llx\n",
266 __func__, wq->sq.qid, wq->rq.qid, wq->db,
267 (unsigned long long)wq->sq.udb, (unsigned long long)wq->rq.udb);
271 dma_free_coherent(&(rdev->lldi.pdev->dev),
272 wq->rq.memsize, wq->rq.queue,
273 dma_unmap_addr(&wq->rq, mapping));
275 dealloc_sq(rdev, &wq->sq);
277 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
283 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
285 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
289 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
290 struct ib_send_wr *wr, int max, u32 *plenp)
297 dstp = (u8 *)immdp->data;
298 for (i = 0; i < wr->num_sge; i++) {
299 if ((plen + wr->sg_list[i].length) > max)
301 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
302 plen += wr->sg_list[i].length;
303 rem = wr->sg_list[i].length;
305 if (dstp == (u8 *)&sq->queue[sq->size])
306 dstp = (u8 *)sq->queue;
307 if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
310 len = (u8 *)&sq->queue[sq->size] - dstp;
311 memcpy(dstp, srcp, len);
317 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
319 memset(dstp, 0, len);
320 immdp->op = FW_RI_DATA_IMMD;
323 immdp->immdlen = cpu_to_be32(plen);
328 static int build_isgl(__be64 *queue_start, __be64 *queue_end,
329 struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
330 int num_sge, u32 *plenp)
335 __be64 *flitp = (__be64 *)isglp->sge;
337 for (i = 0; i < num_sge; i++) {
338 if ((plen + sg_list[i].length) < plen)
340 plen += sg_list[i].length;
341 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
343 if (++flitp == queue_end)
345 *flitp = cpu_to_be64(sg_list[i].addr);
346 if (++flitp == queue_end)
349 *flitp = (__force __be64)0;
350 isglp->op = FW_RI_DATA_ISGL;
352 isglp->nsge = cpu_to_be16(num_sge);
359 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
360 struct ib_send_wr *wr, u8 *len16)
366 if (wr->num_sge > T4_MAX_SEND_SGE)
368 switch (wr->opcode) {
370 if (wr->send_flags & IB_SEND_SOLICITED)
371 wqe->send.sendop_pkd = cpu_to_be32(
372 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE));
374 wqe->send.sendop_pkd = cpu_to_be32(
375 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND));
376 wqe->send.stag_inv = 0;
378 case IB_WR_SEND_WITH_INV:
379 if (wr->send_flags & IB_SEND_SOLICITED)
380 wqe->send.sendop_pkd = cpu_to_be32(
381 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV));
383 wqe->send.sendop_pkd = cpu_to_be32(
384 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV));
385 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
394 if (wr->send_flags & IB_SEND_INLINE) {
395 ret = build_immd(sq, wqe->send.u.immd_src, wr,
396 T4_MAX_SEND_INLINE, &plen);
399 size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
402 ret = build_isgl((__be64 *)sq->queue,
403 (__be64 *)&sq->queue[sq->size],
404 wqe->send.u.isgl_src,
405 wr->sg_list, wr->num_sge, &plen);
408 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
409 wr->num_sge * sizeof(struct fw_ri_sge);
412 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
413 wqe->send.u.immd_src[0].r1 = 0;
414 wqe->send.u.immd_src[0].r2 = 0;
415 wqe->send.u.immd_src[0].immdlen = 0;
416 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
419 *len16 = DIV_ROUND_UP(size, 16);
420 wqe->send.plen = cpu_to_be32(plen);
424 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
425 struct ib_send_wr *wr, u8 *len16)
431 if (wr->num_sge > T4_MAX_SEND_SGE)
434 wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey);
435 wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr);
437 if (wr->send_flags & IB_SEND_INLINE) {
438 ret = build_immd(sq, wqe->write.u.immd_src, wr,
439 T4_MAX_WRITE_INLINE, &plen);
442 size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
445 ret = build_isgl((__be64 *)sq->queue,
446 (__be64 *)&sq->queue[sq->size],
447 wqe->write.u.isgl_src,
448 wr->sg_list, wr->num_sge, &plen);
451 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
452 wr->num_sge * sizeof(struct fw_ri_sge);
455 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
456 wqe->write.u.immd_src[0].r1 = 0;
457 wqe->write.u.immd_src[0].r2 = 0;
458 wqe->write.u.immd_src[0].immdlen = 0;
459 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
462 *len16 = DIV_ROUND_UP(size, 16);
463 wqe->write.plen = cpu_to_be32(plen);
467 static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
472 wqe->read.stag_src = cpu_to_be32(wr->wr.rdma.rkey);
473 wqe->read.to_src_hi = cpu_to_be32((u32)(wr->wr.rdma.remote_addr
475 wqe->read.to_src_lo = cpu_to_be32((u32)wr->wr.rdma.remote_addr);
476 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
477 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
478 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
480 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
482 wqe->read.stag_src = cpu_to_be32(2);
483 wqe->read.to_src_hi = 0;
484 wqe->read.to_src_lo = 0;
485 wqe->read.stag_sink = cpu_to_be32(2);
487 wqe->read.to_sink_hi = 0;
488 wqe->read.to_sink_lo = 0;
492 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
496 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
497 struct ib_recv_wr *wr, u8 *len16)
501 ret = build_isgl((__be64 *)qhp->wq.rq.queue,
502 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
503 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
506 *len16 = DIV_ROUND_UP(sizeof wqe->recv +
507 wr->num_sge * sizeof(struct fw_ri_sge), 16);
511 static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe,
512 struct ib_send_wr *wr, u8 *len16)
515 struct fw_ri_immd *imdp;
518 int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32);
521 if (wr->wr.fast_reg.page_list_len > T4_MAX_FR_DEPTH)
524 wqe->fr.qpbinde_to_dcacpu = 0;
525 wqe->fr.pgsz_shift = wr->wr.fast_reg.page_shift - 12;
526 wqe->fr.addr_type = FW_RI_VA_BASED_TO;
527 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->wr.fast_reg.access_flags);
529 wqe->fr.len_lo = cpu_to_be32(wr->wr.fast_reg.length);
530 wqe->fr.stag = cpu_to_be32(wr->wr.fast_reg.rkey);
531 wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32);
532 wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start &
534 WARN_ON(pbllen > T4_MAX_FR_IMMD);
535 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
536 imdp->op = FW_RI_DATA_IMMD;
539 imdp->immdlen = cpu_to_be32(pbllen);
540 p = (__be64 *)(imdp + 1);
542 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
543 *p = cpu_to_be64((u64)wr->wr.fast_reg.page_list->page_list[i]);
545 if (++p == (__be64 *)&sq->queue[sq->size])
546 p = (__be64 *)sq->queue;
552 if (++p == (__be64 *)&sq->queue[sq->size])
553 p = (__be64 *)sq->queue;
555 *len16 = DIV_ROUND_UP(sizeof wqe->fr + sizeof *imdp + pbllen, 16);
559 static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr,
562 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
564 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
568 void c4iw_qp_add_ref(struct ib_qp *qp)
570 PDBG("%s ib_qp %p\n", __func__, qp);
571 atomic_inc(&(to_c4iw_qp(qp)->refcnt));
574 void c4iw_qp_rem_ref(struct ib_qp *qp)
576 PDBG("%s ib_qp %p\n", __func__, qp);
577 if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt)))
578 wake_up(&(to_c4iw_qp(qp)->wait));
581 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
582 struct ib_send_wr **bad_wr)
586 enum fw_wr_opcodes fw_opcode = 0;
587 enum fw_ri_wr_flags fw_flags;
591 struct t4_swsqe *swsqe;
595 qhp = to_c4iw_qp(ibqp);
596 spin_lock_irqsave(&qhp->lock, flag);
597 if (t4_wq_in_error(&qhp->wq)) {
598 spin_unlock_irqrestore(&qhp->lock, flag);
601 num_wrs = t4_sq_avail(&qhp->wq);
603 spin_unlock_irqrestore(&qhp->lock, flag);
612 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
613 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
616 if (wr->send_flags & IB_SEND_SOLICITED)
617 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
618 if (wr->send_flags & IB_SEND_SIGNALED)
619 fw_flags |= FW_RI_COMPLETION_FLAG;
620 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
621 switch (wr->opcode) {
622 case IB_WR_SEND_WITH_INV:
624 if (wr->send_flags & IB_SEND_FENCE)
625 fw_flags |= FW_RI_READ_FENCE_FLAG;
626 fw_opcode = FW_RI_SEND_WR;
627 if (wr->opcode == IB_WR_SEND)
628 swsqe->opcode = FW_RI_SEND;
630 swsqe->opcode = FW_RI_SEND_WITH_INV;
631 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
633 case IB_WR_RDMA_WRITE:
634 fw_opcode = FW_RI_RDMA_WRITE_WR;
635 swsqe->opcode = FW_RI_RDMA_WRITE;
636 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
638 case IB_WR_RDMA_READ:
639 case IB_WR_RDMA_READ_WITH_INV:
640 fw_opcode = FW_RI_RDMA_READ_WR;
641 swsqe->opcode = FW_RI_READ_REQ;
642 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
643 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
646 err = build_rdma_read(wqe, wr, &len16);
649 swsqe->read_len = wr->sg_list[0].length;
650 if (!qhp->wq.sq.oldest_read)
651 qhp->wq.sq.oldest_read = swsqe;
653 case IB_WR_FAST_REG_MR:
654 fw_opcode = FW_RI_FR_NSMR_WR;
655 swsqe->opcode = FW_RI_FAST_REGISTER;
656 err = build_fastreg(&qhp->wq.sq, wqe, wr, &len16);
658 case IB_WR_LOCAL_INV:
659 if (wr->send_flags & IB_SEND_FENCE)
660 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
661 fw_opcode = FW_RI_INV_LSTAG_WR;
662 swsqe->opcode = FW_RI_LOCAL_INV;
663 err = build_inv_stag(wqe, wr, &len16);
666 PDBG("%s post of type=%d TBD!\n", __func__,
674 swsqe->idx = qhp->wq.sq.pidx;
676 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED);
677 swsqe->wr_id = wr->wr_id;
679 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
681 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
682 __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
683 swsqe->opcode, swsqe->read_len);
686 t4_sq_produce(&qhp->wq, len16);
687 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
689 if (t4_wq_db_enabled(&qhp->wq))
690 t4_ring_sq_db(&qhp->wq, idx);
691 spin_unlock_irqrestore(&qhp->lock, flag);
695 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
696 struct ib_recv_wr **bad_wr)
700 union t4_recv_wr *wqe;
706 qhp = to_c4iw_qp(ibqp);
707 spin_lock_irqsave(&qhp->lock, flag);
708 if (t4_wq_in_error(&qhp->wq)) {
709 spin_unlock_irqrestore(&qhp->lock, flag);
712 num_wrs = t4_rq_avail(&qhp->wq);
714 spin_unlock_irqrestore(&qhp->lock, flag);
718 if (wr->num_sge > T4_MAX_RECV_SGE) {
723 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
727 err = build_rdma_recv(qhp, wqe, wr, &len16);
735 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
737 wqe->recv.opcode = FW_RI_RECV_WR;
739 wqe->recv.wrid = qhp->wq.rq.pidx;
743 wqe->recv.len16 = len16;
744 PDBG("%s cookie 0x%llx pidx %u\n", __func__,
745 (unsigned long long) wr->wr_id, qhp->wq.rq.pidx);
746 t4_rq_produce(&qhp->wq, len16);
747 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
751 if (t4_wq_db_enabled(&qhp->wq))
752 t4_ring_rq_db(&qhp->wq, idx);
753 spin_unlock_irqrestore(&qhp->lock, flag);
757 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, struct ib_mw_bind *mw_bind)
762 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
772 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
777 status = CQE_STATUS(err_cqe);
778 opcode = CQE_OPCODE(err_cqe);
779 rqtype = RQ_TYPE(err_cqe);
780 send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
781 (opcode == FW_RI_SEND_WITH_SE_INV);
782 tagged = (opcode == FW_RI_RDMA_WRITE) ||
783 (rqtype && (opcode == FW_RI_READ_RESP));
788 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
789 *ecode = RDMAP_CANT_INV_STAG;
791 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
792 *ecode = RDMAP_INV_STAG;
796 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
797 if ((opcode == FW_RI_SEND_WITH_INV) ||
798 (opcode == FW_RI_SEND_WITH_SE_INV))
799 *ecode = RDMAP_CANT_INV_STAG;
801 *ecode = RDMAP_STAG_NOT_ASSOC;
804 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
805 *ecode = RDMAP_STAG_NOT_ASSOC;
808 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
809 *ecode = RDMAP_ACC_VIOL;
812 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
813 *ecode = RDMAP_TO_WRAP;
817 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
818 *ecode = DDPT_BASE_BOUNDS;
820 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
821 *ecode = RDMAP_BASE_BOUNDS;
824 case T4_ERR_INVALIDATE_SHARED_MR:
825 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
826 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
827 *ecode = RDMAP_CANT_INV_STAG;
830 case T4_ERR_ECC_PSTAG:
831 case T4_ERR_INTERNAL_ERR:
832 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
835 case T4_ERR_OUT_OF_RQE:
836 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
837 *ecode = DDPU_INV_MSN_NOBUF;
839 case T4_ERR_PBL_ADDR_BOUND:
840 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
841 *ecode = DDPT_BASE_BOUNDS;
844 *layer_type = LAYER_MPA|DDP_LLP;
845 *ecode = MPA_CRC_ERR;
848 *layer_type = LAYER_MPA|DDP_LLP;
849 *ecode = MPA_MARKER_ERR;
851 case T4_ERR_PDU_LEN_ERR:
852 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
853 *ecode = DDPU_MSG_TOOBIG;
855 case T4_ERR_DDP_VERSION:
857 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
858 *ecode = DDPT_INV_VERS;
860 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
861 *ecode = DDPU_INV_VERS;
864 case T4_ERR_RDMA_VERSION:
865 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
866 *ecode = RDMAP_INV_VERS;
869 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
870 *ecode = RDMAP_INV_OPCODE;
872 case T4_ERR_DDP_QUEUE_NUM:
873 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
874 *ecode = DDPU_INV_QN;
878 case T4_ERR_MSN_RANGE:
879 case T4_ERR_IRD_OVERFLOW:
880 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
881 *ecode = DDPU_INV_MSN_RANGE;
884 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
888 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
889 *ecode = DDPU_INV_MO;
892 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
898 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
901 struct fw_ri_wr *wqe;
903 struct terminate_message *term;
905 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
908 skb = alloc_skb(sizeof *wqe, gfp);
911 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
913 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
914 memset(wqe, 0, sizeof *wqe);
915 wqe->op_compl = cpu_to_be32(FW_WR_OP(FW_RI_INIT_WR));
916 wqe->flowid_len16 = cpu_to_be32(
917 FW_WR_FLOWID(qhp->ep->hwtid) |
918 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
920 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
921 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
922 term = (struct terminate_message *)wqe->u.terminate.termmsg;
923 if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) {
924 term->layer_etype = qhp->attr.layer_etype;
925 term->ecode = qhp->attr.ecode;
927 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
928 c4iw_ofld_send(&qhp->rhp->rdev, skb);
932 * Assumes qhp lock is held.
934 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
935 struct c4iw_cq *schp)
941 PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
943 /* locking hierarchy: cq lock first, then qp lock. */
944 spin_lock_irqsave(&rchp->lock, flag);
945 spin_lock(&qhp->lock);
946 c4iw_flush_hw_cq(&rchp->cq);
947 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
948 flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
949 spin_unlock(&qhp->lock);
950 spin_unlock_irqrestore(&rchp->lock, flag);
952 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
953 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
954 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
957 /* locking hierarchy: cq lock first, then qp lock. */
958 spin_lock_irqsave(&schp->lock, flag);
959 spin_lock(&qhp->lock);
960 c4iw_flush_hw_cq(&schp->cq);
961 c4iw_count_scqes(&schp->cq, &qhp->wq, &count);
962 flushed = c4iw_flush_sq(&qhp->wq, &schp->cq, count);
963 spin_unlock(&qhp->lock);
964 spin_unlock_irqrestore(&schp->lock, flag);
966 spin_lock_irqsave(&schp->comp_handler_lock, flag);
967 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context);
968 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
972 static void flush_qp(struct c4iw_qp *qhp)
974 struct c4iw_cq *rchp, *schp;
977 rchp = get_chp(qhp->rhp, qhp->attr.rcq);
978 schp = get_chp(qhp->rhp, qhp->attr.scq);
980 if (qhp->ibqp.uobject) {
981 t4_set_wq_in_error(&qhp->wq);
982 t4_set_cq_in_error(&rchp->cq);
983 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
984 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
985 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
987 t4_set_cq_in_error(&schp->cq);
988 spin_lock_irqsave(&schp->comp_handler_lock, flag);
989 (*schp->ibcq.comp_handler)(&schp->ibcq,
990 schp->ibcq.cq_context);
991 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
995 __flush_qp(qhp, rchp, schp);
998 static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1001 struct fw_ri_wr *wqe;
1003 struct sk_buff *skb;
1005 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1008 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1011 set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
1013 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1014 memset(wqe, 0, sizeof *wqe);
1015 wqe->op_compl = cpu_to_be32(
1016 FW_WR_OP(FW_RI_INIT_WR) |
1018 wqe->flowid_len16 = cpu_to_be32(
1019 FW_WR_FLOWID(ep->hwtid) |
1020 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1021 wqe->cookie = (unsigned long) &ep->com.wr_wait;
1023 wqe->u.fini.type = FW_RI_TYPE_FINI;
1024 ret = c4iw_ofld_send(&rhp->rdev, skb);
1028 ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid,
1029 qhp->wq.sq.qid, __func__);
1031 PDBG("%s ret %d\n", __func__, ret);
1035 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1037 PDBG("%s p2p_type = %d\n", __func__, p2p_type);
1038 memset(&init->u, 0, sizeof init->u);
1040 case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1041 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1042 init->u.write.stag_sink = cpu_to_be32(1);
1043 init->u.write.to_sink = cpu_to_be64(1);
1044 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1045 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1046 sizeof(struct fw_ri_immd),
1049 case FW_RI_INIT_P2PTYPE_READ_REQ:
1050 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1051 init->u.read.stag_src = cpu_to_be32(1);
1052 init->u.read.to_src_lo = cpu_to_be32(1);
1053 init->u.read.stag_sink = cpu_to_be32(1);
1054 init->u.read.to_sink_lo = cpu_to_be32(1);
1055 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1060 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1062 struct fw_ri_wr *wqe;
1064 struct sk_buff *skb;
1066 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1069 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1072 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1074 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1075 memset(wqe, 0, sizeof *wqe);
1076 wqe->op_compl = cpu_to_be32(
1077 FW_WR_OP(FW_RI_INIT_WR) |
1079 wqe->flowid_len16 = cpu_to_be32(
1080 FW_WR_FLOWID(qhp->ep->hwtid) |
1081 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1083 wqe->cookie = (unsigned long) &qhp->ep->com.wr_wait;
1085 wqe->u.init.type = FW_RI_TYPE_INIT;
1086 wqe->u.init.mpareqbit_p2ptype =
1087 V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) |
1088 V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type);
1089 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1090 if (qhp->attr.mpa_attr.recv_marker_enabled)
1091 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1092 if (qhp->attr.mpa_attr.xmit_marker_enabled)
1093 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1094 if (qhp->attr.mpa_attr.crc_enabled)
1095 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1097 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1098 FW_RI_QP_RDMA_WRITE_ENABLE |
1099 FW_RI_QP_BIND_ENABLE;
1100 if (!qhp->ibqp.uobject)
1101 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1102 FW_RI_QP_STAG0_ENABLE;
1103 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1104 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1105 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1106 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1107 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1108 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1109 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1110 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1111 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1112 wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
1113 wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
1114 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1115 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1116 rhp->rdev.lldi.vr->rq.start);
1117 if (qhp->attr.mpa_attr.initiator)
1118 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1120 ret = c4iw_ofld_send(&rhp->rdev, skb);
1124 ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait,
1125 qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
1127 PDBG("%s ret %d\n", __func__, ret);
1131 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1132 enum c4iw_qp_attr_mask mask,
1133 struct c4iw_qp_attributes *attrs,
1137 struct c4iw_qp_attributes newattr = qhp->attr;
1142 struct c4iw_ep *ep = NULL;
1144 PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__,
1145 qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1146 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1148 mutex_lock(&qhp->mutex);
1150 /* Process attr changes if in IDLE */
1151 if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1152 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1156 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1157 newattr.enable_rdma_read = attrs->enable_rdma_read;
1158 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1159 newattr.enable_rdma_write = attrs->enable_rdma_write;
1160 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1161 newattr.enable_bind = attrs->enable_bind;
1162 if (mask & C4IW_QP_ATTR_MAX_ORD) {
1163 if (attrs->max_ord > c4iw_max_read_depth) {
1167 newattr.max_ord = attrs->max_ord;
1169 if (mask & C4IW_QP_ATTR_MAX_IRD) {
1170 if (attrs->max_ird > c4iw_max_read_depth) {
1174 newattr.max_ird = attrs->max_ird;
1176 qhp->attr = newattr;
1179 if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1181 if (qhp->attr.state == attrs->next_state)
1184 switch (qhp->attr.state) {
1185 case C4IW_QP_STATE_IDLE:
1186 switch (attrs->next_state) {
1187 case C4IW_QP_STATE_RTS:
1188 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1192 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1196 qhp->attr.mpa_attr = attrs->mpa_attr;
1197 qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1198 qhp->ep = qhp->attr.llp_stream_handle;
1199 set_state(qhp, C4IW_QP_STATE_RTS);
1202 * Ref the endpoint here and deref when we
1203 * disassociate the endpoint from the QP. This
1204 * happens in CLOSING->IDLE transition or *->ERROR
1207 c4iw_get_ep(&qhp->ep->com);
1208 ret = rdma_init(rhp, qhp);
1212 case C4IW_QP_STATE_ERROR:
1213 set_state(qhp, C4IW_QP_STATE_ERROR);
1221 case C4IW_QP_STATE_RTS:
1222 switch (attrs->next_state) {
1223 case C4IW_QP_STATE_CLOSING:
1224 BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
1225 set_state(qhp, C4IW_QP_STATE_CLOSING);
1230 c4iw_get_ep(&qhp->ep->com);
1232 if (qhp->ibqp.uobject)
1233 t4_set_wq_in_error(&qhp->wq);
1234 ret = rdma_fini(rhp, qhp, ep);
1238 case C4IW_QP_STATE_TERMINATE:
1239 set_state(qhp, C4IW_QP_STATE_TERMINATE);
1240 qhp->attr.layer_etype = attrs->layer_etype;
1241 qhp->attr.ecode = attrs->ecode;
1242 if (qhp->ibqp.uobject)
1243 t4_set_wq_in_error(&qhp->wq);
1248 c4iw_get_ep(&qhp->ep->com);
1250 case C4IW_QP_STATE_ERROR:
1251 set_state(qhp, C4IW_QP_STATE_ERROR);
1252 if (qhp->ibqp.uobject)
1253 t4_set_wq_in_error(&qhp->wq);
1258 c4iw_get_ep(&qhp->ep->com);
1267 case C4IW_QP_STATE_CLOSING:
1272 switch (attrs->next_state) {
1273 case C4IW_QP_STATE_IDLE:
1275 set_state(qhp, C4IW_QP_STATE_IDLE);
1276 qhp->attr.llp_stream_handle = NULL;
1277 c4iw_put_ep(&qhp->ep->com);
1279 wake_up(&qhp->wait);
1281 case C4IW_QP_STATE_ERROR:
1288 case C4IW_QP_STATE_ERROR:
1289 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1293 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1297 set_state(qhp, C4IW_QP_STATE_IDLE);
1299 case C4IW_QP_STATE_TERMINATE:
1307 printk(KERN_ERR "%s in a bad state %d\n",
1308 __func__, qhp->attr.state);
1315 PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1318 /* disassociate the LLP connection */
1319 qhp->attr.llp_stream_handle = NULL;
1323 set_state(qhp, C4IW_QP_STATE_ERROR);
1325 wake_up(&qhp->wait);
1329 mutex_unlock(&qhp->mutex);
1332 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
1335 * If disconnect is 1, then we need to initiate a disconnect
1336 * on the EP. This can be a normal close (RTS->CLOSING) or
1337 * an abnormal close (RTS/CLOSING->ERROR).
1340 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1342 c4iw_put_ep(&ep->com);
1346 * If free is 1, then we've disassociated the EP from the QP
1347 * and we need to dereference the EP.
1350 c4iw_put_ep(&ep->com);
1351 PDBG("%s exit state %d\n", __func__, qhp->attr.state);
1355 int c4iw_destroy_qp(struct ib_qp *ib_qp)
1357 struct c4iw_dev *rhp;
1358 struct c4iw_qp *qhp;
1359 struct c4iw_qp_attributes attrs;
1360 struct c4iw_ucontext *ucontext;
1362 qhp = to_c4iw_qp(ib_qp);
1365 attrs.next_state = C4IW_QP_STATE_ERROR;
1366 if (qhp->attr.state == C4IW_QP_STATE_TERMINATE)
1367 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
1369 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
1370 wait_event(qhp->wait, !qhp->ep);
1372 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1373 atomic_dec(&qhp->refcnt);
1374 wait_event(qhp->wait, !atomic_read(&qhp->refcnt));
1376 ucontext = ib_qp->uobject ?
1377 to_c4iw_ucontext(ib_qp->uobject->context) : NULL;
1378 destroy_qp(&rhp->rdev, &qhp->wq,
1379 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1381 PDBG("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid);
1386 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1387 struct ib_udata *udata)
1389 struct c4iw_dev *rhp;
1390 struct c4iw_qp *qhp;
1391 struct c4iw_pd *php;
1392 struct c4iw_cq *schp;
1393 struct c4iw_cq *rchp;
1394 struct c4iw_create_qp_resp uresp;
1396 struct c4iw_ucontext *ucontext;
1398 struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4, *mm5 = NULL;
1400 PDBG("%s ib_pd %p\n", __func__, pd);
1402 if (attrs->qp_type != IB_QPT_RC)
1403 return ERR_PTR(-EINVAL);
1405 php = to_c4iw_pd(pd);
1407 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1408 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1410 return ERR_PTR(-EINVAL);
1412 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1413 return ERR_PTR(-EINVAL);
1415 rqsize = roundup(attrs->cap.max_recv_wr + 1, 16);
1416 if (rqsize > T4_MAX_RQ_SIZE)
1417 return ERR_PTR(-E2BIG);
1419 sqsize = roundup(attrs->cap.max_send_wr + 1, 16);
1420 if (sqsize > T4_MAX_SQ_SIZE)
1421 return ERR_PTR(-E2BIG);
1423 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1426 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1428 return ERR_PTR(-ENOMEM);
1429 qhp->wq.sq.size = sqsize;
1430 qhp->wq.sq.memsize = (sqsize + 1) * sizeof *qhp->wq.sq.queue;
1431 qhp->wq.rq.size = rqsize;
1432 qhp->wq.rq.memsize = (rqsize + 1) * sizeof *qhp->wq.rq.queue;
1435 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1436 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
1439 PDBG("%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu\n",
1440 __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize);
1442 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1443 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1447 attrs->cap.max_recv_wr = rqsize - 1;
1448 attrs->cap.max_send_wr = sqsize - 1;
1449 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
1452 qhp->attr.pd = php->pdid;
1453 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
1454 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
1455 qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
1456 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
1457 qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
1458 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
1459 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
1460 qhp->attr.state = C4IW_QP_STATE_IDLE;
1461 qhp->attr.next_state = C4IW_QP_STATE_IDLE;
1462 qhp->attr.enable_rdma_read = 1;
1463 qhp->attr.enable_rdma_write = 1;
1464 qhp->attr.enable_bind = 1;
1465 qhp->attr.max_ord = 1;
1466 qhp->attr.max_ird = 1;
1467 spin_lock_init(&qhp->lock);
1468 mutex_init(&qhp->mutex);
1469 init_waitqueue_head(&qhp->wait);
1470 atomic_set(&qhp->refcnt, 1);
1472 ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
1477 mm1 = kmalloc(sizeof *mm1, GFP_KERNEL);
1482 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL);
1487 mm3 = kmalloc(sizeof *mm3, GFP_KERNEL);
1492 mm4 = kmalloc(sizeof *mm4, GFP_KERNEL);
1497 if (t4_sq_onchip(&qhp->wq.sq)) {
1498 mm5 = kmalloc(sizeof *mm5, GFP_KERNEL);
1503 uresp.flags = C4IW_QPF_ONCHIP;
1506 uresp.qid_mask = rhp->rdev.qpmask;
1507 uresp.sqid = qhp->wq.sq.qid;
1508 uresp.sq_size = qhp->wq.sq.size;
1509 uresp.sq_memsize = qhp->wq.sq.memsize;
1510 uresp.rqid = qhp->wq.rq.qid;
1511 uresp.rq_size = qhp->wq.rq.size;
1512 uresp.rq_memsize = qhp->wq.rq.memsize;
1513 spin_lock(&ucontext->mmap_lock);
1515 uresp.ma_sync_key = ucontext->key;
1516 ucontext->key += PAGE_SIZE;
1518 uresp.sq_key = ucontext->key;
1519 ucontext->key += PAGE_SIZE;
1520 uresp.rq_key = ucontext->key;
1521 ucontext->key += PAGE_SIZE;
1522 uresp.sq_db_gts_key = ucontext->key;
1523 ucontext->key += PAGE_SIZE;
1524 uresp.rq_db_gts_key = ucontext->key;
1525 ucontext->key += PAGE_SIZE;
1526 spin_unlock(&ucontext->mmap_lock);
1527 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1530 mm1->key = uresp.sq_key;
1531 mm1->addr = qhp->wq.sq.phys_addr;
1532 mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1533 insert_mmap(ucontext, mm1);
1534 mm2->key = uresp.rq_key;
1535 mm2->addr = virt_to_phys(qhp->wq.rq.queue);
1536 mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize);
1537 insert_mmap(ucontext, mm2);
1538 mm3->key = uresp.sq_db_gts_key;
1539 mm3->addr = qhp->wq.sq.udb;
1540 mm3->len = PAGE_SIZE;
1541 insert_mmap(ucontext, mm3);
1542 mm4->key = uresp.rq_db_gts_key;
1543 mm4->addr = qhp->wq.rq.udb;
1544 mm4->len = PAGE_SIZE;
1545 insert_mmap(ucontext, mm4);
1547 mm5->key = uresp.ma_sync_key;
1548 mm5->addr = (pci_resource_start(rhp->rdev.lldi.pdev, 0)
1549 + A_PCIE_MA_SYNC) & PAGE_MASK;
1550 mm5->len = PAGE_SIZE;
1551 insert_mmap(ucontext, mm5);
1554 qhp->ibqp.qp_num = qhp->wq.sq.qid;
1555 init_timer(&(qhp->timer));
1556 PDBG("%s qhp %p sq_num_entries %d, rq_num_entries %d qpid 0x%0x\n",
1557 __func__, qhp, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries,
1571 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1573 destroy_qp(&rhp->rdev, &qhp->wq,
1574 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1577 return ERR_PTR(ret);
1580 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1581 int attr_mask, struct ib_udata *udata)
1583 struct c4iw_dev *rhp;
1584 struct c4iw_qp *qhp;
1585 enum c4iw_qp_attr_mask mask = 0;
1586 struct c4iw_qp_attributes attrs;
1588 PDBG("%s ib_qp %p\n", __func__, ibqp);
1590 /* iwarp does not support the RTR state */
1591 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
1592 attr_mask &= ~IB_QP_STATE;
1594 /* Make sure we still have something left to do */
1598 memset(&attrs, 0, sizeof attrs);
1599 qhp = to_c4iw_qp(ibqp);
1602 attrs.next_state = c4iw_convert_state(attr->qp_state);
1603 attrs.enable_rdma_read = (attr->qp_access_flags &
1604 IB_ACCESS_REMOTE_READ) ? 1 : 0;
1605 attrs.enable_rdma_write = (attr->qp_access_flags &
1606 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
1607 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
1610 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
1611 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
1612 (C4IW_QP_ATTR_ENABLE_RDMA_READ |
1613 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
1614 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
1616 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
1619 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
1621 PDBG("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn);
1622 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);