2 * 3-axis accelerometer driver supporting following Bosch-Sensortec chips:
10 * Copyright (c) 2014, Intel Corporation.
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms and conditions of the GNU General Public License,
14 * version 2, as published by the Free Software Foundation.
16 * This program is distributed in the hope it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
22 #include <linux/module.h>
23 #include <linux/i2c.h>
24 #include <linux/interrupt.h>
25 #include <linux/delay.h>
26 #include <linux/slab.h>
27 #include <linux/acpi.h>
28 #include <linux/gpio/consumer.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/iio/iio.h>
32 #include <linux/iio/sysfs.h>
33 #include <linux/iio/buffer.h>
34 #include <linux/iio/events.h>
35 #include <linux/iio/trigger.h>
36 #include <linux/iio/trigger_consumer.h>
37 #include <linux/iio/triggered_buffer.h>
39 #define BMC150_ACCEL_DRV_NAME "bmc150_accel"
40 #define BMC150_ACCEL_IRQ_NAME "bmc150_accel_event"
41 #define BMC150_ACCEL_GPIO_NAME "bmc150_accel_int"
43 #define BMC150_ACCEL_REG_CHIP_ID 0x00
45 #define BMC150_ACCEL_REG_INT_STATUS_2 0x0B
46 #define BMC150_ACCEL_ANY_MOTION_MASK 0x07
47 #define BMC150_ACCEL_ANY_MOTION_BIT_SIGN BIT(3)
49 #define BMC150_ACCEL_REG_PMU_LPW 0x11
50 #define BMC150_ACCEL_PMU_MODE_MASK 0xE0
51 #define BMC150_ACCEL_PMU_MODE_SHIFT 5
52 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_MASK 0x17
53 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT 1
55 #define BMC150_ACCEL_REG_PMU_RANGE 0x0F
57 #define BMC150_ACCEL_DEF_RANGE_2G 0x03
58 #define BMC150_ACCEL_DEF_RANGE_4G 0x05
59 #define BMC150_ACCEL_DEF_RANGE_8G 0x08
60 #define BMC150_ACCEL_DEF_RANGE_16G 0x0C
62 /* Default BW: 125Hz */
63 #define BMC150_ACCEL_REG_PMU_BW 0x10
64 #define BMC150_ACCEL_DEF_BW 125
66 #define BMC150_ACCEL_REG_INT_MAP_0 0x19
67 #define BMC150_ACCEL_INT_MAP_0_BIT_SLOPE BIT(2)
69 #define BMC150_ACCEL_REG_INT_MAP_1 0x1A
70 #define BMC150_ACCEL_INT_MAP_1_BIT_DATA BIT(0)
72 #define BMC150_ACCEL_REG_INT_RST_LATCH 0x21
73 #define BMC150_ACCEL_INT_MODE_LATCH_RESET 0x80
74 #define BMC150_ACCEL_INT_MODE_LATCH_INT 0x0F
75 #define BMC150_ACCEL_INT_MODE_NON_LATCH_INT 0x00
77 #define BMC150_ACCEL_REG_INT_EN_0 0x16
78 #define BMC150_ACCEL_INT_EN_BIT_SLP_X BIT(0)
79 #define BMC150_ACCEL_INT_EN_BIT_SLP_Y BIT(1)
80 #define BMC150_ACCEL_INT_EN_BIT_SLP_Z BIT(2)
82 #define BMC150_ACCEL_REG_INT_EN_1 0x17
83 #define BMC150_ACCEL_INT_EN_BIT_DATA_EN BIT(4)
85 #define BMC150_ACCEL_REG_INT_OUT_CTRL 0x20
86 #define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL BIT(0)
88 #define BMC150_ACCEL_REG_INT_5 0x27
89 #define BMC150_ACCEL_SLOPE_DUR_MASK 0x03
91 #define BMC150_ACCEL_REG_INT_6 0x28
92 #define BMC150_ACCEL_SLOPE_THRES_MASK 0xFF
94 /* Slope duration in terms of number of samples */
95 #define BMC150_ACCEL_DEF_SLOPE_DURATION 2
96 /* in terms of multiples of g's/LSB, based on range */
97 #define BMC150_ACCEL_DEF_SLOPE_THRESHOLD 5
99 #define BMC150_ACCEL_REG_XOUT_L 0x02
101 #define BMC150_ACCEL_MAX_STARTUP_TIME_MS 100
103 /* Sleep Duration values */
104 #define BMC150_ACCEL_SLEEP_500_MICRO 0x05
105 #define BMC150_ACCEL_SLEEP_1_MS 0x06
106 #define BMC150_ACCEL_SLEEP_2_MS 0x07
107 #define BMC150_ACCEL_SLEEP_4_MS 0x08
108 #define BMC150_ACCEL_SLEEP_6_MS 0x09
109 #define BMC150_ACCEL_SLEEP_10_MS 0x0A
110 #define BMC150_ACCEL_SLEEP_25_MS 0x0B
111 #define BMC150_ACCEL_SLEEP_50_MS 0x0C
112 #define BMC150_ACCEL_SLEEP_100_MS 0x0D
113 #define BMC150_ACCEL_SLEEP_500_MS 0x0E
114 #define BMC150_ACCEL_SLEEP_1_SEC 0x0F
116 #define BMC150_ACCEL_REG_TEMP 0x08
117 #define BMC150_ACCEL_TEMP_CENTER_VAL 24
119 #define BMC150_ACCEL_AXIS_TO_REG(axis) (BMC150_ACCEL_REG_XOUT_L + (axis * 2))
120 #define BMC150_AUTO_SUSPEND_DELAY_MS 2000
122 enum bmc150_accel_axis {
128 enum bmc150_power_modes {
129 BMC150_ACCEL_SLEEP_MODE_NORMAL,
130 BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND,
131 BMC150_ACCEL_SLEEP_MODE_LPM,
132 BMC150_ACCEL_SLEEP_MODE_SUSPEND = 0x04,
135 struct bmc150_scale_info {
140 struct bmc150_accel_chip_info {
142 const struct iio_chan_spec *channels;
144 const struct bmc150_scale_info scale_table[4];
147 struct bmc150_accel_data {
148 struct i2c_client *client;
149 struct iio_trigger *dready_trig;
150 struct iio_trigger *motion_trig;
158 bool dready_trigger_on;
159 bool motion_trigger_on;
161 const struct bmc150_accel_chip_info *chip_info;
164 static const struct {
168 } bmc150_accel_samp_freq_table[] = { {7, 810000, 0x08},
177 static const struct {
180 } bmc150_accel_sample_upd_time[] = { {0x08, 64},
189 static const struct {
192 } bmc150_accel_sleep_value_table[] = { {0, 0},
193 {500, BMC150_ACCEL_SLEEP_500_MICRO},
194 {1000, BMC150_ACCEL_SLEEP_1_MS},
195 {2000, BMC150_ACCEL_SLEEP_2_MS},
196 {4000, BMC150_ACCEL_SLEEP_4_MS},
197 {6000, BMC150_ACCEL_SLEEP_6_MS},
198 {10000, BMC150_ACCEL_SLEEP_10_MS},
199 {25000, BMC150_ACCEL_SLEEP_25_MS},
200 {50000, BMC150_ACCEL_SLEEP_50_MS},
201 {100000, BMC150_ACCEL_SLEEP_100_MS},
202 {500000, BMC150_ACCEL_SLEEP_500_MS},
203 {1000000, BMC150_ACCEL_SLEEP_1_SEC} };
206 static int bmc150_accel_set_mode(struct bmc150_accel_data *data,
207 enum bmc150_power_modes mode,
216 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sleep_value_table);
218 if (bmc150_accel_sleep_value_table[i].sleep_dur ==
221 bmc150_accel_sleep_value_table[i].reg_value;
229 lpw_bits = mode << BMC150_ACCEL_PMU_MODE_SHIFT;
230 lpw_bits |= (dur_val << BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT);
232 dev_dbg(&data->client->dev, "Set Mode bits %x\n", lpw_bits);
234 ret = i2c_smbus_write_byte_data(data->client,
235 BMC150_ACCEL_REG_PMU_LPW, lpw_bits);
237 dev_err(&data->client->dev, "Error writing reg_pmu_lpw\n");
244 static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val,
250 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
251 if (bmc150_accel_samp_freq_table[i].val == val &&
252 bmc150_accel_samp_freq_table[i].val2 == val2) {
253 ret = i2c_smbus_write_byte_data(
255 BMC150_ACCEL_REG_PMU_BW,
256 bmc150_accel_samp_freq_table[i].bw_bits);
261 bmc150_accel_samp_freq_table[i].bw_bits;
269 static int bmc150_accel_chip_init(struct bmc150_accel_data *data)
273 ret = i2c_smbus_read_byte_data(data->client, BMC150_ACCEL_REG_CHIP_ID);
275 dev_err(&data->client->dev,
276 "Error: Reading chip id\n");
280 dev_dbg(&data->client->dev, "Chip Id %x\n", ret);
281 if (ret != data->chip_info->chip_id) {
282 dev_err(&data->client->dev, "Invalid chip %x\n", ret);
286 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
291 ret = bmc150_accel_set_bw(data, BMC150_ACCEL_DEF_BW, 0);
295 /* Set Default Range */
296 ret = i2c_smbus_write_byte_data(data->client,
297 BMC150_ACCEL_REG_PMU_RANGE,
298 BMC150_ACCEL_DEF_RANGE_4G);
300 dev_err(&data->client->dev,
301 "Error writing reg_pmu_range\n");
305 data->range = BMC150_ACCEL_DEF_RANGE_4G;
307 /* Set default slope duration */
308 ret = i2c_smbus_read_byte_data(data->client, BMC150_ACCEL_REG_INT_5);
310 dev_err(&data->client->dev, "Error reading reg_int_5\n");
313 data->slope_dur |= BMC150_ACCEL_DEF_SLOPE_DURATION;
314 ret = i2c_smbus_write_byte_data(data->client,
315 BMC150_ACCEL_REG_INT_5,
318 dev_err(&data->client->dev, "Error writing reg_int_5\n");
321 dev_dbg(&data->client->dev, "slope_dur %x\n", data->slope_dur);
323 /* Set default slope thresholds */
324 ret = i2c_smbus_write_byte_data(data->client,
325 BMC150_ACCEL_REG_INT_6,
326 BMC150_ACCEL_DEF_SLOPE_THRESHOLD);
328 dev_err(&data->client->dev, "Error writing reg_int_6\n");
331 data->slope_thres = BMC150_ACCEL_DEF_SLOPE_THRESHOLD;
332 dev_dbg(&data->client->dev, "slope_thres %x\n", data->slope_thres);
334 /* Set default as latched interrupts */
335 ret = i2c_smbus_write_byte_data(data->client,
336 BMC150_ACCEL_REG_INT_RST_LATCH,
337 BMC150_ACCEL_INT_MODE_LATCH_INT |
338 BMC150_ACCEL_INT_MODE_LATCH_RESET);
340 dev_err(&data->client->dev,
341 "Error writing reg_int_rst_latch\n");
348 static int bmc150_accel_setup_any_motion_interrupt(
349 struct bmc150_accel_data *data,
354 /* Enable/Disable INT1 mapping */
355 ret = i2c_smbus_read_byte_data(data->client,
356 BMC150_ACCEL_REG_INT_MAP_0);
358 dev_err(&data->client->dev, "Error reading reg_int_map_0\n");
362 ret |= BMC150_ACCEL_INT_MAP_0_BIT_SLOPE;
364 ret &= ~BMC150_ACCEL_INT_MAP_0_BIT_SLOPE;
366 ret = i2c_smbus_write_byte_data(data->client,
367 BMC150_ACCEL_REG_INT_MAP_0,
370 dev_err(&data->client->dev, "Error writing reg_int_map_0\n");
375 /* Set slope duration (no of samples) */
376 ret = i2c_smbus_write_byte_data(data->client,
377 BMC150_ACCEL_REG_INT_5,
380 dev_err(&data->client->dev, "Error write reg_int_5\n");
384 /* Set slope thresholds */
385 ret = i2c_smbus_write_byte_data(data->client,
386 BMC150_ACCEL_REG_INT_6,
389 dev_err(&data->client->dev, "Error write reg_int_6\n");
394 * New data interrupt is always non-latched,
395 * which will have higher priority, so no need
396 * to set latched mode, we will be flooded anyway with INTR
398 if (!data->dready_trigger_on) {
399 ret = i2c_smbus_write_byte_data(data->client,
400 BMC150_ACCEL_REG_INT_RST_LATCH,
401 BMC150_ACCEL_INT_MODE_LATCH_INT |
402 BMC150_ACCEL_INT_MODE_LATCH_RESET);
404 dev_err(&data->client->dev,
405 "Error writing reg_int_rst_latch\n");
410 ret = i2c_smbus_write_byte_data(data->client,
411 BMC150_ACCEL_REG_INT_EN_0,
412 BMC150_ACCEL_INT_EN_BIT_SLP_X |
413 BMC150_ACCEL_INT_EN_BIT_SLP_Y |
414 BMC150_ACCEL_INT_EN_BIT_SLP_Z);
416 ret = i2c_smbus_write_byte_data(data->client,
417 BMC150_ACCEL_REG_INT_EN_0,
421 dev_err(&data->client->dev, "Error writing reg_int_en_0\n");
428 static int bmc150_accel_setup_new_data_interrupt(struct bmc150_accel_data *data,
433 /* Enable/Disable INT1 mapping */
434 ret = i2c_smbus_read_byte_data(data->client,
435 BMC150_ACCEL_REG_INT_MAP_1);
437 dev_err(&data->client->dev, "Error reading reg_int_map_1\n");
441 ret |= BMC150_ACCEL_INT_MAP_1_BIT_DATA;
443 ret &= ~BMC150_ACCEL_INT_MAP_1_BIT_DATA;
445 ret = i2c_smbus_write_byte_data(data->client,
446 BMC150_ACCEL_REG_INT_MAP_1,
449 dev_err(&data->client->dev, "Error writing reg_int_map_1\n");
455 * Set non latched mode interrupt and clear any latched
458 ret = i2c_smbus_write_byte_data(data->client,
459 BMC150_ACCEL_REG_INT_RST_LATCH,
460 BMC150_ACCEL_INT_MODE_NON_LATCH_INT |
461 BMC150_ACCEL_INT_MODE_LATCH_RESET);
463 dev_err(&data->client->dev,
464 "Error writing reg_int_rst_latch\n");
468 ret = i2c_smbus_write_byte_data(data->client,
469 BMC150_ACCEL_REG_INT_EN_1,
470 BMC150_ACCEL_INT_EN_BIT_DATA_EN);
473 /* Restore default interrupt mode */
474 ret = i2c_smbus_write_byte_data(data->client,
475 BMC150_ACCEL_REG_INT_RST_LATCH,
476 BMC150_ACCEL_INT_MODE_LATCH_INT |
477 BMC150_ACCEL_INT_MODE_LATCH_RESET);
479 dev_err(&data->client->dev,
480 "Error writing reg_int_rst_latch\n");
484 ret = i2c_smbus_write_byte_data(data->client,
485 BMC150_ACCEL_REG_INT_EN_1,
490 dev_err(&data->client->dev, "Error writing reg_int_en_1\n");
497 static int bmc150_accel_get_bw(struct bmc150_accel_data *data, int *val,
502 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
503 if (bmc150_accel_samp_freq_table[i].bw_bits == data->bw_bits) {
504 *val = bmc150_accel_samp_freq_table[i].val;
505 *val2 = bmc150_accel_samp_freq_table[i].val2;
506 return IIO_VAL_INT_PLUS_MICRO;
513 #ifdef CONFIG_PM_RUNTIME
514 static int bmc150_accel_get_startup_times(struct bmc150_accel_data *data)
518 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sample_upd_time); ++i) {
519 if (bmc150_accel_sample_upd_time[i].bw_bits == data->bw_bits)
520 return bmc150_accel_sample_upd_time[i].msec;
523 return BMC150_ACCEL_MAX_STARTUP_TIME_MS;
526 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
531 ret = pm_runtime_get_sync(&data->client->dev);
533 pm_runtime_mark_last_busy(&data->client->dev);
534 ret = pm_runtime_put_autosuspend(&data->client->dev);
537 dev_err(&data->client->dev,
538 "Failed: bmc150_accel_set_power_state for %d\n", on);
545 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
551 static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val)
555 for (i = 0; i < ARRAY_SIZE(data->chip_info->scale_table); ++i) {
556 if (data->chip_info->scale_table[i].scale == val) {
557 ret = i2c_smbus_write_byte_data(
559 BMC150_ACCEL_REG_PMU_RANGE,
560 data->chip_info->scale_table[i].reg_range);
562 dev_err(&data->client->dev,
563 "Error writing pmu_range\n");
567 data->range = data->chip_info->scale_table[i].reg_range;
575 static int bmc150_accel_get_temp(struct bmc150_accel_data *data, int *val)
579 mutex_lock(&data->mutex);
581 ret = i2c_smbus_read_byte_data(data->client, BMC150_ACCEL_REG_TEMP);
583 dev_err(&data->client->dev, "Error reading reg_temp\n");
584 mutex_unlock(&data->mutex);
587 *val = sign_extend32(ret, 7);
589 mutex_unlock(&data->mutex);
594 static int bmc150_accel_get_axis(struct bmc150_accel_data *data,
595 struct iio_chan_spec const *chan,
599 int axis = chan->scan_index;
601 mutex_lock(&data->mutex);
602 ret = bmc150_accel_set_power_state(data, true);
604 mutex_unlock(&data->mutex);
608 ret = i2c_smbus_read_word_data(data->client,
609 BMC150_ACCEL_AXIS_TO_REG(axis));
611 dev_err(&data->client->dev, "Error reading axis %d\n", axis);
612 bmc150_accel_set_power_state(data, false);
613 mutex_unlock(&data->mutex);
616 *val = sign_extend32(ret >> chan->scan_type.shift,
617 chan->scan_type.realbits - 1);
618 ret = bmc150_accel_set_power_state(data, false);
619 mutex_unlock(&data->mutex);
626 static int bmc150_accel_read_raw(struct iio_dev *indio_dev,
627 struct iio_chan_spec const *chan,
628 int *val, int *val2, long mask)
630 struct bmc150_accel_data *data = iio_priv(indio_dev);
634 case IIO_CHAN_INFO_RAW:
635 switch (chan->type) {
637 return bmc150_accel_get_temp(data, val);
639 if (iio_buffer_enabled(indio_dev))
642 return bmc150_accel_get_axis(data, chan, val);
646 case IIO_CHAN_INFO_OFFSET:
647 if (chan->type == IIO_TEMP) {
648 *val = BMC150_ACCEL_TEMP_CENTER_VAL;
652 case IIO_CHAN_INFO_SCALE:
654 switch (chan->type) {
657 return IIO_VAL_INT_PLUS_MICRO;
661 const struct bmc150_scale_info *si;
662 int st_size = ARRAY_SIZE(data->chip_info->scale_table);
664 for (i = 0; i < st_size; ++i) {
665 si = &data->chip_info->scale_table[i];
666 if (si->reg_range == data->range) {
668 return IIO_VAL_INT_PLUS_MICRO;
676 case IIO_CHAN_INFO_SAMP_FREQ:
677 mutex_lock(&data->mutex);
678 ret = bmc150_accel_get_bw(data, val, val2);
679 mutex_unlock(&data->mutex);
686 static int bmc150_accel_write_raw(struct iio_dev *indio_dev,
687 struct iio_chan_spec const *chan,
688 int val, int val2, long mask)
690 struct bmc150_accel_data *data = iio_priv(indio_dev);
694 case IIO_CHAN_INFO_SAMP_FREQ:
695 mutex_lock(&data->mutex);
696 ret = bmc150_accel_set_bw(data, val, val2);
697 mutex_unlock(&data->mutex);
699 case IIO_CHAN_INFO_SCALE:
703 mutex_lock(&data->mutex);
704 ret = bmc150_accel_set_scale(data, val2);
705 mutex_unlock(&data->mutex);
714 static int bmc150_accel_read_event(struct iio_dev *indio_dev,
715 const struct iio_chan_spec *chan,
716 enum iio_event_type type,
717 enum iio_event_direction dir,
718 enum iio_event_info info,
721 struct bmc150_accel_data *data = iio_priv(indio_dev);
725 case IIO_EV_INFO_VALUE:
726 *val = data->slope_thres;
728 case IIO_EV_INFO_PERIOD:
729 *val = data->slope_dur & BMC150_ACCEL_SLOPE_DUR_MASK;
738 static int bmc150_accel_write_event(struct iio_dev *indio_dev,
739 const struct iio_chan_spec *chan,
740 enum iio_event_type type,
741 enum iio_event_direction dir,
742 enum iio_event_info info,
745 struct bmc150_accel_data *data = iio_priv(indio_dev);
747 if (data->ev_enable_state)
751 case IIO_EV_INFO_VALUE:
752 data->slope_thres = val;
754 case IIO_EV_INFO_PERIOD:
755 data->slope_dur &= ~BMC150_ACCEL_SLOPE_DUR_MASK;
756 data->slope_dur |= val & BMC150_ACCEL_SLOPE_DUR_MASK;
765 static int bmc150_accel_read_event_config(struct iio_dev *indio_dev,
766 const struct iio_chan_spec *chan,
767 enum iio_event_type type,
768 enum iio_event_direction dir)
771 struct bmc150_accel_data *data = iio_priv(indio_dev);
773 return data->ev_enable_state;
776 static int bmc150_accel_write_event_config(struct iio_dev *indio_dev,
777 const struct iio_chan_spec *chan,
778 enum iio_event_type type,
779 enum iio_event_direction dir,
782 struct bmc150_accel_data *data = iio_priv(indio_dev);
785 if (state && data->ev_enable_state)
788 mutex_lock(&data->mutex);
790 if (!state && data->motion_trigger_on) {
791 data->ev_enable_state = 0;
792 mutex_unlock(&data->mutex);
797 * We will expect the enable and disable to do operation in
798 * in reverse order. This will happen here anyway as our
799 * resume operation uses sync mode runtime pm calls, the
800 * suspend operation will be delayed by autosuspend delay
801 * So the disable operation will still happen in reverse of
802 * enable operation. When runtime pm is disabled the mode
803 * is always on so sequence doesn't matter
806 ret = bmc150_accel_set_power_state(data, state);
808 mutex_unlock(&data->mutex);
812 ret = bmc150_accel_setup_any_motion_interrupt(data, state);
814 mutex_unlock(&data->mutex);
818 data->ev_enable_state = state;
819 mutex_unlock(&data->mutex);
824 static int bmc150_accel_validate_trigger(struct iio_dev *indio_dev,
825 struct iio_trigger *trig)
827 struct bmc150_accel_data *data = iio_priv(indio_dev);
829 if (data->dready_trig != trig && data->motion_trig != trig)
835 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
836 "7.810000 15.630000 31.250000 62.500000 125 250 500 1000");
838 static struct attribute *bmc150_accel_attributes[] = {
839 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
843 static const struct attribute_group bmc150_accel_attrs_group = {
844 .attrs = bmc150_accel_attributes,
847 static const struct iio_event_spec bmc150_accel_event = {
848 .type = IIO_EV_TYPE_ROC,
849 .dir = IIO_EV_DIR_RISING | IIO_EV_DIR_FALLING,
850 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
851 BIT(IIO_EV_INFO_ENABLE) |
852 BIT(IIO_EV_INFO_PERIOD)
855 #define BMC150_ACCEL_CHANNEL(_axis, bits) { \
858 .channel2 = IIO_MOD_##_axis, \
859 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
860 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
861 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
862 .scan_index = AXIS_##_axis, \
865 .realbits = (bits), \
867 .shift = 16 - (bits), \
869 .event_spec = &bmc150_accel_event, \
870 .num_event_specs = 1 \
873 #define BMC150_ACCEL_CHANNELS(bits) { \
876 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
877 BIT(IIO_CHAN_INFO_SCALE) | \
878 BIT(IIO_CHAN_INFO_OFFSET), \
881 BMC150_ACCEL_CHANNEL(X, bits), \
882 BMC150_ACCEL_CHANNEL(Y, bits), \
883 BMC150_ACCEL_CHANNEL(Z, bits), \
884 IIO_CHAN_SOFT_TIMESTAMP(3), \
887 static const struct iio_chan_spec bma222e_accel_channels[] =
888 BMC150_ACCEL_CHANNELS(8);
889 static const struct iio_chan_spec bma250e_accel_channels[] =
890 BMC150_ACCEL_CHANNELS(10);
891 static const struct iio_chan_spec bmc150_accel_channels[] =
892 BMC150_ACCEL_CHANNELS(12);
893 static const struct iio_chan_spec bma280_accel_channels[] =
894 BMC150_ACCEL_CHANNELS(14);
905 static const struct bmc150_accel_chip_info bmc150_accel_chip_info_tbl[] = {
908 .channels = bmc150_accel_channels,
909 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
910 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
911 {19122, BMC150_ACCEL_DEF_RANGE_4G},
912 {38344, BMC150_ACCEL_DEF_RANGE_8G},
913 {76590, BMC150_ACCEL_DEF_RANGE_16G} },
917 .channels = bmc150_accel_channels,
918 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
919 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
920 {19122, BMC150_ACCEL_DEF_RANGE_4G},
921 {38344, BMC150_ACCEL_DEF_RANGE_8G},
922 {76590, BMC150_ACCEL_DEF_RANGE_16G} },
926 .channels = bmc150_accel_channels,
927 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
928 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
929 {19122, BMC150_ACCEL_DEF_RANGE_4G},
930 {38344, BMC150_ACCEL_DEF_RANGE_8G},
931 {76590, BMC150_ACCEL_DEF_RANGE_16G} },
935 .channels = bma250e_accel_channels,
936 .num_channels = ARRAY_SIZE(bma250e_accel_channels),
937 .scale_table = { {38344, BMC150_ACCEL_DEF_RANGE_2G},
938 {76590, BMC150_ACCEL_DEF_RANGE_4G},
939 {153277, BMC150_ACCEL_DEF_RANGE_8G},
940 {306457, BMC150_ACCEL_DEF_RANGE_16G} },
944 .channels = bma222e_accel_channels,
945 .num_channels = ARRAY_SIZE(bma222e_accel_channels),
946 .scale_table = { {153277, BMC150_ACCEL_DEF_RANGE_2G},
947 {306457, BMC150_ACCEL_DEF_RANGE_4G},
948 {612915, BMC150_ACCEL_DEF_RANGE_8G},
949 {1225831, BMC150_ACCEL_DEF_RANGE_16G} },
953 .channels = bma280_accel_channels,
954 .num_channels = ARRAY_SIZE(bma280_accel_channels),
955 .scale_table = { {2392, BMC150_ACCEL_DEF_RANGE_2G},
956 {4785, BMC150_ACCEL_DEF_RANGE_4G},
957 {9581, BMC150_ACCEL_DEF_RANGE_8G},
958 {19152, BMC150_ACCEL_DEF_RANGE_16G} },
962 static const struct iio_info bmc150_accel_info = {
963 .attrs = &bmc150_accel_attrs_group,
964 .read_raw = bmc150_accel_read_raw,
965 .write_raw = bmc150_accel_write_raw,
966 .read_event_value = bmc150_accel_read_event,
967 .write_event_value = bmc150_accel_write_event,
968 .write_event_config = bmc150_accel_write_event_config,
969 .read_event_config = bmc150_accel_read_event_config,
970 .validate_trigger = bmc150_accel_validate_trigger,
971 .driver_module = THIS_MODULE,
974 static irqreturn_t bmc150_accel_trigger_handler(int irq, void *p)
976 struct iio_poll_func *pf = p;
977 struct iio_dev *indio_dev = pf->indio_dev;
978 struct bmc150_accel_data *data = iio_priv(indio_dev);
981 mutex_lock(&data->mutex);
982 for_each_set_bit(bit, indio_dev->buffer->scan_mask,
983 indio_dev->masklength) {
984 ret = i2c_smbus_read_word_data(data->client,
985 BMC150_ACCEL_AXIS_TO_REG(bit));
987 mutex_unlock(&data->mutex);
990 data->buffer[i++] = ret;
992 mutex_unlock(&data->mutex);
994 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
997 iio_trigger_notify_done(indio_dev->trig);
1002 static int bmc150_accel_trig_try_reen(struct iio_trigger *trig)
1004 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
1005 struct bmc150_accel_data *data = iio_priv(indio_dev);
1008 /* new data interrupts don't need ack */
1009 if (data->dready_trigger_on)
1012 mutex_lock(&data->mutex);
1013 /* clear any latched interrupt */
1014 ret = i2c_smbus_write_byte_data(data->client,
1015 BMC150_ACCEL_REG_INT_RST_LATCH,
1016 BMC150_ACCEL_INT_MODE_LATCH_INT |
1017 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1018 mutex_unlock(&data->mutex);
1020 dev_err(&data->client->dev,
1021 "Error writing reg_int_rst_latch\n");
1028 static int bmc150_accel_data_rdy_trigger_set_state(struct iio_trigger *trig,
1031 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
1032 struct bmc150_accel_data *data = iio_priv(indio_dev);
1035 mutex_lock(&data->mutex);
1037 if (!state && data->ev_enable_state && data->motion_trigger_on) {
1038 data->motion_trigger_on = false;
1039 mutex_unlock(&data->mutex);
1044 * Refer to comment in bmc150_accel_write_event_config for
1045 * enable/disable operation order
1047 ret = bmc150_accel_set_power_state(data, state);
1049 mutex_unlock(&data->mutex);
1052 if (data->motion_trig == trig)
1053 ret = bmc150_accel_setup_any_motion_interrupt(data, state);
1055 ret = bmc150_accel_setup_new_data_interrupt(data, state);
1057 mutex_unlock(&data->mutex);
1060 if (data->motion_trig == trig)
1061 data->motion_trigger_on = state;
1063 data->dready_trigger_on = state;
1065 mutex_unlock(&data->mutex);
1070 static const struct iio_trigger_ops bmc150_accel_trigger_ops = {
1071 .set_trigger_state = bmc150_accel_data_rdy_trigger_set_state,
1072 .try_reenable = bmc150_accel_trig_try_reen,
1073 .owner = THIS_MODULE,
1076 static irqreturn_t bmc150_accel_event_handler(int irq, void *private)
1078 struct iio_dev *indio_dev = private;
1079 struct bmc150_accel_data *data = iio_priv(indio_dev);
1083 ret = i2c_smbus_read_byte_data(data->client,
1084 BMC150_ACCEL_REG_INT_STATUS_2);
1086 dev_err(&data->client->dev, "Error reading reg_int_status_2\n");
1087 goto ack_intr_status;
1090 if (ret & BMC150_ACCEL_ANY_MOTION_BIT_SIGN)
1091 dir = IIO_EV_DIR_FALLING;
1093 dir = IIO_EV_DIR_RISING;
1095 if (ret & BMC150_ACCEL_ANY_MOTION_MASK)
1096 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ACCEL,
1098 IIO_MOD_X_OR_Y_OR_Z,
1103 if (!data->dready_trigger_on)
1104 ret = i2c_smbus_write_byte_data(data->client,
1105 BMC150_ACCEL_REG_INT_RST_LATCH,
1106 BMC150_ACCEL_INT_MODE_LATCH_INT |
1107 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1112 static irqreturn_t bmc150_accel_data_rdy_trig_poll(int irq, void *private)
1114 struct iio_dev *indio_dev = private;
1115 struct bmc150_accel_data *data = iio_priv(indio_dev);
1117 data->timestamp = iio_get_time_ns();
1119 if (data->dready_trigger_on)
1120 iio_trigger_poll(data->dready_trig);
1121 else if (data->motion_trigger_on)
1122 iio_trigger_poll(data->motion_trig);
1124 if (data->ev_enable_state)
1125 return IRQ_WAKE_THREAD;
1130 static const char *bmc150_accel_match_acpi_device(struct device *dev, int *data)
1132 const struct acpi_device_id *id;
1134 id = acpi_match_device(dev->driver->acpi_match_table, dev);
1139 *data = (int) id->driver_data;
1141 return dev_name(dev);
1144 static int bmc150_accel_gpio_probe(struct i2c_client *client,
1145 struct bmc150_accel_data *data)
1148 struct gpio_desc *gpio;
1156 /* data ready gpio interrupt pin */
1157 gpio = devm_gpiod_get_index(dev, BMC150_ACCEL_GPIO_NAME, 0);
1159 dev_err(dev, "Failed: gpio get index\n");
1160 return PTR_ERR(gpio);
1163 ret = gpiod_direction_input(gpio);
1167 ret = gpiod_to_irq(gpio);
1169 dev_dbg(dev, "GPIO resource, no:%d irq:%d\n", desc_to_gpio(gpio), ret);
1174 static int bmc150_accel_probe(struct i2c_client *client,
1175 const struct i2c_device_id *id)
1177 struct bmc150_accel_data *data;
1178 struct iio_dev *indio_dev;
1180 const char *name = NULL;
1183 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
1187 data = iio_priv(indio_dev);
1188 i2c_set_clientdata(client, indio_dev);
1189 data->client = client;
1193 chip_id = id->driver_data;
1196 if (ACPI_HANDLE(&client->dev))
1197 name = bmc150_accel_match_acpi_device(&client->dev, &chip_id);
1199 data->chip_info = &bmc150_accel_chip_info_tbl[chip_id];
1201 ret = bmc150_accel_chip_init(data);
1205 mutex_init(&data->mutex);
1207 indio_dev->dev.parent = &client->dev;
1208 indio_dev->channels = data->chip_info->channels;
1209 indio_dev->num_channels = data->chip_info->num_channels;
1210 indio_dev->name = name;
1211 indio_dev->modes = INDIO_DIRECT_MODE;
1212 indio_dev->info = &bmc150_accel_info;
1214 if (client->irq < 0)
1215 client->irq = bmc150_accel_gpio_probe(client, data);
1217 if (client->irq >= 0) {
1218 ret = devm_request_threaded_irq(
1219 &client->dev, client->irq,
1220 bmc150_accel_data_rdy_trig_poll,
1221 bmc150_accel_event_handler,
1222 IRQF_TRIGGER_RISING,
1223 BMC150_ACCEL_IRQ_NAME,
1228 data->dready_trig = devm_iio_trigger_alloc(&client->dev,
1232 if (!data->dready_trig)
1235 data->motion_trig = devm_iio_trigger_alloc(&client->dev,
1236 "%s-any-motion-dev%d",
1239 if (!data->motion_trig)
1242 data->dready_trig->dev.parent = &client->dev;
1243 data->dready_trig->ops = &bmc150_accel_trigger_ops;
1244 iio_trigger_set_drvdata(data->dready_trig, indio_dev);
1245 ret = iio_trigger_register(data->dready_trig);
1249 data->motion_trig->dev.parent = &client->dev;
1250 data->motion_trig->ops = &bmc150_accel_trigger_ops;
1251 iio_trigger_set_drvdata(data->motion_trig, indio_dev);
1252 ret = iio_trigger_register(data->motion_trig);
1254 data->motion_trig = NULL;
1255 goto err_trigger_unregister;
1258 ret = iio_triggered_buffer_setup(indio_dev,
1259 &iio_pollfunc_store_time,
1260 bmc150_accel_trigger_handler,
1263 dev_err(&client->dev,
1264 "Failed: iio triggered buffer setup\n");
1265 goto err_trigger_unregister;
1269 ret = iio_device_register(indio_dev);
1271 dev_err(&client->dev, "Unable to register iio device\n");
1272 goto err_buffer_cleanup;
1275 ret = pm_runtime_set_active(&client->dev);
1277 goto err_iio_unregister;
1279 pm_runtime_enable(&client->dev);
1280 pm_runtime_set_autosuspend_delay(&client->dev,
1281 BMC150_AUTO_SUSPEND_DELAY_MS);
1282 pm_runtime_use_autosuspend(&client->dev);
1287 iio_device_unregister(indio_dev);
1289 if (data->dready_trig)
1290 iio_triggered_buffer_cleanup(indio_dev);
1291 err_trigger_unregister:
1292 if (data->dready_trig)
1293 iio_trigger_unregister(data->dready_trig);
1294 if (data->motion_trig)
1295 iio_trigger_unregister(data->motion_trig);
1300 static int bmc150_accel_remove(struct i2c_client *client)
1302 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1303 struct bmc150_accel_data *data = iio_priv(indio_dev);
1305 pm_runtime_disable(&client->dev);
1306 pm_runtime_set_suspended(&client->dev);
1307 pm_runtime_put_noidle(&client->dev);
1309 iio_device_unregister(indio_dev);
1311 if (data->dready_trig) {
1312 iio_triggered_buffer_cleanup(indio_dev);
1313 iio_trigger_unregister(data->dready_trig);
1314 iio_trigger_unregister(data->motion_trig);
1317 mutex_lock(&data->mutex);
1318 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 0);
1319 mutex_unlock(&data->mutex);
1324 #ifdef CONFIG_PM_SLEEP
1325 static int bmc150_accel_suspend(struct device *dev)
1327 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1328 struct bmc150_accel_data *data = iio_priv(indio_dev);
1330 mutex_lock(&data->mutex);
1331 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1332 mutex_unlock(&data->mutex);
1337 static int bmc150_accel_resume(struct device *dev)
1339 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1340 struct bmc150_accel_data *data = iio_priv(indio_dev);
1342 mutex_lock(&data->mutex);
1343 if (data->dready_trigger_on || data->motion_trigger_on ||
1344 data->ev_enable_state)
1345 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1346 mutex_unlock(&data->mutex);
1352 #ifdef CONFIG_PM_RUNTIME
1353 static int bmc150_accel_runtime_suspend(struct device *dev)
1355 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1356 struct bmc150_accel_data *data = iio_priv(indio_dev);
1358 dev_dbg(&data->client->dev, __func__);
1360 return bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1363 static int bmc150_accel_runtime_resume(struct device *dev)
1365 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1366 struct bmc150_accel_data *data = iio_priv(indio_dev);
1370 dev_dbg(&data->client->dev, __func__);
1372 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1376 sleep_val = bmc150_accel_get_startup_times(data);
1378 usleep_range(sleep_val * 1000, 20000);
1380 msleep_interruptible(sleep_val);
1386 static const struct dev_pm_ops bmc150_accel_pm_ops = {
1387 SET_SYSTEM_SLEEP_PM_OPS(bmc150_accel_suspend, bmc150_accel_resume)
1388 SET_RUNTIME_PM_OPS(bmc150_accel_runtime_suspend,
1389 bmc150_accel_runtime_resume, NULL)
1392 static const struct acpi_device_id bmc150_accel_acpi_match[] = {
1393 {"BSBA0150", bmc150},
1394 {"BMC150A", bmc150},
1395 {"BMI055A", bmi055},
1396 {"BMA0255", bma255},
1397 {"BMA250E", bma250e},
1398 {"BMA222E", bma222e},
1399 {"BMA0280", bma280},
1402 MODULE_DEVICE_TABLE(acpi, bmc150_accel_acpi_match);
1404 static const struct i2c_device_id bmc150_accel_id[] = {
1405 {"bmc150_accel", bmc150},
1406 {"bmi055_accel", bmi055},
1408 {"bma250e", bma250e},
1409 {"bma222e", bma222e},
1414 MODULE_DEVICE_TABLE(i2c, bmc150_accel_id);
1416 static struct i2c_driver bmc150_accel_driver = {
1418 .name = BMC150_ACCEL_DRV_NAME,
1419 .acpi_match_table = ACPI_PTR(bmc150_accel_acpi_match),
1420 .pm = &bmc150_accel_pm_ops,
1422 .probe = bmc150_accel_probe,
1423 .remove = bmc150_accel_remove,
1424 .id_table = bmc150_accel_id,
1426 module_i2c_driver(bmc150_accel_driver);
1428 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
1429 MODULE_LICENSE("GPL v2");
1430 MODULE_DESCRIPTION("BMC150 accelerometer driver");